[PATCH v1 0/2] Print reset information in SPL
Show reset information such as reset types (cold/warm) and which events triggered the reset.
Chee Hong Ang (2): arm: socfpga: soc64: Add SDM triggered warm reset bit mask arm: socfpga: soc64: Show reset state in SPL
.../include/mach/reset_manager_soc64.h | 12 ++++++++++-- arch/arm/mach-socfpga/reset_manager_s10.c | 22 ++++++++++++++++++++++ arch/arm/mach-socfpga/spl_agilex.c | 1 + arch/arm/mach-socfpga/spl_s10.c | 1 + 4 files changed, 34 insertions(+), 2 deletions(-)
Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat register when checking for HPS warm reset status. Refactor the warm reset mask macro for clarity purpose.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com --- arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index 3f952bc..fc60f6a 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -21,8 +21,15 @@ void socfpga_bridges_reset(int enable); #define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 #define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004
-/* Watchdogs and MPU warm reset mask */ -#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00 +/* SDM, Watchdogs and MPU warm reset mask */ +#define RSTMGR_STAT_SDMWARMRST BIT(1) +#define RSTMGR_STAT_MPU0RST_BITPOS 8 +#define RSTMGR_STAT_L4WD0RST_BITPOS 16 +#define RSTMGR_L4WD_MPU_WARMRESET_MASK (RSTMGR_STAT_SDMWARMRST | \ + GENMASK(RSTMGR_STAT_MPU0RST_BITPOS + 3, \ + RSTMGR_STAT_MPU0RST_BITPOS) | \ + GENMASK(RSTMGR_STAT_L4WD0RST_BITPOS + 3, \ + RSTMGR_STAT_L4WD0RST_BITPOS))
/* * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
-----Original Message----- From: Ang, Chee Hong chee.hong.ang@intel.com Sent: Wednesday, August 5, 2020 9:16 PM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Tom Rini trini@konsulko.com; See, Chin Liang chin.liang.see@intel.com; Tan, Ley Foon ley.foon.tan@intel.com; Ang, Chee Hong chee.hong.ang@intel.com; Chee, Tien Fong tien.fong.chee@intel.com; Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Subject: [PATCH v1 1/2] arm: socfpga: soc64: Add SDM triggered warm reset bit mask
Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat register when checking for HPS warm reset status. Refactor the warm reset mask macro for clarity purpose.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com
arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-)
Reviewed-by: Ley Foon Tan ley.foon.tan@intel.com
Print reset state (warm/cold) together with the source (watchdog/MPU) which has triggered the warm reset on S10 & Agilex.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com --- .../include/mach/reset_manager_soc64.h | 1 + arch/arm/mach-socfpga/reset_manager_s10.c | 22 ++++++++++++++++++++++ arch/arm/mach-socfpga/spl_agilex.c | 1 + arch/arm/mach-socfpga/spl_s10.c | 1 + 4 files changed, 25 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index fc60f6a..c8bb727 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -8,6 +8,7 @@
void reset_deassert_peripherals_handoff(void); int cpu_has_been_warmreset(void); +void print_reset_info(void); void socfpga_bridges_reset(int enable);
#define RSTMGR_SOC64_STATUS 0x00 diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index c743077..9f16bf9 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -104,3 +104,25 @@ int cpu_has_been_warmreset(void) return readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) & RSTMGR_L4WD_MPU_WARMRESET_MASK; } + +void print_reset_info(void) +{ + bool iswd; + int n; + u32 stat = cpu_has_been_warmreset(); + + printf("Reset state: %s%s", stat ? "Warm " : "Cold", + (stat & RSTMGR_STAT_SDMWARMRST) ? "[from SDM] " : ""); + + stat &= ~RSTMGR_STAT_SDMWARMRST; + if (!stat) { + puts("\n"); + return; + } + + n = generic_ffs(stat) - 1; + iswd = (n >= RSTMGR_STAT_L4WD0RST_BITPOS); + printf("(Triggered by %s %d)\n", iswd ? "Watchdog" : "MPU", + iswd ? (n - RSTMGR_STAT_L4WD0RST_BITPOS) : + (n - RSTMGR_STAT_MPU0RST_BITPOS)); +} diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index bd971ec..0121ff4 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -76,6 +76,7 @@ void board_init_f(ulong dummy) }
preloader_console_init(); + print_reset_info(); cm_print_clock_quick_summary();
firewall_setup(); diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index b3c6f6a..1f71182 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -81,6 +81,7 @@ void board_init_f(ulong dummy) #endif
preloader_console_init(); + print_reset_info(); cm_print_clock_quick_summary();
firewall_setup();
-----Original Message----- From: Ang, Chee Hong chee.hong.ang@intel.com Sent: Wednesday, August 5, 2020 9:16 PM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Tom Rini trini@konsulko.com; See, Chin Liang chin.liang.see@intel.com; Tan, Ley Foon ley.foon.tan@intel.com; Ang, Chee Hong chee.hong.ang@intel.com; Chee, Tien Fong tien.fong.chee@intel.com; Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Subject: [PATCH v1 2/2] arm: socfpga: soc64: Show reset state in SPL
Print reset state (warm/cold) together with the source (watchdog/MPU) which has triggered the warm reset on S10 & Agilex.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com
.../include/mach/reset_manager_soc64.h | 1 + arch/arm/mach-socfpga/reset_manager_s10.c | 22 ++++++++++++++++++++++ arch/arm/mach-socfpga/spl_agilex.c | 1 + arch/arm/mach-socfpga/spl_s10.c | 1 + 4 files changed, 25 insertions(+)
Reviewed-by: Ley Foon Tan ley.foon.tan@intel.com
participants (2)
-
Chee Hong Ang -
Tan, Ley Foon