[U-Boot] [PATCH v2 00/11] Add ethernet support for phyCORE-RK3288
- Remove 0004-Net-phy-ti-Fix-fifo_depth-register-write.patch because of the change from 0005-net-phy-ti-Recover-from-port-mirroring- N-A-MODE4.patch it isn't needed anymore. Before, the MII_DP83867_ PHYCTRL-register wasn't write correctly without the fix-patch.
- correct commit reference format
Janine Hagemann (11): arch: arm: mach-rockchip: rk3288: Enable regulators in board_init config: phycore-rk3288_defconfig: add PHY_TI net: gmac_rockchip: Fix a register write in rk3328_gmac_set_to_rgmii net: phy: ti: Add lane swapping support in the DP83867 TI's PHY driver net: phy: ti: Recover from "port mirroring" N/A MODE4 net: phy: ti: add workaround for incorrect RX_CTRL pin strap net: gmac_rockchip: Add handeling for RGMII_ID/RXID/TXID drivers: net: designware: Add reading of DT phy-handle node net: phy: ti: Add binding for the CLK_OUT pin muxing ARM: dts: rockchip: ADD dp83867 CLK_OUT muxing rockchip: rk3288-phycore: set flash1 iodomain to 1.8V
arch/arm/dts/rk3288-phycore-som.dtsi | 1 + arch/arm/mach-rockchip/rk3288-board.c | 6 ++ board/phytec/phycore_rk3288/phycore-rk3288.c | 16 +++++ configs/phycore-rk3288_defconfig | 1 + doc/device-tree-bindings/net/ti,dp83867.txt | 3 + drivers/net/designware.c | 11 ++- drivers/net/designware.h | 1 + drivers/net/gmac_rockchip.c | 80 ++++++++++++++++----- drivers/net/phy/ti.c | 104 ++++++++++++++++++++++++++- include/dt-bindings/net/ti-dp83867.h | 15 ++++ 10 files changed, 219 insertions(+), 19 deletions(-)
At start-up, the regulators have to be enabled. Let's use regulators_enable_boot_on() to enable the regulators needed for boot.
Signed-off-by: Wadim Egorov w.egorov@phytec.de Signed-off-by: Janine Hagemann j.hagemann@phytec.de --- v2: No changes --- arch/arm/mach-rockchip/rk3288-board.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 8c128d4..759bfbe 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -159,6 +159,12 @@ err: #else int ret;
+ ret = regulators_enable_boot_on(false); + if (ret) { + debug("%s: Cannot enable boot on regulator\n", __func__); + return ret; + } + /* We do some SoC one time setting here */ if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { ret = veyron_init();
Janine,
On 18 Jul 2018, at 10:46, Janine Hagemann j.hagemann@phytec.de wrote:
At start-up, the regulators have to be enabled. Let's use regulators_enable_boot_on() to enable the regulators needed for boot.
Signed-off-by: Wadim Egorov w.egorov@phytec.de Signed-off-by: Janine Hagemann j.hagemann@phytec.de
An equivalent change from Carlo has already been applied to U-Boot master. Please review whether there’s additional changes needed, otherwise I’ll just skip this one when processing.
Thanks, Philipp.
Hi Philipp,
Am 18.07.2018 um 11:05 schrieb Dr. Philipp Tomsich:
Janine,
On 18 Jul 2018, at 10:46, Janine Hagemann j.hagemann@phytec.de wrote:
At start-up, the regulators have to be enabled. Let's use regulators_enable_boot_on() to enable the regulators needed for boot.
Signed-off-by: Wadim Egorov w.egorov@phytec.de Signed-off-by: Janine Hagemann j.hagemann@phytec.de
An equivalent change from Carlo has already been applied to U-Boot master. Please review whether there’s additional changes needed, otherwise I’ll just skip this one when processing.
I don't see this patch on master. Anyway, Carlos patch enables the regulators only for the google veyrons.
Regards, Wadim
Thanks, Philipp.
add PHY_TI to support dp83867
Signed-off-by: Janine Hagemann j.hagemann@phytec.de --- v2: No changes --- configs/phycore-rk3288_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index 50b0c98..7d0535f 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -53,6 +53,7 @@ CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_TI=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y
We have to use RK3328_RXCLK_DLY_ENA_GMAC_ENABLE instead of RK3328_RXCLK_DLY_ENA_GMAC_MASK in rk3328_gmac_set_to_rgmii() to enable the RX delay. The MASK was used in a wrong way.
Signed-off-by: Janine Hagemann j.hagemann@phytec.de --- v2: No changes --- drivers/net/gmac_rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 30a24d1..0f91731 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -350,7 +350,7 @@ static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) RK3328_RXCLK_DLY_ENA_GMAC_MASK | RK3328_TXCLK_DLY_ENA_GMAC_MASK, RK3328_GMAC_PHY_INTF_SEL_RGMII | - RK3328_RXCLK_DLY_ENA_GMAC_MASK | + RK3328_RXCLK_DLY_ENA_GMAC_ENABLE | RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
rk_clrsetreg(&grf->mac_con[0],
This patch adds support for enabling or disabling the lane swapping (called "port mirroring" in PHY's CFG4 register) feature of the DP83867 TI's PHY device.
One use case is when bootstrap configuration enables this feature (because of e.g. LED_0 wrong wiring) so then one needs to disable it in software (at u-boot/Linux).
Based on commit fc6d39c39581 ("net: phy: dp83867: Add lane swapping support in the DP83867 TI's PHY driver") of mainline linux kernel.
Signed-off-by: Janine Hagemann j.hagemann@phytec.de --- v2: Change commit reference format --- drivers/net/phy/ti.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+)
diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index 8f3ed8a..bc4fb2b 100644 --- a/drivers/net/phy/ti.c +++ b/drivers/net/phy/ti.c @@ -24,6 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; #define DP83867_CTRL 0x1f
/* Extended Registers */ +#define DP83867_CFG4 0x0031 #define DP83867_RGMIICTL 0x0032 #define DP83867_RGMIIDCTL 0x0086 #define DP83867_IO_MUX_CFG 0x0170 @@ -90,11 +91,21 @@ DECLARE_GLOBAL_DATA_PTR; #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
+/* CFG4 bits */ +#define DP83867_CFG4_PORT_MIRROR_EN BIT(0) + +enum { + DP83867_PORT_MIRRORING_KEEP, + DP83867_PORT_MIRRORING_EN, + DP83867_PORT_MIRRORING_DIS, +}; + struct dp83867_private { int rx_id_delay; int tx_id_delay; int fifo_depth; int io_impedance; + int port_mirroring; };
/** @@ -163,6 +174,26 @@ void phy_write_mmd_indirect(struct phy_device *phydev, int prtad, phy_write(phydev, addr, MII_MMD_DATA, data); }
+static int dp83867_config_port_mirroring(struct phy_device *phydev) +{ + struct dp83867_private *dp83867 = + (struct dp83867_private *)phydev->priv; + u16 val; + + val = phy_read_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR, + phydev->addr); + + if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN) + val |= DP83867_CFG4_PORT_MIRROR_EN; + else + val &= ~DP83867_CFG4_PORT_MIRROR_EN; + + phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR, + phydev->addr, val); + + return 0; +} + #if defined(CONFIG_DM_ETH) /** * dp83867_data_init - Convenience function for setting PHY specific data @@ -189,6 +220,12 @@ static int dp83867_of_init(struct phy_device *phydev) dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "ti,tx-internal-delay", -1);
+ if (fdtdec_get_bool(fdt, node, "enet-phy-lane-swap")) + dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN; + + if (fdtdec_get_bool(fdt, node, "enet-phy-lane-no-swap")) + dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS; + dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "ti,fifo-depth", -1);
@@ -300,6 +337,9 @@ static int dp83867_config(struct phy_device *phydev) } }
+ if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP) + dp83867_config_port_mirroring(phydev); + genphy_config_aneg(phydev); return 0;
The DP83867 when not properly bootstrapped - especially with LED_0 pin - can enter N/A MODE4 for "port mirroring" feature.
To provide normal operation of the PHY, one needs not only to explicitly disable the port mirroring feature, but as well stop some IC internal testing (which disables RGMII communication).
To do that the STRAP_STS1 (0x006E) register must be read and RESERVED bit 11 examined. When it is set, the another RESERVED bit (11) at PHYCR (0x0010) register must be clear to disable testing mode and enable RGMII communication.
Thorough explanation of the problem can be found at following e2e thread: "DP83867IR: Problem with RESERVED bits in PHY Control Register (PHYCR) - Linux driver"
https://e2e.ti.com/support/interface/ethernet/f/903/p/571313/2096954#2096954
Based on commit ac6e058b75be ("net: phy: dp83867: Recover from "port mirroring" N/A MODE4") of mainline linux kernel.
Signed-off-by: Janine Hagemann j.hagemann@phytec.de --- v2: - Change commit reference format - Add an additional phy_read() to fill variable val correct --- drivers/net/phy/ti.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index bc4fb2b..ea1ee24 100644 --- a/drivers/net/phy/ti.c +++ b/drivers/net/phy/ti.c @@ -26,6 +26,7 @@ DECLARE_GLOBAL_DATA_PTR; /* Extended Registers */ #define DP83867_CFG4 0x0031 #define DP83867_RGMIICTL 0x0032 +#define DP83867_STRAP_STS1 0x006E #define DP83867_RGMIIDCTL 0x0086 #define DP83867_IO_MUX_CFG 0x0170
@@ -50,8 +51,12 @@ DECLARE_GLOBAL_DATA_PTR; #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
+/* STRAP_STS1 bits */ +#define DP83867_STRAP_STS1_RESERVED BIT(11) + /* PHY CTRL bits */ #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 +#define DP83867_PHYCR_RESERVED_MASK BIT(11) #define DP83867_MDI_CROSSOVER 5 #define DP83867_MDI_CROSSOVER_AUTO 2 #define DP83867_MDI_CROSSOVER_MDIX 2 @@ -249,7 +254,7 @@ static int dp83867_config(struct phy_device *phydev) { struct dp83867_private *dp83867; unsigned int val, delay, cfg2; - int ret; + int ret, bs;
if (!phydev->priv) { dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL); @@ -275,6 +280,25 @@ static int dp83867_config(struct phy_device *phydev) (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); if (ret) goto err_out; + + /* The code below checks if "port mirroring" N/A MODE4 has been + * enabled during power on bootstrap. + * + * Such N/A mode enabled by mistake can put PHY IC in some + * internal testing mode and disable RGMII transmission. + * + * In this particular case one needs to check STRAP_STS1 + * register's bit 11 (marked as RESERVED). + */ + + bs = phy_read_mmd_indirect(phydev, DP83867_STRAP_STS1, + DP83867_DEVADDR, phydev->addr); + val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL); + if (bs & DP83867_STRAP_STS1_RESERVED) { + val &= ~DP83867_PHYCR_RESERVED_MASK; + phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, val); + } + } else if (phy_interface_is_sgmii(phydev)) { phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
The data manual for DP83867IR/CR, SNLS484E[1], revised march 2017, advises that strapping RX_DV/RX_CTRL pin in mode 1 and 2 is not supported (see note below Table 5 (4-Level Strap Pins)).
There are some boards which have the pin strapped this way and need software workaround suggested by the data manual. Bit[7] of Configuration Register 4 (address 0x0031) must be cleared to 0. This ensures proper operation of the PHY.
Implement driver support for device-tree property meant to advertise the wrong strapping.
[1] http://www.ti.com/lit/ds/snls484e/snls484e.pdf
Based on commit 371444764b98 ("net: phy: dp83867: add workaround for incorrect RX_CTRL pin strap") of mainline linux kernel.
Signed-off-by: Janine Hagemann j.hagemann@phytec.de --- v2: Change commit reference format --- drivers/net/phy/ti.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index ea1ee24..f0ca8f2 100644 --- a/drivers/net/phy/ti.c +++ b/drivers/net/phy/ti.c @@ -111,6 +111,7 @@ struct dp83867_private { int fifo_depth; int io_impedance; int port_mirroring; + bool rxctrl_strap_quirk; };
/** @@ -219,6 +220,9 @@ static int dp83867_of_init(struct phy_device *phydev) else dp83867->io_impedance = -EINVAL;
+ dp83867->rxctrl_strap_quirk = fdtdec_get_bool(fdt, node, + "ti,dp83867-rxctrl-strap-quirk"); + dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "ti,rx-internal-delay", -1);
@@ -274,6 +278,15 @@ static int dp83867_config(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, val | DP83867_SW_RESTART);
+ /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */ + if (dp83867->rxctrl_strap_quirk) { + val = phy_read_mmd_indirect(phydev, DP83867_CFG4, + DP83867_DEVADDR, phydev->addr); + val &= ~BIT(7); + phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR, + phydev->addr, val); + } + if (phy_interface_is_rgmii(phydev)) { ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
On 07/18/2018 03:46 AM, Janine Hagemann wrote:
The data manual for DP83867IR/CR, SNLS484E[1], revised march 2017, advises that strapping RX_DV/RX_CTRL pin in mode 1 and 2 is not supported (see note below Table 5 (4-Level Strap Pins)).
There are some boards which have the pin strapped this way and need software workaround suggested by the data manual. Bit[7] of Configuration Register 4 (address 0x0031) must be cleared to 0. This ensures proper operation of the PHY.
Implement driver support for device-tree property meant to advertise the wrong strapping.
[1] http://www.ti.com/lit/ds/snls484e/snls484e.pdf
Based on commit 371444764b98 ("net: phy: dp83867: add workaround for incorrect RX_CTRL pin strap") of mainline linux kernel.
Signed-off-by: Janine Hagemann j.hagemann@phytec.de
v2: Change commit reference format
drivers/net/phy/ti.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index ea1ee24..f0ca8f2 100644 --- a/drivers/net/phy/ti.c +++ b/drivers/net/phy/ti.c @@ -111,6 +111,7 @@ struct dp83867_private { int fifo_depth; int io_impedance; int port_mirroring;
bool rxctrl_strap_quirk; };
/**
@@ -219,6 +220,9 @@ static int dp83867_of_init(struct phy_device *phydev) else dp83867->io_impedance = -EINVAL;
- dp83867->rxctrl_strap_quirk = fdtdec_get_bool(fdt, node,
"ti,dp83867-rxctrl-strap-quirk");- dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "ti,rx-internal-delay", -1);
@@ -274,6 +278,15 @@ static int dp83867_config(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, val | DP83867_SW_RESTART);
- /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
- if (dp83867->rxctrl_strap_quirk) {
val = phy_read_mmd_indirect(phydev, DP83867_CFG4,DP83867_DEVADDR, phydev->addr);val &= ~BIT(7);phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,phydev->addr, val);- }
- if (phy_interface_is_rgmii(phydev)) { ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
Pls, check https://patchwork.ozlabs.org/cover/936370/ and https://patchwork.ozlabs.org/cover/936380/
i'd need to rebase your series.
On Fri, Jul 20, 2018 at 6:00 PM, Grygorii Strashko grygorii.strashko@ti.com wrote:
On 07/18/2018 03:46 AM, Janine Hagemann wrote:
The data manual for DP83867IR/CR, SNLS484E[1], revised march 2017, advises that strapping RX_DV/RX_CTRL pin in mode 1 and 2 is not supported (see note below Table 5 (4-Level Strap Pins)).
There are some boards which have the pin strapped this way and need software workaround suggested by the data manual. Bit[7] of Configuration Register 4 (address 0x0031) must be cleared to 0. This ensures proper operation of the PHY.
Implement driver support for device-tree property meant to advertise the wrong strapping.
[1] http://www.ti.com/lit/ds/snls484e/snls484e.pdf
Based on commit 371444764b98 ("net: phy: dp83867: add workaround for incorrect RX_CTRL pin strap") of mainline linux kernel.
Signed-off-by: Janine Hagemann j.hagemann@phytec.de
v2: Change commit reference format
drivers/net/phy/ti.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index ea1ee24..f0ca8f2 100644 --- a/drivers/net/phy/ti.c +++ b/drivers/net/phy/ti.c @@ -111,6 +111,7 @@ struct dp83867_private { int fifo_depth; int io_impedance; int port_mirroring;
bool rxctrl_strap_quirk;@@ -219,6 +220,9 @@ static int dp83867_of_init(struct phy_device *phydev) else dp83867->io_impedance = -EINVAL;
dp83867->rxctrl_strap_quirk = fdtdec_get_bool(fdt, node,"ti,dp83867-rxctrl-strap-quirk");dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob,dev_of_offset(dev), "ti,rx-internal-delay", -1); @@ -274,6 +278,15 @@ static int dp83867_config(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, val | DP83867_SW_RESTART);
/* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */if (dp83867->rxctrl_strap_quirk) {val = phy_read_mmd_indirect(phydev, DP83867_CFG4,DP83867_DEVADDR,phydev->addr);
val &= ~BIT(7);phy_write_mmd_indirect(phydev, DP83867_CFG4,DP83867_DEVADDR,
phydev->addr, val);}if (phy_interface_is_rgmii(phydev)) { ret = phy_write(phydev, MDIO_DEVAD_NONE,MII_DP83867_PHYCTRL, (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
Pls, check https://patchwork.ozlabs.org/cover/936370/ and https://patchwork.ozlabs.org/cover/936380/
i'd need to rebase your series.
These are now in my tree, so you could rebase on that and resend.
-Joe
Using PHY internal delays in combination with the phy-mode rgmii-id/rxid/txid was not possible. Only rgmii was supported.
Now we can disable rockchip's gmac delay lines and also use rgmii-id/rxid/txid.
Based on commit eaf70ad14cbb ("net: stmmac: dwmac-rk: Add handling for RGMII_ID/RXID/TXID") for mainline linux kernel.
Signed-off-by: Janine Hagemann j.hagemann@phytec.de --- v2: Change commit reference format --- drivers/net/gmac_rockchip.c | 80 +++++++++++++++++++++++++++++++++++---------- 1 file changed, 63 insertions(+), 17 deletions(-)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 0f91731..c01ae75 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -24,6 +24,11 @@ #include <dt-bindings/clock/rk3288-cru.h> #include "designware.h"
+DECLARE_GLOBAL_DATA_PTR; +#define DELAY_ENABLE(soc, tx, rx) \ + (((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE : soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \ + ((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE : soc##_RXCLK_DLY_ENA_GMAC_DISABLE)) + /* * Platform data for the gmac * @@ -286,8 +291,7 @@ static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) RK3228_RXCLK_DLY_ENA_GMAC_MASK | RK3228_TXCLK_DLY_ENA_GMAC_MASK, RK3228_GMAC_PHY_INTF_SEL_RGMII | - RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | - RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); + DELAY_ENABLE(RK3228, pdata->tx_delay, pdata->rx_delay));
rk_clrsetreg(&grf->mac_con[0], RK3228_CLK_RX_DL_CFG_GMAC_MASK | @@ -310,8 +314,7 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) RK3288_TXCLK_DLY_ENA_GMAC_MASK | RK3288_CLK_RX_DL_CFG_GMAC_MASK | RK3288_CLK_TX_DL_CFG_GMAC_MASK, - RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | - RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | + DELAY_ENABLE(RK3288, pdata->rx_delay, pdata->tx_delay) | pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); } @@ -350,8 +353,7 @@ static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) RK3328_RXCLK_DLY_ENA_GMAC_MASK | RK3328_TXCLK_DLY_ENA_GMAC_MASK, RK3328_GMAC_PHY_INTF_SEL_RGMII | - RK3328_RXCLK_DLY_ENA_GMAC_ENABLE | - RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); + DELAY_ENABLE(RK3328, pdata->tx_delay, pdata->rx_delay));
rk_clrsetreg(&grf->mac_con[0], RK3328_CLK_RX_DL_CFG_GMAC_MASK | @@ -392,8 +394,7 @@ static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) RK3368_TXCLK_DLY_ENA_GMAC_MASK | RK3368_CLK_RX_DL_CFG_GMAC_MASK | RK3368_CLK_TX_DL_CFG_GMAC_MASK, - RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | - RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | + DELAY_ENABLE(RK3368, pdata->tx_delay, pdata->rx_delay) | pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT | pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT); } @@ -413,8 +414,7 @@ static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) RK3399_TXCLK_DLY_ENA_GMAC_MASK | RK3399_CLK_RX_DL_CFG_GMAC_MASK | RK3399_CLK_TX_DL_CFG_GMAC_MASK, - RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | - RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | + DELAY_ENABLE(RK3399, pdata->tx_delay, pdata->rx_delay) | pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT | pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); } @@ -451,40 +451,86 @@ static int gmac_rockchip_probe(struct udevice *dev)
switch (eth_pdata->phy_interface) { case PHY_INTERFACE_MODE_RGMII: + /* Set to RGMII mode */ + if (ops->set_to_rgmii) + ops->set_to_rgmii(pdata); + else + return -EPERM; + /* * If the gmac clock is from internal pll, need to set and * check the return value for gmac clock at RGMII mode. If * the gmac clock is from external source, the clock rate * is not set, because of it is bypassed. */ + if (!pdata->clock_input) { rate = clk_set_rate(&clk, 125000000); if (rate != 125000000) return -EINVAL; } + break;
+ case PHY_INTERFACE_MODE_RGMII_ID: /* Set to RGMII mode */ - if (ops->set_to_rgmii) + if (ops->set_to_rgmii) { + pdata->tx_delay = 0; + pdata->rx_delay = 0; ops->set_to_rgmii(pdata); - else + } else return -EPERM;
- break; - case PHY_INTERFACE_MODE_RMII: - /* The commet is the same as RGMII mode */ if (!pdata->clock_input) { - rate = clk_set_rate(&clk, 50000000); - if (rate != 50000000) + rate = clk_set_rate(&clk, 125000000); + if (rate != 125000000) return -EINVAL; } + break;
+ case PHY_INTERFACE_MODE_RMII: /* Set to RMII mode */ if (ops->set_to_rmii) ops->set_to_rmii(pdata); else return -EPERM;
+ if (!pdata->clock_input) { + rate = clk_set_rate(&clk, 50000000); + if (rate != 50000000) + return -EINVAL; + } + break; + + case PHY_INTERFACE_MODE_RGMII_RXID: + /* Set to RGMII_RXID mode */ + if (ops->set_to_rgmii) { + pdata->tx_delay = 0; + ops->set_to_rgmii(pdata); + } else + return -EPERM; + + if (!pdata->clock_input) { + rate = clk_set_rate(&clk, 125000000); + if (rate != 125000000) + return -EINVAL; + } break; + + case PHY_INTERFACE_MODE_RGMII_TXID: + /* Set to RGMII_TXID mode */ + if (ops->set_to_rgmii) { + pdata->rx_delay = 0; + ops->set_to_rgmii(pdata); + } else + return -EPERM; + + if (!pdata->clock_input) { + rate = clk_set_rate(&clk, 125000000); + if (rate != 125000000) + return -EINVAL; + } + break; + default: debug("NO interface defined!\n"); return -ENXIO;
Add the ability to read the phy-handle node of the gmac. Upon reading this handle the phy-id can be stored based on the reg node in the DT.
The phy-handle also needs to be stored and passed to the phy to access any phy data that is available.
Signed-off-by: Janine Hagemann j.hagemann@phytec.de --- v2: No changes --- drivers/net/designware.c | 11 ++++++++++- drivers/net/designware.h | 1 + 2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c index cf12521..8cc7fb9 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -467,7 +467,7 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev) { struct phy_device *phydev; int mask = 0xffffffff, ret; - + struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); #ifdef CONFIG_PHY_ADDR mask = 1 << CONFIG_PHY_ADDR; #endif @@ -486,6 +486,11 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev) } phydev->advertising = phydev->supported;
+#ifdef CONFIG_DM_ETH + if (dw_pdata->phy_of_handle) + dev_set_of_offset(phydev->dev, dw_pdata->phy_of_handle); +#endif + priv->phydev = phydev; phy_config(phydev);
@@ -786,6 +791,7 @@ int designware_eth_ofdata_to_platdata(struct udevice *dev) int reset_flags = GPIOD_IS_OUT; #endif int ret = 0; + int node = dev_of_offset(dev);
pdata->iobase = dev_read_addr(dev); pdata->phy_interface = -1; @@ -797,6 +803,9 @@ int designware_eth_ofdata_to_platdata(struct udevice *dev) return -EINVAL; }
+ dw_pdata->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node, + "phy-handle"); + pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
#ifdef CONFIG_DM_GPIO diff --git a/drivers/net/designware.h b/drivers/net/designware.h index dea12b7..a6b0443 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -255,6 +255,7 @@ extern const struct eth_ops designware_eth_ops; struct dw_eth_pdata { struct eth_pdata eth_pdata; u32 reset_delays[3]; + int phy_of_handle; };
int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr);
On Wed, Jul 18, 2018 at 3:46 AM, Janine Hagemann j.hagemann@phytec.de wrote:
Add the ability to read the phy-handle node of the gmac. Upon reading this handle the phy-id can be stored based on the reg node in the DT.
The phy-handle also needs to be stored and passed to the phy to access any phy data that is available.
Signed-off-by: Janine Hagemann j.hagemann@phytec.de
v2: No changes
You dropped my Acks from this series. Please correct and resend.
-Joe
drivers/net/designware.c | 11 ++++++++++- drivers/net/designware.h | 1 + 2 files changed, 11 insertions(+), 1 deletion(-)
On 07/18/2018 03:46 AM, Janine Hagemann wrote:
Add the ability to read the phy-handle node of the gmac. Upon reading this handle the phy-id can be stored based on the reg node in the DT.
The phy-handle also needs to be stored and passed to the phy to access any phy data that is available.
Signed-off-by: Janine Hagemann j.hagemann@phytec.de
v2: No changes
drivers/net/designware.c | 11 ++++++++++- drivers/net/designware.h | 1 + 2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c index cf12521..8cc7fb9 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -467,7 +467,7 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev) { struct phy_device *phydev; int mask = 0xffffffff, ret;
- struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); #ifdef CONFIG_PHY_ADDR mask = 1 << CONFIG_PHY_ADDR; #endif
@@ -486,6 +486,11 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev) } phydev->advertising = phydev->supported;
+#ifdef CONFIG_DM_ETH
- if (dw_pdata->phy_of_handle)
dev_set_of_offset(phydev->dev, dw_pdata->phy_of_handle);+#endif
hence https://patchwork.ozlabs.org/cover/936380/ is merged you can't do this any more. Instead you need to setup phydev->node.
[...]
The DP83867 has a muxing option for the CLK_OUT pin. It is possible to set CLK_OUT for different channels. Create a binding to select a specific clock for CLK_OUT pin.
Based on commit 9708fb630d19 ("net: phy: dp83867: Add binding for the CLK_OUT pin muxing option") of mainline linux kernel.
Signed-off-by: Janine Hagemann j.hagemann@phytec.de --- v2: - Change commit reference format - Add a/doc/device-tree-bindings/net/ti,dp83867.txt - Use GENMASK() for shift - Correct multi-line comment format --- doc/device-tree-bindings/net/ti,dp83867.txt | 3 +++ drivers/net/phy/ti.c | 25 +++++++++++++++++++++++++ include/dt-bindings/net/ti-dp83867.h | 15 +++++++++++++++ 3 files changed, 43 insertions(+)
diff --git a/doc/device-tree-bindings/net/ti,dp83867.txt b/doc/device-tree-bindings/net/ti,dp83867.txt index cb77fdf..2561caa 100644 --- a/doc/device-tree-bindings/net/ti,dp83867.txt +++ b/doc/device-tree-bindings/net/ti,dp83867.txt @@ -8,6 +8,8 @@ Required properties: for applicable values - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h for applicable values + - ti,clk-output-sel - Clock output select - see dt-bindings/net/ti-dp83867.h + for applicable values
Default child nodes are standard Ethernet PHY device nodes as described in doc/devicetree/bindings/net/ethernet.txt @@ -19,6 +21,7 @@ Example: ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>; };
Datasheet can be found: diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index f0ca8f2..a509aed 100644 --- a/drivers/net/phy/ti.c +++ b/drivers/net/phy/ti.c @@ -95,6 +95,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f +#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 +#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK GENMASK(0x1f, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT)
/* CFG4 bits */ #define DP83867_CFG4_PORT_MIRROR_EN BIT(0) @@ -112,6 +114,7 @@ struct dp83867_private { int io_impedance; int port_mirroring; bool rxctrl_strap_quirk; + int clk_output_sel; };
/** @@ -212,6 +215,17 @@ static int dp83867_of_init(struct phy_device *phydev) struct udevice *dev = phydev->dev; int node = dev_of_offset(dev); const void *fdt = gd->fdt_blob; + u16 val; + + /* Optional configuration */ + + /* + * Keep the default value if ti,clk-output-sel is not set + * or to high + */ + + dp83867->clk_output_sel = fdtdec_get_uint(fdt, node, + "ti,clk-output-sel", DP83867_CLK_O_SEL_REF_CLK);
if (fdtdec_get_bool(fdt, node, "ti,max-output-impedance")) dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; @@ -238,6 +252,17 @@ static int dp83867_of_init(struct phy_device *phydev) dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "ti,fifo-depth", -1);
+ /* Clock output selection if muxing property is set */ + if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) { + val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG, + DP83867_DEVADDR, phydev->addr); + val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK; + val |= (dp83867->clk_output_sel << + DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT); + phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG, + DP83867_DEVADDR, phydev->addr, val); + } + return 0; } #else diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h index b8e5df6..85d08f6 100644 --- a/include/dt-bindings/net/ti-dp83867.h +++ b/include/dt-bindings/net/ti-dp83867.h @@ -31,4 +31,19 @@ #define DP83867_RGMIIDCTL_3_75_NS 0xe #define DP83867_RGMIIDCTL_4_00_NS 0xf
+/* IO_MUX_CFG - Clock output selection */ +#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 +#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 +#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 +#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 +#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 +#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 +#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 +#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 +#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 +#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 +#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA +#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB +#define DP83867_CLK_O_SEL_REF_CLK 0xC + #endif
The CLK_O_SEL default is synchronus to XI input clock, which is 25 MHz. Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.
Signed-off-by: Janine Hagemann j.hagemann@phytec.de --- v2: No changes --- arch/arm/dts/rk3288-phycore-som.dtsi | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi b/arch/arm/dts/rk3288-phycore-som.dtsi index 02d1196..2dba0aa 100644 --- a/arch/arm/dts/rk3288-phycore-som.dtsi +++ b/arch/arm/dts/rk3288-phycore-som.dtsi @@ -191,6 +191,7 @@ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; enet-phy-lane-no-swap; + ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>; }; }; };
This pin is supplied by 1.8V, but the default iodomain setting is 3.3V.
Signed-off-by: Janine Hagemann j.hagemann@phytec.de --- v2: No changes --- board/phytec/phycore_rk3288/phycore-rk3288.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c index ffe1833..8c1844a 100644 --- a/board/phytec/phycore_rk3288/phycore-rk3288.c +++ b/board/phytec/phycore_rk3288/phycore-rk3288.c @@ -11,6 +11,11 @@ #include <i2c.h> #include <i2c_eeprom.h> #include <netdev.h> +#include <syscon.h> +#include <asm/arch/cru_rk3288.h> +#include <asm/arch/clock.h> +#include <asm/arch/hardware.h> +#include <asm/arch/grf_rk3288.h> #include "som.h"
static int valid_rk3288_som(struct rk3288_som *som) @@ -27,6 +32,15 @@ static int valid_rk3288_som(struct rk3288_som *som) return hw == som->bs; }
+static void setup_iodomain(void) +{ + const u32 GRF_IO_VSEL_FLASH1_SHIFT = 3; + struct rk3288_grf *grf = + syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_FLASH1_SHIFT); +} + int rk_board_late_init(void) { int ret; @@ -34,6 +48,8 @@ int rk_board_late_init(void) struct rk3288_som opt; int off;
+ setup_iodomain(); + /* Get the identificatioin page of M24C32-D EEPROM */ off = fdt_path_offset(gd->fdt_blob, "eeprom0"); if (off < 0) {
On 07/18/2018 03:46 AM, Janine Hagemann wrote:
- Remove 0004-Net-phy-ti-Fix-fifo_depth-register-write.patch because of the change from 0005-net-phy-ti-Recover-from-port-mirroring- N-A-MODE4.patch it isn't needed anymore. Before, the MII_DP83867_ PHYCTRL-register wasn't write correctly without the fix-patch.
I can't find v1 of this series, so above comment looks strange. What's wrong exactly with "PHYCTRL-register wasn't write correctly"?
- correct commit reference format
Janine Hagemann (11): arch: arm: mach-rockchip: rk3288: Enable regulators in board_init config: phycore-rk3288_defconfig: add PHY_TI net: gmac_rockchip: Fix a register write in rk3328_gmac_set_to_rgmii net: phy: ti: Add lane swapping support in the DP83867 TI's PHY driver net: phy: ti: Recover from "port mirroring" N/A MODE4 net: phy: ti: add workaround for incorrect RX_CTRL pin strap net: gmac_rockchip: Add handeling for RGMII_ID/RXID/TXID drivers: net: designware: Add reading of DT phy-handle node net: phy: ti: Add binding for the CLK_OUT pin muxing ARM: dts: rockchip: ADD dp83867 CLK_OUT muxing rockchip: rk3288-phycore: set flash1 iodomain to 1.8V
arch/arm/dts/rk3288-phycore-som.dtsi | 1 + arch/arm/mach-rockchip/rk3288-board.c | 6 ++ board/phytec/phycore_rk3288/phycore-rk3288.c | 16 +++++ configs/phycore-rk3288_defconfig | 1 + doc/device-tree-bindings/net/ti,dp83867.txt | 3 + drivers/net/designware.c | 11 ++- drivers/net/designware.h | 1 + drivers/net/gmac_rockchip.c | 80 ++++++++++++++++----- drivers/net/phy/ti.c | 104 ++++++++++++++++++++++++++- include/dt-bindings/net/ti-dp83867.h | 15 ++++ 10 files changed, 219 insertions(+), 19 deletions(-)
Unfortunately the v1-patches were only send to the maintainers and not to the official mailinglist.
Am 21.07.2018 um 01:25 schrieb Grygorii Strashko:
On 07/18/2018 03:46 AM, Janine Hagemann wrote:
- Remove 0004-Net-phy-ti-Fix-fifo_depth-register-write.patch because
of the change from 0005-net-phy-ti-Recover-from-port-mirroring- N-A-MODE4.patch it isn't needed anymore. Before, the MII_DP83867_ PHYCTRL-register wasn't write correctly without the fix-patch.
I can't find v1 of this series, so above comment looks strange. What's wrong exactly with "PHYCTRL-register wasn't write correctly"?
- correct commit reference format
Janine Hagemann (11): arch: arm: mach-rockchip: rk3288: Enable regulators in board_init config: phycore-rk3288_defconfig: add PHY_TI net: gmac_rockchip: Fix a register write in rk3328_gmac_set_to_rgmii net: phy: ti: Add lane swapping support in the DP83867 TI's PHY driver net: phy: ti: Recover from "port mirroring" N/A MODE4 net: phy: ti: add workaround for incorrect RX_CTRL pin strap net: gmac_rockchip: Add handeling for RGMII_ID/RXID/TXID drivers: net: designware: Add reading of DT phy-handle node net: phy: ti: Add binding for the CLK_OUT pin muxing ARM: dts: rockchip: ADD dp83867 CLK_OUT muxing rockchip: rk3288-phycore: set flash1 iodomain to 1.8V
arch/arm/dts/rk3288-phycore-som.dtsi | 1 + arch/arm/mach-rockchip/rk3288-board.c | 6 ++ board/phytec/phycore_rk3288/phycore-rk3288.c | 16 +++++ configs/phycore-rk3288_defconfig | 1 + doc/device-tree-bindings/net/ti,dp83867.txt | 3 + drivers/net/designware.c | 11 ++- drivers/net/designware.h | 1 + drivers/net/gmac_rockchip.c | 80 ++++++++++++++++----- drivers/net/phy/ti.c | 104 ++++++++++++++++++++++++++- include/dt-bindings/net/ti-dp83867.h | 15 ++++ 10 files changed, 219 insertions(+), 19 deletions(-)
On 07/23/2018 04:29 AM, Janine Hagemann wrote:
Unfortunately the v1-patches were only send to the maintainers and not to the official mailinglist.
Could you separate "net: phy: ti: " patches in standalone series pls?
[...]
participants (5)
-
Dr. Philipp Tomsich -
Grygorii Strashko -
Janine Hagemann -
Joe Hershberger -
Wadim Egorov