Sync rk3588 device tree from v6.7-rockchip-dts64-1 tag.

Adds PCIe, button and led nodes to rk3588-evb1-v10 and rk3588-rock-5b boards. Also remove includes from u-boot.dtsi-files that is no longer needed.

Linux commits: 42145b7a8235 ("arm64: dts: rockchip: add PCIe network controller to rock-5b") 199cbd5f195a ("arm64: dts: rockchip: add PCIe for M.2 M-key to rock-5b") da447ec38780 ("arm64: dts: rockchip: add PCIe for M.2 E-Key to rock-5b") 86a2024d95e2 ("arm64: dts: rockchip: add PCIe2 network controller to rk3588-evb1") 46bb398ea1d8 ("arm64: dts: rockchip: add PCIe3 bus to rk3588-evb1") 1c9a53ff7ece ("arm64: dts: rockchip: Add sdio node to rock-5b") 3eaf2abd11aa ("arm64: dts: rockchip: Add sfc node to rk3588s") bf012368bb0a ("arm64: dts: rockchip: Add I2S2 M0 pin definitions to rk3588s") 3d77a3e51b0f ("arm64: dts: rockchip: Add UART9 M0 pin definitions to rk3588s") 0002c377e862 ("arm64: dts: rockchip: Remove duplicate regulator vcc3v3_wf from rock-5b") a6169ab36923 ("arm64: dts: rockchip: Enable UART6 on rock-5b") dd6dc0c4c126 ("arm64: dts: rockchip: Add AV1 decoder node to rk3588s") afa933c208e5 ("arm64: dts: rockchip: add ADC buttons to rk3588-evb1") 7952cbbda301 ("arm64: dts: rockchip: add status LED to rock-5b")

Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Christopher Obbard chris.obbard@collabora.com Reviewed-by: Kever Yang kever.yang@rock-chips.com --- v2: - Sync with "Rockchip dts64 changes for 6.7" PR [1] - Collect r-b tags

[1] https://lore.kernel.org/all/1870252.CQOukoFCf9@phil/

arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi | 11 +- arch/arm/dts/rk3588-evb1-v10.dts | 136 +++++++++++++++++++++ arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 60 ---------- arch/arm/dts/rk3588-rock-5b.dts | 145 +++++++++++++++++++++++ arch/arm/dts/rk3588-u-boot.dtsi | 1 - arch/arm/dts/rk3588s-pinctrl.dtsi | 44 +++++++ arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi | 4 - arch/arm/dts/rk3588s-u-boot.dtsi | 10 -- arch/arm/dts/rk3588s.dtsi | 24 ++++ 9 files changed, 350 insertions(+), 85 deletions(-)

diff --git a/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi b/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi index bd2e25948633..e8566785e965 100644 --- a/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi +++ b/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi @@ -6,16 +6,7 @@ #include "rk3588-u-boot.dtsi"

/ { - aliases { - mmc0 = &sdmmc; - mmc1 = &sdhci; - }; - chosen { - u-boot,spl-boot-order = &sdhci; + u-boot,spl-boot-order = "same-as-spl", &sdhci; }; }; - -&sdhci { - bootph-all; -}; diff --git a/arch/arm/dts/rk3588-evb1-v10.dts b/arch/arm/dts/rk3588-evb1-v10.dts index 229a9111f5eb..b9d789d57862 100644 --- a/arch/arm/dts/rk3588-evb1-v10.dts +++ b/arch/arm/dts/rk3588-evb1-v10.dts @@ -7,6 +7,7 @@ /dts-v1/;

#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> #include <dt-bindings/pinctrl/rockchip.h> #include "rk3588.dtsi"

@@ -23,12 +24,84 @@ stdout-path = "serial2:1500000n8"; };

+ adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-vol-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <17000>; + }; + + button-vol-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <417000>; + }; + + button-menu { + label = "Menu"; + linux,code = <KEY_MENU>; + press-threshold-microvolt = <890000>; + }; + + button-escape { + label = "Escape"; + linux,code = <KEY_ESC>; + press-threshold-microvolt = <1235000>; + }; + }; + backlight: backlight { compatible = "pwm-backlight"; power-supply = <&vcc12v_dcin>; pwms = <&pwm2 0 25000 0>; };

+ pcie20_avdd0v85: pcie20-avdd0v85-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&avdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -38,6 +111,19 @@ regulator-max-microvolt = <12000000>; };

+ vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie30_en>; + }; + vcc5v0_host: vcc5v0-host-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_host"; @@ -87,6 +173,10 @@ status = "okay"; };

+&combphy2_psu { + status = "okay"; +}; + &cpu_b0 { cpu-supply = <&vdd_cpu_big0_s0>; }; @@ -163,7 +253,32 @@ }; };

+&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_1_rst>, <&rtl8111_isolate>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_reset>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + &pinctrl { + rtl8111 { + rtl8111_isolate: rtl8111-isolate { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + rtl8211f { rtl8211f_rst: rtl8211f-rst { rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; @@ -177,6 +292,22 @@ }; };

+ pcie2 { + pcie2_1_rst: pcie2-1-rst { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3_reset: pcie3-reset { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc3v3_pcie30_en: vcc3v3-pcie30-en { + rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + usb { vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; @@ -188,6 +319,11 @@ status = "okay"; };

+&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + &sdhci { bus-width = <8>; no-sdio; diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 96cc84e5aac9..3f390ef26a3f 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -4,9 +4,6 @@ */

#include "rk3588-u-boot.dtsi" -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/usb/pd.h>

/ { @@ -23,19 +20,6 @@ regulator-max-microvolt = <12000000>; };

- vcc3v3_pcie30: vcc3v3-pcie30-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - vin-supply = <&vcc5v0_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_vcc3v3_en>; - }; - vcc5v0_usbdcin: vcc5v0-usbdcin { compatible = "regulator-fixed"; regulator-name = "vcc5v0_usbdcin"; @@ -69,53 +53,11 @@ }; };

-&combphy0_ps { - status = "okay"; -}; - &fspim2_pins { bootph-all; };

-&pcie2x1l2 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie2x1l2_pins &pcie_reset_h>; - reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x4 { - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_rst>; - status = "okay"; -}; - &pinctrl { - pcie { - pcie_reset_h: pcie-reset-h { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie2x1l2_pins: pcie2x1l2-pins { - rockchip,pins = <3 RK_PC7 4 &pcfg_pull_none>, - <3 RK_PD0 4 &pcfg_pull_none>; - }; - - pcie3_rst: pcie3-rst { - rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie3_vcc3v3_en: pcie3-vcc3v3-en { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - usb-typec { usbc0_int: usbc0-int { rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; @@ -138,8 +80,6 @@ u-boot,spl-sfc-no-dma; pinctrl-names = "default"; pinctrl-0 = <&fspim2_pins>; - #address-cells = <1>; - #size-cells = <0>; status = "okay";

flash@0 { diff --git a/arch/arm/dts/rk3588-rock-5b.dts b/arch/arm/dts/rk3588-rock-5b.dts index 8ab60968f275..741f631db345 100644 --- a/arch/arm/dts/rk3588-rock-5b.dts +++ b/arch/arm/dts/rk3588-rock-5b.dts @@ -3,6 +3,7 @@ /dts-v1/;

#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> #include "rk3588.dtsi"

/ { @@ -12,6 +13,7 @@ aliases { mmc0 = &sdhci; mmc1 = &sdmmc; + mmc2 = &sdio; serial2 = &uart2; };

@@ -36,6 +38,19 @@ pinctrl-0 = <&hp_detect>; };

+ leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_rgb_b>; + + led_rgb_b { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + fan: pwm-fan { compatible = "pwm-fan"; cooling-levels = <0 95 145 195 255>; @@ -44,6 +59,43 @@ #cooling-cells = <2>; };

+ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_vcc3v3_en>; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_vcc3v3_en>; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + vcc5v0_host: vcc5v0-host-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_host"; @@ -78,6 +130,14 @@ }; };

+&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + &cpu_b0 { cpu-supply = <&vdd_cpu_big0_s0>; }; @@ -204,6 +264,34 @@ }; };

+&pcie2x1l0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_rst>; + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; +}; + +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_2_rst>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_rst>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { @@ -211,12 +299,42 @@ }; };

+ leds { + led_rgb_b: led-rgb-b { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sound { hp_detect: hp-detect { rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; }; };

+ pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_0_vcc3v3_en: pcie2-0-vcc-en { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_2_rst: pcie2-2-rst { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3_rst: pcie3-rst { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3_vcc3v3_en: pcie3-vcc3v3-en { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + usb { vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; @@ -258,6 +376,33 @@ status = "okay"; };

+&sdio { + max-frequency = <200000000>; + no-sd; + no-mmc; + non-removable; + bus-width = <4>; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + wakeup-source; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_pcie2x1l0>; + vqmmc-supply = <&vcc_1v8_s3>; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom0_pins>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; + status = "okay"; +}; + &spi2 { status = "okay"; assigned-clocks = <&cru CLK_SPI2>; diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi index 68b419f3abd5..15de4706254e 100644 --- a/arch/arm/dts/rk3588-u-boot.dtsi +++ b/arch/arm/dts/rk3588-u-boot.dtsi @@ -3,7 +3,6 @@ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. */

-#include "rockchip-u-boot.dtsi" #include "rk3588s-u-boot.dtsi"

/ { diff --git a/arch/arm/dts/rk3588s-pinctrl.dtsi b/arch/arm/dts/rk3588s-pinctrl.dtsi index 48181671eacb..63151d9d2377 100644 --- a/arch/arm/dts/rk3588s-pinctrl.dtsi +++ b/arch/arm/dts/rk3588s-pinctrl.dtsi @@ -1349,6 +1349,41 @@ };

i2s2 { + /omit-if-no-ref/ + i2s2m0_lrck: i2s2m0-lrck { + rockchip,pins = + /* i2s2m0_lrck */ + <2 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = + /* i2s2m0_mclk */ + <2 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sclk: i2s2m0-sclk { + rockchip,pins = + /* i2s2m0_sclk */ + <2 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = + /* i2s2m0_sdi */ + <2 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = + /* i2s2m0_sdo */ + <4 RK_PC3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ i2s2m1_lrck: i2s2m1-lrck { rockchip,pins = @@ -3307,6 +3342,15 @@ };

uart9 { + /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins = + /* uart9_rx_m0 */ + <2 RK_PC4 10 &pcfg_pull_up>, + /* uart9_tx_m0 */ + <2 RK_PC2 10 &pcfg_pull_up>; + }; + /omit-if-no-ref/ uart9m1_xfer: uart9m1-xfer { rockchip,pins = diff --git a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi index c47b0a7112c8..584476f77b13 100644 --- a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi @@ -4,10 +4,6 @@ */

#include "rk3588s-u-boot.dtsi" -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/usb/pd.h>

/ { chosen { diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index 27b2d7eff87b..878936fa07d6 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -4,7 +4,6 @@ */

#include "rockchip-u-boot.dtsi" -#include <dt-bindings/phy/phy.h>

/ { aliases { @@ -102,15 +101,6 @@ reg = <0x0 0xfd5c8000 0x0 0x4000>; };

- sfc: spi@fe2b0000 { - compatible = "rockchip,sfc"; - reg = <0x0 0xfe2b0000 0x0 0x4000>; - interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; - clock-names = "clk_sfc", "hclk_sfc"; - status = "disabled"; - }; - rng: rng@fe378000 { compatible = "rockchip,trngv1"; reg = <0x0 0xfe378000 0x0 0x200>; diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi index 5544f66c6ff4..61a9a11c3bb0 100644 --- a/arch/arm/dts/rk3588s.dtsi +++ b/arch/arm/dts/rk3588s.dtsi @@ -1424,6 +1424,17 @@ }; };

+ sfc: spi@fe2b0000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sdmmc: mmc@fe2c0000 { compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe2c0000 0x0 0x4000>; @@ -2304,6 +2315,19 @@ #interrupt-cells = <2>; }; }; + + av1d: video-codec@fdc70000 { + compatible = "rockchip,rk3588-av1-vpu"; + reg = <0x0 0xfdc70000 0x0 0x800>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "vdpu"; + assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + assigned-clock-rates = <400000000>, <400000000>; + clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3588_PD_AV1>; + resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; + }; };

#include "rk3588s-pinctrl.dtsi"

The device tree for rk3588 and rock-5b contain usb3 nodes that have deviated too much from current state of submitted mainline linux usb3 patches, see [1].

Sync usb3 related nodes from latest patches and collaboras rk3588 tree so that dwc3-generic driver can be updated to include support for the rockchip,rk3588-dwc3 compatible in the future, use rockchip,rk3568-dwc3 compatible until final node is merged in linux maintainer tree.

[1] https://lore.kernel.org/lkml/20231009172129.43568-1-sebastian.reichel@collab...

Signed-off-by: Jonas Karlman jonas@kwiboo.se --- v2: - Use rockchip,rk3568-dwc3 compatible so that driver change can be submitted in a separate series.

RK3588 USB 3.0 binding update [2] has not been merged for linux v6.7. Our options is to update these nodes to latest submitted state, as done in this patch, or to remove them until a sync of final nodes can be done.

[2] https://lore.kernel.org/all/20231009172129.43568-2-sebastian.reichel@collabo...

arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 148 +++++++----------------- arch/arm/dts/rk3588-u-boot.dtsi | 39 +++---- arch/arm/dts/rk3588s-u-boot.dtsi | 68 ++++++----- configs/rock5b-rk3588_defconfig | 1 - 4 files changed, 99 insertions(+), 157 deletions(-)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 3f390ef26a3f..b595ddef7028 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -19,38 +19,10 @@ regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; }; +};

- vcc5v0_usbdcin: vcc5v0-usbdcin { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usbdcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usbdcin>; - }; - - vbus5v0_typec: vbus5v0-typec { - compatible = "regulator-fixed"; - regulator-name = "vbus5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; - }; +&combphy2_psu { + status = "okay"; };

&fspim2_pins { @@ -58,13 +30,9 @@ };

&pinctrl { - usb-typec { + usb { usbc0_int: usbc0-int { - rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - typec5v_pwren: typec5v-pwren { - rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; @@ -97,7 +65,6 @@ };

&u2phy0_otg { - rockchip,typec-vbus-det; status = "okay"; };

@@ -109,25 +76,17 @@ status = "okay"; };

-&usb2phy2_grf { +&usbdp_phy1 { status = "okay"; };

-&usb2phy3_grf { +&usbdp_phy1_u3 { status = "okay"; };

-&usb_host0_ehci { - companion = <&usb_host0_ohci>; -}; - -&usb_host1_ehci { - companion = <&usb_host1_ohci>; -}; - &usbdp_phy0 { orientation-switch; - svid = <0xff01>; + mode-switch; sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; status = "okay"; @@ -135,14 +94,15 @@ port { #address-cells = <1>; #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { + + usbdp_phy0_typec_ss: endpoint@0 { reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; + remote-endpoint = <&usbc0_ss>; };

- usbdp_phy0_dp_altmode_mux: endpoint@1 { + usbdp_phy0_typec_sbu: endpoint@1 { reg = <1>; - remote-endpoint = <&dp_altmode_mux>; + remote-endpoint = <&usbc0_sbu>; }; }; }; @@ -151,84 +111,53 @@ status = "okay"; };

-&usbdp_phy1 { - rockchip,dp-lane-mux = <2 3>; +&usb_host0_xhci { + usb-role-switch; status = "okay"; -};

-&usbdp_phy1_u3 { - status = "okay"; -}; + port { + #address-cells = <1>; + #size-cells = <0>;

-&usbdrd3_0 { - status = "okay"; + usb_host0_xhci_drd_sw: endpoint { + remote-endpoint = <&usbc0_hs>; + }; + }; };

-&usbdrd3_1 { +&usb_host1_xhci { status = "okay"; };

-&usbdrd_dwc3_0 { - usb-role-switch; - - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; +&usb_host2_xhci { + status = "okay"; };

&i2c4 { + pinctrl-names = "default"; pinctrl-0 = <&i2c4m1_xfer>; status = "okay";

- usbc0: fusb302@22 { + usbc0: usb-typec@22 { compatible = "fcs,fusb302"; reg = <0x22>; interrupt-parent = <&gpio3>; interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vbus5v0_typec>; + vbus-supply = <&vcc12v_dcin>; status = "okay";

- ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - usb_con: connector { compatible = "usb-c-connector"; label = "USB-C"; data-role = "dual"; - power-role = "dual"; + power-role = "sink"; try-power-role = "sink"; op-sink-microwatt = <1000000>; sink-pdos = - <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>; - source-pdos = - <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - - altmodes { - #address-cells = <1>; - #size-cells = <0>; - - altmode@0 { - reg = <0>; - svid = <0xff01>; - vdo = <0xffffffff>; - }; - }; + <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>, + <PDO_VAR(5000, 20000, 5000)>;

ports { #address-cells = <1>; @@ -236,15 +165,22 @@

port@0 { reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; + usbc0_hs: endpoint { + remote-endpoint = <&usb_host0_xhci_drd_sw>; }; };

port@1 { reg = <1>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + usbc0_ss: endpoint { + remote-endpoint = <&usbdp_phy0_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + usbc0_sbu: endpoint { + remote-endpoint = <&usbdp_phy0_typec_sbu>; }; }; }; diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi index 15de4706254e..31046fc7febb 100644 --- a/arch/arm/dts/rk3588-u-boot.dtsi +++ b/arch/arm/dts/rk3588-u-boot.dtsi @@ -6,32 +6,24 @@ #include "rk3588s-u-boot.dtsi"

/ { - usbdrd3_1: usbdrd3_1 { - compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; + usb_host1_xhci: usb@fc400000 { + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, <&cru ACLK_USB3OTG1>; - clock-names = "ref", "suspend", "bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + dr_mode = "host"; + phys = <&u2phy1_otg>, <&usbdp_phy1_u3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG1>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; status = "disabled"; - - usbdrd_dwc3_1: usb@fc400000 { - compatible = "snps,dwc3"; - reg = <0x0 0xfc400000 0x0 0x400000>; - interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; - power-domains = <&power RK3588_PD_USB>; - resets = <&cru SRST_A_USB3OTG1>; - reset-names = "usb3-otg"; - dr_mode = "host"; - phys = <&u2phy1_otg>, <&usbdp_phy1_u3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - }; };

usbdpphy1_grf: syscon@fd5cc000 { @@ -56,7 +48,6 @@ clock-names = "phyclk"; clock-output-names = "usb480m_phy1"; #clock-cells = <0>; - rockchip,usbctrl-grf = <&usb_grf>; status = "disabled";

u2phy1_otg: otg-port { diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index 878936fa07d6..c0fd16c4022b 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -21,35 +21,47 @@ status = "okay"; };

- usbdrd3_0: usbdrd3_0 { - compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; + usb_host0_xhci: usb@fc000000 { + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3"; + reg = <0x0 0xfc000000 0x0 0x400000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, <&cru ACLK_USB3OTG0>; - clock-names = "ref", "suspend", "bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&usbdp_phy0_u3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG0>; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; status = "disabled"; + };

- usbdrd_dwc3_0: usb@fc000000 { - compatible = "snps,dwc3"; - reg = <0x0 0xfc000000 0x0 0x400000>; - interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; - power-domains = <&power RK3588_PD_USB>; - resets = <&cru SRST_A_USB3OTG0>; - reset-names = "usb3-otg"; - dr_mode = "otg"; - phys = <&u2phy0_otg>, <&usbdp_phy0_u3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - quirk-skip-phy-init; - }; + usb_host2_xhci: usb@fcd00000 { + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3"; + reg = <0x0 0xfcd00000 0x0 0x400000>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, + <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, + <&cru CLK_PIPEPHY2_PIPE_U3_G>; + clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; + dr_mode = "host"; + phys = <&combphy2_psu PHY_TYPE_USB3>; + phy-names = "usb3-phy"; + phy_type = "utmi_wide"; + resets = <&cru SRST_A_USB3OTG2>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + status = "disabled"; };

pmu1_grf: syscon@fd58a000 { @@ -58,6 +70,11 @@ reg = <0x0 0xfd58a000 0x0 0x2000>; };

+ usbdpphy0_grf: syscon@fd5c8000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5c8000 0x0 0x4000>; + }; + usb2phy0_grf: syscon@fd5d0000 { compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; @@ -75,7 +92,6 @@ clock-names = "phyclk"; clock-output-names = "usb480m_phy0"; #clock-cells = <0>; - rockchip,usbctrl-grf = <&usb_grf>; status = "disabled";

u2phy0_otg: otg-port { diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index ec22e70033a0..0595325e8107 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -101,7 +101,6 @@ CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y -# CONFIG_USB_XHCI_DWC3_OF_SIMPLE is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y