[U-Boot] [PATCH v2 0/7] dm: x86: Convert ICH driver fully to driver model PCI API

Simon Glass

17 Dec 2015 17 Dec '15

5:12 a.m.

This is a small series to move the ICH driver over to use the driver model PCI API. It involves creating PCH drivers which the ICH driver can use to find out its base address.

At present irq-router is the 'PCH' node in most device tree files. This is not really correct since the router is just one of the functions of the PCH. Another is the SPI bus. So this series also moves irq-router down a level. This still works with the same irq-router driver, since it just searches for the first compatible node it can find.

A driver-model-compatible irq-router driver should be written but that is left for later.

This series unfortunately needs testing on each board since each has a separate change. I have tested minnowmax and chromebook_link so far.

Changes in v2: - Add more detail to the function comment - Rename the last parameter to 'addr' - Update the comment to explain usable of this function - Update the commit message and header file comments - Use an enum for the PCH version - Replace SBASE with SPI base - Add a TODO to check if the init() method can be removed later - Rename the PCH functions - Update the get_version() handle to use an enum - Add a function to obtain the SPI base address - Rename the PCH functions - Update the get_version() handle to use an enum - Adjust code for earlier commits - Move the SPI base code into the PCH drivers

Simon Glass (7): dm: pci: Move pci_bus_to_hose() to compatibility dm: pci: Add a function to write a BAR dm: pci: Avoid using pci_bus_to_hose() in the uclass dm: Expand the uclass for Platform Controller Hubs (PCH) dm: x86: Add a driver for Intel PCH7 dm: x86: Add a driver for Intel PCH9 dm: x86: spi: Convert ICH SPI driver to driver model PCI API

arch/x86/cpu/coreboot/pci.c | 3 +- arch/x86/cpu/irq.c | 7 +- arch/x86/cpu/ivybridge/bd82x6x.c | 25 +++++ arch/x86/dts/bayleybay.dts | 160 +++++++++++++++-------------- arch/x86/dts/broadwell_som-6896.dts | 23 +++-- arch/x86/dts/chromebook_link.dts | 5 +- arch/x86/dts/chromebox_panther.dts | 33 +++--- arch/x86/dts/crownbay.dts | 150 ++++++++++++++------------- arch/x86/dts/galileo.dts | 98 +++++++++--------- arch/x86/dts/minnowmax.dts | 158 ++++++++++++++-------------- arch/x86/dts/qemu-x86_i440fx.dts | 26 +++-- arch/x86/dts/qemu-x86_q35.dts | 38 ++++--- arch/x86/lib/Makefile | 1 - drivers/Makefile | 1 + drivers/pch/Makefile | 7 ++ {arch/x86/lib => drivers/pch}/pch-uclass.c | 32 ++++++ drivers/pch/pch7.c | 43 ++++++++ drivers/pch/pch9.c | 43 ++++++++ drivers/pci/pci-uclass.c | 24 ++--- drivers/pci/pci_auto.c | 14 +-- drivers/pci/pci_compat.c | 15 +++ drivers/pci/pci_internal.h | 12 +++ drivers/spi/ich.c | 143 ++++++-------------------- include/pch.h | 80 +++++++++++++++ include/pci.h | 17 ++- 25 files changed, 699 insertions(+), 459 deletions(-) create mode 100644 drivers/pch/Makefile rename {arch/x86/lib => drivers/pch}/pch-uclass.c (53%) create mode 100644 drivers/pch/pch7.c create mode 100644 drivers/pch/pch9.c create mode 100644 include/pch.h

-- 2.6.0.rc2.230.g3dd15c0

Show replies by date

Simon Glass

17 Dec 17 Dec

5:12 a.m.

New subject: [U-Boot] [PATCH v2 1/7] dm: pci: Move pci_bus_to_hose() to compatibility

This function should not be used by driver-model code, so move it to the compatibility portion.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Add more detail to the function comment

drivers/pci/pci-uclass.c | 16 +--------------- drivers/pci/pci_compat.c | 15 +++++++++++++++ drivers/pci/pci_internal.h | 12 ++++++++++++ 3 files changed, 28 insertions(+), 15 deletions(-)

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 685df9d..6dd4883 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -22,7 +22,7 @@

DECLARE_GLOBAL_DATA_PTR;

-static int pci_get_bus(int busnum, struct udevice **busp) +int pci_get_bus(int busnum, struct udevice **busp) { int ret;

@@ -41,20 +41,6 @@ static int pci_get_bus(int busnum, struct udevice **busp) return ret; }

-struct pci_controller *pci_bus_to_hose(int busnum) -{ - struct udevice *bus; - int ret; - - ret = pci_get_bus(busnum, &bus); - if (ret) { - debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret); - return NULL; - } - - return dev_get_uclass_priv(bus); -} - struct udevice *pci_get_controller(struct udevice *dev) { while (device_is_on_pci_bus(dev)) diff --git a/drivers/pci/pci_compat.c b/drivers/pci/pci_compat.c index dd15eb1..ddaf358 100644 --- a/drivers/pci/pci_compat.c +++ b/drivers/pci/pci_compat.c @@ -12,6 +12,7 @@ #include <pci.h> #include <dm/device-internal.h> #include <dm/lists.h> +#include "pci_internal.h"

#define PCI_HOSE_OP(rw, name, size, type) \ int pci_hose_##rw##_config_##name(struct pci_controller *hose, \ @@ -36,3 +37,17 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) return -1; return dm_pci_get_bdf(dev); } + +struct pci_controller *pci_bus_to_hose(int busnum) +{ + struct udevice *bus; + int ret; + + ret = pci_get_bus(busnum, &bus); + if (ret) { + debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret); + return NULL; + } + + return dev_get_uclass_priv(bus); +} diff --git a/drivers/pci/pci_internal.h b/drivers/pci/pci_internal.h index 0867575..616b9c1 100644 --- a/drivers/pci/pci_internal.h +++ b/drivers/pci/pci_internal.h @@ -47,4 +47,16 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus); */ int dm_pciauto_config_device(struct udevice *dev);

+/** + * pci_get_bus() - Get a pointer to a bus, given its number + * + * This looks up a PCI bus based on its bus number. The bus is probed if + * necessary. + * + * @busnum: PCI bus number to look up + * @busp: Returns PCI bus on success + * @return 0 on success, or -ve error + */ +int pci_get_bus(int busnum, struct udevice **busp); + #endif

-- 2.6.0.rc2.230.g3dd15c0

Simon Glass

5:12 a.m.

New subject: [U-Boot] [PATCH v2 2/7] dm: pci: Add a function to write a BAR

Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Rename the last parameter to 'addr' - Update the comment to explain usable of this function

drivers/pci/pci-uclass.c | 8 ++++++++ include/pci.h | 17 +++++++++++++++-- 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 6dd4883..61292d7 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1053,6 +1053,14 @@ u32 dm_pci_read_bar32(struct udevice *dev, int barnum) return addr & PCI_BASE_ADDRESS_MEM_MASK; }

+void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr) +{ + int bar; + + bar = PCI_BASE_ADDRESS_0 + barnum * 4; + dm_pci_write_config32(dev, bar, addr); +} + static int _dm_pci_bus_to_phys(struct udevice *ctlr, pci_addr_t bus_addr, unsigned long flags, unsigned long skip_mask, phys_addr_t *pa) diff --git a/include/pci.h b/include/pci.h index cb2562f..96f9189 100644 --- a/include/pci.h +++ b/include/pci.h @@ -757,7 +757,9 @@ extern void pci_mpc85xx_init (struct pci_controller *hose); /** * pci_write_bar32() - Write the address of a BAR including control bits * - * This writes a raw address (with control bits) to a bar + * This writes a raw address (with control bits) to a bar. This can be used + * with devices which require hard-coded addresses, not part of the normal + * PCI enumeration process. * * @hose: PCI hose to use * @dev: PCI device to update @@ -765,7 +767,7 @@ extern void pci_mpc85xx_init (struct pci_controller *hose); * @addr: BAR address with control bits */ void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, - u32 addr_and_ctrl); + u32 addr);

/** * pci_read_bar32() - read the address of a bar @@ -1167,6 +1169,17 @@ int pci_get_regions(struct udevice *dev, struct pci_region **iop, struct pci_region **memp, struct pci_region **prefp);

/** + * dm_pci_write_bar32() - Write the address of a BAR including control bits + * + * This writes a raw address (with control bits) to a bar + * + * @dev: PCI device to update + * @barnum: BAR number (0-5) + * @addr: BAR address with control bits + */ +void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr_and_ctrl); + +/** * dm_pci_read_bar32() - read a base address register from a device * * @dev: Device to check

-- 2.6.0.rc2.230.g3dd15c0

Simon Glass

5:12 a.m.

New subject: [U-Boot] [PATCH v2 3/7] dm: pci: Avoid using pci_bus_to_hose() in the uclass

This function is only available for compatibility with old code. Avoid using it in the uclass.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Tested-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: None

drivers/pci/pci_auto.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 842eafc..c5638e9 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -9,6 +9,7 @@ */

#include <common.h> +#include <dm.h> #include <errno.h> #include <pci.h>

@@ -167,8 +168,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) struct pci_region *pci_prefetch; struct pci_region *pci_io; u16 cmdstat, prefechable_64; - /* The root controller has the region information */ - struct pci_controller *ctlr_hose = pci_bus_to_hose(0); + struct udevice *ctlr = pci_get_controller(dev); + struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);

pci_mem = ctlr_hose->pci_mem; pci_prefetch = ctlr_hose->pci_prefetch; @@ -248,9 +249,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) struct pci_region *pci_mem; struct pci_region *pci_prefetch; struct pci_region *pci_io; - - /* The root controller has the region information */ - struct pci_controller *ctlr_hose = pci_bus_to_hose(0); + struct udevice *ctlr = pci_get_controller(dev); + struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);

pci_mem = ctlr_hose->pci_mem; pci_prefetch = ctlr_hose->pci_prefetch; @@ -311,13 +311,13 @@ int dm_pciauto_config_device(struct udevice *dev) unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev)); unsigned short class; bool enum_only = false; + struct udevice *ctlr = pci_get_controller(dev); + struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); int n;

#ifdef CONFIG_PCI_ENUM_ONLY enum_only = true; #endif - /* The root controller has the region information */ - struct pci_controller *ctlr_hose = pci_bus_to_hose(0);

pci_mem = ctlr_hose->pci_mem; pci_prefetch = ctlr_hose->pci_prefetch;

-- 2.6.0.rc2.230.g3dd15c0

Simon Glass

5:12 a.m.

New subject: [U-Boot] [PATCH v2 4/7] dm: Expand the uclass for Platform Controller Hubs (PCH)

A Platform Controller Hub is an Intel concept - it is like the peripherals on an SoC and is often in a separate chip from the CPU. The chip is typically found on the first PCI bus and integrates multiple devices.

We have a very simple uclass to support PCHs. Add a few operations, such as setting up the devices on the PCH and finding the SPI controller base address. Also move it into drivers/pch/ since we will be adding a few PCH drivers.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Update the commit message and header file comments - Use an enum for the PCH version - Replace SBASE with SPI base - Add a TODO to check if the init() method can be removed later

arch/x86/lib/Makefile | 1 - drivers/Makefile | 1 + drivers/pch/Makefile | 5 ++ {arch/x86/lib => drivers/pch}/pch-uclass.c | 32 +++++++++++++ include/pch.h | 76 ++++++++++++++++++++++++++++++ 5 files changed, 114 insertions(+), 1 deletion(-) create mode 100644 drivers/pch/Makefile rename {arch/x86/lib => drivers/pch}/pch-uclass.c (53%) create mode 100644 include/pch.h

diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index cd5ecb6..43792bc 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -24,7 +24,6 @@ obj-$(CONFIG_I8254_TIMER) += i8254.o ifndef CONFIG_DM_PCI obj-$(CONFIG_PCI) += pci_type1.o endif -obj-y += pch-uclass.o obj-y += pirq_routing.o obj-y += relocate.o obj-y += physmem.o diff --git a/drivers/Makefile b/drivers/Makefile index c9031f2..acc6af9 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -51,6 +51,7 @@ obj-y += hwmon/ obj-y += misc/ obj-y += pcmcia/ obj-y += dfu/ +obj-$(CONFIG_X86) += pch/ obj-y += rtc/ obj-y += sound/ obj-y += timer/ diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile new file mode 100644 index 0000000..d69a99c --- /dev/null +++ b/drivers/pch/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += pch-uclass.o diff --git a/arch/x86/lib/pch-uclass.c b/drivers/pch/pch-uclass.c similarity index 53% rename from arch/x86/lib/pch-uclass.c rename to drivers/pch/pch-uclass.c index 20dfa81..0ba2cd5 100644 --- a/arch/x86/lib/pch-uclass.c +++ b/drivers/pch/pch-uclass.c @@ -7,10 +7,42 @@

#include <common.h> #include <dm.h> +#include <pch.h> #include <dm/root.h>

DECLARE_GLOBAL_DATA_PTR;

+int pch_init(struct udevice *dev) +{ + struct pch_ops *ops = pch_get_ops(dev); + + if (!ops->init) + return -ENOSYS; + + return ops->init(dev); +} + +int pch_get_sbase(struct udevice *dev, ulong *sbasep) +{ + struct pch_ops *ops = pch_get_ops(dev); + + *sbasep = 0; + if (!ops->get_sbase) + return -ENOSYS; + + return ops->get_sbase(dev, sbasep); +} + +enum pch_version pch_get_version(struct udevice *dev) +{ + struct pch_ops *ops = pch_get_ops(dev); + + if (!ops->get_version) + return -ENOSYS; + + return ops->get_version(dev); +} + static int pch_uclass_post_bind(struct udevice *bus) { /* diff --git a/include/pch.h b/include/pch.h new file mode 100644 index 0000000..ef23570 --- /dev/null +++ b/include/pch.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __pch_h +#define __pch_h + +enum pch_version { + PCHV_UNKNOWN, + PCHV_7, + PCHV_9, +}; + +/* Operations for the Platform Controller Hub */ +struct pch_ops { + /** + * init() - set up the PCH devices + * + * This makes sure that all the devices are ready for use. They are + * not actually started, just set up so that they can be probed. + * + * TODO(sjg@chromium.org): See if this method is actually needed once + * the ivybridge refactoring is done. + */ + int (*init)(struct udevice *dev); + + /** + * get_sbase() - get the address of SPI base + * + * @dev: PCH device to check + * @sbasep: Returns address of SPI base if available, else 0 + * @return 0 if OK, -ve on error (e.g. there is no SPI base) + */ + int (*get_sbase)(struct udevice *dev, ulong *sbasep); + + /** + * get_version() - get the PCH version + * + * @return version, or -1 if unknown + */ + enum pch_version (*get_version)(struct udevice *dev); +}; + +#define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops) + +/** + * pch_init() - init a PCH + * + * This makes sure that all the devices are ready for use. They are + * not actually started, just set up so that they can be probed. + * + * @dev: PCH device to init + * @return 0 if OK, -ve on error + */ +int pch_init(struct udevice *dev); + +/** + * pch_get_sbase() - get the address of SPI base + * + * @dev: PCH device to check + * @sbasep: Returns address of SPI base if available, else 0 + * @return 0 if OK, -ve on error (e.g. there is no SPI base) + */ +int pch_get_sbase(struct udevice *dev, ulong *sbasep); + +/** + * pch_get_version() - get the PCH version + * + * @return version, or -ve if unknown/error + */ +enum pch_version pch_get_version(struct udevice *dev); + +#endif

-- 2.6.0.rc2.230.g3dd15c0

Simon Glass

5:12 a.m.

New subject: [U-Boot] [PATCH v2 5/7] dm: x86: Add a driver for Intel PCH7

At some point we may need to distinguish between different types of PCHs, but for existing supported platforms we only need to worry about version 7 and version 9 bridges. Add a driver for the PCH7.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Rename the PCH functions - Update the get_version() handle to use an enum - Add a function to obtain the SPI base address

drivers/pch/Makefile | 1 + drivers/pch/pch7.c | 43 +++++++++++++++++++++++++++++++++++++++++++ include/pch.h | 4 ++++ 3 files changed, 48 insertions(+) create mode 100644 drivers/pch/pch7.c

diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile index d69a99c..33aa727 100644 --- a/drivers/pch/Makefile +++ b/drivers/pch/Makefile @@ -3,3 +3,4 @@ #

obj-y += pch-uclass.o +obj-y += pch7.o diff --git a/drivers/pch/pch7.c b/drivers/pch/pch7.c new file mode 100644 index 0000000..4532223 --- /dev/null +++ b/drivers/pch/pch7.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <pch.h> + +static int pch7_get_sbase(struct udevice *dev, ulong *sbasep) +{ + u32 rcba; + + dm_pci_read_config32(dev, PCH_RCBA, &rcba); + /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */ + rcba = rcba & 0xffffc000; + *sbasep = rcba + 0x3020; + + return 0; +} + +static enum pch_version pch7_get_version(struct udevice *dev) +{ + return PCHV_7; +} + +static const struct pch_ops pch7_ops = { + .get_sbase = pch7_get_sbase, + .get_version = pch7_get_version, +}; + +static const struct udevice_id pch7_ids[] = { + { .compatible = "intel,pch7" }, + { } +}; + +U_BOOT_DRIVER(pch7_drv) = { + .name = "intel-pch7", + .id = UCLASS_PCH, + .of_match = pch7_ids, + .ops = &pch7_ops, +}; diff --git a/include/pch.h b/include/pch.h index ef23570..b3f88bd 100644 --- a/include/pch.h +++ b/include/pch.h @@ -14,6 +14,10 @@ enum pch_version { PCHV_9, };

+enum { + PCH_RCBA = 0xf0, +}; + /* Operations for the Platform Controller Hub */ struct pch_ops { /**

-- 2.6.0.rc2.230.g3dd15c0

Simon Glass

5:12 a.m.

New subject: [U-Boot] [PATCH v2 6/7] dm: x86: Add a driver for Intel PCH9

At some point we may need to distinguish between different types of PCHs, but for existing supported platforms we only need to worry about version 7 and version 9 bridges. Add a driver for the PCH9.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Rename the PCH functions - Update the get_version() handle to use an enum

drivers/pch/Makefile | 1 + drivers/pch/pch9.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) create mode 100644 drivers/pch/pch9.c

diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile index 33aa727..dde9e86 100644 --- a/drivers/pch/Makefile +++ b/drivers/pch/Makefile @@ -4,3 +4,4 @@

obj-y += pch-uclass.o obj-y += pch7.o +obj-y += pch9.o diff --git a/drivers/pch/pch9.c b/drivers/pch/pch9.c new file mode 100644 index 0000000..529cb02 --- /dev/null +++ b/drivers/pch/pch9.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <pch.h> + +#define SBASE_ADDR 0x54 + +static int pch9_get_sbase(struct udevice *dev, ulong *sbasep) +{ + uint32_t sbase_addr; + + dm_pci_read_config32(dev, SBASE_ADDR, &sbase_addr); + *sbasep = sbase_addr & 0xfffffe00; + + return 0; +} + +static enum pch_version pch9_get_version(struct udevice *dev) +{ + return PCHV_9; +} + +static const struct pch_ops pch9_ops = { + .get_sbase = pch9_get_sbase, + .get_version = pch9_get_version, +}; + +static const struct udevice_id pch9_ids[] = { + { .compatible = "intel,pch9" }, + { } +}; + +U_BOOT_DRIVER(pch9_drv) = { + .name = "intel-pch9", + .id = UCLASS_PCH, + .of_match = pch9_ids, + .ops = &pch9_ops, +};

-- 2.6.0.rc2.230.g3dd15c0

Simon Glass

5:12 a.m.

New subject: [U-Boot] [PATCH v2 7/7] dm: x86: spi: Convert ICH SPI driver to driver model PCI API

At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API.

In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need.

While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device.

Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Adjust code for earlier commits - Move the SPI base code into the PCH drivers

arch/x86/cpu/coreboot/pci.c | 3 +- arch/x86/cpu/irq.c | 7 +- arch/x86/cpu/ivybridge/bd82x6x.c | 25 ++++++ arch/x86/dts/bayleybay.dts | 160 +++++++++++++++++++----------------- arch/x86/dts/broadwell_som-6896.dts | 23 ++++-- arch/x86/dts/chromebook_link.dts | 5 +- arch/x86/dts/chromebox_panther.dts | 33 ++++---- arch/x86/dts/crownbay.dts | 150 +++++++++++++++++---------------- arch/x86/dts/galileo.dts | 98 +++++++++++----------- arch/x86/dts/minnowmax.dts | 158 ++++++++++++++++++----------------- arch/x86/dts/qemu-x86_i440fx.dts | 26 +++--- arch/x86/dts/qemu-x86_q35.dts | 38 +++++---- drivers/spi/ich.c | 143 ++++++++------------------------ 13 files changed, 435 insertions(+), 434 deletions(-)

diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c index 41e29a6..7f5087a 100644 --- a/arch/x86/cpu/coreboot/pci.c +++ b/arch/x86/cpu/coreboot/pci.c @@ -14,7 +14,8 @@ #include <pci.h>

static const struct udevice_id generic_pch_ids[] = { - { .compatible = "intel,pch" }, + { .compatible = "intel,pch7" }, + { .compatible = "intel,pch9" }, { } };

diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index 35b29f6..205405b 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -97,6 +97,7 @@ static int create_pirq_routing_table(void) struct irq_routing_table *rt; struct irq_info *slot, *slot_base; int irq_entries = 0; + int parent; int i; int ret;

@@ -106,7 +107,11 @@ static int create_pirq_routing_table(void) return -EINVAL; }

- ret = fdtdec_get_pci_addr(blob, node, FDT_PCI_SPACE_CONFIG, + /* TODO(sjg@chromium.org): Drop this when PIRQ is a driver */ + parent = fdt_parent_offset(blob, node); + if (parent < 0) + return -EINVAL; + ret = fdtdec_get_pci_addr(blob, parent, FDT_PCI_SPACE_CONFIG, "reg", &addr); if (ret) return ret; diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 434dfd6..05a21d4 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -9,6 +9,7 @@ #include <errno.h> #include <fdtdec.h> #include <malloc.h> +#include <pch.h> #include <asm/lapic.h> #include <asm/pci.h> #include <asm/arch/bd82x6x.h> @@ -96,6 +97,7 @@ static int bd82x6x_probe(struct udevice *dev) return 0; }

+/* TODO(sjg@chromium.org): Move this to the PCH init() method */ int bd82x6x_init(void) { const void *blob = gd->fdt_blob; @@ -116,6 +118,28 @@ int bd82x6x_init(void) return 0; }

+static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep) +{ + u32 rcba; + + dm_pci_read_config32(dev, PCH_RCBA, &rcba); + /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */ + rcba = rcba & 0xffffc000; + *sbasep = rcba + 0x3800; + + return 0; +} + +static enum pch_version bd82x6x_pch_get_version(struct udevice *dev) +{ + return PCHV_9; +} + +static const struct pch_ops bd82x6x_pch_ops = { + .get_sbase = bd82x6x_pch_get_sbase, + .get_version = bd82x6x_pch_get_version, +}; + static const struct udevice_id bd82x6x_ids[] = { { .compatible = "intel,bd82x6x" }, { } @@ -126,4 +150,5 @@ U_BOOT_DRIVER(bd82x6x_drv) = { .id = UCLASS_PCH, .of_match = bd82x6x_ids, .probe = bd82x6x_probe, + .ops = &bd82x6x_pch_ops, }; diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index d3380de..87d809b 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -65,23 +65,6 @@ }; };

- spi { - #address-cells = <1>; - #size-cells = <0>; - compatible = "intel,ich-spi"; - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - compatible = "winbond,w25q64dw", "spi-flash"; - memory-map = <0xff800000 0x00800000>; - rw-mrc-cache { - label = "rw-mrc-cache"; - reg = <0x006e0000 0x00010000>; - }; - }; - }; - gpioa { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; @@ -133,66 +116,91 @@ 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 0x01000000 0x0 0x2000 0x2000 0 0xe000>;

- irq-router@1f,0 { + pch@1f,0 { reg = <0x0000f800 0 0 0 0>; - compatible = "intel,irq-router"; - intel,pirq-config = "ibase"; - intel,ibase-offset = <0x50>; - intel,pirq-link = <8 8>; - intel,pirq-mask = <0xdee0>; - intel,pirq-routing = < - /* BayTrail PCI devices */ - PCI_BDF(0, 2, 0) INTA PIRQA - PCI_BDF(0, 3, 0) INTA PIRQA - PCI_BDF(0, 16, 0) INTA PIRQA - PCI_BDF(0, 17, 0) INTA PIRQA - PCI_BDF(0, 18, 0) INTA PIRQA - PCI_BDF(0, 19, 0) INTA PIRQA - PCI_BDF(0, 20, 0) INTA PIRQA - PCI_BDF(0, 21, 0) INTA PIRQA - PCI_BDF(0, 22, 0) INTA PIRQA - PCI_BDF(0, 23, 0) INTA PIRQA - PCI_BDF(0, 24, 0) INTA PIRQA - PCI_BDF(0, 24, 1) INTC PIRQC - PCI_BDF(0, 24, 2) INTD PIRQD - PCI_BDF(0, 24, 3) INTB PIRQB - PCI_BDF(0, 24, 4) INTA PIRQA - PCI_BDF(0, 24, 5) INTC PIRQC - PCI_BDF(0, 24, 6) INTD PIRQD - PCI_BDF(0, 24, 7) INTB PIRQB - PCI_BDF(0, 26, 0) INTA PIRQA - PCI_BDF(0, 27, 0) INTA PIRQA - PCI_BDF(0, 28, 0) INTA PIRQA - PCI_BDF(0, 28, 1) INTB PIRQB - PCI_BDF(0, 28, 2) INTC PIRQC - PCI_BDF(0, 28, 3) INTD PIRQD - PCI_BDF(0, 29, 0) INTA PIRQA - PCI_BDF(0, 30, 0) INTA PIRQA - PCI_BDF(0, 30, 1) INTD PIRQD - PCI_BDF(0, 30, 2) INTB PIRQB - PCI_BDF(0, 30, 3) INTC PIRQC - PCI_BDF(0, 30, 4) INTD PIRQD - PCI_BDF(0, 30, 5) INTB PIRQB - PCI_BDF(0, 31, 3) INTB PIRQB - - /* PCIe root ports downstream interrupts */ - PCI_BDF(1, 0, 0) INTA PIRQA - PCI_BDF(1, 0, 0) INTB PIRQB - PCI_BDF(1, 0, 0) INTC PIRQC - PCI_BDF(1, 0, 0) INTD PIRQD - PCI_BDF(2, 0, 0) INTA PIRQB - PCI_BDF(2, 0, 0) INTB PIRQC - PCI_BDF(2, 0, 0) INTC PIRQD - PCI_BDF(2, 0, 0) INTD PIRQA - PCI_BDF(3, 0, 0) INTA PIRQC - PCI_BDF(3, 0, 0) INTB PIRQD - PCI_BDF(3, 0, 0) INTC PIRQA - PCI_BDF(3, 0, 0) INTD PIRQB - PCI_BDF(4, 0, 0) INTA PIRQD - PCI_BDF(4, 0, 0) INTB PIRQA - PCI_BDF(4, 0, 0) INTC PIRQB - PCI_BDF(4, 0, 0) INTD PIRQC - >; + compatible = "intel,pch7"; + + irq-router { + compatible = "intel,irq-router"; + intel,pirq-config = "ibase"; + intel,ibase-offset = <0x50>; + intel,pirq-link = <8 8>; + intel,pirq-mask = <0xdee0>; + intel,pirq-routing = < + /* BayTrail PCI devices */ + PCI_BDF(0, 2, 0) INTA PIRQA + PCI_BDF(0, 3, 0) INTA PIRQA + PCI_BDF(0, 16, 0) INTA PIRQA + PCI_BDF(0, 17, 0) INTA PIRQA + PCI_BDF(0, 18, 0) INTA PIRQA + PCI_BDF(0, 19, 0) INTA PIRQA + PCI_BDF(0, 20, 0) INTA PIRQA + PCI_BDF(0, 21, 0) INTA PIRQA + PCI_BDF(0, 22, 0) INTA PIRQA + PCI_BDF(0, 23, 0) INTA PIRQA + PCI_BDF(0, 24, 0) INTA PIRQA + PCI_BDF(0, 24, 1) INTC PIRQC + PCI_BDF(0, 24, 2) INTD PIRQD + PCI_BDF(0, 24, 3) INTB PIRQB + PCI_BDF(0, 24, 4) INTA PIRQA + PCI_BDF(0, 24, 5) INTC PIRQC + PCI_BDF(0, 24, 6) INTD PIRQD + PCI_BDF(0, 24, 7) INTB PIRQB + PCI_BDF(0, 26, 0) INTA PIRQA + PCI_BDF(0, 27, 0) INTA PIRQA + PCI_BDF(0, 28, 0) INTA PIRQA + PCI_BDF(0, 28, 1) INTB PIRQB + PCI_BDF(0, 28, 2) INTC PIRQC + PCI_BDF(0, 28, 3) INTD PIRQD + PCI_BDF(0, 29, 0) INTA PIRQA + PCI_BDF(0, 30, 0) INTA PIRQA + PCI_BDF(0, 30, 1) INTD PIRQD + PCI_BDF(0, 30, 2) INTB PIRQB + PCI_BDF(0, 30, 3) INTC PIRQC + PCI_BDF(0, 30, 4) INTD PIRQD + PCI_BDF(0, 30, 5) INTB PIRQB + PCI_BDF(0, 31, 3) INTB PIRQB + + /* + * PCIe root ports downstream + * interrupts + */ + PCI_BDF(1, 0, 0) INTA PIRQA + PCI_BDF(1, 0, 0) INTB PIRQB + PCI_BDF(1, 0, 0) INTC PIRQC + PCI_BDF(1, 0, 0) INTD PIRQD + PCI_BDF(2, 0, 0) INTA PIRQB + PCI_BDF(2, 0, 0) INTB PIRQC + PCI_BDF(2, 0, 0) INTC PIRQD + PCI_BDF(2, 0, 0) INTD PIRQA + PCI_BDF(3, 0, 0) INTA PIRQC + PCI_BDF(3, 0, 0) INTB PIRQD + PCI_BDF(3, 0, 0) INTC PIRQA + PCI_BDF(3, 0, 0) INTD PIRQB + PCI_BDF(4, 0, 0) INTA PIRQD + PCI_BDF(4, 0, 0) INTB PIRQA + PCI_BDF(4, 0, 0) INTC PIRQB + PCI_BDF(4, 0, 0) INTD PIRQC + >; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + compatible = "winbond,w25q64dw", + "spi-flash"; + memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x006e0000 0x00010000>; + }; + }; + }; }; };

diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts index 194f0eb..57a2943 100644 --- a/arch/x86/dts/broadwell_som-6896.dts +++ b/arch/x86/dts/broadwell_som-6896.dts @@ -29,16 +29,21 @@ ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 0x01000000 0x0 0x2000 0x2000 0 0xe000>; - };

- spi { - #address-cells = <1>; - #size-cells = <0>; - compatible = "intel,ich-spi"; - spi-flash@0 { - reg = <0>; - compatible = "winbond,w25q128", "spi-flash"; - memory-map = <0xff000000 0x01000000>; + pch@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,pch9"; + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + reg = <0>; + compatible = "winbond,w25q128", "spi-flash"; + memory-map = <0xff000000 0x01000000>; + }; + }; }; }; + }; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index c4469a9..a5c5dc1 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -186,9 +186,9 @@ intel,pch-backlight = <0x04000000>; };

- pch { + pch@1f,0 { reg = <0x0000f800 0 0 0 0>; - compatible = "intel,bd82x6x", "intel,pch"; + compatible = "intel,bd82x6x", "intel,pch9"; u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; @@ -200,6 +200,7 @@ 1 0 0 0 0 0 0 0>; /* Enable EC SMI source */ intel,alt-gp-smi-enable = <0x0100>; + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts index 4e2b517..bc0c7bb 100644 --- a/arch/x86/dts/chromebox_panther.dts +++ b/arch/x86/dts/chromebox_panther.dts @@ -51,21 +51,26 @@ ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 0x01000000 0x0 0x1000 0x1000 0 0xf000>; - };

- spi { - #address-cells = <1>; - #size-cells = <0>; - compatible = "intel,ich-spi"; - spi-flash@0 { - #size-cells = <1>; - #address-cells = <1>; - reg = <0>; - compatible = "winbond,w25q64", "spi-flash"; - memory-map = <0xff800000 0x00800000>; - rw-mrc-cache { - label = "rw-mrc-cache"; - reg = <0x003e0000 0x00010000>; + pch@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,pch9"; + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + #size-cells = <1>; + #address-cells = <1>; + reg = <0>; + compatible = "winbond,w25q64", + "spi-flash"; + memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x003e0000 0x00010000>; + }; + }; }; }; }; diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index 84231b3..ff739d4 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -72,17 +72,6 @@ stdout-path = "/serial"; };

- spi { - #address-cells = <1>; - #size-cells = <0>; - compatible = "intel,ich-spi"; - spi-flash@0 { - reg = <0>; - compatible = "sst,25vf016b", "spi-flash"; - memory-map = <0xffe00000 0x00200000>; - }; - }; - microcode { update@0 { #include "microcode/m0220661105_cv.dtsi" @@ -105,6 +94,18 @@ u-boot,dm-pre-reloc; reg = <0x0000b800 0x0 0x0 0x0 0x0>;

+ spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + reg = <0>; + compatible = "sst,25vf016b", + "spi-flash"; + memory-map = <0xffe00000 0x00200000>; + }; + }; + topcliff@0,0 { #address-cells = <3>; #size-cells = <2>; @@ -170,68 +171,73 @@ }; };

- irq-router@1f,0 { + pch@1f,0 { reg = <0x0000f800 0 0 0 0>; - compatible = "intel,irq-router"; - intel,pirq-config = "pci"; - intel,pirq-link = <0x60 8>; - intel,pirq-mask = <0xcee0>; - intel,pirq-routing = < - /* TunnelCreek PCI devices */ - PCI_BDF(0, 2, 0) INTA PIRQE - PCI_BDF(0, 3, 0) INTA PIRQF - PCI_BDF(0, 23, 0) INTA PIRQA - PCI_BDF(0, 23, 0) INTB PIRQB - PCI_BDF(0, 23, 0) INTC PIRQC - PCI_BDF(0, 23, 0) INTD PIRQD - PCI_BDF(0, 24, 0) INTA PIRQB - PCI_BDF(0, 24, 0) INTB PIRQC - PCI_BDF(0, 24, 0) INTC PIRQD - PCI_BDF(0, 24, 0) INTD PIRQA - PCI_BDF(0, 25, 0) INTA PIRQC - PCI_BDF(0, 25, 0) INTB PIRQD - PCI_BDF(0, 25, 0) INTC PIRQA - PCI_BDF(0, 25, 0) INTD PIRQB - PCI_BDF(0, 26, 0) INTA PIRQD - PCI_BDF(0, 26, 0) INTB PIRQA - PCI_BDF(0, 26, 0) INTC PIRQB - PCI_BDF(0, 26, 0) INTD PIRQC - PCI_BDF(0, 27, 0) INTA PIRQG - /* - * Topcliff PCI devices - * - * Note on the Crown Bay board, Topcliff chipset - * is connected to TunnelCreek PCIe port 0, so - * its bus number is 1 for its PCIe port and 2 - * for its PCI devices per U-Boot current PCI - * bus enumeration algorithm. - */ - PCI_BDF(1, 0, 0) INTA PIRQA - PCI_BDF(2, 0, 1) INTA PIRQA - PCI_BDF(2, 0, 2) INTA PIRQA - PCI_BDF(2, 2, 0) INTB PIRQD - PCI_BDF(2, 2, 1) INTB PIRQD - PCI_BDF(2, 2, 2) INTB PIRQD - PCI_BDF(2, 2, 3) INTB PIRQD - PCI_BDF(2, 2, 4) INTB PIRQD - PCI_BDF(2, 4, 0) INTC PIRQC - PCI_BDF(2, 4, 1) INTC PIRQC - PCI_BDF(2, 6, 0) INTD PIRQB - PCI_BDF(2, 8, 0) INTA PIRQA - PCI_BDF(2, 8, 1) INTA PIRQA - PCI_BDF(2, 8, 2) INTA PIRQA - PCI_BDF(2, 8, 3) INTA PIRQA - PCI_BDF(2, 10, 0) INTB PIRQD - PCI_BDF(2, 10, 1) INTB PIRQD - PCI_BDF(2, 10, 2) INTB PIRQD - PCI_BDF(2, 10, 3) INTB PIRQD - PCI_BDF(2, 10, 4) INTB PIRQD - PCI_BDF(2, 12, 0) INTC PIRQC - PCI_BDF(2, 12, 1) INTC PIRQC - PCI_BDF(2, 12, 2) INTC PIRQC - PCI_BDF(2, 12, 3) INTC PIRQC - PCI_BDF(2, 12, 4) INTC PIRQC - >; + compatible = "intel,pch7"; + + irq-router { + compatible = "intel,irq-router"; + intel,pirq-config = "pci"; + intel,pirq-link = <0x60 8>; + intel,pirq-mask = <0xcee0>; + intel,pirq-routing = < + /* TunnelCreek PCI devices */ + PCI_BDF(0, 2, 0) INTA PIRQE + PCI_BDF(0, 3, 0) INTA PIRQF + PCI_BDF(0, 23, 0) INTA PIRQA + PCI_BDF(0, 23, 0) INTB PIRQB + PCI_BDF(0, 23, 0) INTC PIRQC + PCI_BDF(0, 23, 0) INTD PIRQD + PCI_BDF(0, 24, 0) INTA PIRQB + PCI_BDF(0, 24, 0) INTB PIRQC + PCI_BDF(0, 24, 0) INTC PIRQD + PCI_BDF(0, 24, 0) INTD PIRQA + PCI_BDF(0, 25, 0) INTA PIRQC + PCI_BDF(0, 25, 0) INTB PIRQD + PCI_BDF(0, 25, 0) INTC PIRQA + PCI_BDF(0, 25, 0) INTD PIRQB + PCI_BDF(0, 26, 0) INTA PIRQD + PCI_BDF(0, 26, 0) INTB PIRQA + PCI_BDF(0, 26, 0) INTC PIRQB + PCI_BDF(0, 26, 0) INTD PIRQC + PCI_BDF(0, 27, 0) INTA PIRQG + /* + * Topcliff PCI devices + * + * Note on the Crown Bay board, Topcliff + * chipset is connected to TunnelCreek + * PCIe port 0, so its bus number is 1 + * for its PCIe port and 2 for its PCI + * devices per U-Boot current PCI bus + * enumeration algorithm. + */ + PCI_BDF(1, 0, 0) INTA PIRQA + PCI_BDF(2, 0, 1) INTA PIRQA + PCI_BDF(2, 0, 2) INTA PIRQA + PCI_BDF(2, 2, 0) INTB PIRQD + PCI_BDF(2, 2, 1) INTB PIRQD + PCI_BDF(2, 2, 2) INTB PIRQD + PCI_BDF(2, 2, 3) INTB PIRQD + PCI_BDF(2, 2, 4) INTB PIRQD + PCI_BDF(2, 4, 0) INTC PIRQC + PCI_BDF(2, 4, 1) INTC PIRQC + PCI_BDF(2, 6, 0) INTD PIRQB + PCI_BDF(2, 8, 0) INTA PIRQA + PCI_BDF(2, 8, 1) INTA PIRQA + PCI_BDF(2, 8, 2) INTA PIRQA + PCI_BDF(2, 8, 3) INTA PIRQA + PCI_BDF(2, 10, 0) INTB PIRQD + PCI_BDF(2, 10, 1) INTB PIRQD + PCI_BDF(2, 10, 2) INTB PIRQD + PCI_BDF(2, 10, 3) INTB PIRQD + PCI_BDF(2, 10, 4) INTB PIRQD + PCI_BDF(2, 12, 0) INTC PIRQC + PCI_BDF(2, 12, 1) INTC PIRQC + PCI_BDF(2, 12, 2) INTC PIRQC + PCI_BDF(2, 12, 3) INTC PIRQC + PCI_BDF(2, 12, 4) INTC PIRQC + >; + }; }; };

diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index 55165e1..4eca325 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -79,37 +79,58 @@ current-speed = <115200>; };

- irq-router@1f,0 { + pch@1f,0 { reg = <0x0000f800 0 0 0 0>; - compatible = "intel,irq-router"; - intel,pirq-config = "pci"; - intel,pirq-link = <0x60 8>; - intel,pirq-mask = <0xdef8>; - intel,pirq-routing = < - PCI_BDF(0, 20, 0) INTA PIRQE - PCI_BDF(0, 20, 1) INTB PIRQF - PCI_BDF(0, 20, 2) INTC PIRQG - PCI_BDF(0, 20, 3) INTD PIRQH - PCI_BDF(0, 20, 4) INTA PIRQE - PCI_BDF(0, 20, 5) INTB PIRQF - PCI_BDF(0, 20, 6) INTC PIRQG - PCI_BDF(0, 20, 7) INTD PIRQH - PCI_BDF(0, 21, 0) INTA PIRQE - PCI_BDF(0, 21, 1) INTB PIRQF - PCI_BDF(0, 21, 2) INTC PIRQG - PCI_BDF(0, 23, 0) INTA PIRQA - PCI_BDF(0, 23, 1) INTB PIRQB - - /* PCIe root ports downstream interrupts */ - PCI_BDF(1, 0, 0) INTA PIRQA - PCI_BDF(1, 0, 0) INTB PIRQB - PCI_BDF(1, 0, 0) INTC PIRQC - PCI_BDF(1, 0, 0) INTD PIRQD - PCI_BDF(2, 0, 0) INTA PIRQB - PCI_BDF(2, 0, 0) INTB PIRQC - PCI_BDF(2, 0, 0) INTC PIRQD - PCI_BDF(2, 0, 0) INTD PIRQA - >; + + irq-router { + compatible = "intel,irq-router"; + intel,pirq-config = "pci"; + intel,pirq-link = <0x60 8>; + intel,pirq-mask = <0xdef8>; + intel,pirq-routing = < + PCI_BDF(0, 20, 0) INTA PIRQE + PCI_BDF(0, 20, 1) INTB PIRQF + PCI_BDF(0, 20, 2) INTC PIRQG + PCI_BDF(0, 20, 3) INTD PIRQH + PCI_BDF(0, 20, 4) INTA PIRQE + PCI_BDF(0, 20, 5) INTB PIRQF + PCI_BDF(0, 20, 6) INTC PIRQG + PCI_BDF(0, 20, 7) INTD PIRQH + PCI_BDF(0, 21, 0) INTA PIRQE + PCI_BDF(0, 21, 1) INTB PIRQF + PCI_BDF(0, 21, 2) INTC PIRQG + PCI_BDF(0, 23, 0) INTA PIRQA + PCI_BDF(0, 23, 1) INTB PIRQB + + /* PCIe root ports downstream interrupts */ + PCI_BDF(1, 0, 0) INTA PIRQA + PCI_BDF(1, 0, 0) INTB PIRQB + PCI_BDF(1, 0, 0) INTC PIRQC + PCI_BDF(1, 0, 0) INTD PIRQD + PCI_BDF(2, 0, 0) INTA PIRQB + PCI_BDF(2, 0, 0) INTB PIRQC + PCI_BDF(2, 0, 0) INTC PIRQD + PCI_BDF(2, 0, 0) INTD PIRQA + >; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + #size-cells = <1>; + #address-cells = <1>; + reg = <0>; + compatible = "winbond,w25q64", + "spi-flash"; + memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x00010000 0x00010000>; + }; + }; + }; }; };

@@ -127,21 +148,4 @@ bank-name = "B"; };

- /* PCIe root ports downstream interrupts */ - PCI_BDF(1, 0, 0) INTA PIRQA - PCI_BDF(1, 0, 0) INTB PIRQB - PCI_BDF(1, 0, 0) INTC PIRQC - PCI_BDF(1, 0, 0) INTD PIRQD - PCI_BDF(2, 0, 0) INTA PIRQB - PCI_BDF(2, 0, 0) INTB PIRQC - PCI_BDF(2, 0, 0) INTC PIRQD - PCI_BDF(2, 0, 0) INTD PIRQA - PCI_BDF(3, 0, 0) INTA PIRQC - PCI_BDF(3, 0, 0) INTB PIRQD - PCI_BDF(3, 0, 0) INTC PIRQA - PCI_BDF(3, 0, 0) INTD PIRQB - PCI_BDF(4, 0, 0) INTA PIRQD - PCI_BDF(4, 0, 0) INTB PIRQA - PCI_BDF(4, 0, 0) INTC PIRQB - PCI_BDF(4, 0, 0) INTD PIRQC - >; + irq-router { + compatible = "intel,irq-router"; + intel,pirq-config = "ibase"; + intel,ibase-offset = <0x50>; + intel,pirq-link = <8 8>; + intel,pirq-mask = <0xdee0>; + intel,pirq-routing = < + /* BayTrail PCI devices */ + PCI_BDF(0, 2, 0) INTA PIRQA + PCI_BDF(0, 3, 0) INTA PIRQA + PCI_BDF(0, 16, 0) INTA PIRQA + PCI_BDF(0, 17, 0) INTA PIRQA + PCI_BDF(0, 18, 0) INTA PIRQA + PCI_BDF(0, 19, 0) INTA PIRQA + PCI_BDF(0, 20, 0) INTA PIRQA + PCI_BDF(0, 21, 0) INTA PIRQA + PCI_BDF(0, 22, 0) INTA PIRQA + PCI_BDF(0, 23, 0) INTA PIRQA + PCI_BDF(0, 24, 0) INTA PIRQA + PCI_BDF(0, 24, 1) INTC PIRQC + PCI_BDF(0, 24, 2) INTD PIRQD + PCI_BDF(0, 24, 3) INTB PIRQB + PCI_BDF(0, 24, 4) INTA PIRQA + PCI_BDF(0, 24, 5) INTC PIRQC + PCI_BDF(0, 24, 6) INTD PIRQD + PCI_BDF(0, 24, 7) INTB PIRQB + PCI_BDF(0, 26, 0) INTA PIRQA + PCI_BDF(0, 27, 0) INTA PIRQA + PCI_BDF(0, 28, 0) INTA PIRQA + PCI_BDF(0, 28, 1) INTB PIRQB + PCI_BDF(0, 28, 2) INTC PIRQC + PCI_BDF(0, 28, 3) INTD PIRQD + PCI_BDF(0, 29, 0) INTA PIRQA + PCI_BDF(0, 30, 0) INTA PIRQA + PCI_BDF(0, 30, 1) INTD PIRQD + PCI_BDF(0, 30, 2) INTB PIRQB + PCI_BDF(0, 30, 3) INTC PIRQC + PCI_BDF(0, 30, 4) INTD PIRQD + PCI_BDF(0, 30, 5) INTB PIRQB + PCI_BDF(0, 31, 3) INTB PIRQB + + /* + * PCIe root ports downstream + * interrupts + */ + PCI_BDF(1, 0, 0) INTA PIRQA + PCI_BDF(1, 0, 0) INTB PIRQB + PCI_BDF(1, 0, 0) INTC PIRQC + PCI_BDF(1, 0, 0) INTD PIRQD + PCI_BDF(2, 0, 0) INTA PIRQB + PCI_BDF(2, 0, 0) INTB PIRQC + PCI_BDF(2, 0, 0) INTC PIRQD + PCI_BDF(2, 0, 0) INTD PIRQA + PCI_BDF(3, 0, 0) INTA PIRQC + PCI_BDF(3, 0, 0) INTB PIRQD + PCI_BDF(3, 0, 0) INTC PIRQA + PCI_BDF(3, 0, 0) INTD PIRQB + PCI_BDF(4, 0, 0) INTA PIRQD + PCI_BDF(4, 0, 0) INTB PIRQA + PCI_BDF(4, 0, 0) INTC PIRQB + PCI_BDF(4, 0, 0) INTD PIRQC + >; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + compatible = "stmicro,n25q064a", + "spi-flash"; + memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x006f0000 0x00010000>; + }; + }; + }; }; };

@@ -269,23 +294,6 @@ }; };

- spi { - #address-cells = <1>; - #size-cells = <0>; - compatible = "intel,ich-spi"; - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - compatible = "stmicro,n25q064a", "spi-flash"; - memory-map = <0xff800000 0x00800000>; - rw-mrc-cache { - label = "rw-mrc-cache"; - reg = <0x006f0000 0x00010000>; - }; - }; - }; - microcode { update@0 { #include "microcode/m0130673322.dtsi" diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts index 8a06229..a16875f 100644 --- a/arch/x86/dts/qemu-x86_i440fx.dts +++ b/arch/x86/dts/qemu-x86_i440fx.dts @@ -58,18 +58,22 @@ 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 0x01000000 0x0 0x2000 0x2000 0 0xe000>;

- irq-router@1,0 { + pch@1,0 { reg = <0x00000800 0 0 0 0>; - compatible = "intel,irq-router"; - intel,pirq-config = "pci"; - intel,pirq-link = <0x60 4>; - intel,pirq-mask = <0x0e40>; - intel,pirq-routing = < - /* PIIX UHCI */ - PCI_BDF(0, 1, 2) INTD PIRQD - /* e1000 NIC */ - PCI_BDF(0, 3, 0) INTA PIRQC - >; + compatible = "intel,pch7"; + + irq-router { + compatible = "intel,irq-router"; + intel,pirq-config = "pci"; + intel,pirq-link = <0x60 4>; + intel,pirq-mask = <0x0e40>; + intel,pirq-routing = < + /* PIIX UHCI */ + PCI_BDF(0, 1, 2) INTD PIRQD + /* e1000 NIC */ + PCI_BDF(0, 3, 0) INTA PIRQC + >; + }; }; };

diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts index 0b685c8..c00a4a8 100644 --- a/arch/x86/dts/qemu-x86_q35.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -69,24 +69,28 @@ 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 0x01000000 0x0 0x2000 0x2000 0 0xe000>;

- irq-router@1f,0 { + pch@1f,0 { reg = <0x0000f800 0 0 0 0>; - compatible = "intel,irq-router"; - intel,pirq-config = "pci"; - intel,pirq-link = <0x60 8>; - intel,pirq-mask = <0x0e40>; - intel,pirq-routing = < - /* e1000 NIC */ - PCI_BDF(0, 2, 0) INTA PIRQG - /* ICH9 UHCI */ - PCI_BDF(0, 29, 0) INTA PIRQA - PCI_BDF(0, 29, 1) INTB PIRQB - PCI_BDF(0, 29, 2) INTC PIRQC - /* ICH9 EHCI */ - PCI_BDF(0, 29, 7) INTD PIRQD - /* ICH9 SATA */ - PCI_BDF(0, 31, 2) INTA PIRQA - >; + compatible = "intel,pch7"; + + irq-router { + compatible = "intel,irq-router"; + intel,pirq-config = "pci"; + intel,pirq-link = <0x60 8>; + intel,pirq-mask = <0x0e40>; + intel,pirq-routing = < + /* e1000 NIC */ + PCI_BDF(0, 2, 0) INTA PIRQG + /* ICH9 UHCI */ + PCI_BDF(0, 29, 0) INTA PIRQA + PCI_BDF(0, 29, 1) INTB PIRQB + PCI_BDF(0, 29, 2) INTC PIRQC + /* ICH9 EHCI */ + PCI_BDF(0, 29, 7) INTD PIRQD + /* ICH9 SATA */ + PCI_BDF(0, 31, 2) INTA PIRQA + >; + }; }; };

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index f85af9c..7f83509 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -10,9 +10,10 @@ #include <dm.h> #include <errno.h> #include <malloc.h> -#include <spi.h> +#include <pch.h> #include <pci.h> #include <pci_ids.h> +#include <spi.h> #include <asm/io.h>

#include "ich.h" @@ -21,9 +22,7 @@ #define SPI_OPCODE_FAST_READ 0x0b

struct ich_spi_platdata { - pci_dev_t dev; /* PCI device number */ - int ich_version; /* Controller version, 7 or 9 */ - bool use_sbase; /* Use SBASE instead of RCB */ + enum pch_version ich_version; /* Controller version, 7 or 9 */ };

struct ich_spi_priv { @@ -116,40 +115,16 @@ static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr) ich_writel(ctlr, ichspi_bbar, ctlr->bbar); }

-/* - * Check if this device ID matches one of supported Intel PCH devices. - * - * Return the ICH version if there is a match, or zero otherwise. - */ -static int get_ich_version(uint16_t device_id) -{ - if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC || - device_id == PCI_DEVICE_ID_INTEL_ITC_LPC || - device_id == PCI_DEVICE_ID_INTEL_QRK_ILB) - return 7; - - if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && - device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || - (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && - device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) || - device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC || - device_id == PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC || - device_id == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LPC) - return 9; - - return 0; -} - /* @return 1 if the SPI flash supports the 33MHz speed */ -static int ich9_can_do_33mhz(pci_dev_t dev) +static int ich9_can_do_33mhz(struct udevice *dev) { u32 fdod, speed;

/* Observe SPI Descriptor Component Section 0 */ - pci_write_config_dword(dev, 0xb0, 0x1000); + dm_pci_write_config32(dev->parent, 0xb0, 0x1000);

/* Extract the Write/Erase SPI Frequency from descriptor */ - pci_read_config_dword(dev, 0xb4, &fdod); + dm_pci_read_config32(dev->parent, 0xb4, &fdod);

/* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */ speed = (fdod >> 21) & 7; @@ -157,59 +132,22 @@ static int ich9_can_do_33mhz(pci_dev_t dev) return speed == 1; }

-static int ich_find_spi_controller(struct ich_spi_platdata *ich) -{ - int last_bus = pci_last_busno(); - int bus; - - if (last_bus == -1) { - debug("No PCI busses?\n"); - return -ENODEV; - } - - for (bus = 0; bus <= last_bus; bus++) { - uint16_t vendor_id, device_id; - uint32_t ids; - pci_dev_t dev; - - dev = PCI_BDF(bus, 31, 0); - pci_read_config_dword(dev, 0, &ids); - vendor_id = ids; - device_id = ids >> 16; - - if (vendor_id == PCI_VENDOR_ID_INTEL) { - ich->dev = dev; - ich->ich_version = get_ich_version(device_id); - if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC) - ich->use_sbase = true; - return ich->ich_version == 0 ? -ENODEV : 0; - } - } - - debug("ICH SPI: No ICH found.\n"); - return -ENODEV; -} - -static int ich_init_controller(struct ich_spi_platdata *plat, +static int ich_init_controller(struct udevice *dev, + struct ich_spi_platdata *plat, struct ich_spi_priv *ctlr) { - uint8_t *rcrb; /* Root Complex Register Block */ - uint32_t rcba; /* Root Complex Base Address */ - uint32_t sbase_addr; - uint8_t *sbase; - - pci_read_config_dword(plat->dev, 0xf0, &rcba); - /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ - rcrb = (uint8_t *)(rcba & 0xffffc000); + ulong sbase_addr; + void *sbase;

/* SBASE is similar */ - pci_read_config_dword(plat->dev, 0x54, &sbase_addr); - sbase = (uint8_t *)(sbase_addr & 0xfffffe00); + pch_get_sbase(dev->parent, &sbase_addr); + sbase = (void *)sbase_addr; + debug("%s: sbase=%p\n", __func__, sbase);

- if (plat->ich_version == 7) { - struct ich7_spi_regs *ich7_spi; + if (plat->ich_version == PCHV_7) { + struct ich7_spi_regs *ich7_spi = sbase;

- ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020); + ich7_spi = (struct ich7_spi_regs *)sbase; ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK; ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); ctlr->menubytes = sizeof(ich7_spi->opmenu); @@ -222,13 +160,9 @@ static int ich_init_controller(struct ich_spi_platdata *plat, ctlr->bbar = offsetof(struct ich7_spi_regs, bbar); ctlr->preop = offsetof(struct ich7_spi_regs, preop); ctlr->base = ich7_spi; - } else if (plat->ich_version == 9) { - struct ich9_spi_regs *ich9_spi; + } else if (plat->ich_version == PCHV_9) { + struct ich9_spi_regs *ich9_spi = sbase;

- if (plat->use_sbase) - ich9_spi = (struct ich9_spi_regs *)sbase; - else - ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800); ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu); ctlr->menubytes = sizeof(ich9_spi->opmenu); @@ -252,9 +186,9 @@ static int ich_init_controller(struct ich_spi_platdata *plat,

/* Work out the maximum speed we can support */ ctlr->max_speed = 20000000; - if (plat->ich_version == 9 && ich9_can_do_33mhz(plat->dev)) + if (plat->ich_version == PCHV_9 && ich9_can_do_33mhz(dev)) ctlr->max_speed = 33000000; - debug("ICH SPI: Version %d detected at %p, speed %ld\n", + debug("ICH SPI: Version ID %d detected at %p, speed %ld\n", plat->ich_version, ctlr->base, ctlr->max_speed);

ich_set_bbar(ctlr, 0); @@ -481,7 +415,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, if (ret < 0) return ret;

- if (plat->ich_version == 7) + if (plat->ich_version == PCHV_7) ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); else ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); @@ -676,30 +610,34 @@ int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit, return 0; }

-static int ich_spi_probe(struct udevice *bus) +static int ich_spi_probe(struct udevice *dev) { - struct ich_spi_platdata *plat = dev_get_platdata(bus); - struct ich_spi_priv *priv = dev_get_priv(bus); + struct ich_spi_platdata *plat = dev_get_platdata(dev); + struct ich_spi_priv *priv = dev_get_priv(dev); uint8_t bios_cntl; + ulong sbase_addr; int ret;

- ret = ich_init_controller(plat, priv); + /* Check the ICH version */ + plat->ich_version = pch_get_version(dev->parent); + + ret = ich_init_controller(dev, plat, priv); if (ret) return ret; /* * Disable the BIOS write protect so write commands are allowed. On * v9, deassert SMM BIOS Write Protect Disable. */ - if (plat->use_sbase) { + if (!pch_get_sbase(dev->parent, &sbase_addr)) { bios_cntl = ich_readb(priv, priv->bcr); bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */ bios_cntl |= 1; /* Write Protect Disable (WPD) */ ich_writeb(priv, bios_cntl, priv->bcr); } else { - pci_read_config_byte(plat->dev, 0xdc, &bios_cntl); - if (plat->ich_version == 9) + dm_pci_read_config8(dev->parent, 0xdc, &bios_cntl); + if (plat->ich_version == PCHV_9) bios_cntl &= ~BIT(5); - pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1); + dm_pci_write_config8(dev->parent, 0xdc, bios_cntl | 0x1); }

priv->cur_speed = priv->max_speed; @@ -707,18 +645,6 @@ static int ich_spi_probe(struct udevice *bus) return 0; }

-static int ich_spi_ofdata_to_platdata(struct udevice *bus) -{ - struct ich_spi_platdata *plat = dev_get_platdata(bus); - int ret; - - ret = ich_find_spi_controller(plat); - if (ret) - return ret; - - return 0; -} - static int ich_spi_set_speed(struct udevice *bus, uint speed) { struct ich_spi_priv *priv = dev_get_priv(bus); @@ -751,7 +677,7 @@ static int ich_spi_child_pre_probe(struct udevice *dev) * ICH 7 SPI controller only supports array read command * and byte program command for SST flash */ - if (plat->ich_version == 7) { + if (plat->ich_version == PCHV_7) { slave->op_mode_rx = SPI_OPM_RX_AS; slave->op_mode_tx = SPI_OPM_TX_BP; } @@ -779,7 +705,6 @@ U_BOOT_DRIVER(ich_spi) = { .id = UCLASS_SPI, .of_match = ich_spi_ids, .ops = &ich_spi_ops, - .ofdata_to_platdata = ich_spi_ofdata_to_platdata, .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata), .priv_auto_alloc_size = sizeof(struct ich_spi_priv), .child_pre_probe = ich_spi_child_pre_probe,

-- 2.6.0.rc2.230.g3dd15c0

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Simon Glass