Signed-off-by: Vikas Manocha vikas.manocha@st.com cc: Christophe KERELLO christophe.kerello@st.com --- Changed in v4: None Changed in v3: None Changed in v2: None

arch/arm/dts/stm32f746.dtsi | 1 + drivers/spi/stm32_qspi.c | 16 +++++++++++++++- 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index b2b0b5f..883f818 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -78,6 +78,7 @@ reg-names = "QuadSPI", "QuadSPI-memory"; interrupts = <92>; spi-max-frequency = <108000000>; + clocks = <&rcc 0 65>; status = "disabled"; }; usart1: serial@40011000 { diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c index 05358eb..f0434a4 100644 --- a/drivers/spi/stm32_qspi.c +++ b/drivers/spi/stm32_qspi.c @@ -17,6 +17,7 @@ #include <errno.h> #include <asm/arch/stm32.h> #include <asm/arch/stm32_defs.h> +#include <clk.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -457,7 +458,20 @@ static int stm32_qspi_probe(struct udevice *bus)

priv->max_hz = plat->max_hz;

- clock_setup(QSPI_CLOCK_CFG); +#ifdef CONFIG_CLK + int ret; + struct clk clk; + ret = clk_get_by_index(bus, 0, &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + + if (ret) { + dev_err(bus, "failed to enable clock\n"); + return ret; + } +#endif

setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);

Signed-off-by: Vikas Manocha vikas.manocha@st.com cc: Christophe KERELLO christophe.kerello@st.com --- Changed in v4: None Changed in v3: None Changed in v2: None

board/st/stm32f746-disco/stm32f746-disco.c | 113 +-------------------------- configs/stm32f746-disco_defconfig | 2 + drivers/ram/Kconfig | 8 ++ drivers/ram/Makefile | 1 + drivers/ram/stm32_sdram.c | 119 +++++++++++++++++++++++++++++ 5 files changed, 131 insertions(+), 112 deletions(-) create mode 100644 drivers/ram/stm32_sdram.c

diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index fdad8d1..1569358 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -10,7 +10,6 @@ #include <asm/armv7m.h> #include <asm/arch/stm32.h> #include <asm/arch/gpio.h> -#include <asm/arch/fmc.h> #include <dm/platdata.h> #include <dm/platform_data/serial_stm32x7.h> #include <asm/arch/stm32_periph.h> @@ -106,57 +105,8 @@ out: return rv; }

-static inline u32 _ns2clk(u32 ns, u32 freq) -{ - u32 tmp = freq/1000000; - return (tmp * ns) / 1000; -} - -#define NS2CLK(ns) (_ns2clk(ns, freq)) - -/* - * Following are timings for IS42S16400J, from corresponding datasheet - */ -#define SDRAM_CAS 3 /* 3 cycles */ -#define SDRAM_NB 1 /* Number of banks */ -#define SDRAM_MWID 1 /* 16 bit memory */ - -#define SDRAM_NR 0x1 /* 12-bit row */ -#define SDRAM_NC 0x0 /* 8-bit col */ -#define SDRAM_RBURST 0x1 /* Single read requests always as bursts */ -#define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */ - -#define SDRAM_TRRD NS2CLK(12) -#define SDRAM_TRCD NS2CLK(18) -#define SDRAM_TRP NS2CLK(18) -#define SDRAM_TRAS NS2CLK(42) -#define SDRAM_TRC NS2CLK(60) -#define SDRAM_TRFC NS2CLK(60) -#define SDRAM_TCDL (1 - 1) -#define SDRAM_TRDL NS2CLK(12) -#define SDRAM_TBDL (1 - 1) -#define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20) -#define SDRAM_TCCD (1 - 1) - -#define SDRAM_TXSR SDRAM_TRFC /* Row cycle time after precharge */ -#define SDRAM_TMRD 1 /* Page 10, Mode Register Set */ - - -/* Last data in to row precharge, need also comply ineq on page 1648 */ -#define SDRAM_TWR max(\ - (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \ - (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\ -) - - -#define SDRAM_MODE_BL_SHIFT 0 -#define SDRAM_MODE_CAS_SHIFT 4 -#define SDRAM_MODE_BL 0 -#define SDRAM_MODE_CAS SDRAM_CAS - int dram_init(void) { - u32 freq; int rv;

rv = fmc_setup_gpio(); @@ -164,67 +114,7 @@ int dram_init(void) return rv;

clock_setup(FMC_CLOCK_CFG); - - /* - * Get frequency for NS2CLK calculation. - */ - freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV; - - writel( - CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT - | SDRAM_CAS << FMC_SDCR_CAS_SHIFT - | SDRAM_NB << FMC_SDCR_NB_SHIFT - | SDRAM_MWID << FMC_SDCR_MWID_SHIFT - | SDRAM_NR << FMC_SDCR_NR_SHIFT - | SDRAM_NC << FMC_SDCR_NC_SHIFT - | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT - | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, - &STM32_SDRAM_FMC->sdcr1); - - writel( - SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT - | SDRAM_TRP << FMC_SDTR_TRP_SHIFT - | SDRAM_TWR << FMC_SDTR_TWR_SHIFT - | SDRAM_TRC << FMC_SDTR_TRC_SHIFT - | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT - | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT - | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT, - &STM32_SDRAM_FMC->sdtr1); - - writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, - &STM32_SDRAM_FMC->sdcmr); - - udelay(200); /* 200 us delay, page 10, "Power-Up" */ - FMC_BUSY_WAIT(); - - writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE, - &STM32_SDRAM_FMC->sdcmr); - - udelay(100); - FMC_BUSY_WAIT(); - - writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH - | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr); - - udelay(100); - FMC_BUSY_WAIT(); - - writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT - | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT) - << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, - &STM32_SDRAM_FMC->sdcmr); - - udelay(100); - - FMC_BUSY_WAIT(); - - writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL, - &STM32_SDRAM_FMC->sdcmr); - - FMC_BUSY_WAIT(); - - /* Refresh timer */ - writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr); + stm32_sdram_init();

/* * Fill in global info with description of SRAM configuration @@ -233,7 +123,6 @@ int dram_init(void) gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;

gd->ram_size = CONFIG_SYS_RAM_SIZE; - return rv; }

diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index b5457c6..046041a 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -43,3 +43,5 @@ CONFIG_CLK=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_FULL is not set CONFIG_PINCTRL_STM32=y +CONFIG_RAM=y +CONFIG_STM32_SDRAM=y diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index ff09f22..61afd7a 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -16,3 +16,11 @@ config SPL_RAM If this is acceptable and you have a need to use RAM drivers in SPL, enable this option. It might provide a cleaner interface to setting up RAM (e.g. SDRAM / DDR) within SPL. + +config STM32_SDRAM + bool "Enable STM32 SDRAM support" + depends on RAM + help + STM32F7 family devices support flexible memory controller(FMC) to + support external memories like sdram, psram & nand. + This driver is for the sdram memory interface with the FMC. diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 0e10249..ecb036d 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -6,3 +6,4 @@ # obj-$(CONFIG_RAM) += ram-uclass.o obj-$(CONFIG_SANDBOX) += sandbox_ram.o +obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c new file mode 100644 index 0000000..13f8964 --- /dev/null +++ b/drivers/ram/stm32_sdram.c @@ -0,0 +1,119 @@ +/* + * (C) Copyright 2017 + * Vikas Manocha, vikas.manocha@st.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/fmc.h> +#include <asm/arch/stm32.h> + +static inline u32 _ns2clk(u32 ns, u32 freq) +{ + u32 tmp = freq/1000000; + return (tmp * ns) / 1000; +} + +#define NS2CLK(ns) (_ns2clk(ns, freq)) + +/* + * Following are timings for IS42S16400J, from corresponding datasheet + */ +#define SDRAM_CAS 3 /* 3 cycles */ +#define SDRAM_NB 1 /* Number of banks */ +#define SDRAM_MWID 1 /* 16 bit memory */ + +#define SDRAM_NR 0x1 /* 12-bit row */ +#define SDRAM_NC 0x0 /* 8-bit col */ +#define SDRAM_RBURST 0x1 /* Single read requests always as bursts */ +#define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */ + +#define SDRAM_TRRD NS2CLK(12) +#define SDRAM_TRCD NS2CLK(18) +#define SDRAM_TRP NS2CLK(18) +#define SDRAM_TRAS NS2CLK(42) +#define SDRAM_TRC NS2CLK(60) +#define SDRAM_TRFC NS2CLK(60) +#define SDRAM_TCDL (1 - 1) +#define SDRAM_TRDL NS2CLK(12) +#define SDRAM_TBDL (1 - 1) +#define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20) +#define SDRAM_TCCD (1 - 1) + +#define SDRAM_TXSR SDRAM_TRFC /* Row cycle time after precharge */ +#define SDRAM_TMRD 1 /* Page 10, Mode Register Set */ + + +/* Last data in to row precharge, need also comply ineq on page 1648 */ +#define SDRAM_TWR max(\ + (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \ + (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\ + ) + + +#define SDRAM_MODE_BL_SHIFT 0 +#define SDRAM_MODE_CAS_SHIFT 4 +#define SDRAM_MODE_BL 0 +#define SDRAM_MODE_CAS SDRAM_CAS + +int stm32_sdram_init(void) +{ + u32 freq; + + /* + * Get frequency for NS2CLK calculation. + */ + freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV; + + writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT + | SDRAM_CAS << FMC_SDCR_CAS_SHIFT + | SDRAM_NB << FMC_SDCR_NB_SHIFT + | SDRAM_MWID << FMC_SDCR_MWID_SHIFT + | SDRAM_NR << FMC_SDCR_NR_SHIFT + | SDRAM_NC << FMC_SDCR_NC_SHIFT + | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT + | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, + &STM32_SDRAM_FMC->sdcr1); + + writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT + | SDRAM_TRP << FMC_SDTR_TRP_SHIFT + | SDRAM_TWR << FMC_SDTR_TWR_SHIFT + | SDRAM_TRC << FMC_SDTR_TRC_SHIFT + | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT + | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT + | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT, + &STM32_SDRAM_FMC->sdtr1); + + writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, + &STM32_SDRAM_FMC->sdcmr); + udelay(200); /* 200 us delay, page 10, "Power-Up" */ + FMC_BUSY_WAIT(); + + writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE, + &STM32_SDRAM_FMC->sdcmr); + udelay(100); + FMC_BUSY_WAIT(); + + writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH + | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr); + udelay(100); + FMC_BUSY_WAIT(); + + writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT + | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT) + << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, + &STM32_SDRAM_FMC->sdcmr); + udelay(100); + FMC_BUSY_WAIT(); + + writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL, + &STM32_SDRAM_FMC->sdcmr); + FMC_BUSY_WAIT(); + + /* Refresh timer */ + writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr); + + return 0; +}

Signed-off-by: Vikas Manocha vikas.manocha@st.com cc: Christophe KERELLO christophe.kerello@st.com --- Changed in v4: None Changed in v3: None Changed in v2: None

drivers/ram/stm32_sdram.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)

diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 13f8964..67be61f 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -6,6 +6,8 @@ */

#include <common.h> +#include <dm.h> +#include <ram.h> #include <asm/io.h> #include <asm/arch/fmc.h> #include <asm/arch/stm32.h> @@ -117,3 +119,32 @@ int stm32_sdram_init(void)

return 0; } + +static int stm32_fmc_probe(struct udevice *dev) +{ + stm32_sdram_init(); + return 0; +} + +static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info) +{ + info->size = CONFIG_SYS_RAM_SIZE; + return 0; +} + +static struct ram_ops stm32_fmc_ops = { + .get_info = stm32_fmc_get_info, +}; + +static const struct udevice_id stm32_fmc_ids[] = { + { .compatible = "st,stm32-fmc" }, + { } +}; + +U_BOOT_DRIVER(stm32_fmc) = { + .name = "stm32_fmc", + .id = UCLASS_RAM, + .of_match = stm32_fmc_ids, + .ops = &stm32_fmc_ops, + .probe = stm32_fmc_probe, +};

Also added DT binding doc for stm32 fmc(flexible memory controller).

Signed-off-by: Vikas Manocha vikas.manocha@st.com cc: Christophe KERELLO christophe.kerello@st.com --- Changed in v4: None Changed in v3: None Changed in v2: None

arch/arm/dts/stm32f746-disco.dts | 7 ++++ arch/arm/dts/stm32f746.dtsi | 56 +++++++++++++++++++++++++++ doc/device-tree-bindings/ram/st,stm32-fmc.txt | 51 ++++++++++++++++++++++++ 3 files changed, 114 insertions(+) create mode 100644 doc/device-tree-bindings/ram/st,stm32-fmc.txt

diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index 07e0ca7..5846b0d 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -1,5 +1,6 @@ /* * Copyright 2016 - Michael Kurz michi.kurz@gmail.com + * Copyright 2016 - Vikas MANOCHA vikas.manocha@st.com * * Based on: * stm32f469-disco.dts from Linux @@ -76,6 +77,12 @@ status = "okay"; };

+&fmc { + pinctrl-0 = <&fmc_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &mac { status = "okay"; pinctrl-0 = <&ethernet_mii>; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index 883f818..3707550 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -1,5 +1,6 @@ /* * Copyright 2016 - Michael Kurz michi.kurz@gmail.com + * Copyright 2016 - Vikas MANOCHA vikas.manocha@st.com * * Based on: * stm32f429.dtsi from Linux @@ -70,6 +71,12 @@ status = "disabled"; };

+ fmc: fmc@A0000000 { + compatible = "st,stm32-fmc"; + reg = <0xA0000000 0x1000>; + u-boot,dm-pre-reloc; + }; + qspi: quadspi@A0001000 { compatible = "st,stm32-qspi"; #address-cells = <1>; @@ -143,6 +150,55 @@ slew-rate = <2>; }; }; + + fmc_pins: fmc@0 { + pins { + pinmux = <STM32F746_PD10_FUNC_FMC_D15>, + <STM32F746_PD9_FUNC_FMC_D14>, + <STM32F746_PD8_FUNC_FMC_D13>, + <STM32F746_PE15_FUNC_FMC_D12>, + <STM32F746_PE14_FUNC_FMC_D11>, + <STM32F746_PE13_FUNC_FMC_D10>, + <STM32F746_PE12_FUNC_FMC_D9>, + <STM32F746_PE11_FUNC_FMC_D8>, + <STM32F746_PE10_FUNC_FMC_D7>, + <STM32F746_PE9_FUNC_FMC_D6>, + <STM32F746_PE8_FUNC_FMC_D5>, + <STM32F746_PE7_FUNC_FMC_D4>, + <STM32F746_PD1_FUNC_FMC_D3>, + <STM32F746_PD0_FUNC_FMC_D2>, + <STM32F746_PD15_FUNC_FMC_D1>, + <STM32F746_PD14_FUNC_FMC_D0>, + + <STM32F746_PE1_FUNC_FMC_NBL1>, + <STM32F746_PE0_FUNC_FMC_NBL0>, + + <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, + <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, + + <STM32F746_PG1_FUNC_FMC_A11>, + <STM32F746_PG0_FUNC_FMC_A10>, + <STM32F746_PF15_FUNC_FMC_A9>, + <STM32F746_PF14_FUNC_FMC_A8>, + <STM32F746_PF13_FUNC_FMC_A7>, + <STM32F746_PF12_FUNC_FMC_A6>, + <STM32F746_PF5_FUNC_FMC_A5>, + <STM32F746_PF4_FUNC_FMC_A4>, + <STM32F746_PF3_FUNC_FMC_A3>, + <STM32F746_PF2_FUNC_FMC_A2>, + <STM32F746_PF1_FUNC_FMC_A1>, + <STM32F746_PF0_FUNC_FMC_A0>, + + <STM32F746_PH3_FUNC_FMC_SDNE0>, + <STM32F746_PH5_FUNC_FMC_SDNWE>, + <STM32F746_PF11_FUNC_FMC_SDNRAS>, + <STM32F746_PG15_FUNC_FMC_SDNCAS>, + <STM32F746_PC3_FUNC_FMC_SDCKE0>, + <STM32F746_PG8_FUNC_FMC_SDCLK>; + slew-rate = <2>; + }; + }; + }; }; }; diff --git a/doc/device-tree-bindings/ram/st,stm32-fmc.txt b/doc/device-tree-bindings/ram/st,stm32-fmc.txt new file mode 100644 index 0000000..3d1392c --- /dev/null +++ b/doc/device-tree-bindings/ram/st,stm32-fmc.txt @@ -0,0 +1,51 @@ +ST, stm32 flexible memory controller Drive +Required properties: +- compatible : "st,stm32-fmc" +- reg : fmc controller base address +- clocks : fmc controller clock +u-boot,dm-pre-reloc: flag to initialize memory before relocation. + +on-board sdram memory attributes: +- st,sdram-control : parameters for sdram configuration, in this order: + number of columns + number of rows + memory width + number of intenal banks in memory + cas latency + read burst enable or disable + read pipe delay + +- st,sdram-timing: timings for sdram, in this order: + tmrd + txsr + tras + trc + trp + trcd + +There is device tree include file at : +include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing +parameters as MACROS. + +Example: + fmc: fmc@A0000000 { + compatible = "st,stm32-fmc"; + reg = <0xA0000000 0x1000>; + clocks = <&rcc 0 64>; + u-boot,dm-pre-reloc; + }; + + &fmc { + pinctrl-0 = <&fmc_pins>; + pinctrl-names = "default"; + status = "okay"; + + mr-nbanks = <1>; + /* sdram memory configuration from sdram datasheet */ + bank1: bank@0 { + st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2 + CAS_3 RD_BURST_EN RD_PIPE_DL_0>; + st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18 + TRCD_18>; + }; +}

As driver model takes care of pin control configuraion, this patch also removes the sdram/fmc pin configuration.

Signed-off-by: Vikas Manocha vikas.manocha@st.com cc: Christophe KERELLO christophe.kerello@st.com --- Changed in v4: None Changed in v3: None Changed in v2: None

board/st/stm32f746-disco/stm32f746-disco.c | 89 +++++++----------------------- 1 file changed, 19 insertions(+), 70 deletions(-)

diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 1569358..e1113a6 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -6,6 +6,8 @@ */

#include <common.h> +#include <dm.h> +#include <ram.h> #include <asm/io.h> #include <asm/armv7m.h> #include <asm/arch/stm32.h> @@ -26,66 +28,8 @@ const struct stm32_gpio_ctl gpio_ctl_gpout = { .af = STM32_GPIO_AF0 };

-const struct stm32_gpio_ctl gpio_ctl_fmc = { - .mode = STM32_GPIO_MODE_AF, - .otype = STM32_GPIO_OTYPE_PP, - .speed = STM32_GPIO_SPEED_100M, - .pupd = STM32_GPIO_PUPD_NO, - .af = STM32_GPIO_AF12 -}; - -static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = { - /* Chip is LQFP144, see DM00077036.pdf for details */ - {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */ - {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */ - {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */ - {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */ - {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */ - {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */ - {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */ - - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */ - - {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */ - {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */ - - {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */ - {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */ - - {STM32_GPIO_PORT_H, STM32_GPIO_PIN_3}, /* 136, SDRAM_NE */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */ - {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */ - {STM32_GPIO_PORT_H, STM32_GPIO_PIN_5}, /* 26, SDRAM_NWE */ - {STM32_GPIO_PORT_C, STM32_GPIO_PIN_3}, /* 135, SDRAM_CKE */ - - {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */ -}; - static int fmc_setup_gpio(void) { - int rv = 0; - int i; - clock_setup(GPIO_B_CLOCK_CFG); clock_setup(GPIO_C_CLOCK_CFG); clock_setup(GPIO_D_CLOCK_CFG); @@ -94,19 +38,13 @@ static int fmc_setup_gpio(void) clock_setup(GPIO_G_CLOCK_CFG); clock_setup(GPIO_H_CLOCK_CFG);

- for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) { - rv = stm32_gpio_config(&ext_ram_fmc_gpio[i], - &gpio_ctl_fmc); - if (rv) - goto out; - } - -out: - return rv; + return 0; }

int dram_init(void) { + struct udevice *dev; + struct ram_info ram; int rv;

rv = fmc_setup_gpio(); @@ -114,15 +52,26 @@ int dram_init(void) return rv;

clock_setup(FMC_CLOCK_CFG); - stm32_sdram_init(); + + rv = uclass_get_device(UCLASS_RAM, 0, &dev); + if (rv) { + debug("DRAM init failed: %d\n", rv); + return rv; + } + rv = ram_get_info(dev, &ram); + if (rv) { + debug("Cannot get DRAM size: %d\n", rv); + return rv; + } + debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size); + gd->ram_size = ram.size;

/* * Fill in global info with description of SRAM configuration */ gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE; - gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE; + gd->bd->bi_dram[0].size = ram.size;

- gd->ram_size = CONFIG_SYS_RAM_SIZE; return rv; }

This patch also removes the sdram/fmc clock enable from board specific code.

Signed-off-by: Vikas Manocha vikas.manocha@st.com cc: Christophe KERELLO christophe.kerello@st.com --- Changed in v4: None Changed in v3: None Changed in v2: None

arch/arm/dts/stm32f746.dtsi | 1 + board/st/stm32f746-disco/stm32f746-disco.c | 2 -- drivers/ram/stm32_sdram.c | 15 +++++++++++++++ 3 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index 3707550..e9fd6f4 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -74,6 +74,7 @@ fmc: fmc@A0000000 { compatible = "st,stm32-fmc"; reg = <0xA0000000 0x1000>; + clocks = <&rcc 0 64>; u-boot,dm-pre-reloc; };

diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index e1113a6..370db15 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -51,8 +51,6 @@ int dram_init(void) if (rv) return rv;

- clock_setup(FMC_CLOCK_CFG); - rv = uclass_get_device(UCLASS_RAM, 0, &dev); if (rv) { debug("DRAM init failed: %d\n", rv); diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 67be61f..67d8855 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -6,6 +6,7 @@ */

#include <common.h> +#include <clk.h> #include <dm.h> #include <ram.h> #include <asm/io.h> @@ -122,6 +123,20 @@ int stm32_sdram_init(void)

static int stm32_fmc_probe(struct udevice *dev) { +#ifdef CONFIG_CLK + int ret; + struct clk clk; + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } +#endif stm32_sdram_init(); return 0; }

Signed-off-by: Vikas Manocha vikas.manocha@st.com cc: Christophe KERELLO christophe.kerello@st.com --- Changed in v4: None Changed in v3: None Changed in v2: None

arch/arm/dts/stm32f746-disco.dts | 10 +++ drivers/ram/stm32_sdram.c | 144 +++++++++++++++++++------------ include/dt-bindings/memory/stm32-sdram.h | 34 ++++++++ 3 files changed, 135 insertions(+), 53 deletions(-) create mode 100644 include/dt-bindings/memory/stm32-sdram.h

diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index 5846b0d..f098d2e 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -47,6 +47,7 @@

/dts-v1/; #include "stm32f746.dtsi" +#include <dt-bindings/memory/stm32-sdram.h>

/ { model = "STMicroelectronics STM32F746-DISCO board"; @@ -81,6 +82,15 @@ pinctrl-0 = <&fmc_pins>; pinctrl-names = "default"; status = "okay"; + + mr-nbanks = <1>; + /* sdram memory configuration from sdram datasheet IS42S16400J */ + bank1: bank@0 { + st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2 + CAS_3 RD_BURST_EN RD_PIPE_DL_0>; + st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18 + TRCD_18>; + }; };

&mac { diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 67d8855..eb1ab94 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -13,6 +13,31 @@ #include <asm/arch/fmc.h> #include <asm/arch/stm32.h>

+DECLARE_GLOBAL_DATA_PTR; + +struct stm32_sdram_control { + u8 no_columns; + u8 no_rows; + u8 memory_width; + u8 no_banks; + u8 cas_latency; + u8 rd_burst; + u8 rd_pipe_delay; +}; + +struct stm32_sdram_timing { + u8 tmrd; + u8 txsr; + u8 tras; + u8 trc; + u8 trp; + u8 trcd; +}; +struct stm32_sdram_params { + u8 no_sdram_banks; + struct stm32_sdram_control sdram_control; + struct stm32_sdram_timing sdram_timing; +}; static inline u32 _ns2clk(u32 ns, u32 freq) { u32 tmp = freq/1000000; @@ -21,73 +46,53 @@ static inline u32 _ns2clk(u32 ns, u32 freq)

#define NS2CLK(ns) (_ns2clk(ns, freq))

-/* - * Following are timings for IS42S16400J, from corresponding datasheet - */ -#define SDRAM_CAS 3 /* 3 cycles */ -#define SDRAM_NB 1 /* Number of banks */ -#define SDRAM_MWID 1 /* 16 bit memory */ - -#define SDRAM_NR 0x1 /* 12-bit row */ -#define SDRAM_NC 0x0 /* 8-bit col */ -#define SDRAM_RBURST 0x1 /* Single read requests always as bursts */ -#define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */ - -#define SDRAM_TRRD NS2CLK(12) -#define SDRAM_TRCD NS2CLK(18) -#define SDRAM_TRP NS2CLK(18) -#define SDRAM_TRAS NS2CLK(42) -#define SDRAM_TRC NS2CLK(60) -#define SDRAM_TRFC NS2CLK(60) -#define SDRAM_TCDL (1 - 1) -#define SDRAM_TRDL NS2CLK(12) -#define SDRAM_TBDL (1 - 1) #define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20) -#define SDRAM_TCCD (1 - 1) - -#define SDRAM_TXSR SDRAM_TRFC /* Row cycle time after precharge */ -#define SDRAM_TMRD 1 /* Page 10, Mode Register Set */ - - -/* Last data in to row precharge, need also comply ineq on page 1648 */ -#define SDRAM_TWR max(\ - (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \ - (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\ - ) -

#define SDRAM_MODE_BL_SHIFT 0 #define SDRAM_MODE_CAS_SHIFT 4 #define SDRAM_MODE_BL 0 -#define SDRAM_MODE_CAS SDRAM_CAS +#define SDRAM_MODE_CAS 3 + +#define SDRAM_TRDL 12

-int stm32_sdram_init(void) +int stm32_sdram_init(struct udevice *dev) { u32 freq; + u32 sdram_twr; + struct stm32_sdram_params *params = dev_get_platdata(dev);

/* * Get frequency for NS2CLK calculation. */ freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV; + debug("%s, sdram freq = %d\n", __func__, freq); + + /* Last data in to row precharge, need also comply ineq on page 1648 */ + sdram_twr = max( + max(SDRAM_TRDL, params->sdram_timing.tras + - params->sdram_timing.trcd), + params->sdram_timing.trc - params->sdram_timing.trcd + - params->sdram_timing.trp + );

writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT - | SDRAM_CAS << FMC_SDCR_CAS_SHIFT - | SDRAM_NB << FMC_SDCR_NB_SHIFT - | SDRAM_MWID << FMC_SDCR_MWID_SHIFT - | SDRAM_NR << FMC_SDCR_NR_SHIFT - | SDRAM_NC << FMC_SDCR_NC_SHIFT - | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT - | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, - &STM32_SDRAM_FMC->sdcr1); - - writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT - | SDRAM_TRP << FMC_SDTR_TRP_SHIFT - | SDRAM_TWR << FMC_SDTR_TWR_SHIFT - | SDRAM_TRC << FMC_SDTR_TRC_SHIFT - | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT - | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT - | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT, - &STM32_SDRAM_FMC->sdtr1); + | params->sdram_control.cas_latency << FMC_SDCR_CAS_SHIFT + | params->sdram_control.no_banks << FMC_SDCR_NB_SHIFT + | params->sdram_control.memory_width << FMC_SDCR_MWID_SHIFT + | params->sdram_control.no_rows << FMC_SDCR_NR_SHIFT + | params->sdram_control.no_columns << FMC_SDCR_NC_SHIFT + | params->sdram_control.rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT + | params->sdram_control.rd_burst << FMC_SDCR_RBURST_SHIFT, + &STM32_SDRAM_FMC->sdcr1); + + writel(NS2CLK(params->sdram_timing.trcd) << FMC_SDTR_TRCD_SHIFT + | NS2CLK(params->sdram_timing.trp) << FMC_SDTR_TRP_SHIFT + | NS2CLK(sdram_twr) << FMC_SDTR_TWR_SHIFT + | NS2CLK(params->sdram_timing.trc) << FMC_SDTR_TRC_SHIFT + | NS2CLK(params->sdram_timing.tras) << FMC_SDTR_TRAS_SHIFT + | NS2CLK(params->sdram_timing.txsr) << FMC_SDTR_TXSR_SHIFT + | NS2CLK(params->sdram_timing.tmrd) << FMC_SDTR_TMRD_SHIFT, + &STM32_SDRAM_FMC->sdtr1);

writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, &STM32_SDRAM_FMC->sdcmr); @@ -121,11 +126,39 @@ int stm32_sdram_init(void) return 0; }

+static int stm32_fmc_ofdata_to_platdata(struct udevice *dev) +{ + int ret; + int node = dev->of_offset; + const void *blob = gd->fdt_blob; + struct stm32_sdram_params *params = dev_get_platdata(dev); + + params->no_sdram_banks = fdtdec_get_uint(blob, node, "mr-nbanks", 1); + debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks); + + fdt_for_each_subnode(node, blob, node) { + ret = fdtdec_get_byte_array(blob, node, "st,sdram-control", + (u8 *)&params->sdram_control, + sizeof(params->sdram_control)); + if (ret) + return ret; + + ret = fdtdec_get_byte_array(blob, node, "st,sdram-timing", + (u8 *)&params->sdram_timing, + sizeof(params->sdram_timing)); + if (ret) + return ret; + } + + return 0; +} + static int stm32_fmc_probe(struct udevice *dev) { #ifdef CONFIG_CLK int ret; struct clk clk; + ret = clk_get_by_index(dev, 0, &clk); if (ret < 0) return ret; @@ -137,7 +170,10 @@ static int stm32_fmc_probe(struct udevice *dev) return ret; } #endif - stm32_sdram_init(); + ret = stm32_sdram_init(dev); + if (ret) + return ret; + return 0; }

@@ -161,5 +197,7 @@ U_BOOT_DRIVER(stm32_fmc) = { .id = UCLASS_RAM, .of_match = stm32_fmc_ids, .ops = &stm32_fmc_ops, + .ofdata_to_platdata = stm32_fmc_ofdata_to_platdata, .probe = stm32_fmc_probe, + .platdata_auto_alloc_size = sizeof(struct stm32_sdram_params), }; diff --git a/include/dt-bindings/memory/stm32-sdram.h b/include/dt-bindings/memory/stm32-sdram.h new file mode 100644 index 0000000..4cd6c2b --- /dev/null +++ b/include/dt-bindings/memory/stm32-sdram.h @@ -0,0 +1,34 @@ +#ifndef DT_BINDINGS_STM32_SDRAM_H +#define DT_BINDINGS_STM32_SDRAM_H + +#define NO_COL_8 0x0 +#define NO_COL_9 0x1 +#define NO_COL_10 0x2 +#define NO_COL_11 0x3 + +#define NO_ROW_11 0x0 +#define NO_ROW_12 0x1 +#define NO_ROW_13 0x2 + +#define MWIDTH_8 0x0 +#define MWIDTH_16 0x1 +#define MWIDTH_32 0x2 +#define BANKS_2 0x0 +#define BANKS_4 0x1 +#define CAS_1 0x1 +#define CAS_2 0x2 +#define CAS_3 0x3 +#define RD_BURST_EN 0x1 +#define RD_BURST_DIS 0x0 +#define RD_PIPE_DL_0 0x0 +#define RD_PIPE_DL_1 0x1 +#define RD_PIPE_DL_2 0x2 + +#define TMRD_1 0x1 +#define TXSR_60 60 +#define TRAS_42 42 +#define TRC_60 60 +#define TRP_18 18 +#define TRCD_18 18 + +#endif

This patch adds gpio driver supporting driver model for stm32f7 gpio.

Signed-off-by: Vikas Manocha vikas.manocha@st.com Reviewed-by: Simon Glass sjg@chromium.org cc: Christophe KERELLO christophe.kerello@st.com ---

Changed in v4: - rebased to master.

Changed in v3: - made stm32_gpio_config() static. - moved common.h inclusion before clk.h

Changes in v2: - included files in correct order. - moved the pinctrl specific routine from gpio driver to pinctrl - used dev_get_addr() instead of fdtdec_get_addr_size_auto_parent() in gpio driver. - pointed gpio name to bank name in device tree blob rather than copy.

arch/arm/include/asm/arch-stm32f7/gpio.h | 20 ++++- drivers/gpio/Kconfig | 9 +++ drivers/gpio/Makefile | 1 + drivers/gpio/stm32f7_gpio.c | 135 +++++++++++++++++++++++++++++++ drivers/pinctrl/pinctrl_stm32.c | 38 ++++++++- 5 files changed, 198 insertions(+), 5 deletions(-) create mode 100644 drivers/gpio/stm32f7_gpio.c

diff --git a/arch/arm/include/asm/arch-stm32f7/gpio.h b/arch/arm/include/asm/arch-stm32f7/gpio.h index 2942cd9..45999b4 100644 --- a/arch/arm/include/asm/arch-stm32f7/gpio.h +++ b/arch/arm/include/asm/arch-stm32f7/gpio.h @@ -96,6 +96,22 @@ struct stm32_gpio_ctl { enum stm32_gpio_af af; };

+struct stm32_gpio_regs { + u32 moder; /* GPIO port mode */ + u32 otyper; /* GPIO port output type */ + u32 ospeedr; /* GPIO port output speed */ + u32 pupdr; /* GPIO port pull-up/pull-down */ + u32 idr; /* GPIO port input data */ + u32 odr; /* GPIO port output data */ + u32 bsrr; /* GPIO port bit set/reset */ + u32 lckr; /* GPIO port configuration lock */ + u32 afr[2]; /* GPIO alternate function */ +}; + +struct stm32_gpio_priv { + struct stm32_gpio_regs *regs; +}; + static inline unsigned stm32_gpio_to_port(unsigned gpio) { return gpio / 16; @@ -106,8 +122,4 @@ static inline unsigned stm32_gpio_to_pin(unsigned gpio) return gpio % 16; }

-int stm32_gpio_config(const struct stm32_gpio_dsc *gpio_dsc, - const struct stm32_gpio_ctl *gpio_ctl); -int stm32_gpout_set(const struct stm32_gpio_dsc *gpio_dsc, int state); - #endif /* _STM32_GPIO_H_ */ diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index dc4108f..7c28e26 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -158,6 +158,15 @@ config PIC32_GPIO help Say yes here to support Microchip PIC32 GPIOs.

+config STM32F7_GPIO + bool "ST STM32 GPIO driver" + depends on DM_GPIO + default y + help + Device model driver support for STM32 GPIO controller. It should be + usable on many stm32 families like stm32f4 & stm32H7. + Tested on STM32F7. + config MVEBU_GPIO bool "Marvell MVEBU GPIO driver" depends on DM_GPIO && ARCH_MVEBU diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 27f8068..0ca845f 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -49,6 +49,7 @@ oby-$(CONFIG_SX151X) += sx151x.o obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o +obj-$(CONFIG_STM32F7_GPIO) += stm32f7_gpio.o obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o diff --git a/drivers/gpio/stm32f7_gpio.c b/drivers/gpio/stm32f7_gpio.c new file mode 100644 index 0000000..5e05463 --- /dev/null +++ b/drivers/gpio/stm32f7_gpio.c @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2017 + * Vikas Manocha, vikas.manocha@st.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <fdtdec.h> +#include <asm/arch/gpio.h> +#include <asm/arch/stm32.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <linux/errno.h> +#include <linux/io.h> + +#define MAX_SIZE_BANK_NAME 5 +#define STM32_GPIOS_PER_BANK 16 +#define MODE_BITS(gpio_pin) (gpio_pin * 2) +#define MODE_BITS_MASK 3 +#define IN_OUT_BIT_INDEX(gpio_pin) (1UL << (gpio_pin)) + +DECLARE_GLOBAL_DATA_PTR; + +static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset) +{ + struct stm32_gpio_priv *priv = dev_get_priv(dev); + struct stm32_gpio_regs *regs = priv->regs; + int bits_index = MODE_BITS(offset); + int mask = MODE_BITS_MASK << bits_index; + + clrsetbits_le32(&regs->moder, mask, STM32_GPIO_MODE_IN << bits_index); + + return 0; +} + +static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset, + int value) +{ + struct stm32_gpio_priv *priv = dev_get_priv(dev); + struct stm32_gpio_regs *regs = priv->regs; + int bits_index = MODE_BITS(offset); + int mask = MODE_BITS_MASK << bits_index; + + clrsetbits_le32(&regs->moder, mask, STM32_GPIO_MODE_OUT << bits_index); + mask = IN_OUT_BIT_INDEX(offset); + clrsetbits_le32(&regs->odr, mask, value ? mask : 0); + + return 0; +} + +static int stm32_gpio_get_value(struct udevice *dev, unsigned offset) +{ + struct stm32_gpio_priv *priv = dev_get_priv(dev); + struct stm32_gpio_regs *regs = priv->regs; + + return readl(&regs->idr) & IN_OUT_BIT_INDEX(offset) ? 1 : 0; +} + +static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value) +{ + struct stm32_gpio_priv *priv = dev_get_priv(dev); + struct stm32_gpio_regs *regs = priv->regs; + int mask = IN_OUT_BIT_INDEX(offset); + + clrsetbits_le32(&regs->odr, mask, value ? mask : 0); + + return 0; +} + +static const struct dm_gpio_ops gpio_stm32_ops = { + .direction_input = stm32_gpio_direction_input, + .direction_output = stm32_gpio_direction_output, + .get_value = stm32_gpio_get_value, + .set_value = stm32_gpio_set_value, +}; + +static int gpio_stm32_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct stm32_gpio_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + char *name; + + addr = dev_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = (struct stm32_gpio_regs *)addr; + name = (char *)fdtdec_locate_byte_array(gd->fdt_blob, + dev_of_offset(dev), + "st,bank-name", + MAX_SIZE_BANK_NAME); + if (!name) + return -EINVAL; + uc_priv->bank_name = name; + uc_priv->gpio_count = STM32_GPIOS_PER_BANK; + debug("%s, addr = 0x%p, bank_name = %s\n", __func__, (u32 *)priv->regs, + uc_priv->bank_name); + +#ifdef CONFIG_CLK + struct clk clk; + int ret; + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + debug("clock enabled for device %s\n", dev->name); +#endif + + return 0; +} + +static const struct udevice_id stm32_gpio_ids[] = { + { .compatible = "st,stm32-gpio" }, + { } +}; + +U_BOOT_DRIVER(gpio_stm32) = { + .name = "gpio_stm32", + .id = UCLASS_GPIO, + .of_match = stm32_gpio_ids, + .probe = gpio_stm32_probe, + .ops = &gpio_stm32_ops, + .flags = DM_FLAG_PRE_RELOC | DM_UC_FLAG_SEQ_ALIAS, + .priv_auto_alloc_size = sizeof(struct stm32_gpio_priv), +}; diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index aa2c440..0e74d05 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -1,10 +1,45 @@ #include <common.h> -#include <asm/arch/gpio.h> #include <dm.h> #include <dm/pinctrl.h> +#include <asm/arch/gpio.h> +#include <asm/gpio.h> +#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

+#define MODE_BITS_MASK 3 +#define OSPEED_MASK 3 +#define PUPD_MASK 3 +#define OTYPE_MSK 1 +#define AFR_MASK 0xF + +static int stm32_gpio_config(struct gpio_desc *desc, + const struct stm32_gpio_ctl *ctl) +{ + struct stm32_gpio_priv *priv = dev_get_priv(desc->dev); + struct stm32_gpio_regs *regs = priv->regs; + u32 index; + + if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 || + ctl->pupd > 2 || ctl->speed > 3) + return -EINVAL; + + index = (desc->offset & 0x07) * 4; + clrsetbits_le32(&regs->afr[desc->offset >> 3], AFR_MASK << index, + ctl->af << index); + + index = desc->offset * 2; + clrsetbits_le32(&regs->moder, MODE_BITS_MASK << index, + ctl->mode << index); + clrsetbits_le32(&regs->ospeedr, OSPEED_MASK << index, + ctl->speed << index); + clrsetbits_le32(&regs->pupdr, PUPD_MASK << index, ctl->pupd << index); + + index = desc->offset; + clrsetbits_le32(&regs->otyper, OTYPE_MSK << index, ctl->otype << index); + + return 0; +} static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin) { gpio_dsc->port = (port_pin & 0xF000) >> 12; @@ -18,6 +53,7 @@ static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin) static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node) { gpio_fn &= 0x00FF; + gpio_ctl->af = 0;

switch (gpio_fn) { case 0:

Also created alias for gpios for stm32f7 discovery board. Based on these aliases, it would be possible to get gpio devices by sequence.

Signed-off-by: Vikas Manocha vikas.manocha@st.com cc: Christophe KERELLO christophe.kerello@st.com --- Changed in v4: None Changed in v3: None Changed in v2: None

arch/arm/dts/stm32f746-disco.dts | 12 +++++ arch/arm/dts/stm32f746.dtsi | 111 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 123 insertions(+)

diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index f098d2e..f830aa9 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -65,6 +65,18 @@ aliases { serial0 = &usart1; spi0 = &qspi; + /* Aliases for gpios so as to use sequence */ + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; }; };

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index e9fd6f4..865d5cf 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -114,6 +114,117 @@ u-boot,dm-pre-reloc; pins-are-numbered;

+ gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x0 0x400>; + clocks = <&rcc 0 0>; + st,bank-name = "GPIOA"; + u-boot,dm-pre-reloc; + }; + + gpiob: gpio@40020400 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x400 0x400>; + clocks = <&rcc 0 1>; + st,bank-name = "GPIOB"; + u-boot,dm-pre-reloc; + }; + + + gpioc: gpio@40020800 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x800 0x400>; + clocks = <&rcc 0 2>; + st,bank-name = "GPIOC"; + u-boot,dm-pre-reloc; + }; + + gpiod: gpio@40020c00 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0xc00 0x400>; + clocks = <&rcc 0 3>; + st,bank-name = "GPIOD"; + u-boot,dm-pre-reloc; + }; + + gpioe: gpio@40021000 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x1000 0x400>; + clocks = <&rcc 0 4>; + st,bank-name = "GPIOE"; + u-boot,dm-pre-reloc; + }; + + gpiof: gpio@40021400 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x1400 0x400>; + clocks = <&rcc 0 5>; + st,bank-name = "GPIOF"; + u-boot,dm-pre-reloc; + }; + + gpiog: gpio@40021800 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x1800 0x400>; + clocks = <&rcc 0 6>; + st,bank-name = "GPIOG"; + u-boot,dm-pre-reloc; + }; + + gpioh: gpio@40021c00 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x1c00 0x400>; + clocks = <&rcc 0 7>; + st,bank-name = "GPIOH"; + u-boot,dm-pre-reloc; + }; + + gpioi: gpio@40022000 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x2000 0x400>; + clocks = <&rcc 0 8>; + st,bank-name = "GPIOI"; + u-boot,dm-pre-reloc; + }; + + gpioj: gpio@40022400 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x2400 0x400>; + clocks = <&rcc 0 9>; + st,bank-name = "GPIOJ"; + u-boot,dm-pre-reloc; + }; + + gpiok: gpio@40022800 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x2800 0x400>; + clocks = <&rcc 0 10>; + st,bank-name = "GPIOK"; + u-boot,dm-pre-reloc; + }; + usart1_pins_a: usart1@0 { pins1 { pinmux = <STM32F746_PA9_FUNC_USART1_TX>;

With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code.

Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree.

Signed-off-by: Vikas Manocha vikas.manocha@st.com cc: Christophe KERELLO christophe.kerello@st.com Reviewed-by: Simon Glass sjg@chromium.org --- Changed in v4: None Changed in v3: None Changed in v2: None

arch/arm/include/asm/arch-stm32f7/gpio.h | 1 + board/st/stm32f746-disco/stm32f746-disco.c | 70 ++---------------------------- configs/stm32f746-disco_defconfig | 4 ++ drivers/clk/clk_stm32f7.c | 39 ----------------- drivers/pinctrl/pinctrl_stm32.c | 9 +++- include/configs/stm32f746-disco.h | 1 - 6 files changed, 15 insertions(+), 109 deletions(-)

diff --git a/arch/arm/include/asm/arch-stm32f7/gpio.h b/arch/arm/include/asm/arch-stm32f7/gpio.h index 45999b4..56e469e 100644 --- a/arch/arm/include/asm/arch-stm32f7/gpio.h +++ b/arch/arm/include/asm/arch-stm32f7/gpio.h @@ -7,6 +7,7 @@

#ifndef _STM32_GPIO_H_ #define _STM32_GPIO_H_ +#include <asm/gpio.h>

enum stm32_gpio_port { STM32_GPIO_PORT_A = 0, diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 370db15..45a2c47 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -20,37 +20,12 @@

DECLARE_GLOBAL_DATA_PTR;

-const struct stm32_gpio_ctl gpio_ctl_gpout = { - .mode = STM32_GPIO_MODE_OUT, - .otype = STM32_GPIO_OTYPE_PP, - .speed = STM32_GPIO_SPEED_50M, - .pupd = STM32_GPIO_PUPD_NO, - .af = STM32_GPIO_AF0 -}; - -static int fmc_setup_gpio(void) -{ - clock_setup(GPIO_B_CLOCK_CFG); - clock_setup(GPIO_C_CLOCK_CFG); - clock_setup(GPIO_D_CLOCK_CFG); - clock_setup(GPIO_E_CLOCK_CFG); - clock_setup(GPIO_F_CLOCK_CFG); - clock_setup(GPIO_G_CLOCK_CFG); - clock_setup(GPIO_H_CLOCK_CFG); - - return 0; -} - int dram_init(void) { struct udevice *dev; struct ram_info ram; int rv;

- rv = fmc_setup_gpio(); - if (rv) - return rv; - rv = uclass_get_device(UCLASS_RAM, 0, &dev); if (rv) { debug("DRAM init failed: %d\n", rv); @@ -73,37 +48,21 @@ int dram_init(void) return rv; }

-int uart_setup_gpio(void) -{ - clock_setup(GPIO_A_CLOCK_CFG); - clock_setup(GPIO_B_CLOCK_CFG); - return 0; -} - #ifdef CONFIG_ETH_DESIGNWARE - static int stmmac_setup(void) { clock_setup(SYSCFG_CLOCK_CFG); /* Set >RMII mode */ STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL; - - clock_setup(GPIO_A_CLOCK_CFG); - clock_setup(GPIO_C_CLOCK_CFG); - clock_setup(GPIO_G_CLOCK_CFG); clock_setup(STMMAC_CLOCK_CFG);

return 0; } -#endif

-#ifdef CONFIG_STM32_QSPI - -static int qspi_setup(void) +int board_early_init_f(void) { - clock_setup(GPIO_B_CLOCK_CFG); - clock_setup(GPIO_D_CLOCK_CFG); - clock_setup(GPIO_E_CLOCK_CFG); + stmmac_setup(); + return 0; } #endif @@ -113,29 +72,6 @@ u32 get_board_rev(void) return 0; }

-int board_early_init_f(void) -{ - int res; - - res = uart_setup_gpio(); - if (res) - return res; - -#ifdef CONFIG_ETH_DESIGNWARE - res = stmmac_setup(); - if (res) - return res; -#endif - -#ifdef CONFIG_STM32_QSPI - res = qspi_setup(); - if (res) - return res; -#endif - - return 0; -} - int board_init(void) { gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index 046041a..5e86a76 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_DNS=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_TIMER=y CONFIG_OF_CONTROL=y +CONFIG_DM_SEQ_ALIAS=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y # CONFIG_MMC is not set @@ -45,3 +46,6 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_STM32=y CONFIG_RAM=y CONFIG_STM32_SDRAM=y +CONFIG_DM_GPIO=y +CONFIG_STM32F7_GPIO=y +CONFIG_SYS_MALLOC_F_LEN=0xC00 diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f7.c index 0d86395..da3c204 100644 --- a/drivers/clk/clk_stm32f7.c +++ b/drivers/clk/clk_stm32f7.c @@ -228,56 +228,17 @@ static int stm32_clk_enable(struct clk *clk) void clock_setup(int peripheral) { switch (peripheral) { - case GPIO_A_CLOCK_CFG: - setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_A_EN); - break; - case GPIO_B_CLOCK_CFG: - setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_B_EN); - break; - case GPIO_C_CLOCK_CFG: - setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_C_EN); - break; - case GPIO_D_CLOCK_CFG: - setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_D_EN); - break; - case GPIO_E_CLOCK_CFG: - setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_E_EN); - break; - case GPIO_F_CLOCK_CFG: - setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_F_EN); - break; - case GPIO_G_CLOCK_CFG: - setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_G_EN); - break; - case GPIO_H_CLOCK_CFG: - setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_H_EN); - break; - case GPIO_I_CLOCK_CFG: - setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_I_EN); - break; - case GPIO_J_CLOCK_CFG: - setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_J_EN); - break; - case GPIO_K_CLOCK_CFG: - setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_K_EN); - break; case SYSCFG_CLOCK_CFG: setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN); break; case TIMER2_CLOCK_CFG: setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN); break; - case FMC_CLOCK_CFG: - setbits_le32(&STM32_RCC->ahb3enr, RCC_AHB3ENR_FMC_EN); - break; case STMMAC_CLOCK_CFG: setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN); setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN); setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN); break; - case QSPI_CLOCK_CFG: - setbits_le32(&STM32_RCC->ahb3enr, RCC_AHB3ENR_QSPI_EN); - break; default: break; } diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 0e74d05..01f0429 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -121,11 +121,16 @@ static int stm32_pinctrl_set_state_simple(struct udevice *dev, if (len < 0) return -EINVAL; for (i = 0; i < len; i++) { + struct gpio_desc desc; debug("%s: pinmux = %x\n", __func__, *(pin_mux + i)); prep_gpio_dsc(&gpio_dsc, *(pin_mux + i)); prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), args.node); - - rv = stm32_gpio_config(&gpio_dsc, &gpio_ctl); + rv = uclass_get_device_by_seq(UCLASS_GPIO, + gpio_dsc.port, &desc.dev); + if (rv) + return rv; + desc.offset = gpio_dsc.pin; + rv = stm32_gpio_config(&desc, &gpio_ctl); debug("%s: rv = %d\n\n", __func__, rv); if (rv) return rv; diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index de3d661..e917ba9 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -30,7 +30,6 @@ #define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_SIZE (8 << 10)

-#define CONFIG_STM32_GPIO #define CONFIG_STM32_FLASH #define CONFIG_STM32X7_SERIAL

All discovery boards have one user button & one user LED. Here we are just reading the button status & switching ON the user LED.

Signed-off-by: Vikas Manocha vikas.manocha@st.com cc: Christophe KERELLO christophe.kerello@st.com --- Changed in v4: None Changed in v3: None Changed in v2: None

arch/arm/dts/stm32f746-disco.dts | 10 ++++++++ board/st/stm32f746-disco/stm32f746-disco.c | 37 ++++++++++++++++++++++++++++++ include/configs/stm32f746-disco.h | 1 + 3 files changed, 48 insertions(+)

diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index f830aa9..8e4576b 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -78,6 +78,16 @@ gpio9 = &gpioj; gpio10 = &gpiok; }; + + led1 { + compatible = "st,led1"; + led-gpio = <&gpioi 1 0>; + }; + + button1 { + compatible = "st,button1"; + button-gpio = <&gpioi 11 0>; + }; };

&clk_hse { diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 45a2c47..52c1900 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -17,6 +17,7 @@ #include <asm/arch/stm32_periph.h> #include <asm/arch/stm32_defs.h> #include <asm/arch/syscfg.h> +#include <asm/gpio.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -72,6 +73,42 @@ u32 get_board_rev(void) return 0; }

+int board_late_init(void) +{ + struct gpio_desc gpio = {}; + int node; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,led1"); + if (node < 0) + return -1; + + gpio_request_by_name_nodev(gd->fdt_blob, node, "led-gpio", 0, &gpio, + GPIOD_IS_OUT); + + if (dm_gpio_is_valid(&gpio)) { + dm_gpio_set_value(&gpio, 0); + mdelay(10); + dm_gpio_set_value(&gpio, 1); + } + + /* read button 1*/ + node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,button1"); + if (node < 0) + return -1; + + gpio_request_by_name_nodev(gd->fdt_blob, node, "button-gpio", 0, &gpio, + GPIOD_IS_IN); + + if (dm_gpio_is_valid(&gpio)) { + if (dm_gpio_get_value(&gpio)) + puts("usr button is at HIGH LEVEL\n"); + else + puts("usr button is at LOW LEVEL\n"); + } + + return 0; +} + int board_init(void) { gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index e917ba9..48ac441 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -75,4 +75,5 @@

#define CONFIG_CMD_MEM #define CONFIG_CMD_CACHE +#define CONFIG_BOARD_LATE_INIT #endif /* __CONFIG_H */

Signed-off-by: Vikas Manocha vikas.manocha@st.com cc: Christophe KERELLO christophe.kerello@st.com --- Changed in v4: - Rebased to master as dram_init_banksize() prototype is changed. Changed in v3: None Changed in v2: None

board/st/stm32f746-disco/stm32f746-disco.c | 42 +++++++++++++++++++++--------- drivers/ram/stm32_sdram.c | 1 - include/configs/stm32f746-disco.h | 6 +---- 3 files changed, 31 insertions(+), 18 deletions(-)

diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 52c1900..dc3a9dc 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -21,32 +21,51 @@

DECLARE_GLOBAL_DATA_PTR;

+int get_memory_base_size(fdt_addr_t *mr_base, fdt_addr_t *mr_size) +{ + int mr_node; + + mr_node = fdt_path_offset(gd->fdt_blob, "/memory"); + if (mr_node < 0) + return mr_node; + *mr_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, mr_node, + "reg", 0, mr_size, false); + debug("mr_base = %lx, mr_size= %lx\n", *mr_base, *mr_size); + + return 0; +} int dram_init(void) { struct udevice *dev; - struct ram_info ram; int rv; + fdt_addr_t mr_base, mr_size;

rv = uclass_get_device(UCLASS_RAM, 0, &dev); if (rv) { debug("DRAM init failed: %d\n", rv); return rv; } - rv = ram_get_info(dev, &ram); - if (rv) { - debug("Cannot get DRAM size: %d\n", rv); + + rv = get_memory_base_size(&mr_base, &mr_size); + if (rv) return rv; - } - debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size); - gd->ram_size = ram.size; + gd->ram_size = mr_size; + gd->ram_top = mr_base;

+ return rv; +} + +int dram_init_banksize(void) +{ + fdt_addr_t mr_base, mr_size; + get_memory_base_size(&mr_base, &mr_size); /* * Fill in global info with description of SRAM configuration */ - gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE; - gd->bd->bi_dram[0].size = ram.size; + gd->bd->bi_dram[0].start = mr_base; + gd->bd->bi_dram[0].size = mr_size;

- return rv; + return 0; }

#ifdef CONFIG_ETH_DESIGNWARE @@ -111,7 +130,6 @@ int board_late_init(void)

int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; return 0; } diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index eb1ab94..5e09f35 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -179,7 +179,6 @@ static int stm32_fmc_probe(struct udevice *dev)

static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info) { - info->size = CONFIG_SYS_RAM_SIZE; return 0; }

diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 48ac441..349ee3a 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -16,11 +16,7 @@ * Configuration of the external SDRAM memory */ #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_RAM_SIZE (8 * 1024 * 1024) -#define CONFIG_SYS_RAM_CS 1 -#define CONFIG_SYS_RAM_FREQ_DIV 2 -#define CONFIG_SYS_RAM_BASE 0xC0000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE +#define CONFIG_SYS_RAM_FREQ_DIV 2 #define CONFIG_SYS_LOAD_ADDR 0xC0400000 #define CONFIG_LOADADDR 0xC0400000

Signed-off-by: Vikas Manocha vikas.manocha@st.com cc: Christophe KERELLO christophe.kerello@st.com --- Changed in v4: None Changed in v3: None Changed in v2: None

include/configs/stm32f746-disco.h | 1 + 1 file changed, 1 insertion(+)

diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 349ee3a..73a316d 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -72,4 +72,5 @@ #define CONFIG_CMD_MEM #define CONFIG_CMD_CACHE #define CONFIG_BOARD_LATE_INIT +#define CONFIG_DISPLAY_BOARDINFO #endif /* __CONFIG_H */

Actually the sdram memory on stm32f746 discovery board is micron part MT48LC_4M32_B2B5_6A. This patch does the modification required in the device tree node & driver for the same.

Also we are passing here all the timing parameters in terms of clock cycles, so no need to convert time(ns or ms) to cycles.

Signed-off-by: Vikas Manocha vikas.manocha@st.com cc: Christophe KERELLO christophe.kerello@st.com --- Changed in v4: None Changed in v3: None Changed in v2: None

arch/arm/dts/stm32f746-disco.dts | 13 +++++--- drivers/ram/stm32_sdram.c | 55 ++++++++++---------------------- include/configs/stm32f746-disco.h | 1 - include/dt-bindings/memory/stm32-sdram.h | 15 +++++---- 4 files changed, 33 insertions(+), 51 deletions(-)

diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index 8e4576b..e720ff1 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -106,12 +106,15 @@ status = "okay";

mr-nbanks = <1>; - /* sdram memory configuration from sdram datasheet IS42S16400J */ + /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ bank1: bank@0 { - st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2 - CAS_3 RD_BURST_EN RD_PIPE_DL_0>; - st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18 - TRCD_18>; + st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_4 + CAS_3 SDCLK_2 RD_BURST_EN + RD_PIPE_DL_0>; + st,sdram-timing = /bits/ 8 <TMRD_2 TXSR_6 TRAS_4 TRC_6 TWR_2 + TRP_2 TRCD_2>; + /* refcount = (64msec/total_row_sdram)*freq - 20 */ + st,sdram-refcount = < 1542 >; }; };

diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 5e09f35..48b4979 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -21,6 +21,7 @@ struct stm32_sdram_control { u8 memory_width; u8 no_banks; u8 cas_latency; + u8 sdclk; u8 rd_burst; u8 rd_pipe_delay; }; @@ -31,51 +32,25 @@ struct stm32_sdram_timing { u8 tras; u8 trc; u8 trp; + u8 twr; u8 trcd; }; struct stm32_sdram_params { u8 no_sdram_banks; struct stm32_sdram_control sdram_control; struct stm32_sdram_timing sdram_timing; + u32 sdram_ref_count; }; -static inline u32 _ns2clk(u32 ns, u32 freq) -{ - u32 tmp = freq/1000000; - return (tmp * ns) / 1000; -} - -#define NS2CLK(ns) (_ns2clk(ns, freq)) - -#define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20)

#define SDRAM_MODE_BL_SHIFT 0 #define SDRAM_MODE_CAS_SHIFT 4 #define SDRAM_MODE_BL 0 -#define SDRAM_MODE_CAS 3 - -#define SDRAM_TRDL 12

int stm32_sdram_init(struct udevice *dev) { - u32 freq; - u32 sdram_twr; struct stm32_sdram_params *params = dev_get_platdata(dev);

- /* - * Get frequency for NS2CLK calculation. - */ - freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV; - debug("%s, sdram freq = %d\n", __func__, freq); - - /* Last data in to row precharge, need also comply ineq on page 1648 */ - sdram_twr = max( - max(SDRAM_TRDL, params->sdram_timing.tras - - params->sdram_timing.trcd), - params->sdram_timing.trc - params->sdram_timing.trcd - - params->sdram_timing.trp - ); - - writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT + writel(params->sdram_control.sdclk << FMC_SDCR_SDCLK_SHIFT | params->sdram_control.cas_latency << FMC_SDCR_CAS_SHIFT | params->sdram_control.no_banks << FMC_SDCR_NB_SHIFT | params->sdram_control.memory_width << FMC_SDCR_MWID_SHIFT @@ -85,13 +60,13 @@ int stm32_sdram_init(struct udevice *dev) | params->sdram_control.rd_burst << FMC_SDCR_RBURST_SHIFT, &STM32_SDRAM_FMC->sdcr1);

- writel(NS2CLK(params->sdram_timing.trcd) << FMC_SDTR_TRCD_SHIFT - | NS2CLK(params->sdram_timing.trp) << FMC_SDTR_TRP_SHIFT - | NS2CLK(sdram_twr) << FMC_SDTR_TWR_SHIFT - | NS2CLK(params->sdram_timing.trc) << FMC_SDTR_TRC_SHIFT - | NS2CLK(params->sdram_timing.tras) << FMC_SDTR_TRAS_SHIFT - | NS2CLK(params->sdram_timing.txsr) << FMC_SDTR_TXSR_SHIFT - | NS2CLK(params->sdram_timing.tmrd) << FMC_SDTR_TMRD_SHIFT, + writel(params->sdram_timing.trcd << FMC_SDTR_TRCD_SHIFT + | params->sdram_timing.trp << FMC_SDTR_TRP_SHIFT + | params->sdram_timing.twr << FMC_SDTR_TWR_SHIFT + | params->sdram_timing.trc << FMC_SDTR_TRC_SHIFT + | params->sdram_timing.tras << FMC_SDTR_TRAS_SHIFT + | params->sdram_timing.txsr << FMC_SDTR_TXSR_SHIFT + | params->sdram_timing.tmrd << FMC_SDTR_TMRD_SHIFT, &STM32_SDRAM_FMC->sdtr1);

writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, @@ -110,7 +85,7 @@ int stm32_sdram_init(struct udevice *dev) FMC_BUSY_WAIT();

writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT - | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT) + | params->sdram_control.cas_latency << SDRAM_MODE_CAS_SHIFT) << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, &STM32_SDRAM_FMC->sdcmr); udelay(100); @@ -121,7 +96,7 @@ int stm32_sdram_init(struct udevice *dev) FMC_BUSY_WAIT();

/* Refresh timer */ - writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr); + writel((params->sdram_ref_count) << 1, &STM32_SDRAM_FMC->sdrtr);

return 0; } @@ -142,12 +117,14 @@ static int stm32_fmc_ofdata_to_platdata(struct udevice *dev) sizeof(params->sdram_control)); if (ret) return ret; - ret = fdtdec_get_byte_array(blob, node, "st,sdram-timing", (u8 *)&params->sdram_timing, sizeof(params->sdram_timing)); if (ret) return ret; + + params->sdram_ref_count = fdtdec_get_int(blob, node, + "st,sdram-refcount", 8196); }

return 0; diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 73a316d..cc0f8fd 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -16,7 +16,6 @@ * Configuration of the external SDRAM memory */ #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_RAM_FREQ_DIV 2 #define CONFIG_SYS_LOAD_ADDR 0xC0400000 #define CONFIG_LOADADDR 0xC0400000

diff --git a/include/dt-bindings/memory/stm32-sdram.h b/include/dt-bindings/memory/stm32-sdram.h index 4cd6c2b..89b719a 100644 --- a/include/dt-bindings/memory/stm32-sdram.h +++ b/include/dt-bindings/memory/stm32-sdram.h @@ -18,17 +18,20 @@ #define CAS_1 0x1 #define CAS_2 0x2 #define CAS_3 0x3 +#define SDCLK_2 0x2 #define RD_BURST_EN 0x1 #define RD_BURST_DIS 0x0 #define RD_PIPE_DL_0 0x0 #define RD_PIPE_DL_1 0x1 #define RD_PIPE_DL_2 0x2

-#define TMRD_1 0x1 -#define TXSR_60 60 -#define TRAS_42 42 -#define TRC_60 60 -#define TRP_18 18 -#define TRCD_18 18 +/* Timing = value +1 cycles */ +#define TMRD_2 (2 - 1) +#define TXSR_6 (6 - 1) +#define TRAS_4 (4 - 1) +#define TRC_6 (6 - 1) +#define TWR_2 (2 - 1) +#define TRP_2 (2 - 1) +#define TRCD_2 (2 - 1)

#endif

The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals).

Signed-off-by: Vikas Manocha vikas.manocha@st.com cc: Christophe KERELLO christophe.kerello@st.com --- Changed in v4: None Changed in v3: None Changed in v2: None

drivers/pinctrl/pinctrl_stm32.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 01f0429..d7b5ea3 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -7,6 +7,7 @@

DECLARE_GLOBAL_DATA_PTR;

+#define MAX_PINS_ONE_IP 70 #define MODE_BITS_MASK 3 #define OSPEED_MASK 3 #define PUPD_MASK 3 @@ -95,7 +96,7 @@ static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node) static int stm32_pinctrl_set_state_simple(struct udevice *dev, struct udevice *periph) { - u32 pin_mux[50]; + u32 pin_mux[MAX_PINS_ONE_IP]; struct fdtdec_phandle_args args; int rv, len;

Signed-off-by: Vikas Manocha vikas.manocha@st.com cc: Christophe KERELLO christophe.kerello@st.com --- Changed in v4: None Changed in v3: None Changed in v2: None

arch/arm/dts/stm32f746-disco.dts | 90 ++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/stm32f746.dtsi | 86 -------------------------------------- 2 files changed, 90 insertions(+), 86 deletions(-)

diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index e720ff1..2c7fa79 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -94,6 +94,96 @@ clock-frequency = <25000000>; };

+&pinctrl { + usart1_pins_a: usart1@0 { + pins1 { + pinmux = <STM32F746_PA9_FUNC_USART1_TX>; + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32F746_PB7_FUNC_USART1_RX>; + bias-disable; + }; + }; + + ethernet_mii: mii@0 { + pins { + pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, + <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, + <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, + <STM32F746_PA2_FUNC_ETH_MDIO>, + <STM32F746_PC1_FUNC_ETH_MDC>, + <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, + <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, + <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, + <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>; + slew-rate = <2>; + }; + }; + + qspi_pins: qspi@0 { + pins { + pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>, + <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>, + <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>, + <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>, + <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>, + <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>; + slew-rate = <2>; + }; + }; + + fmc_pins: fmc@0 { + pins { + pinmux = <STM32F746_PD10_FUNC_FMC_D15>, + <STM32F746_PD9_FUNC_FMC_D14>, + <STM32F746_PD8_FUNC_FMC_D13>, + <STM32F746_PE15_FUNC_FMC_D12>, + <STM32F746_PE14_FUNC_FMC_D11>, + <STM32F746_PE13_FUNC_FMC_D10>, + <STM32F746_PE12_FUNC_FMC_D9>, + <STM32F746_PE11_FUNC_FMC_D8>, + <STM32F746_PE10_FUNC_FMC_D7>, + <STM32F746_PE9_FUNC_FMC_D6>, + <STM32F746_PE8_FUNC_FMC_D5>, + <STM32F746_PE7_FUNC_FMC_D4>, + <STM32F746_PD1_FUNC_FMC_D3>, + <STM32F746_PD0_FUNC_FMC_D2>, + <STM32F746_PD15_FUNC_FMC_D1>, + <STM32F746_PD14_FUNC_FMC_D0>, + + <STM32F746_PE1_FUNC_FMC_NBL1>, + <STM32F746_PE0_FUNC_FMC_NBL0>, + + <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, + <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, + + <STM32F746_PG1_FUNC_FMC_A11>, + <STM32F746_PG0_FUNC_FMC_A10>, + <STM32F746_PF15_FUNC_FMC_A9>, + <STM32F746_PF14_FUNC_FMC_A8>, + <STM32F746_PF13_FUNC_FMC_A7>, + <STM32F746_PF12_FUNC_FMC_A6>, + <STM32F746_PF5_FUNC_FMC_A5>, + <STM32F746_PF4_FUNC_FMC_A4>, + <STM32F746_PF3_FUNC_FMC_A3>, + <STM32F746_PF2_FUNC_FMC_A2>, + <STM32F746_PF1_FUNC_FMC_A1>, + <STM32F746_PF0_FUNC_FMC_A0>, + + <STM32F746_PH3_FUNC_FMC_SDNE0>, + <STM32F746_PH5_FUNC_FMC_SDNWE>, + <STM32F746_PF11_FUNC_FMC_SDNRAS>, + <STM32F746_PG15_FUNC_FMC_SDNCAS>, + <STM32F746_PC3_FUNC_FMC_SDCKE0>, + <STM32F746_PG8_FUNC_FMC_SDCLK>; + slew-rate = <2>; + }; + }; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index 865d5cf..ac24d98 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -225,92 +225,6 @@ u-boot,dm-pre-reloc; };

- usart1_pins_a: usart1@0 { - pins1 { - pinmux = <STM32F746_PA9_FUNC_USART1_TX>; - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = <STM32F746_PB7_FUNC_USART1_RX>; - bias-disable; - }; - }; - ethernet_mii: mii@0 { - pins { - pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, - <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, - <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, - <STM32F746_PA2_FUNC_ETH_MDIO>, - <STM32F746_PC1_FUNC_ETH_MDC>, - <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, - <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, - <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, - <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>; - slew-rate = <2>; - }; - }; - qspi_pins: qspi@0{ - pins { - pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>, - <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>, - <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>, - <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>, - <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>, - <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>; - slew-rate = <2>; - }; - }; - - fmc_pins: fmc@0 { - pins { - pinmux = <STM32F746_PD10_FUNC_FMC_D15>, - <STM32F746_PD9_FUNC_FMC_D14>, - <STM32F746_PD8_FUNC_FMC_D13>, - <STM32F746_PE15_FUNC_FMC_D12>, - <STM32F746_PE14_FUNC_FMC_D11>, - <STM32F746_PE13_FUNC_FMC_D10>, - <STM32F746_PE12_FUNC_FMC_D9>, - <STM32F746_PE11_FUNC_FMC_D8>, - <STM32F746_PE10_FUNC_FMC_D7>, - <STM32F746_PE9_FUNC_FMC_D6>, - <STM32F746_PE8_FUNC_FMC_D5>, - <STM32F746_PE7_FUNC_FMC_D4>, - <STM32F746_PD1_FUNC_FMC_D3>, - <STM32F746_PD0_FUNC_FMC_D2>, - <STM32F746_PD15_FUNC_FMC_D1>, - <STM32F746_PD14_FUNC_FMC_D0>, - - <STM32F746_PE1_FUNC_FMC_NBL1>, - <STM32F746_PE0_FUNC_FMC_NBL0>, - - <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, - <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, - - <STM32F746_PG1_FUNC_FMC_A11>, - <STM32F746_PG0_FUNC_FMC_A10>, - <STM32F746_PF15_FUNC_FMC_A9>, - <STM32F746_PF14_FUNC_FMC_A8>, - <STM32F746_PF13_FUNC_FMC_A7>, - <STM32F746_PF12_FUNC_FMC_A6>, - <STM32F746_PF5_FUNC_FMC_A5>, - <STM32F746_PF4_FUNC_FMC_A4>, - <STM32F746_PF3_FUNC_FMC_A3>, - <STM32F746_PF2_FUNC_FMC_A2>, - <STM32F746_PF1_FUNC_FMC_A1>, - <STM32F746_PF0_FUNC_FMC_A0>, - - <STM32F746_PH3_FUNC_FMC_SDNE0>, - <STM32F746_PH5_FUNC_FMC_SDNWE>, - <STM32F746_PF11_FUNC_FMC_SDNRAS>, - <STM32F746_PG15_FUNC_FMC_SDNCAS>, - <STM32F746_PC3_FUNC_FMC_SDCKE0>, - <STM32F746_PG8_FUNC_FMC_SDCLK>; - slew-rate = <2>; - }; - }; - }; }; };

This board support stm32f7 family device stm32f769-I with 2MB internal Flash & 512KB RAM. STM32F769 lines offer the performance of the Cortex-M7 core (with double precision floating point unit) running up to 216 MHz.

To compile for stm32f769 board, use same defconfig as stm32f746-disco, the only difference is to pass "DEVICE_TREE=stm32f769-disco".

Signed-off-by: Vikas Manocha vikas.manocha@st.com cc: Christophe KERELLO christophe.kerello@st.com --- Changed in v4: None Changed in v3: None Changed in v2: None

arch/arm/dts/Makefile | 3 +- arch/arm/dts/stm32f769-disco.dts | 255 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 257 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/stm32f769-disco.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a2c0717..4456ced 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -184,7 +184,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \

dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb

-dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb +dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \ + stm32f769-disco.dtb

dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts new file mode 100644 index 0000000..6591cc8 --- /dev/null +++ b/arch/arm/dts/stm32f769-disco.dts @@ -0,0 +1,255 @@ +/* + * Copyright 2016 - Vikas Manocha vikas.manocha@st.com + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "stm32f746.dtsi" +#include <dt-bindings/memory/stm32-sdram.h> + +/ { + model = "STMicroelectronics STM32F769-DISCO board"; + compatible = "st,stm32f769-disco", "st,stm32f7"; + + chosen { + bootargs = "root=/dev/ram rdinit=/linuxrc"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0xC0000000 0x1000000>; + }; + + aliases { + serial0 = &usart1; + spi0 = &qspi; + /* Aliases for gpios so as to use sequence */ + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + }; + + led1 { + compatible = "st,led1"; + led-gpio = <&gpioj 5 0>; + }; + + button1 { + compatible = "st,button1"; + button-gpio = <&gpioa 0 0>; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&pinctrl { + usart1_pins_a: usart1@0 { + pins1 { + pinmux = <STM32F746_PA9_FUNC_USART1_TX>; + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32F746_PA10_FUNC_USART1_RX>; + bias-disable; + }; + }; + + ethernet_mii: mii@0 { + pins { + pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, + <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, + <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, + <STM32F746_PA2_FUNC_ETH_MDIO>, + <STM32F746_PC1_FUNC_ETH_MDC>, + <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, + <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, + <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, + <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>; + slew-rate = <2>; + }; + }; + + qspi_pins: qspi@0 { + pins { + pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>, + <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>, + <STM32F746_PC9_FUNC_QUADSPI_BK1_IO0>, + <STM32F746_PC10_FUNC_QUADSPI_BK1_IO1>, + <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>, + <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>; + slew-rate = <2>; + }; + }; + + fmc_pins: fmc@0 { + pins { + pinmux = <STM32F746_PI10_FUNC_FMC_D31>, + <STM32F746_PI9_FUNC_FMC_D30>, + <STM32F746_PI7_FUNC_FMC_D29>, + <STM32F746_PI6_FUNC_FMC_D28>, + <STM32F746_PI3_FUNC_FMC_D27>, + <STM32F746_PI2_FUNC_FMC_D26>, + <STM32F746_PI1_FUNC_FMC_D25>, + <STM32F746_PI0_FUNC_FMC_D24>, + <STM32F746_PH15_FUNC_FMC_D23>, + <STM32F746_PH14_FUNC_FMC_D22>, + <STM32F746_PH13_FUNC_FMC_D21>, + <STM32F746_PH12_FUNC_FMC_D20>, + <STM32F746_PH11_FUNC_FMC_D19>, + <STM32F746_PH10_FUNC_FMC_D18>, + <STM32F746_PH9_FUNC_FMC_D17>, + <STM32F746_PH8_FUNC_FMC_D16>, + + <STM32F746_PD10_FUNC_FMC_D15>, + <STM32F746_PD9_FUNC_FMC_D14>, + <STM32F746_PD8_FUNC_FMC_D13>, + <STM32F746_PE15_FUNC_FMC_D12>, + <STM32F746_PE14_FUNC_FMC_D11>, + <STM32F746_PE13_FUNC_FMC_D10>, + <STM32F746_PE12_FUNC_FMC_D9>, + <STM32F746_PE11_FUNC_FMC_D8>, + <STM32F746_PE10_FUNC_FMC_D7>, + <STM32F746_PE9_FUNC_FMC_D6>, + <STM32F746_PE8_FUNC_FMC_D5>, + <STM32F746_PE7_FUNC_FMC_D4>, + <STM32F746_PD1_FUNC_FMC_D3>, + <STM32F746_PD0_FUNC_FMC_D2>, + <STM32F746_PD15_FUNC_FMC_D1>, + <STM32F746_PD14_FUNC_FMC_D0>, + + <STM32F746_PI5_FUNC_FMC_NBL3>, + <STM32F746_PI4_FUNC_FMC_NBL2>, + <STM32F746_PE1_FUNC_FMC_NBL1>, + <STM32F746_PE0_FUNC_FMC_NBL0>, + + <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, + <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, + + <STM32F746_PG1_FUNC_FMC_A11>, + <STM32F746_PG0_FUNC_FMC_A10>, + <STM32F746_PF15_FUNC_FMC_A9>, + <STM32F746_PF14_FUNC_FMC_A8>, + <STM32F746_PF13_FUNC_FMC_A7>, + <STM32F746_PF12_FUNC_FMC_A6>, + <STM32F746_PF5_FUNC_FMC_A5>, + <STM32F746_PF4_FUNC_FMC_A4>, + <STM32F746_PF3_FUNC_FMC_A3>, + <STM32F746_PF2_FUNC_FMC_A2>, + <STM32F746_PF1_FUNC_FMC_A1>, + <STM32F746_PF0_FUNC_FMC_A0>, + + <STM32F746_PH3_FUNC_FMC_SDNE0>, + <STM32F746_PH5_FUNC_FMC_SDNWE>, + <STM32F746_PF11_FUNC_FMC_SDNRAS>, + <STM32F746_PG15_FUNC_FMC_SDNCAS>, + <STM32F746_PH2_FUNC_FMC_SDCKE0>, + <STM32F746_PG8_FUNC_FMC_SDCLK>; + slew-rate = <2>; + }; + }; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&fmc { + pinctrl-0 = <&fmc_pins>; + pinctrl-names = "default"; + status = "okay"; + + mr-nbanks = <1>; + /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ + bank1: bank@0 { + st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_32 BANKS_4 + CAS_3 SDCLK_2 RD_BURST_EN + RD_PIPE_DL_0>; + st,sdram-timing = /bits/ 8 <TMRD_2 TXSR_6 TRAS_4 TRC_6 TWR_2 + TRP_2 TRCD_2>; + /* refcount = (64msec/total_row_sdram)*freq - 20 */ + st,sdram-refcount = < 1542 >; + }; +}; + +&mac { + status = "okay"; + pinctrl-0 = <&ethernet_mii>; + phy-mode = "rmii"; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&qspi { + pinctrl-0 = <&qspi_pins>; + status = "okay"; + + qflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a13", "spi-flash"; + spi-max-frequency = <108000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + memory-map = <0x90000000 0x1000000>; + reg = <0>; + }; +};

This patch removes: - CONFIG_CMD_MEM: enabled by default - CONFIG_DESIGNWARE_ETH : not being used anywhere.

Signed-off-by: Vikas Manocha vikas.manocha@st.com cc: Christophe KERELLO christophe.kerello@st.com --- Changed in v4: None Changed in v3: None Changed in v2: None

include/configs/stm32f746-disco.h | 3 --- 1 file changed, 3 deletions(-)

diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index cc0f8fd..1ee5815 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -28,7 +28,6 @@ #define CONFIG_STM32_FLASH #define CONFIG_STM32X7_SERIAL

-#define CONFIG_DESIGNWARE_ETH #define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8) #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_MII @@ -67,8 +66,6 @@ #define CONFIG_SYS_LONGHELP #define CONFIG_AUTO_COMPLETE #define CONFIG_CMDLINE_EDITING - -#define CONFIG_CMD_MEM #define CONFIG_CMD_CACHE #define CONFIG_BOARD_LATE_INIT #define CONFIG_DISPLAY_BOARDINFO