This is not supported with driver model, so print a message instead of generating a build error. Rescanning PCI is not yet implemented.

This function will be implemented later once some additional PCI driver model improvements are merged. It was confirmed on the mailing list that no one on the tegra side will miss this feature, so it is disabled for tegra.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Update commit message to explain that the feature is not important - Drop the feature from tegra boards

common/cmd_pci.c | 4 ++++ include/configs/apalis_t30.h | 1 - include/configs/beaver.h | 1 - include/configs/cardhu.h | 1 - include/configs/jetson-tk1.h | 1 - include/configs/trimslice.h | 1 - 6 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/common/cmd_pci.c b/common/cmd_pci.c index dcecef8..69c5332 100644 --- a/common/cmd_pci.c +++ b/common/cmd_pci.c @@ -457,7 +457,11 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return pci_cfg_display(bdf, addr, size, value); #ifdef CONFIG_CMD_PCI_ENUM case 'e': +# ifdef CONFIG_DM_PCI + printf("This command is not yet supported with driver model\n"); +# else pci_init(); +# endif return 0; #endif case 'n': /* next */ diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index 7552a80..e1eb700 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -51,7 +51,6 @@ #define CONFIG_PCI #define CONFIG_PCI_PNP #define CONFIG_CMD_PCI -#define CONFIG_CMD_PCI_ENUM

/* PCI networking support */ #define CONFIG_E1000_NO_NVM diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 9e8dcf3f7..a2c9622 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -75,7 +75,6 @@ #define CONFIG_PCI #define CONFIG_PCI_PNP #define CONFIG_CMD_PCI -#define CONFIG_CMD_PCI_ENUM

/* PCI networking support */ #define CONFIG_RTL8169 diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 174bb48..0d857bb 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -77,7 +77,6 @@ #define CONFIG_PCI #define CONFIG_PCI_PNP #define CONFIG_CMD_PCI -#define CONFIG_CMD_PCI_ENUM

/* PCI networking support */ #define CONFIG_RTL8169 diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 618ffa6..7e0cc5e 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -61,7 +61,6 @@ #define CONFIG_PCI #define CONFIG_PCI_PNP #define CONFIG_CMD_PCI -#define CONFIG_CMD_PCI_ENUM

/* PCI networking support */ #define CONFIG_RTL8169 diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index bdf1bd4..add5d40 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -60,7 +60,6 @@ #define CONFIG_PCI #define CONFIG_PCI_PNP #define CONFIG_CMD_PCI -#define CONFIG_CMD_PCI_ENUM

/* PCI networking support */ #define CONFIG_RTL8169

At present we add a new resource entry for every range entry. But some range entries refer to configuration regions. To make this work, avoid adding two regions of the same type. The later ranges will overwrite the earlier (configuration) ones.

There does not seem to be a way to distinguish the configuration ranges other than by ordering (as per the device tree binding).

We could perhaps instead just store one region of each type in a simple array. Once we are sure that we don't need to support multiple regions, we could change this. It would be easier to do it when all drivers are converted to use driver model for PCI.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Update commit message to mention future work

drivers/pci/pci-uclass.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 6d860c4..7b48879 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -704,6 +704,7 @@ static int decode_regions(struct pci_controller *hose, const void *blob, int space_code; u32 flags; int type; + int pos;

if (len < cells_per_record) break; @@ -726,9 +727,15 @@ static int decode_regions(struct pci_controller *hose, const void *blob, } else { continue; } - debug(" - type=%d\n", type); - pci_set_region(hose->regions + hose->region_count++, pci_addr, - addr, size, type); + pos = -1; + for (i = 0; i < hose->region_count; i++) { + if (hose->regions[i].flags == type) + pos = i; + } + if (pos == -1) + pos = hose->region_count++; + debug(" - type=%d, pos=%d\n", type, pos); + pci_set_region(hose->regions + pos, pci_addr, addr, size, type); }

/* Add a region for our local memory */

A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device.

Signed-off-by: Simon Glass sjg@chromium.org Acked-by: Stephen Warren swarren@nvidia.com ---

Changes in v2: - Use the device_is_on_pci_bus() API

drivers/pci/pci-uclass.c | 8 ++++++++ include/pci.h | 8 ++++++++ 2 files changed, 16 insertions(+)

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index e38e0b2..f3f5f00 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -53,6 +53,14 @@ struct pci_controller *pci_bus_to_hose(int busnum) return dev_get_uclass_priv(bus); }

+struct udevice *pci_get_controller(struct udevice *dev) +{ + while (device_is_on_pci_bus(dev)) + dev = dev->parent; + + return dev; +} + pci_dev_t pci_get_bdf(struct udevice *dev) { struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); diff --git a/include/pci.h b/include/pci.h index ec2d104..f3dda70 100644 --- a/include/pci.h +++ b/include/pci.h @@ -1123,6 +1123,14 @@ ulong pci_conv_size_to_32(ulong old, ulong value, uint offset, enum pci_size_t size);

/** + * pci_get_controller() - obtain the controller to use for a bus + * + * @dev: Device to check + * @return pointer to the controller device for this bus + */ +struct udevice *pci_get_controller(struct udevice *dev); + +/** * struct dm_pci_emul_ops - PCI device emulator operations */ struct dm_pci_emul_ops {

Adjust the Tegra PCI driver to support driver model and move all boards over at the same time. This can make use of some generic driver model code, such as the range-decoding logic.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Leave pci_skip_dev() at the bottom of the file to reduce the diff size

arch/arm/mach-tegra/Kconfig | 1 + drivers/pci/pci_tegra.c | 394 +++++++++++++++----------------------------- include/fdtdec.h | 3 - lib/fdtdec.c | 3 - 4 files changed, 138 insertions(+), 263 deletions(-)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index de2454e..e5c135f 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -13,6 +13,7 @@ config TEGRA_ARMV7_COMMON select DM_SPI select DM_GPIO select DM_KEYBOARD + select DM_PCI

choice prompt "Tegra SoC select" diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index ebb959f..6bc91ec 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -10,10 +10,10 @@ * SPDX-License-Identifier: GPL-2.0 */

-#define DEBUG #define pr_fmt(fmt) "tegra-pcie: " fmt

#include <common.h> +#include <dm.h> #include <errno.h> #include <fdtdec.h> #include <malloc.h> @@ -174,7 +174,11 @@ DECLARE_GLOBAL_DATA_PTR; #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000

-struct tegra_pcie; +enum tegra_pci_id { + TEGRA20_PCIE, + TEGRA30_PCIE, + TEGRA124_PCIE, +};

struct tegra_pcie_port { struct tegra_pcie *pcie; @@ -203,10 +207,6 @@ struct tegra_pcie { struct fdt_resource afi; struct fdt_resource cs;

- struct fdt_resource prefetch; - struct fdt_resource mem; - struct fdt_resource io; - struct list_head ports; unsigned long xbar;

@@ -214,11 +214,6 @@ struct tegra_pcie { struct tegra_xusb_phy *phy; };

-static inline struct tegra_pcie *to_tegra_pcie(struct pci_controller *hose) -{ - return container_of(hose, struct tegra_pcie, hose); -} - static void afi_writel(struct tegra_pcie *pcie, unsigned long value, unsigned long offset) { @@ -280,46 +275,54 @@ static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf, return 0; }

- return -1; + return -EFAULT; }

-static int tegra_pcie_read_conf(struct pci_controller *hose, pci_dev_t bdf, - int where, u32 *value) +static int pci_tegra_read_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong *valuep, + enum pci_size_t size) { - struct tegra_pcie *pcie = to_tegra_pcie(hose); - unsigned long address; + struct tegra_pcie *pcie = dev_get_priv(bus); + unsigned long address, value; int err;

- err = tegra_pcie_conf_address(pcie, bdf, where, &address); + err = tegra_pcie_conf_address(pcie, bdf, offset, &address); if (err < 0) { - *value = 0xffffffff; - return 1; + value = 0xffffffff; + goto done; }

- *value = readl(address); + value = readl(address);

/* fixup root port class */ if (PCI_BUS(bdf) == 0) { - if (where == PCI_CLASS_REVISION) { - *value &= ~0x00ff0000; - *value |= PCI_CLASS_BRIDGE_PCI << 16; + if (offset == PCI_CLASS_REVISION) { + value &= ~0x00ff0000; + value |= PCI_CLASS_BRIDGE_PCI << 16; } }

+done: + *valuep = pci_conv_32_to_size(value, offset, size); + return 0; }

-static int tegra_pcie_write_conf(struct pci_controller *hose, pci_dev_t bdf, - int where, u32 value) +static int pci_tegra_write_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) { - struct tegra_pcie *pcie = to_tegra_pcie(hose); + struct tegra_pcie *pcie = dev_get_priv(bus); unsigned long address; + ulong old; int err;

- err = tegra_pcie_conf_address(pcie, bdf, where, &address); + err = tegra_pcie_conf_address(pcie, bdf, offset, &address); if (err < 0) - return 1; + return 0;

+ old = readl(address); + value = pci_conv_size_to_32(old, value, offset, size); writel(value, address);

return 0; @@ -344,12 +347,10 @@ static int tegra_pcie_port_parse_dt(const void *fdt, int node, }

static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes, - unsigned long *xbar) + enum tegra_pci_id id, unsigned long *xbar) { - enum fdt_compat_id id = fdtdec_lookup(fdt, node); - switch (id) { - case COMPAT_NVIDIA_TEGRA20_PCIE: + case TEGRA20_PCIE: switch (lanes) { case 0x00000004: debug("single-mode configuration\n"); @@ -362,8 +363,7 @@ static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes, return 0; } break; - - case COMPAT_NVIDIA_TEGRA30_PCIE: + case TEGRA30_PCIE: switch (lanes) { case 0x00000204: debug("4x1, 2x1 configuration\n"); @@ -381,8 +381,7 @@ static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes, return 0; } break; - - case COMPAT_NVIDIA_TEGRA124_PCIE: + case TEGRA124_PCIE: switch (lanes) { case 0x0000104: debug("4x1, 1x1 configuration\n"); @@ -395,7 +394,6 @@ static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes, return 0; } break; - default: break; } @@ -403,57 +401,6 @@ static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes, return -FDT_ERR_NOTFOUND; }

-static int tegra_pcie_parse_dt_ranges(const void *fdt, int node, - struct tegra_pcie *pcie) -{ - const u32 *ptr, *end; - int len; - - ptr = fdt_getprop(fdt, node, "ranges", &len); - if (!ptr) { - error("missing "ranges" property"); - return -FDT_ERR_NOTFOUND; - } - - end = ptr + len / 4; - - while (ptr < end) { - struct fdt_resource *res = NULL; - u32 space = fdt32_to_cpu(*ptr); - - switch ((space >> 24) & 0x3) { - case 0x01: - res = &pcie->io; - break; - - case 0x02: /* 32 bit */ - case 0x03: /* 64 bit */ - if (space & (1 << 30)) - res = &pcie->prefetch; - else - res = &pcie->mem; - - break; - } - - if (res) { - res->start = fdt32_to_cpu(ptr[3]); - res->end = res->start + fdt32_to_cpu(ptr[5]); - } - - ptr += 3 + 1 + 2; - } - - debug("PCI regions:\n"); - debug(" I/O: %pa-%pa\n", &pcie->io.start, &pcie->io.end); - debug(" non-prefetchable memory: %pa-%pa\n", &pcie->mem.start, - &pcie->mem.end); - debug(" prefetchable memory: %pa-%pa\n", &pcie->prefetch.start, - &pcie->prefetch.end); - - return 0; -} - static int tegra_pcie_parse_port_info(const void *fdt, int node, unsigned int *index, unsigned int *lanes) @@ -480,7 +427,7 @@ static int tegra_pcie_parse_port_info(const void *fdt, int node, return 0; }

-static int tegra_pcie_parse_dt(const void *fdt, int node, +static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id, struct tegra_pcie *pcie) { int err, subnode; @@ -516,12 +463,6 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, } }

- err = tegra_pcie_parse_dt_ranges(fdt, node, pcie); - if (err < 0) { - error("failed to parse "ranges" property"); - return err; - } - fdt_for_each_subnode(fdt, subnode, node) { unsigned int index = 0, num_lanes = 0; struct tegra_pcie_port *port; @@ -556,7 +497,7 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, port->pcie = pcie; }

- err = tegra_pcie_get_xbar_config(fdt, node, lanes, &pcie->xbar); + err = tegra_pcie_get_xbar_config(fdt, node, lanes, id, &pcie->xbar); if (err < 0) { error("invalid lane configuration"); return err; @@ -758,9 +699,12 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) return 0; }

-static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) +static int tegra_pcie_setup_translations(struct udevice *bus) { + struct tegra_pcie *pcie = dev_get_priv(bus); unsigned long fpci, axi, size; + struct pci_region *io, *mem, *pref; + int count;

/* BAR 0: type 1 extended configuration space */ fpci = 0xfe100000; @@ -771,28 +715,32 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ); afi_writel(pcie, fpci, AFI_FPCI_BAR0);

+ count = pci_get_regions(bus, &io, &mem, &pref); + if (count != 3) + return -EINVAL; + /* BAR 1: downstream I/O */ fpci = 0xfdfc0000; - size = fdt_resource_size(&pcie->io); - axi = pcie->io.start; + size = io->size; + axi = io->phys_start;

afi_writel(pcie, axi, AFI_AXI_BAR1_START); afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ); afi_writel(pcie, fpci, AFI_FPCI_BAR1);

/* BAR 2: prefetchable memory */ - fpci = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1; - size = fdt_resource_size(&pcie->prefetch); - axi = pcie->prefetch.start; + fpci = (((pref->phys_start >> 12) & 0x0fffffff) << 4) | 0x1; + size = pref->size; + axi = pref->phys_start;

afi_writel(pcie, axi, AFI_AXI_BAR2_START); afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ); afi_writel(pcie, fpci, AFI_FPCI_BAR2);

/* BAR 3: non-prefetchable memory */ - fpci = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1; - size = fdt_resource_size(&pcie->mem); - axi = pcie->mem.start; + fpci = (((mem->phys_start >> 12) & 0x0fffffff) << 4) | 0x1; + size = mem->size; + axi = mem->phys_start;

afi_writel(pcie, axi, AFI_AXI_BAR3_START); afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ); @@ -818,6 +766,8 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) afi_writel(pcie, 0, AFI_MSI_BAR_SZ); afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST); afi_writel(pcie, 0, AFI_MSI_BAR_SZ); + + return 0; }

static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) @@ -964,175 +914,105 @@ static int tegra_pcie_enable(struct tegra_pcie *pcie) return 0; }

-static const struct tegra_pcie_soc tegra20_pcie_soc = { - .num_ports = 2, - .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, - .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, - .has_pex_clkreq_en = false, - .has_pex_bias_ctrl = false, - .has_cml_clk = false, - .has_gen2 = false, -}; - -static const struct tegra_pcie_soc tegra30_pcie_soc = { - .num_ports = 3, - .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, - .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, - .has_pex_clkreq_en = true, - .has_pex_bias_ctrl = true, - .has_cml_clk = true, - .has_gen2 = false, -}; - -static const struct tegra_pcie_soc tegra124_pcie_soc = { - .num_ports = 2, - .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, - .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, - .has_pex_clkreq_en = true, - .has_pex_bias_ctrl = true, - .has_cml_clk = true, - .has_gen2 = true, +static const struct tegra_pcie_soc pci_tegra_soc[] = { + [TEGRA20_PCIE] = { + .num_ports = 2, + .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, + .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, + .has_pex_clkreq_en = false, + .has_pex_bias_ctrl = false, + .has_cml_clk = false, + .has_gen2 = false, + }, + [TEGRA30_PCIE] = { + .num_ports = 3, + .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, + .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, + .has_pex_clkreq_en = true, + .has_pex_bias_ctrl = true, + .has_cml_clk = true, + .has_gen2 = false, + }, + [TEGRA124_PCIE] = { + .num_ports = 2, + .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, + .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, + .has_pex_clkreq_en = true, + .has_pex_bias_ctrl = true, + .has_cml_clk = true, + .has_gen2 = true, + } };

-static int process_nodes(const void *fdt, int nodes[], unsigned int count) +static int pci_tegra_ofdata_to_platdata(struct udevice *dev) { - unsigned int i; - - for (i = 0; i < count; i++) { - const struct tegra_pcie_soc *soc; - struct tegra_pcie *pcie; - enum fdt_compat_id id; - int err; - - if (!fdtdec_get_is_enabled(fdt, nodes[i])) - continue; - - id = fdtdec_lookup(fdt, nodes[i]); - switch (id) { - case COMPAT_NVIDIA_TEGRA20_PCIE: - soc = &tegra20_pcie_soc; - break; + struct tegra_pcie *pcie = dev_get_priv(dev); + enum tegra_pci_id id;

- case COMPAT_NVIDIA_TEGRA30_PCIE: - soc = &tegra30_pcie_soc; - break; + id = dev_get_driver_data(dev); + pcie->soc = &pci_tegra_soc[id];

- case COMPAT_NVIDIA_TEGRA124_PCIE: - soc = &tegra124_pcie_soc; - break; + INIT_LIST_HEAD(&pcie->ports);

- default: - error("unsupported compatible: %s", - fdtdec_get_compatible(id)); - continue; - } - - pcie = malloc(sizeof(*pcie)); - if (!pcie) { - error("failed to allocate controller"); - continue; - } - - memset(pcie, 0, sizeof(*pcie)); - pcie->soc = soc; - - INIT_LIST_HEAD(&pcie->ports); - - err = tegra_pcie_parse_dt(fdt, nodes[i], pcie); - if (err < 0) { - free(pcie); - continue; - } - - err = tegra_pcie_power_on(pcie); - if (err < 0) { - error("failed to power on"); - continue; - } - - err = tegra_pcie_enable_controller(pcie); - if (err < 0) { - error("failed to enable controller"); - continue; - } - - tegra_pcie_setup_translations(pcie); - - err = tegra_pcie_enable(pcie); - if (err < 0) { - error("failed to enable PCIe"); - continue; - } - - pcie->hose.first_busno = 0; - pcie->hose.current_busno = 0; - pcie->hose.last_busno = 0; + if (tegra_pcie_parse_dt(gd->fdt_blob, dev->of_offset, id, pcie)) + return -EINVAL;

- pci_set_region(&pcie->hose.regions[0], NV_PA_SDRAM_BASE, - NV_PA_SDRAM_BASE, gd->ram_size, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - pci_set_region(&pcie->hose.regions[1], pcie->io.start, - pcie->io.start, fdt_resource_size(&pcie->io), - PCI_REGION_IO); - - pci_set_region(&pcie->hose.regions[2], pcie->mem.start, - pcie->mem.start, fdt_resource_size(&pcie->mem), - PCI_REGION_MEM); - - pci_set_region(&pcie->hose.regions[3], pcie->prefetch.start, - pcie->prefetch.start, - fdt_resource_size(&pcie->prefetch), - PCI_REGION_MEM | PCI_REGION_PREFETCH); + return 0; +}

- pcie->hose.region_count = 4; +static int pci_tegra_probe(struct udevice *dev) +{ + struct tegra_pcie *pcie = dev_get_priv(dev); + int err;

- pci_set_ops(&pcie->hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - tegra_pcie_read_conf, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - tegra_pcie_write_conf); + err = tegra_pcie_power_on(pcie); + if (err < 0) { + error("failed to power on"); + return err; + }

- pci_register_hose(&pcie->hose); + err = tegra_pcie_enable_controller(pcie); + if (err < 0) { + error("failed to enable controller"); + return err; + }

-#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Enumerating devices...\n"); - printf("---------------------------------------\n"); - printf(" Device ID Description\n"); - printf(" ------ -- -----------\n"); -#endif + err = tegra_pcie_setup_translations(dev); + if (err < 0) { + error("failed to decode ranges"); + return err; + }

- pcie->hose.last_busno = pci_hose_scan(&pcie->hose); + err = tegra_pcie_enable(pcie); + if (err < 0) { + error("failed to enable PCIe"); + return err; }

return 0; }

-void pci_init_board(void) -{ - const void *fdt = gd->fdt_blob; - int count, nodes[1]; - - count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", - COMPAT_NVIDIA_TEGRA124_PCIE, - nodes, ARRAY_SIZE(nodes)); - if (process_nodes(fdt, nodes, count)) - return; - - count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", - COMPAT_NVIDIA_TEGRA30_PCIE, - nodes, ARRAY_SIZE(nodes)); - if (process_nodes(fdt, nodes, count)) - return; - - count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", - COMPAT_NVIDIA_TEGRA20_PCIE, - nodes, ARRAY_SIZE(nodes)); - if (process_nodes(fdt, nodes, count)) - return; -} +static const struct dm_pci_ops pci_tegra_ops = { + .read_config = pci_tegra_read_config, + .write_config = pci_tegra_write_config, +}; + +static const struct udevice_id pci_tegra_ids[] = { + { .compatible = "nvidia,tegra20-pcie", .data = TEGRA20_PCIE }, + { .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE }, + { .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE }, + { } +}; + +U_BOOT_DRIVER(pci_tegra) = { + .name = "pci_tegra", + .id = UCLASS_PCI, + .of_match = pci_tegra_ids, + .ops = &pci_tegra_ops, + .ofdata_to_platdata = pci_tegra_ofdata_to_platdata, + .probe = pci_tegra_probe, + .priv_auto_alloc_size = sizeof(struct tegra_pcie), +};

int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) { diff --git a/include/fdtdec.h b/include/fdtdec.h index a6a1ffc..7fe657d 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -128,9 +128,6 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */ COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */ COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */ - COMPAT_NVIDIA_TEGRA124_PCIE, /* Tegra 124 PCIe controller */ - COMPAT_NVIDIA_TEGRA30_PCIE, /* Tegra 30 PCIe controller */ - COMPAT_NVIDIA_TEGRA20_PCIE, /* Tegra 20 PCIe controller */ COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL, /* Tegra124 XUSB pad controller */ COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL, diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 6f08edf..82d0090 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -34,9 +34,6 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"), COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"), COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"), - COMPAT(NVIDIA_TEGRA124_PCIE, "nvidia,tegra124-pcie"), - COMPAT(NVIDIA_TEGRA30_PCIE, "nvidia,tegra30-pcie"), - COMPAT(NVIDIA_TEGRA20_PCIE, "nvidia,tegra20-pcie"), COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"), COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"), COMPAT(SMSC_LAN9215, "smsc,lan9215"),