[U-Boot] [PATCH 0/5] UniPhier updates for v2015.07-rc2
Masahiro Yamada (5): ARM: UniPhier: use 32 bit register access for debug UART setting ARM: UniPhier: remove unnecessary cache coherency code ARM: UniPhier: remove meaningless CONFIG_SPL_BUILD ifdefs ARM: UniPhier: move CONFIG_SYS_TEXT_BASE to Kconfig ARM: UniPhier: update DDR PHY register map for PH1-Pro5
Kconfig | 2 +- arch/arm/mach-uniphier/ddrphy_training.c | 9 +++------ arch/arm/mach-uniphier/include/mach/ddrphy-regs.h | 13 +++++++++---- arch/arm/mach-uniphier/include/mach/debug-uart.S | 9 +++++---- arch/arm/mach-uniphier/lowlevel_init.S | 20 -------------------- configs/ph1_ld4_defconfig | 1 + configs/ph1_pro4_defconfig | 1 + configs/ph1_sld8_defconfig | 1 + include/configs/uniphier.h | 2 -- 9 files changed, 21 insertions(+), 37 deletions(-)
For the same reason as commit d0c47b3ef7c5 (serial: UniPhier: use 32 bit register access), use "str" instead of "strb" for the LCR register setting.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/mach-uniphier/include/mach/debug-uart.S | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-uniphier/include/mach/debug-uart.S b/arch/arm/mach-uniphier/include/mach/debug-uart.S index af55fee..9ae2e18 100644 --- a/arch/arm/mach-uniphier/include/mach/debug-uart.S +++ b/arch/arm/mach-uniphier/include/mach/debug-uart.S @@ -1,6 +1,7 @@ /* - * Copyright (C) 2014 Panasonic Corporation - * Author: Masahiro Yamada yamada.m@jp.panasonic.com + * Copyright (C) 2014-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada yamada.masahiro@socionext.com * * SPDX-License-Identifier: GPL-2.0+ */ @@ -17,8 +18,8 @@
.macro init_debug_uart, ra, rb, rc addruart \ra, \rb, \rc - mov \rb, #UART_LCR_WLEN8 - strb \rb, [\ra, #0x11] + mov \rb, #UART_LCR_WLEN8 << 8 + str \rb, [\ra, #0x10] ldr \rb, =DIVISOR str \rb, [\ra, #0x24] .endm
Cache coherency for SMP is cared by Linux. In U-Boot, the secondary CPU(s) are just sleeping. Nothing in memory is shared with the primary CPU.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/mach-uniphier/lowlevel_init.S | 20 -------------------- 1 file changed, 20 deletions(-)
diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S index 825b160..aaea7bf 100644 --- a/arch/arm/mach-uniphier/lowlevel_init.S +++ b/arch/arm/mach-uniphier/lowlevel_init.S @@ -67,20 +67,6 @@ secondary_startup: * jump to Linux * kick secondaries ---(sev)---> jump to Linux */ - /* - * ACTLR (Auxiliary Control Register) for Cortex-A9 - * bit[9] Parity on - * bit[8] Alloc in one way - * bit[7] EXCL (Exclusive cache bit) - * bit[6] SMP - * bit[3] Write full line of zeros mode - * bit[2] L1 prefetch enable - * bit[1] L2 prefetch enable - * bit[0] FW (Cache and TLB maintenance broadcast) - */ - mrc p15, 0, r0, c1, c0, 1 @ ACTLR (Auxiliary Control Register) - orr r0, r0, #0x41 @ enable SMP, FW bit - mcr p15, 0, r0, c1, c0, 1
/* branch by CPU ID */ mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Register) @@ -112,12 +98,6 @@ primary_cpu: str r0, [r1] ldr r0, [r1] @ make sure str is complete before sev sev @ kick the secondary CPU - mrc p15, 4, r1, c15, c0, 0 @ Configuration Base Address Register - bfc r1, #0, #13 @ clear bit 12-0 - mov r0, #-1 - str r0, [r1, #SCU_INV_ALL] @ SCU Invalidate All Register - mov r0, #1 @ SCU enable - str r0, [r1, #SCU_CTRL] @ SCU Control Register #endif
bl setup_init_ram @ RAM area for temporary stack pointer
This file is only built for SPL. These ifdef conditionals are unnecessary because UniPhier platform now supports UART on SPL. Show appropriate messages on error.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/mach-uniphier/ddrphy_training.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-uniphier/ddrphy_training.c b/arch/arm/mach-uniphier/ddrphy_training.c index b1d46cf..5f3d591 100644 --- a/arch/arm/mach-uniphier/ddrphy_training.c +++ b/arch/arm/mach-uniphier/ddrphy_training.c @@ -1,6 +1,7 @@ /* - * Copyright (C) 2011-2014 Panasonic Corporation - * Author: Masahiro Yamada yamada.m@jp.panasonic.com + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada yamada.masahiro@socionext.com * * SPDX-License-Identifier: GPL-2.0+ */ @@ -116,10 +117,8 @@ int ddrphy_training(struct ddrphy __iomem *phy)
do { if (--timeout < 0) { -#ifndef CONFIG_SPL_BUILD printf("%s: error: timeout during DDR training\n", __func__); -#endif return -1; } udelay(1); @@ -128,10 +127,8 @@ int ddrphy_training(struct ddrphy __iomem *phy)
for (i = 0; i < ARRAY_SIZE(init_sequence); i++) { if (pgsr0 & init_sequence[i].err_flag) { -#ifndef CONFIG_SPL_BUILD printf("%s: error: %s failed\n", __func__, init_sequence[i].description); -#endif return -1; } }
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
Kconfig | 2 +- configs/ph1_ld4_defconfig | 1 + configs/ph1_pro4_defconfig | 1 + configs/ph1_sld8_defconfig | 1 + include/configs/uniphier.h | 2 -- 5 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/Kconfig b/Kconfig index 85faff7..15e15af 100644 --- a/Kconfig +++ b/Kconfig @@ -178,7 +178,7 @@ config SYS_EXTRA_OPTIONS new boards should not use this option.
config SYS_TEXT_BASE - depends on SPARC || ARC || X86 + depends on SPARC || ARC || X86 || ARCH_UNIPHIER hex "Text Base" help TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig index 036e2d1..b0e02a9 100644 --- a/configs/ph1_ld4_defconfig +++ b/configs/ph1_ld4_defconfig @@ -6,6 +6,7 @@ CONFIG_PFC_MICRO_SUPPORT_CARD=y CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_HUSH_PARSER=y CONFIG_CMD_BDI=y CONFIG_CMD_CONSOLE=y diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig index 9a010ee..af25a3c 100644 --- a/configs/ph1_pro4_defconfig +++ b/configs/ph1_pro4_defconfig @@ -6,6 +6,7 @@ CONFIG_PFC_MICRO_SUPPORT_CARD=y CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_HUSH_PARSER=y CONFIG_CMD_BDI=y CONFIG_CMD_CONSOLE=y diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig index 29fe0e8..9de6b92 100644 --- a/configs/ph1_sld8_defconfig +++ b/configs/ph1_sld8_defconfig @@ -6,6 +6,7 @@ CONFIG_PFC_MICRO_SUPPORT_CARD=y CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_HUSH_PARSER=y CONFIG_CMD_BDI=y CONFIG_CMD_CONSOLE=y diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 331df62..dd64cdc 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -266,8 +266,6 @@ #define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE) #endif
-#define CONFIG_SYS_TEXT_BASE 0x84000000 - #if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8) #define CONFIG_SPL_TEXT_BASE 0x00040000 #endif
PH1-Pro5 includes a newer version of DDR PHY IP. Some registers have been added to the reserved areas.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/mach-uniphier/include/mach/ddrphy-regs.h | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h index 6b7d600..df7d815 100644 --- a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h +++ b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h @@ -1,8 +1,9 @@ /* * UniPhier DDR PHY registers * - * Copyright (C) 2014 Panasonic Corporation - * Author: Masahiro Yamada yamada.m@jp.panasonic.com + * Copyright (C) 2014-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada yamada.masahiro@socionext.com * * SPDX-License-Identifier: GPL-2.0+ */ @@ -37,7 +38,10 @@ struct ddrphy { u32 dtar[4]; /* Data Training Address Register */ u32 dtdr[2]; /* Data Training Data Register */ u32 dtedr[2]; /* Data Training Eye Data Register */ - u32 rsv0[13]; /* Reserved */ + u32 pgcr2; /* PHY General Configuration Register 2 */ + u32 rsv0[8]; /* Reserved */ + u32 rdimmgcr[2]; /* RDIMM General Configuration Register */ + u32 rdimmcr0[2]; /* RDIMM Control Register */ u32 dcuar; /* DCU Address Register */ u32 dcudr; /* DCU Data Register */ u32 dcurr; /* DCU Run Register */ @@ -70,7 +74,8 @@ struct ddrphy { u32 lcdlr[3]; /* Local Calibrated Delay Line Register */ u32 mdlr; /* Master Delay Line Register */ u32 gtr; /* General Timing Register */ - u32 rsv[3]; /* Reserved */ + u32 gsr2; /* General Status Register 2 */ + u32 rsv[2]; /* Reserved */ } dx[9]; };
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Masahiro Yamada