[PATCH 00/12] rockchip: rk3399: Migrate to use TPL on bob and kevin
This is a continuation of an RFC [1] sent back in August.
All Rockchip aarch64 boards, beside bob and kevin, use TPL to initialize DRAM and SPL to load FIT with U-Boot proper and TF-A.
Bob and kevin currently does not use TPL and instead initialize DRAM in SPL and directly after tries to load a FIT with only U-Boot proper.
This series migrate bob and kevin to also use TPL to uniform TPL/SPL use for all Rockchip aarch64 boards.
Features and changes in this series: - Use of Rockchip aarch64 common bss and stack addresses - SHA256 checksum/signature check of FIT images in SPL - Use of dcache to speed up checksum check in SPL - SDMA use for eMMC access to speed up read/write in U-Boot proper - FIT location moved from 0x40000 to 0xE0000 in SPI flash
Changes sinc RFC: - Include pinctrl props and enable regulators based on DT in SPL - Drop bob and kevin board specific code from common rk3399.c
Please note that I do not have any bob or kevin so this has only been compile tested and the original RFC [1] was runtime tested by Simon.
[1] https://patchwork.ozlabs.org/patch/1967517/
Jonas Karlman (12): rockchip: rk3399: Fix TPL build of bob and kevin rockchip: rk3399-gru: Use SYS_SPI_U_BOOT_OFFS value in offset prop rockchip: rk3399-gru: Move SPI flash payload offset for bob and kevin rockchip: rk3399-gru: Fix include of TPL in u-boot.rom image rockchip: rk3399-gru: Use TPL with common bss and stack addresses rockchip: rk3399-gru: Include binman generated FIT in u-boot.rom image rockchip: rk3399: Drop common Kconfig options already implied rockchip: rk3399-gru: Remove unused nodes from xPL control FDT rockchip: rk3399-gru: Enable dcache and signature validation in SPL rockchip: rk3399-gru: Use SDMA mode to read from eMMC rockchip: rk3399-gru: Include pinctrl and regulators in SPL rockchip: rk3399: Drop unneeded bob and kevin board specific code
arch/arm/dts/rk3399-gru-u-boot.dtsi | 29 ++++++++++++++++++++++++-- arch/arm/dts/rk3399-u-boot.dtsi | 14 +++++++++++-- arch/arm/mach-rockchip/rk3399/Kconfig | 12 ----------- arch/arm/mach-rockchip/rk3399/rk3399.c | 23 +------------------- configs/chromebook_bob_defconfig | 23 ++++++-------------- configs/chromebook_kevin_defconfig | 23 ++++++-------------- 6 files changed, 52 insertions(+), 72 deletions(-)
Building chromebook_bob/kevin with TPL=y ends with a linking error:
arch/arm/mach-rockchip/rk3399/rk3399.o: in function `board_debug_uart_init': arch/arm/mach-rockchip/rk3399/rk3399.c:148:(.text.board_debug_uart_init+0x34): undefined reference to `spl_gpio_output' arch/arm/mach-rockchip/rk3399/rk3399.c:148:(.text.board_debug_uart_init+0x34): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `spl_gpio_output'
make[2]: *** [scripts/Makefile.xpl:542: tpl/u-boot-tpl] Error 1 make[1]: *** [Makefile:2134: tpl/u-boot-tpl] Error 2 make: *** [Makefile:568: __build_one_by_one] Error 2
Change to only use spl_gpio functions in SPL to fix this.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 0c28241c603e..ba89079b1e73 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -136,7 +136,7 @@ void board_debug_uart_init(void) struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
- if (IS_ENABLED(CONFIG_XPL_BUILD) && + if (IS_ENABLED(CONFIG_SPL_BUILD) && (IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) || IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) { rk_setreg(&grf->io_vsel, 1 << 0);
On 2024/12/13 07:57, Jonas Karlman wrote:
Building chromebook_bob/kevin with TPL=y ends with a linking error:
arch/arm/mach-rockchip/rk3399/rk3399.o: in function `board_debug_uart_init': arch/arm/mach-rockchip/rk3399/rk3399.c:148:(.text.board_debug_uart_init+0x34): undefined reference to `spl_gpio_output' arch/arm/mach-rockchip/rk3399/rk3399.c:148:(.text.board_debug_uart_init+0x34): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `spl_gpio_output'
make[2]: *** [scripts/Makefile.xpl:542: tpl/u-boot-tpl] Error 1 make[1]: *** [Makefile:2134: tpl/u-boot-tpl] Error 2 make: *** [Makefile:568: __build_one_by_one] Error 2
Change to only use spl_gpio functions in SPL to fix this.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 0c28241c603e..ba89079b1e73 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -136,7 +136,7 @@ void board_debug_uart_init(void) struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
- if (IS_ENABLED(CONFIG_XPL_BUILD) &&
- if (IS_ENABLED(CONFIG_SPL_BUILD) && (IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) || IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) { rk_setreg(&grf->io_vsel, 1 << 0);
Use the offset configured with SYS_SPI_U_BOOT_OFFS Kconfig option instead of a hardcoded 0x40000 for the FIT payload offset.
This has no intended impact as SYS_SPI_U_BOOT_OFFS=0x40000.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-gru-u-boot.dtsi | 2 +- arch/arm/dts/rk3399-u-boot.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi index 6bdc892bd913..2505d9b01b8a 100644 --- a/arch/arm/dts/rk3399-gru-u-boot.dtsi +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi @@ -11,7 +11,7 @@ };
config { - u-boot,spl-payload-offset = <0x40000>; + u-boot,spl-payload-offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>; }; };
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 2bec139d8338..81a3c6fc972b 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -43,7 +43,7 @@ }; }; u-boot-img { - offset = <0x40000>; + offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>; }; u-boot { offset = <0x300000>;
On 2024/12/13 07:57, Jonas Karlman wrote:
Use the offset configured with SYS_SPI_U_BOOT_OFFS Kconfig option instead of a hardcoded 0x40000 for the FIT payload offset.
This has no intended impact as SYS_SPI_U_BOOT_OFFS=0x40000.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-gru-u-boot.dtsi | 2 +- arch/arm/dts/rk3399-u-boot.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi index 6bdc892bd913..2505d9b01b8a 100644 --- a/arch/arm/dts/rk3399-gru-u-boot.dtsi +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi @@ -11,7 +11,7 @@ };
config {
u-boot,spl-payload-offset = <0x40000>;
u-boot,spl-payload-offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 2bec139d8338..81a3c6fc972b 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -43,7 +43,7 @@ }; }; u-boot-img {
offset = <0x40000>;
offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
The BootROM on RK3399 only read the first 2 KB of each 4 KB page from SPI flash. With current FIT payload offset of 0x40000 this limits the supported TPL+SPL size to only 128 KB.
Change to use 0xE0000 as FIT payload offset, similar to other RK3399 boards, to allow a maximum size for TPL of 192 KB and SPL of 256 KB.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- configs/chromebook_bob_defconfig | 2 +- configs/chromebook_kevin_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index decac2e19352..69a07ef7e01e 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -44,7 +44,7 @@ CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 5bbea6c42a8b..d689eeaf2781 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -45,7 +45,7 @@ CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y
On 2024/12/13 07:57, Jonas Karlman wrote:
The BootROM on RK3399 only read the first 2 KB of each 4 KB page from SPI flash. With current FIT payload offset of 0x40000 this limits the supported TPL+SPL size to only 128 KB.
Change to use 0xE0000 as FIT payload offset, similar to other RK3399 boards, to allow a maximum size for TPL of 192 KB and SPL of 256 KB.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
configs/chromebook_bob_defconfig | 2 +- configs/chromebook_kevin_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index decac2e19352..69a07ef7e01e 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -44,7 +44,7 @@ CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 5bbea6c42a8b..d689eeaf2781 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -45,7 +45,7 @@ CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y
The chromebook specific u-boot.rom image does not include TPL when building with TPL=y or ROCKCHIP_EXTERNAL_TPL=y.
Fix this by adding rockchip-tpl and u-boot-tpl nodes to the mkimage node for the u-boot.rom binman image.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-u-boot.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 81a3c6fc972b..bd7527dde223 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -39,6 +39,14 @@
mkimage { args = "-n rk3399 -T rkspi"; + multiple-data-files; +#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL + rockchip-tpl { + }; +#elif defined(CONFIG_TPL) + u-boot-tpl { + }; +#endif u-boot-spl { }; };
On 2024/12/13 07:57, Jonas Karlman wrote:
The chromebook specific u-boot.rom image does not include TPL when building with TPL=y or ROCKCHIP_EXTERNAL_TPL=y.
Fix this by adding rockchip-tpl and u-boot-tpl nodes to the mkimage node for the u-boot.rom binman image.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-u-boot.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 81a3c6fc972b..bd7527dde223 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -39,6 +39,14 @@
mkimage { args = "-n rk3399 -T rkspi";
multiple-data-files;+#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL
rockchip-tpl {};+#elif defined(CONFIG_TPL)
u-boot-tpl {};+#endif u-boot-spl { }; };
Migrate to use TPL, common bss, stack and malloc heap size and addresses to unify memory use in TPL, SPL and pre-reloc with other RK3399 boards.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- configs/chromebook_bob_defconfig | 13 +------------ configs/chromebook_kevin_defconfig | 13 +------------ 2 files changed, 2 insertions(+), 24 deletions(-)
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 69a07ef7e01e..f13c4c1e7d63 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -3,26 +3,15 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-gru-bob" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0 -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 # CONFIG_SPL_MMC is not set -CONFIG_SPL_STACK=0xff8effff -CONFIG_SPL_TEXT_BASE=0xff8c2000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e0000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_SF_DEFAULT_BUS=1 CONFIG_DEBUG_UART_BASE=0xff1a0000 @@ -42,10 +31,10 @@ CONFIG_SPL_MAX_SIZE=0x1e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index d689eeaf2781..7a2b8e70fe69 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -3,27 +3,16 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-gru-kevin" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0 -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 # CONFIG_SPL_MMC is not set CONFIG_TARGET_CHROMEBOOK_KEVIN=y -CONFIG_SPL_STACK=0xff8effff -CONFIG_SPL_TEXT_BASE=0xff8c2000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e0000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_SF_DEFAULT_BUS=1 CONFIG_DEBUG_UART_BASE=0xff1a0000 @@ -43,10 +32,10 @@ CONFIG_SPL_MAX_SIZE=0x1e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y
On 2024/12/13 07:57, Jonas Karlman wrote:
Migrate to use TPL, common bss, stack and malloc heap size and addresses to unify memory use in TPL, SPL and pre-reloc with other RK3399 boards.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
configs/chromebook_bob_defconfig | 13 +------------ configs/chromebook_kevin_defconfig | 13 +------------ 2 files changed, 2 insertions(+), 24 deletions(-)
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 69a07ef7e01e..f13c4c1e7d63 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -3,26 +3,15 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-gru-bob" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0 -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 # CONFIG_SPL_MMC is not set -CONFIG_SPL_STACK=0xff8effff -CONFIG_SPL_TEXT_BASE=0xff8c2000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e0000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_SF_DEFAULT_BUS=1 CONFIG_DEBUG_UART_BASE=0xff1a0000 @@ -42,10 +31,10 @@ CONFIG_SPL_MAX_SIZE=0x1e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index d689eeaf2781..7a2b8e70fe69 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -3,27 +3,16 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-gru-kevin" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0 -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 # CONFIG_SPL_MMC is not set CONFIG_TARGET_CHROMEBOOK_KEVIN=y -CONFIG_SPL_STACK=0xff8effff -CONFIG_SPL_TEXT_BASE=0xff8c2000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e0000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_SF_DEFAULT_BUS=1 CONFIG_DEBUG_UART_BASE=0xff1a0000 @@ -43,10 +32,10 @@ CONFIG_SPL_MAX_SIZE=0x1e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y
The u-boot.rom image contain u-boot.img FIT instead of the FIT generated by binman for the u-boot-rockchip.bin image.
Change to include the binman generated FIT for the u-boot.rom image.
This change result in TF-A being included and the use sha256 instead of crc32 checksum in the u-boot.rom FIT.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-u-boot.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index bd7527dde223..70f35b6c197a 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -50,7 +50,9 @@ u-boot-spl { }; }; - u-boot-img { + fit { + type = "blob"; + filename = "u-boot.itb"; offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>; }; u-boot {
Hi Jonas,
On 12/13/24 12:57 AM, Jonas Karlman wrote:
The u-boot.rom image contain u-boot.img FIT instead of the FIT generated by binman for the u-boot-rockchip.bin image.
Change to include the binman generated FIT for the u-boot.rom image.
This change result in TF-A being included and the use sha256 instead of crc32 checksum in the u-boot.rom FIT.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
IIRC Simon was fine with removing u-boot.rom support for RK3399 when I asked months (probably years?) ago, if that hasn't changed, maybe we should now.
Especially since the only RK3399 with CONGIG_HAS_ROM set are Bob and Kevin.
@Simon, you said you tested the patch series on them, with which image did you do that? Are you still fine with removing the u-boot.rom for RK3399?
Cheers, Quentin
Hi Quentin and Simon,
On 2024-12-13 15:30, Quentin Schulz wrote:
Hi Jonas,
On 12/13/24 12:57 AM, Jonas Karlman wrote:
The u-boot.rom image contain u-boot.img FIT instead of the FIT generated by binman for the u-boot-rockchip.bin image.
Change to include the binman generated FIT for the u-boot.rom image.
This change result in TF-A being included and the use sha256 instead of crc32 checksum in the u-boot.rom FIT.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
IIRC Simon was fine with removing u-boot.rom support for RK3399 when I asked months (probably years?) ago, if that hasn't changed, maybe we should now.
Good to know and fully agree, we should try to remove it now.
I did a compare between u-boot-rockchip-spi.bin and u-boot.rom and after this series they are now identical for the full size of u-boot-rockchip-spi.bin.
However, the u-boot.rom also has a copy of ~u-boot.bin and a fdtmap starting at 0x300000. I have no idea if they are used for anything, if they are it is probably not for bare metal booting (TPL+SPL).
Regards, Jonas
Especially since the only RK3399 with CONGIG_HAS_ROM set are Bob and Kevin.
@Simon, you said you tested the patch series on them, with which image did you do that? Are you still fine with removing the u-boot.rom for RK3399?
Cheers, Quentin
On 2024/12/13 07:57, Jonas Karlman wrote:
The u-boot.rom image contain u-boot.img FIT instead of the FIT generated by binman for the u-boot-rockchip.bin image.
Change to include the binman generated FIT for the u-boot.rom image.
This change result in TF-A being included and the use sha256 instead of crc32 checksum in the u-boot.rom FIT.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-u-boot.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index bd7527dde223..70f35b6c197a 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -50,7 +50,9 @@ u-boot-spl { }; };
u-boot-img {
fit {type = "blob";filename = "u-boot.itb"; offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
The last two RK3399 boards, chromebook bob and kevin, have now migraded to use common bss and stack addresses.
Cleanup and remove Kconfig options no longer needed in rk3399/Kconfig when all boards now use common bss and stack addresses.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/mach-rockchip/rk3399/Kconfig | 12 ------------ 1 file changed, 12 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 04a84e2f6a04..500cfcd87afd 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -146,15 +146,6 @@ config SYS_SOC config ROCKCHIP_COMMON_STACK_ADDR default y
-config SYS_MALLOC_F_LEN - default 0x4000 if !SPL_SHARES_INIT_SP_ADDR - -config SPL_LIBCOMMON_SUPPORT - default y - -config SPL_LIBGENERIC_SUPPORT - default y - config TPL_LDSCRIPT default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
@@ -164,9 +155,6 @@ config TPL_STACK config TPL_TEXT_BASE default 0xff8c2000
-config SPL_STACK_R_ADDR - default 0x04000000 if !SPL_SHARES_INIT_SP_ADDR - if BOOTCOUNT_LIMIT
config BOOTCOUNT_BOOTLIMIT
On 2024/12/13 07:57, Jonas Karlman wrote:
The last two RK3399 boards, chromebook bob and kevin, have now migraded to use common bss and stack addresses.
Cleanup and remove Kconfig options no longer needed in rk3399/Kconfig when all boards now use common bss and stack addresses.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/mach-rockchip/rk3399/Kconfig | 12 ------------ 1 file changed, 12 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 04a84e2f6a04..500cfcd87afd 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -146,15 +146,6 @@ config SYS_SOC config ROCKCHIP_COMMON_STACK_ADDR default y
-config SYS_MALLOC_F_LEN
- default 0x4000 if !SPL_SHARES_INIT_SP_ADDR
-config SPL_LIBCOMMON_SUPPORT
- default y
-config SPL_LIBGENERIC_SUPPORT
- default y
- config TPL_LDSCRIPT default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
@@ -164,9 +155,6 @@ config TPL_STACK config TPL_TEXT_BASE default 0xff8c2000
-config SPL_STACK_R_ADDR
default 0x04000000 if !SPL_SHARES_INIT_SP_ADDR
if BOOTCOUNT_LIMIT
config BOOTCOUNT_BOOTLIMIT
The eMMC PHY and SPI flash is not used in all xPL phases.
Change to no longer include emmc_phy and spi_flash in all xPL phases.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-gru-u-boot.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi index 2505d9b01b8a..5f44327736df 100644 --- a/arch/arm/dts/rk3399-gru-u-boot.dtsi +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi @@ -29,6 +29,11 @@ rockchip,panel = <&edp_panel>; };
+&emmc_phy { + /delete-property/ bootph-pre-ram; +}; + + &pp1800_audio { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -80,7 +85,8 @@
&spi1 { spi_flash: flash@0 { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; };
On 2024/12/13 07:57, Jonas Karlman wrote:
The eMMC PHY and SPI flash is not used in all xPL phases.
Change to no longer include emmc_phy and spi_flash in all xPL phases.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-gru-u-boot.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi index 2505d9b01b8a..5f44327736df 100644 --- a/arch/arm/dts/rk3399-gru-u-boot.dtsi +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi @@ -29,6 +29,11 @@ rockchip,panel = <&edp_panel>; };
+&emmc_phy {
- /delete-property/ bootph-pre-ram;
+};
- &pp1800_audio { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
@@ -80,7 +85,8 @@
&spi1 { spi_flash: flash@0 {
bootph-all;
bootph-pre-ram;bootph-some-ram;
With TPL being used to init DRAM, SPL being used to load FIT and the adjusted FIT payload offset it is now possible to increase the size limit of SPL to 256 KB and enable uses of dcache and FIT signature validation.
Drop SPL_SYS_DCACHE_OFF=y to enable use of dcache in SPL.
Drop SPL_FIT_SIGNATURE=n to enable signature validation of FIT in SPL.
Change SPL_MAX_SIZE to 256 KB now that payload offset has moved in SPI and TF-A may be loaded to 0x40000 in DRAM.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- configs/chromebook_bob_defconfig | 4 +--- configs/chromebook_kevin_defconfig | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index f13c4c1e7d63..9a0f7cf8236a 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y @@ -19,7 +18,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y -# CONFIG_SPL_FIT_SIGNATURE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -27,7 +25,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BLOBLIST=y CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 -CONFIG_SPL_MAX_SIZE=0x1e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 7a2b8e70fe69..d70ec74f7f87 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y @@ -20,7 +19,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y -# CONFIG_SPL_FIT_SIGNATURE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -28,7 +26,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BLOBLIST=y CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 -CONFIG_SPL_MAX_SIZE=0x1e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
On 2024/12/13 07:57, Jonas Karlman wrote:
With TPL being used to init DRAM, SPL being used to load FIT and the adjusted FIT payload offset it is now possible to increase the size limit of SPL to 256 KB and enable uses of dcache and FIT signature validation.
Drop SPL_SYS_DCACHE_OFF=y to enable use of dcache in SPL.
Drop SPL_FIT_SIGNATURE=n to enable signature validation of FIT in SPL.
Change SPL_MAX_SIZE to 256 KB now that payload offset has moved in SPI and TF-A may be loaded to 0x40000 in DRAM.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
configs/chromebook_bob_defconfig | 4 +--- configs/chromebook_kevin_defconfig | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index f13c4c1e7d63..9a0f7cf8236a 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y @@ -19,7 +18,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y -# CONFIG_SPL_FIT_SIGNATURE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -27,7 +25,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BLOBLIST=y CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 -CONFIG_SPL_MAX_SIZE=0x1e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 7a2b8e70fe69..d70ec74f7f87 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y @@ -20,7 +19,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y -# CONFIG_SPL_FIT_SIGNATURE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -28,7 +26,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BLOBLIST=y CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 -CONFIG_SPL_MAX_SIZE=0x1e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Enable use of SDMA mode when reading from eMMC to speed up boot.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- configs/chromebook_bob_defconfig | 1 + configs/chromebook_kevin_defconfig | 1 + 2 files changed, 2 insertions(+)
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 9a0f7cf8236a..af9df4700e35 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -63,6 +63,7 @@ CONFIG_MMC_PWRSEQ=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index d70ec74f7f87..cc51722b521b 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -64,6 +64,7 @@ CONFIG_MMC_PWRSEQ=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y
On 2024/12/13 07:57, Jonas Karlman wrote:
Enable use of SDMA mode when reading from eMMC to speed up boot.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
configs/chromebook_bob_defconfig | 1 + configs/chromebook_kevin_defconfig | 1 + 2 files changed, 2 insertions(+)
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 9a0f7cf8236a..af9df4700e35 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -63,6 +63,7 @@ CONFIG_MMC_PWRSEQ=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index d70ec74f7f87..cc51722b521b 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -64,6 +64,7 @@ CONFIG_MMC_PWRSEQ=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y
Add bootph props and enable related Kconfig options to include vital regulators in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-gru-u-boot.dtsi | 19 +++++++++++++++++++ configs/chromebook_bob_defconfig | 3 ++- configs/chromebook_kevin_defconfig | 3 ++- 3 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi index 5f44327736df..5517176aa4a0 100644 --- a/arch/arm/dts/rk3399-gru-u-boot.dtsi +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi @@ -33,12 +33,31 @@ /delete-property/ bootph-pre-ram; };
+&gpio0 { + bootph-pre-ram; +}; + +&pp1500_ap_io { + bootph-pre-ram; +};
&pp1800_audio { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; };
+&pp1500_en { + bootph-pre-ram; +}; + +&pp3000 { + bootph-pre-ram; +}; + +&pp3000_en { + bootph-pre-ram; +}; + &ppvar_bigcpu_pwm { regulator-init-microvolt = <900000>; }; diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index af9df4700e35..8cdfb64462f1 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -47,7 +47,7 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_LOG=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -73,6 +73,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_CROS_EC=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index cc51722b521b..3992b3da092f 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -48,7 +48,7 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_LOG=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -74,6 +74,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_CROS_EC=y
On 2024/12/13 07:57, Jonas Karlman wrote:
Add bootph props and enable related Kconfig options to include vital regulators in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-gru-u-boot.dtsi | 19 +++++++++++++++++++ configs/chromebook_bob_defconfig | 3 ++- configs/chromebook_kevin_defconfig | 3 ++- 3 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi index 5f44327736df..5517176aa4a0 100644 --- a/arch/arm/dts/rk3399-gru-u-boot.dtsi +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi @@ -33,12 +33,31 @@ /delete-property/ bootph-pre-ram; };
+&gpio0 {
- bootph-pre-ram;
+};
+&pp1500_ap_io {
- bootph-pre-ram;
+};
&pp1800_audio { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; };
+&pp1500_en {
- bootph-pre-ram;
+};
+&pp3000 {
- bootph-pre-ram;
+};
+&pp3000_en {
- bootph-pre-ram;
+};
- &ppvar_bigcpu_pwm { regulator-init-microvolt = <900000>; };
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index af9df4700e35..8cdfb64462f1 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -47,7 +47,7 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_LOG=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -73,6 +73,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_CROS_EC=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index cc51722b521b..3992b3da092f 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -48,7 +48,7 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_LOG=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -74,6 +74,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_CROS_EC=y
The IO-domain driver will configure io_vsel and always-on/boot-on regulators will be enabled based on the board device tree now that required nodes and Kconfig options is enabled for SPL.
Remove the bob and kevin board specific code from the common rk3399.c, the IO-domain and regulator driver provide similar functionality.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/mach-rockchip/rk3399/rk3399.c | 23 +---------------------- 1 file changed, 1 insertion(+), 22 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index ba89079b1e73..1ce43c6f0d40 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -7,7 +7,6 @@ #include <init.h> #include <log.h> #include <spl.h> -#include <spl_gpio.h> #include <syscon.h> #include <asm/armv8/mmu.h> #include <asm/arch-rockchip/bootrom.h> @@ -16,6 +15,7 @@ #include <asm/arch-rockchip/gpio.h> #include <asm/arch-rockchip/grf_rk3399.h> #include <asm/arch-rockchip/hardware.h> +#include <asm/gpio.h> #include <linux/bitops.h> #include <linux/printk.h> #include <power/regulator.h> @@ -133,27 +133,6 @@ void board_debug_uart_init(void) GRF_GPIO3B7_SEL_MASK, GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT); #else - struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; - struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; - - if (IS_ENABLED(CONFIG_SPL_BUILD) && - (IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) || - IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) { - rk_setreg(&grf->io_vsel, 1 << 0); - - /* - * Let's enable these power rails here, we are already running - * the SPI-Flash-based code. - */ - spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */ - spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), - GPIO_PULL_NORMAL); - - spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */ - spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), - GPIO_PULL_NORMAL); - } - /* Enable early UART2 channel C on the RK3399 */ rk_clrsetreg(&grf->gpio4c_iomux, GRF_GPIO4C3_SEL_MASK,
Hi Jonas,
On Thu, 12 Dec 2024 at 16:57, Jonas Karlman jonas@kwiboo.se wrote:
This is a continuation of an RFC [1] sent back in August.
All Rockchip aarch64 boards, beside bob and kevin, use TPL to initialize DRAM and SPL to load FIT with U-Boot proper and TF-A.
Bob and kevin currently does not use TPL and instead initialize DRAM in SPL and directly after tries to load a FIT with only U-Boot proper.
This series migrate bob and kevin to also use TPL to uniform TPL/SPL use for all Rockchip aarch64 boards.
Features and changes in this series:
- Use of Rockchip aarch64 common bss and stack addresses
- SHA256 checksum/signature check of FIT images in SPL
- Use of dcache to speed up checksum check in SPL
- SDMA use for eMMC access to speed up read/write in U-Boot proper
- FIT location moved from 0x40000 to 0xE0000 in SPI flash
Changes sinc RFC:
- Include pinctrl props and enable regulators based on DT in SPL
- Drop bob and kevin board specific code from common rk3399.c
Please note that I do not have any bob or kevin so this has only been compile tested and the original RFC [1] was runtime tested by Simon.
[1] https://patchwork.ozlabs.org/patch/1967517/
Jonas Karlman (12): rockchip: rk3399: Fix TPL build of bob and kevin rockchip: rk3399-gru: Use SYS_SPI_U_BOOT_OFFS value in offset prop rockchip: rk3399-gru: Move SPI flash payload offset for bob and kevin rockchip: rk3399-gru: Fix include of TPL in u-boot.rom image rockchip: rk3399-gru: Use TPL with common bss and stack addresses rockchip: rk3399-gru: Include binman generated FIT in u-boot.rom image rockchip: rk3399: Drop common Kconfig options already implied rockchip: rk3399-gru: Remove unused nodes from xPL control FDT rockchip: rk3399-gru: Enable dcache and signature validation in SPL rockchip: rk3399-gru: Use SDMA mode to read from eMMC rockchip: rk3399-gru: Include pinctrl and regulators in SPL rockchip: rk3399: Drop unneeded bob and kevin board specific code
arch/arm/dts/rk3399-gru-u-boot.dtsi | 29 ++++++++++++++++++++++++-- arch/arm/dts/rk3399-u-boot.dtsi | 14 +++++++++++-- arch/arm/mach-rockchip/rk3399/Kconfig | 12 ----------- arch/arm/mach-rockchip/rk3399/rk3399.c | 23 +------------------- configs/chromebook_bob_defconfig | 23 ++++++-------------- configs/chromebook_kevin_defconfig | 23 ++++++-------------- 6 files changed, 52 insertions(+), 72 deletions(-)
Thank you for doing this!
I'm not sure if you have access to your own denx tree. If so, kevin and bob are in the sjg lab. If not, you can sign up at sjg.u-boot.org to get access to my tree.
This series eems to work for me, except for the final commit, which hangs with no output.
Regards, Simon
Hi Simon,
On 2024-12-13 04:09, Simon Glass wrote:
Hi Jonas,
On Thu, 12 Dec 2024 at 16:57, Jonas Karlman jonas@kwiboo.se wrote:
This is a continuation of an RFC [1] sent back in August.
All Rockchip aarch64 boards, beside bob and kevin, use TPL to initialize DRAM and SPL to load FIT with U-Boot proper and TF-A.
Bob and kevin currently does not use TPL and instead initialize DRAM in SPL and directly after tries to load a FIT with only U-Boot proper.
This series migrate bob and kevin to also use TPL to uniform TPL/SPL use for all Rockchip aarch64 boards.
Features and changes in this series:
- Use of Rockchip aarch64 common bss and stack addresses
- SHA256 checksum/signature check of FIT images in SPL
- Use of dcache to speed up checksum check in SPL
- SDMA use for eMMC access to speed up read/write in U-Boot proper
- FIT location moved from 0x40000 to 0xE0000 in SPI flash
Changes sinc RFC:
- Include pinctrl props and enable regulators based on DT in SPL
- Drop bob and kevin board specific code from common rk3399.c
Please note that I do not have any bob or kevin so this has only been compile tested and the original RFC [1] was runtime tested by Simon.
[1] https://patchwork.ozlabs.org/patch/1967517/
Jonas Karlman (12): rockchip: rk3399: Fix TPL build of bob and kevin rockchip: rk3399-gru: Use SYS_SPI_U_BOOT_OFFS value in offset prop rockchip: rk3399-gru: Move SPI flash payload offset for bob and kevin rockchip: rk3399-gru: Fix include of TPL in u-boot.rom image rockchip: rk3399-gru: Use TPL with common bss and stack addresses rockchip: rk3399-gru: Include binman generated FIT in u-boot.rom image rockchip: rk3399: Drop common Kconfig options already implied rockchip: rk3399-gru: Remove unused nodes from xPL control FDT rockchip: rk3399-gru: Enable dcache and signature validation in SPL rockchip: rk3399-gru: Use SDMA mode to read from eMMC rockchip: rk3399-gru: Include pinctrl and regulators in SPL rockchip: rk3399: Drop unneeded bob and kevin board specific code
arch/arm/dts/rk3399-gru-u-boot.dtsi | 29 ++++++++++++++++++++++++-- arch/arm/dts/rk3399-u-boot.dtsi | 14 +++++++++++-- arch/arm/mach-rockchip/rk3399/Kconfig | 12 ----------- arch/arm/mach-rockchip/rk3399/rk3399.c | 23 +------------------- configs/chromebook_bob_defconfig | 23 ++++++-------------- configs/chromebook_kevin_defconfig | 23 ++++++-------------- 6 files changed, 52 insertions(+), 72 deletions(-)
Thank you for doing this!
I'm not sure if you have access to your own denx tree. If so, kevin and bob are in the sjg lab. If not, you can sign up at sjg.u-boot.org to get access to my tree.
I do not have access to my own tree.
This series eems to work for me, except for the final commit, which hangs with no output.
Strange, guess we can just skip the last patch, should I send a v2 without the last patch?
I wonder if it is not setting io_vsel or the regulators that is causing an issue. Setting io_vsel is probably delayed until U-Boot proper instead of being set very early in SPL (due to no IO-domain driver in SPL), and enable of regulators may happen later in SPL with the last patch applied.
There is also some code in board/google/gru/gru.c that mention a delay related to the regulators may be needed, however board_early_init_f() is never called as following can be found in .config:
# CONFIG_BOARD_EARLY_INIT_F is not set
Will you be able to test with just the rk_setreg(&grf->io_vsel, 1 << 0); and remove the spl_gpio_output/set_pull parts of the last patch before I send a v2?
Regards, Jonas
Regards, Simon
On Fri, Dec 20, 2024 at 05:22:28PM +0100, Jonas Karlman wrote:
Hi Simon,
On 2024-12-13 04:09, Simon Glass wrote:
Hi Jonas,
On Thu, 12 Dec 2024 at 16:57, Jonas Karlman jonas@kwiboo.se wrote:
This is a continuation of an RFC [1] sent back in August.
All Rockchip aarch64 boards, beside bob and kevin, use TPL to initialize DRAM and SPL to load FIT with U-Boot proper and TF-A.
Bob and kevin currently does not use TPL and instead initialize DRAM in SPL and directly after tries to load a FIT with only U-Boot proper.
This series migrate bob and kevin to also use TPL to uniform TPL/SPL use for all Rockchip aarch64 boards.
Features and changes in this series:
- Use of Rockchip aarch64 common bss and stack addresses
- SHA256 checksum/signature check of FIT images in SPL
- Use of dcache to speed up checksum check in SPL
- SDMA use for eMMC access to speed up read/write in U-Boot proper
- FIT location moved from 0x40000 to 0xE0000 in SPI flash
Changes sinc RFC:
- Include pinctrl props and enable regulators based on DT in SPL
- Drop bob and kevin board specific code from common rk3399.c
Please note that I do not have any bob or kevin so this has only been compile tested and the original RFC [1] was runtime tested by Simon.
[1] https://patchwork.ozlabs.org/patch/1967517/
Jonas Karlman (12): rockchip: rk3399: Fix TPL build of bob and kevin rockchip: rk3399-gru: Use SYS_SPI_U_BOOT_OFFS value in offset prop rockchip: rk3399-gru: Move SPI flash payload offset for bob and kevin rockchip: rk3399-gru: Fix include of TPL in u-boot.rom image rockchip: rk3399-gru: Use TPL with common bss and stack addresses rockchip: rk3399-gru: Include binman generated FIT in u-boot.rom image rockchip: rk3399: Drop common Kconfig options already implied rockchip: rk3399-gru: Remove unused nodes from xPL control FDT rockchip: rk3399-gru: Enable dcache and signature validation in SPL rockchip: rk3399-gru: Use SDMA mode to read from eMMC rockchip: rk3399-gru: Include pinctrl and regulators in SPL rockchip: rk3399: Drop unneeded bob and kevin board specific code
arch/arm/dts/rk3399-gru-u-boot.dtsi | 29 ++++++++++++++++++++++++-- arch/arm/dts/rk3399-u-boot.dtsi | 14 +++++++++++-- arch/arm/mach-rockchip/rk3399/Kconfig | 12 ----------- arch/arm/mach-rockchip/rk3399/rk3399.c | 23 +------------------- configs/chromebook_bob_defconfig | 23 ++++++-------------- configs/chromebook_kevin_defconfig | 23 ++++++-------------- 6 files changed, 52 insertions(+), 72 deletions(-)
Thank you for doing this!
I'm not sure if you have access to your own denx tree. If so, kevin and bob are in the sjg lab. If not, you can sign up at sjg.u-boot.org to get access to my tree.
I do not have access to my own tree.
This series eems to work for me, except for the final commit, which hangs with no output.
Strange, guess we can just skip the last patch, should I send a v2 without the last patch?
I wonder if it is not setting io_vsel or the regulators that is causing an issue. Setting io_vsel is probably delayed until U-Boot proper instead of being set very early in SPL (due to no IO-domain driver in SPL), and enable of regulators may happen later in SPL with the last patch applied.
There is also some code in board/google/gru/gru.c that mention a delay related to the regulators may be needed, however board_early_init_f() is never called as following can be found in .config:
# CONFIG_BOARD_EARLY_INIT_F is not set
Will you be able to test with just the rk_setreg(&grf->io_vsel, 1 << 0); and remove the spl_gpio_output/set_pull parts of the last patch before I send a v2?
If you send a v2, please include disabling TPL_BLOBLIST and then the boards should boot in mainline as well as Simon's tree. Thanks!
Hi Tom,
On 2024/12/21 00:29, Tom Rini wrote:
On Fri, Dec 20, 2024 at 05:22:28PM +0100, Jonas Karlman wrote:
Hi Simon,
On 2024-12-13 04:09, Simon Glass wrote:
Hi Jonas,
On Thu, 12 Dec 2024 at 16:57, Jonas Karlman jonas@kwiboo.se wrote:
This is a continuation of an RFC [1] sent back in August.
All Rockchip aarch64 boards, beside bob and kevin, use TPL to initialize DRAM and SPL to load FIT with U-Boot proper and TF-A.
Bob and kevin currently does not use TPL and instead initialize DRAM in SPL and directly after tries to load a FIT with only U-Boot proper.
This series migrate bob and kevin to also use TPL to uniform TPL/SPL use for all Rockchip aarch64 boards.
Features and changes in this series:
- Use of Rockchip aarch64 common bss and stack addresses
- SHA256 checksum/signature check of FIT images in SPL
- Use of dcache to speed up checksum check in SPL
- SDMA use for eMMC access to speed up read/write in U-Boot proper
- FIT location moved from 0x40000 to 0xE0000 in SPI flash
Changes sinc RFC:
- Include pinctrl props and enable regulators based on DT in SPL
- Drop bob and kevin board specific code from common rk3399.c
Please note that I do not have any bob or kevin so this has only been compile tested and the original RFC [1] was runtime tested by Simon.
[1] https://patchwork.ozlabs.org/patch/1967517/
Jonas Karlman (12): rockchip: rk3399: Fix TPL build of bob and kevin rockchip: rk3399-gru: Use SYS_SPI_U_BOOT_OFFS value in offset prop rockchip: rk3399-gru: Move SPI flash payload offset for bob and kevin rockchip: rk3399-gru: Fix include of TPL in u-boot.rom image rockchip: rk3399-gru: Use TPL with common bss and stack addresses rockchip: rk3399-gru: Include binman generated FIT in u-boot.rom image rockchip: rk3399: Drop common Kconfig options already implied rockchip: rk3399-gru: Remove unused nodes from xPL control FDT rockchip: rk3399-gru: Enable dcache and signature validation in SPL rockchip: rk3399-gru: Use SDMA mode to read from eMMC rockchip: rk3399-gru: Include pinctrl and regulators in SPL rockchip: rk3399: Drop unneeded bob and kevin board specific code
arch/arm/dts/rk3399-gru-u-boot.dtsi | 29 ++++++++++++++++++++++++-- arch/arm/dts/rk3399-u-boot.dtsi | 14 +++++++++++-- arch/arm/mach-rockchip/rk3399/Kconfig | 12 ----------- arch/arm/mach-rockchip/rk3399/rk3399.c | 23 +------------------- configs/chromebook_bob_defconfig | 23 ++++++-------------- configs/chromebook_kevin_defconfig | 23 ++++++-------------- 6 files changed, 52 insertions(+), 72 deletions(-)
Thank you for doing this!
I'm not sure if you have access to your own denx tree. If so, kevin and bob are in the sjg lab. If not, you can sign up at sjg.u-boot.org to get access to my tree.
I do not have access to my own tree.
This series eems to work for me, except for the final commit, which hangs with no output.
Strange, guess we can just skip the last patch, should I send a v2 without the last patch?
I wonder if it is not setting io_vsel or the regulators that is causing an issue. Setting io_vsel is probably delayed until U-Boot proper instead of being set very early in SPL (due to no IO-domain driver in SPL), and enable of regulators may happen later in SPL with the last patch applied.
There is also some code in board/google/gru/gru.c that mention a delay related to the regulators may be needed, however board_early_init_f() is never called as following can be found in .config:
# CONFIG_BOARD_EARLY_INIT_F is not set
Will you be able to test with just the rk_setreg(&grf->io_vsel, 1 << 0); and remove the spl_gpio_output/set_pull parts of the last patch before I send a v2?
If you send a v2, please include disabling TPL_BLOBLIST and then the boards should boot in mainline as well as Simon's tree. Thanks!
Do you mean add below code in configs/chromebook_bob_defconfig and configs/chromebook_kevin_defconfig will make this patch set available? # CONFIG_TPL_BLOBLIST is not set If yes, then I can do that when apply the patches.
Thanks, - Kever
On Fri, Jan 10, 2025 at 03:09:33PM +0800, Kever Yang wrote:
Hi Tom,
On 2024/12/21 00:29, Tom Rini wrote:
On Fri, Dec 20, 2024 at 05:22:28PM +0100, Jonas Karlman wrote:
Hi Simon,
On 2024-12-13 04:09, Simon Glass wrote:
Hi Jonas,
On Thu, 12 Dec 2024 at 16:57, Jonas Karlman jonas@kwiboo.se wrote:
This is a continuation of an RFC [1] sent back in August.
All Rockchip aarch64 boards, beside bob and kevin, use TPL to initialize DRAM and SPL to load FIT with U-Boot proper and TF-A.
Bob and kevin currently does not use TPL and instead initialize DRAM in SPL and directly after tries to load a FIT with only U-Boot proper.
This series migrate bob and kevin to also use TPL to uniform TPL/SPL use for all Rockchip aarch64 boards.
Features and changes in this series:
- Use of Rockchip aarch64 common bss and stack addresses
- SHA256 checksum/signature check of FIT images in SPL
- Use of dcache to speed up checksum check in SPL
- SDMA use for eMMC access to speed up read/write in U-Boot proper
- FIT location moved from 0x40000 to 0xE0000 in SPI flash
Changes sinc RFC:
- Include pinctrl props and enable regulators based on DT in SPL
- Drop bob and kevin board specific code from common rk3399.c
Please note that I do not have any bob or kevin so this has only been compile tested and the original RFC [1] was runtime tested by Simon.
[1] https://patchwork.ozlabs.org/patch/1967517/
Jonas Karlman (12): rockchip: rk3399: Fix TPL build of bob and kevin rockchip: rk3399-gru: Use SYS_SPI_U_BOOT_OFFS value in offset prop rockchip: rk3399-gru: Move SPI flash payload offset for bob and kevin rockchip: rk3399-gru: Fix include of TPL in u-boot.rom image rockchip: rk3399-gru: Use TPL with common bss and stack addresses rockchip: rk3399-gru: Include binman generated FIT in u-boot.rom image rockchip: rk3399: Drop common Kconfig options already implied rockchip: rk3399-gru: Remove unused nodes from xPL control FDT rockchip: rk3399-gru: Enable dcache and signature validation in SPL rockchip: rk3399-gru: Use SDMA mode to read from eMMC rockchip: rk3399-gru: Include pinctrl and regulators in SPL rockchip: rk3399: Drop unneeded bob and kevin board specific code
arch/arm/dts/rk3399-gru-u-boot.dtsi | 29 ++++++++++++++++++++++++-- arch/arm/dts/rk3399-u-boot.dtsi | 14 +++++++++++-- arch/arm/mach-rockchip/rk3399/Kconfig | 12 ----------- arch/arm/mach-rockchip/rk3399/rk3399.c | 23 +------------------- configs/chromebook_bob_defconfig | 23 ++++++-------------- configs/chromebook_kevin_defconfig | 23 ++++++-------------- 6 files changed, 52 insertions(+), 72 deletions(-)
Thank you for doing this!
I'm not sure if you have access to your own denx tree. If so, kevin and bob are in the sjg lab. If not, you can sign up at sjg.u-boot.org to get access to my tree.
I do not have access to my own tree.
This series eems to work for me, except for the final commit, which hangs with no output.
Strange, guess we can just skip the last patch, should I send a v2 without the last patch?
I wonder if it is not setting io_vsel or the regulators that is causing an issue. Setting io_vsel is probably delayed until U-Boot proper instead of being set very early in SPL (due to no IO-domain driver in SPL), and enable of regulators may happen later in SPL with the last patch applied.
There is also some code in board/google/gru/gru.c that mention a delay related to the regulators may be needed, however board_early_init_f() is never called as following can be found in .config:
# CONFIG_BOARD_EARLY_INIT_F is not set
Will you be able to test with just the rk_setreg(&grf->io_vsel, 1 << 0); and remove the spl_gpio_output/set_pull parts of the last patch before I send a v2?
If you send a v2, please include disabling TPL_BLOBLIST and then the boards should boot in mainline as well as Simon's tree. Thanks!
Do you mean add below code in configs/chromebook_bob_defconfig and configs/chromebook_kevin_defconfig will make this patch set available? # CONFIG_TPL_BLOBLIST is not set If yes, then I can do that when apply the patches.
Yes, thanks!
participants (5)
-
Jonas Karlman -
Kever Yang -
Quentin Schulz -
Simon Glass -
Tom Rini