Tab space's got adjusted on relevent files.

Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com --- drivers/mtd/spi/sf_internal.h | 20 ++++++++++---------- include/spi.h | 12 ++++++------ include/spi_flash.h | 8 ++++---- 3 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 785f7a9..58007de 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -31,9 +31,9 @@ enum spi_read_cmds { };

/* Normal - Extended - Full command set */ -#define RD_NORM (ARRAY_SLOW | ARRAY_FAST) -#define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST) -#define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST) +#define RD_NORM (ARRAY_SLOW | ARRAY_FAST) +#define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST) +#define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)

/* sf param flags */ enum { @@ -67,12 +67,12 @@ enum { #define CMD_WRITE_STATUS 0x01 #define CMD_PAGE_PROGRAM 0x02 #define CMD_WRITE_DISABLE 0x04 -#define CMD_READ_STATUS 0x05 +#define CMD_READ_STATUS 0x05 #define CMD_QUAD_PAGE_PROGRAM 0x32 #define CMD_READ_STATUS1 0x35 #define CMD_WRITE_ENABLE 0x06 -#define CMD_READ_CONFIG 0x35 -#define CMD_FLAG_STATUS 0x70 +#define CMD_READ_CONFIG 0x35 +#define CMD_FLAG_STATUS 0x70

/* Read commands */ #define CMD_READ_ARRAY_SLOW 0x03 @@ -94,7 +94,7 @@ enum { /* Common status */ #define STATUS_WIP (1 << 0) #define STATUS_QEB_WINSPAN (1 << 1) -#define STATUS_QEB_MXIC (1 << 6) +#define STATUS_QEB_MXIC (1 << 6) #define STATUS_PEC (1 << 7)

#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN @@ -103,13 +103,13 @@ enum {

/* Flash timeout values */ #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) -#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) +#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) #define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)

/* SST specific */ #ifdef CONFIG_SPI_FLASH_SST # define CMD_SST_BP 0x02 /* Byte Program */ -# define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */ +# define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */

int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf); @@ -124,7 +124,7 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id]) * @ext_jedec: Device ext_jedec ID * @sector_size: Sector size of this device - * @nr_sectors: No.of sectors on this device + * @nr_sectors: No.of sectors on this device * @e_rd_cmd: Enum list for read commands * @flags: Important param, for flash specific behaviour */ diff --git a/include/spi.h b/include/spi.h index 7829063..44abe68 100644 --- a/include/spi.h +++ b/include/spi.h @@ -30,7 +30,7 @@ #define SPI_XFER_MMAP 0x08 /* Memory Mapped start */ #define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */ #define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) -#define SPI_XFER_U_PAGE (1 << 5) +#define SPI_XFER_U_PAGE (1 << 5)

/* SPI TX operation modes */ #define SPI_OPM_TX_QPP (1 << 0) @@ -43,18 +43,18 @@ #define SPI_OPM_RX_DIO (1 << 3) #define SPI_OPM_RX_QOF (1 << 4) #define SPI_OPM_RX_QIOF (1 << 5) -#define SPI_OPM_RX_EXTN (SPI_OPM_RX_AS | SPI_OPM_RX_AF | SPI_OPM_RX_DOUT | \ - SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \ - SPI_OPM_RX_QIOF) +#define SPI_OPM_RX_EXTN (SPI_OPM_RX_AS | SPI_OPM_RX_AF | \ + SPI_OPM_RX_DOUT | SPI_OPM_RX_DIO | \ + SPI_OPM_RX_QOF | SPI_OPM_RX_QIOF)

/* SPI bus connection options - see enum spi_dual_flash */ #define SPI_CONN_DUAL_SHARED (1 << 0) -#define SPI_CONN_DUAL_SEPARATED (1 << 1) +#define SPI_CONN_DUAL_SEPARATED (1 << 1)

/* Header byte that marks the start of the message */ #define SPI_PREAMBLE_END_BYTE 0xec

-#define SPI_DEFAULT_WORDLEN 8 +#define SPI_DEFAULT_WORDLEN 8

#ifdef CONFIG_DM_SPI /* TODO(sjg@chromium.org): Remove this and use max_hz from struct spi_slave */ diff --git a/include/spi_flash.h b/include/spi_flash.h index 4791b94..481b4dd 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -38,12 +38,12 @@ struct spi_slave; * * @spi: SPI slave * @name: Name of SPI flash - * @dual_flash: Indicates dual flash memories - dual stacked, parallel + * @dual_flash: Indicates dual flash memories - dual stacked, parallel * @shift: Flash shift useful in dual parallel * @size: Total flash size * @page_size: Write (page) size * @sector_size: Sector size - * @erase_size: Erase size + * @erase_size: Erase size * @bank_read_cmd: Bank read cmd * @bank_write_cmd: Bank write cmd * @bank_curr: Current flash bank @@ -51,8 +51,8 @@ struct spi_slave; * @erase_cmd: Erase cmd 4K, 32K, 64K * @read_cmd: Read cmd - Array Fast, Extn read and quad read. * @write_cmd: Write cmd - page and quad program. - * @dummy_byte: Dummy cycles for read operation. - * @memory_map: Address of read-only SPI flash access + * @dummy_byte: Dummy cycles for read operation. + * @memory_map: Address of read-only SPI flash access * @read: Flash read ops: Read len bytes at offset into buf * Supported cmds: Fast Array Read * @write: Flash write ops: Write len bytes from buf into offset

Zap ftssp010_spi driver since the boards used this driver is no longer been active.

Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com Cc: Kuo-Jung Su dantesu@faraday-tech.com Cc: Axel Lin axel.lin@ingics.com --- drivers/spi/Makefile | 1 - drivers/spi/ftssp010_spi.c | 498 --------------------------------------------- 2 files changed, 499 deletions(-) delete mode 100644 drivers/spi/ftssp010_spi.c

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 93065b7..1e3611d 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -28,7 +28,6 @@ obj-$(CONFIG_CF_QSPI) += cf_qspi.o obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o -obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o diff --git a/drivers/spi/ftssp010_spi.c b/drivers/spi/ftssp010_spi.c deleted file mode 100644 index c7d6480..0000000 --- a/drivers/spi/ftssp010_spi.c +++ /dev/null @@ -1,498 +0,0 @@ -/* - * (C) Copyright 2013 - * Faraday Technology Corporation. http://www.faraday-tech.com/tw/ - * Kuo-Jung Su dantesu@gmail.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <linux/compat.h> -#include <asm/io.h> -#include <malloc.h> -#include <spi.h> - -#ifndef CONFIG_FTSSP010_BASE_LIST -#define CONFIG_FTSSP010_BASE_LIST { CONFIG_FTSSP010_BASE } -#endif - -#ifndef CONFIG_FTSSP010_GPIO_BASE -#define CONFIG_FTSSP010_GPIO_BASE 0 -#endif - -#ifndef CONFIG_FTSSP010_GPIO_LIST -#define CONFIG_FTSSP010_GPIO_LIST { CONFIG_FTSSP010_GPIO_BASE } -#endif - -#ifndef CONFIG_FTSSP010_CLOCK -#define CONFIG_FTSSP010_CLOCK clk_get_rate("SSP"); -#endif - -#ifndef CONFIG_FTSSP010_TIMEOUT -#define CONFIG_FTSSP010_TIMEOUT 100 -#endif - -/* FTSSP010 chip registers */ -struct ftssp010_regs { - uint32_t cr[3];/* control register */ - uint32_t sr; /* status register */ - uint32_t icr; /* interrupt control register */ - uint32_t isr; /* interrupt status register */ - uint32_t dr; /* data register */ - uint32_t rsvd[17]; - uint32_t revr; /* revision register */ - uint32_t fear; /* feature register */ -}; - -/* Control Register 0 */ -#define CR0_FFMT_MASK (7 << 12) -#define CR0_FFMT_SSP (0 << 12) -#define CR0_FFMT_SPI (1 << 12) -#define CR0_FFMT_MICROWIRE (2 << 12) -#define CR0_FFMT_I2S (3 << 12) -#define CR0_FFMT_AC97 (4 << 12) -#define CR0_FLASH (1 << 11) -#define CR0_FSDIST(x) (((x) & 0x03) << 8) -#define CR0_LOOP (1 << 7) /* loopback mode */ -#define CR0_LSB (1 << 6) /* LSB */ -#define CR0_FSPO (1 << 5) /* fs atcive low (I2S only) */ -#define CR0_FSJUSTIFY (1 << 4) -#define CR0_OPM_SLAVE (0 << 2) -#define CR0_OPM_MASTER (3 << 2) -#define CR0_OPM_I2S_MSST (3 << 2) /* master stereo mode */ -#define CR0_OPM_I2S_MSMO (2 << 2) /* master mono mode */ -#define CR0_OPM_I2S_SLST (1 << 2) /* slave stereo mode */ -#define CR0_OPM_I2S_SLMO (0 << 2) /* slave mono mode */ -#define CR0_SCLKPO (1 << 1) /* clock polarity */ -#define CR0_SCLKPH (1 << 0) /* clock phase */ - -/* Control Register 1 */ -#define CR1_PDL(x) (((x) & 0xff) << 24) /* padding length */ -#define CR1_SDL(x) ((((x) - 1) & 0x1f) << 16) /* data length */ -#define CR1_DIV(x) (((x) - 1) & 0xffff) /* clock divider */ - -/* Control Register 2 */ -#define CR2_CS(x) (((x) & 3) << 10) /* CS/FS select */ -#define CR2_FS (1 << 9) /* CS/FS signal level */ -#define CR2_TXEN (1 << 8) /* tx enable */ -#define CR2_RXEN (1 << 7) /* rx enable */ -#define CR2_RESET (1 << 6) /* chip reset */ -#define CR2_TXFC (1 << 3) /* tx fifo Clear */ -#define CR2_RXFC (1 << 2) /* rx fifo Clear */ -#define CR2_TXDOE (1 << 1) /* tx data output enable */ -#define CR2_EN (1 << 0) /* chip enable */ - -/* Status Register */ -#define SR_RFF (1 << 0) /* rx fifo full */ -#define SR_TFNF (1 << 1) /* tx fifo not full */ -#define SR_BUSY (1 << 2) /* chip busy */ -#define SR_RFVE(reg) (((reg) >> 4) & 0x1f) /* rx fifo valid entries */ -#define SR_TFVE(reg) (((reg) >> 12) & 0x1f) /* tx fifo valid entries */ - -/* Feature Register */ -#define FEAR_BITS(reg) ((((reg) >> 0) & 0xff) + 1) /* data width */ -#define FEAR_RFSZ(reg) ((((reg) >> 8) & 0xff) + 1) /* rx fifo size */ -#define FEAR_TFSZ(reg) ((((reg) >> 16) & 0xff) + 1) /* tx fifo size */ -#define FEAR_AC97 (1 << 24) -#define FEAR_I2S (1 << 25) -#define FEAR_SPI_MWR (1 << 26) -#define FEAR_SSP (1 << 27) -#define FEAR_SPDIF (1 << 28) - -/* FTGPIO010 chip registers */ -struct ftgpio010_regs { - uint32_t out; /* 0x00: Data Output */ - uint32_t in; /* 0x04: Data Input */ - uint32_t dir; /* 0x08: Direction */ - uint32_t bypass; /* 0x0c: Bypass */ - uint32_t set; /* 0x10: Data Set */ - uint32_t clr; /* 0x14: Data Clear */ - uint32_t pull_up; /* 0x18: Pull-Up Enabled */ - uint32_t pull_st; /* 0x1c: Pull State (0=pull-down, 1=pull-up) */ -}; - -struct ftssp010_gpio { - struct ftgpio010_regs *regs; - uint32_t pin; -}; - -struct ftssp010_spi { - struct spi_slave slave; - struct ftssp010_gpio gpio; - struct ftssp010_regs *regs; - uint32_t fifo; - uint32_t mode; - uint32_t div; - uint32_t clk; - uint32_t speed; - uint32_t revision; -}; - -static inline struct ftssp010_spi *to_ftssp010_spi(struct spi_slave *slave) -{ - return container_of(slave, struct ftssp010_spi, slave); -} - -static int get_spi_chip(int bus, struct ftssp010_spi *chip) -{ - uint32_t fear, base[] = CONFIG_FTSSP010_BASE_LIST; - - if (bus >= ARRAY_SIZE(base) || !base[bus]) - return -1; - - chip->regs = (struct ftssp010_regs *)base[bus]; - - chip->revision = readl(&chip->regs->revr); - - fear = readl(&chip->regs->fear); - chip->fifo = min_t(uint32_t, FEAR_TFSZ(fear), FEAR_RFSZ(fear)); - - return 0; -} - -static int get_spi_gpio(int bus, struct ftssp010_gpio *chip) -{ - uint32_t base[] = CONFIG_FTSSP010_GPIO_LIST; - - if (bus >= ARRAY_SIZE(base) || !base[bus]) - return -1; - - chip->regs = (struct ftgpio010_regs *)(base[bus] & 0xfff00000); - chip->pin = base[bus] & 0x1f; - - /* make it an output pin */ - setbits_le32(&chip->regs->dir, 1 << chip->pin); - - return 0; -} - -static int ftssp010_wait(struct ftssp010_spi *chip) -{ - struct ftssp010_regs *regs = chip->regs; - ulong t; - - /* wait until device idle */ - for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) { - if (!(readl(&regs->sr) & SR_BUSY)) - return 0; - } - - puts("ftspi010: busy timeout\n"); - - return -1; -} - -static int ftssp010_wait_tx(struct ftssp010_spi *chip) -{ - struct ftssp010_regs *regs = chip->regs; - ulong t; - - /* wait until tx fifo not full */ - for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) { - if (readl(&regs->sr) & SR_TFNF) - return 0; - } - - puts("ftssp010: tx timeout\n"); - - return -1; -} - -static int ftssp010_wait_rx(struct ftssp010_spi *chip) -{ - struct ftssp010_regs *regs = chip->regs; - ulong t; - - /* wait until rx fifo not empty */ - for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) { - if (SR_RFVE(readl(&regs->sr))) - return 0; - } - - puts("ftssp010: rx timeout\n"); - - return -1; -} - -static int ftssp010_spi_work_transfer_v2(struct ftssp010_spi *chip, - const void *tx_buf, void *rx_buf, int len, uint flags) -{ - struct ftssp010_regs *regs = chip->regs; - const uint8_t *txb = tx_buf; - uint8_t *rxb = rx_buf; - - while (len > 0) { - int i, depth = min(chip->fifo >> 2, len); - uint32_t xmsk = 0; - - if (tx_buf) { - for (i = 0; i < depth; ++i) { - ftssp010_wait_tx(chip); - writel(*txb++, &regs->dr); - } - xmsk |= CR2_TXEN | CR2_TXDOE; - if ((readl(&regs->cr[2]) & xmsk) != xmsk) - setbits_le32(&regs->cr[2], xmsk); - } - if (rx_buf) { - xmsk |= CR2_RXEN; - if ((readl(&regs->cr[2]) & xmsk) != xmsk) - setbits_le32(&regs->cr[2], xmsk); - for (i = 0; i < depth; ++i) { - ftssp010_wait_rx(chip); - *rxb++ = (uint8_t)readl(&regs->dr); - } - } - - len -= depth; - } - - return 0; -} - -static int ftssp010_spi_work_transfer_v1(struct ftssp010_spi *chip, - const void *tx_buf, void *rx_buf, int len, uint flags) -{ - struct ftssp010_regs *regs = chip->regs; - const uint8_t *txb = tx_buf; - uint8_t *rxb = rx_buf; - - while (len > 0) { - int i, depth = min(chip->fifo >> 2, len); - uint32_t tmp; - - for (i = 0; i < depth; ++i) { - ftssp010_wait_tx(chip); - writel(txb ? (*txb++) : 0, &regs->dr); - } - for (i = 0; i < depth; ++i) { - ftssp010_wait_rx(chip); - tmp = readl(&regs->dr); - if (rxb) - *rxb++ = (uint8_t)tmp; - } - - len -= depth; - } - - return 0; -} - -static void ftssp010_cs_set(struct ftssp010_spi *chip, int high) -{ - struct ftssp010_regs *regs = chip->regs; - struct ftssp010_gpio *gpio = &chip->gpio; - uint32_t mask; - - /* cs pull high/low */ - if (chip->revision >= 0x11900) { - mask = CR2_CS(chip->slave.cs) | (high ? CR2_FS : 0); - writel(mask, &regs->cr[2]); - } else if (gpio->regs) { - mask = 1 << gpio->pin; - if (high) - writel(mask, &gpio->regs->set); - else - writel(mask, &gpio->regs->clr); - } - - /* extra delay for signal propagation */ - udelay_masked(1); -} - -/* - * Determine if a SPI chipselect is valid. - * This function is provided by the board if the low-level SPI driver - * needs it to determine if a given chipselect is actually valid. - * - * Returns: 1 if bus:cs identifies a valid chip on this board, 0 - * otherwise. - */ -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - struct ftssp010_spi chip; - - if (get_spi_chip(bus, &chip)) - return 0; - - if (!cs) - return 1; - else if ((cs < 4) && (chip.revision >= 0x11900)) - return 1; - - return 0; -} - -/* - * Activate a SPI chipselect. - * This function is provided by the board code when using a driver - * that can't control its chipselects automatically (e.g. - * common/soft_spi.c). When called, it should activate the chip select - * to the device identified by "slave". - */ -void spi_cs_activate(struct spi_slave *slave) -{ - struct ftssp010_spi *chip = to_ftssp010_spi(slave); - struct ftssp010_regs *regs = chip->regs; - - /* cs pull */ - if (chip->mode & SPI_CS_HIGH) - ftssp010_cs_set(chip, 1); - else - ftssp010_cs_set(chip, 0); - - /* chip enable + fifo clear */ - setbits_le32(&regs->cr[2], CR2_EN | CR2_TXFC | CR2_RXFC); -} - -/* - * Deactivate a SPI chipselect. - * This function is provided by the board code when using a driver - * that can't control its chipselects automatically (e.g. - * common/soft_spi.c). When called, it should deactivate the chip - * select to the device identified by "slave". - */ -void spi_cs_deactivate(struct spi_slave *slave) -{ - struct ftssp010_spi *chip = to_ftssp010_spi(slave); - - /* wait until chip idle */ - ftssp010_wait(chip); - - /* cs pull */ - if (chip->mode & SPI_CS_HIGH) - ftssp010_cs_set(chip, 0); - else - ftssp010_cs_set(chip, 1); -} - -void spi_init(void) -{ - /* nothing to do */ -} - -struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode) -{ - struct ftssp010_spi *chip; - - if (mode & SPI_3WIRE) { - puts("ftssp010: can't do 3-wire\n"); - return NULL; - } - - if (mode & SPI_SLAVE) { - puts("ftssp010: can't do slave mode\n"); - return NULL; - } - - if (mode & SPI_PREAMBLE) { - puts("ftssp010: can't skip preamble bytes\n"); - return NULL; - } - - if (!spi_cs_is_valid(bus, cs)) { - puts("ftssp010: invalid (bus, cs)\n"); - return NULL; - } - - chip = spi_alloc_slave(struct ftssp010_spi, bus, cs); - if (!chip) - return NULL; - - if (get_spi_chip(bus, chip)) - goto free_out; - - if (chip->revision < 0x11900 && get_spi_gpio(bus, &chip->gpio)) { - puts("ftssp010: Before revision 1.19.0, its clock & cs are\n" - "controlled by tx engine which is not synced with rx engine,\n" - "so the clock & cs might be shutdown before rx engine\n" - "finishs its jobs.\n" - "If possible, please add a dedicated gpio for it.\n"); - } - - chip->mode = mode; - chip->clk = CONFIG_FTSSP010_CLOCK; - chip->div = 2; - if (max_hz) { - while (chip->div < 0xffff) { - if ((chip->clk / (2 * chip->div)) <= max_hz) - break; - chip->div += 1; - } - } - chip->speed = chip->clk / (2 * chip->div); - - return &chip->slave; - -free_out: - free(chip); - return NULL; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct ftssp010_spi *chip = to_ftssp010_spi(slave); - - free(chip); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - struct ftssp010_spi *chip = to_ftssp010_spi(slave); - struct ftssp010_regs *regs = chip->regs; - - writel(CR1_SDL(8) | CR1_DIV(chip->div), &regs->cr[1]); - - if (chip->revision >= 0x11900) { - writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO | CR0_FLASH, - &regs->cr[0]); - writel(CR2_TXFC | CR2_RXFC, - &regs->cr[2]); - } else { - writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO, - &regs->cr[0]); - writel(CR2_TXFC | CR2_RXFC | CR2_EN | CR2_TXDOE, - &regs->cr[2]); - } - - if (chip->mode & SPI_LOOP) - setbits_le32(&regs->cr[0], CR0_LOOP); - - if (chip->mode & SPI_CPOL) - setbits_le32(&regs->cr[0], CR0_SCLKPO); - - if (chip->mode & SPI_CPHA) - setbits_le32(&regs->cr[0], CR0_SCLKPH); - - spi_cs_deactivate(slave); - - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ - struct ftssp010_spi *chip = to_ftssp010_spi(slave); - struct ftssp010_regs *regs = chip->regs; - - writel(0, &regs->cr[2]); -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - struct ftssp010_spi *chip = to_ftssp010_spi(slave); - uint32_t len = bitlen >> 3; - - if (flags & SPI_XFER_BEGIN) - spi_cs_activate(slave); - - if (chip->revision >= 0x11900) - ftssp010_spi_work_transfer_v2(chip, dout, din, len, flags); - else - ftssp010_spi_work_transfer_v1(chip, dout, din, len, flags); - - if (flags & SPI_XFER_END) - spi_cs_deactivate(slave); - - return 0; -}

Move the header code into driver for more readable and easy to access it.

Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com Cc: Michal Simek michal.simek@xilinx.com --- drivers/spi/xilinx_spi.c | 113 +++++++++++++++++++++++++++++++++++++- drivers/spi/xilinx_spi.h | 138 ----------------------------------------------- 2 files changed, 112 insertions(+), 139 deletions(-) delete mode 100644 drivers/spi/xilinx_spi.h

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 56d99d1..8073edc 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -21,7 +21,118 @@ #include <malloc.h> #include <spi.h>

-#include "xilinx_spi.h" +/* + * Xilinx SPI Register Definition + * + * [1]: [0]/ip_documentation/xps_spi.pdf + * page 8, Register Descriptions + * [2]: [0]/ip_documentation/axi_spi_ds742.pdf + * page 7, Register Overview Table + */ +struct xilinx_spi_reg { + u32 __space0__[7]; + u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */ + u32 ipisr; /* IP Interrupt Status Register (IPISR) */ + u32 __space1__; + u32 ipier; /* IP Interrupt Enable Register (IPIER) */ + u32 __space2__[5]; + u32 srr; /* Softare Reset Register (SRR) */ + u32 __space3__[7]; + u32 spicr; /* SPI Control Register (SPICR) */ + u32 spisr; /* SPI Status Register (SPISR) */ + u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */ + u32 spidrr; /* SPI Data Receive Register (SPIDRR) */ + u32 spissr; /* SPI Slave Select Register (SPISSR) */ + u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */ + u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */ +}; + +/* Device Global Interrupt Enable Register (dgier), [1] p15, [2] p15 */ +#define DGIER_GIE (1 << 31) + +/* IP Interrupt Status Register (ipisr), [1] p15, [2] p15 */ +#define IPISR_DRR_NOT_EMPTY (1 << 8) +#define IPISR_SLAVE_SELECT (1 << 7) +#define IPISR_TXF_HALF_EMPTY (1 << 6) +#define IPISR_DRR_OVERRUN (1 << 5) +#define IPISR_DRR_FULL (1 << 4) +#define IPISR_DTR_UNDERRUN (1 << 3) +#define IPISR_DTR_EMPTY (1 << 2) +#define IPISR_SLAVE_MODF (1 << 1) +#define IPISR_MODF (1 << 0) + +/* IP Interrupt Enable Register (ipier), [1] p17, [2] p18 */ +#define IPIER_DRR_NOT_EMPTY (1 << 8) +#define IPIER_SLAVE_SELECT (1 << 7) +#define IPIER_TXF_HALF_EMPTY (1 << 6) +#define IPIER_DRR_OVERRUN (1 << 5) +#define IPIER_DRR_FULL (1 << 4) +#define IPIER_DTR_UNDERRUN (1 << 3) +#define IPIER_DTR_EMPTY (1 << 2) +#define IPIER_SLAVE_MODF (1 << 1) +#define IPIER_MODF (1 << 0) + +/* Softare Reset Register (srr), [1] p9, [2] p8 */ +#define SRR_RESET_CODE 0x0000000A + +/* SPI Control Register (spicr), [1] p9, [2] p8 */ +#define SPICR_LSB_FIRST (1 << 9) +#define SPICR_MASTER_INHIBIT (1 << 8) +#define SPICR_MANUAL_SS (1 << 7) +#define SPICR_RXFIFO_RESEST (1 << 6) +#define SPICR_TXFIFO_RESEST (1 << 5) +#define SPICR_CPHA (1 << 4) +#define SPICR_CPOL (1 << 3) +#define SPICR_MASTER_MODE (1 << 2) +#define SPICR_SPE (1 << 1) +#define SPICR_LOOP (1 << 0) + +/* SPI Status Register (spisr), [1] p11, [2] p10 */ +#define SPISR_SLAVE_MODE_SELECT (1 << 5) +#define SPISR_MODF (1 << 4) +#define SPISR_TX_FULL (1 << 3) +#define SPISR_TX_EMPTY (1 << 2) +#define SPISR_RX_FULL (1 << 1) +#define SPISR_RX_EMPTY (1 << 0) + +/* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */ +#define SPIDTR_8BIT_MASK (0xff << 0) +#define SPIDTR_16BIT_MASK (0xffff << 0) +#define SPIDTR_32BIT_MASK (0xffffffff << 0) + +/* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */ +#define SPIDRR_8BIT_MASK (0xff << 0) +#define SPIDRR_16BIT_MASK (0xffff << 0) +#define SPIDRR_32BIT_MASK (0xffffffff << 0) + +/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */ +#define SPISSR_MASK(cs) (1 << (cs)) +#define SPISSR_ACT(cs) ~SPISSR_MASK(cs) +#define SPISSR_OFF ~0UL + +/* SPI Transmit FIFO Occupancy Register (spitfor), [1] p13, [2] p14 */ +#define SPITFOR_OCYVAL_POS 0 +#define SPITFOR_OCYVAL_MASK (0xf << SPITFOR_OCYVAL_POS) + +/* SPI Receive FIFO Occupancy Register (spirfor), [1] p14, [2] p14 */ +#define SPIRFOR_OCYVAL_POS 0 +#define SPIRFOR_OCYVAL_MASK (0xf << SPIRFOR_OCYVAL_POS) + +/* SPI Software Reset Register (ssr) */ +#define SPISSR_RESET_VALUE 0x0a + +struct xilinx_spi_slave { + struct spi_slave slave; + struct xilinx_spi_reg *regs; + unsigned int freq; + unsigned int mode; +}; + +static inline struct xilinx_spi_slave *to_xilinx_spi_slave( + struct spi_slave *slave) +{ + return container_of(slave, struct xilinx_spi_slave, slave); +}

#ifndef CONFIG_SYS_XILINX_SPI_LIST #define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE } diff --git a/drivers/spi/xilinx_spi.h b/drivers/spi/xilinx_spi.h deleted file mode 100644 index ce7d82c..0000000 --- a/drivers/spi/xilinx_spi.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Xilinx SPI driver - * - * XPS/AXI bus interface - * - * based on bfin_spi.c, by way of altera_spi.c - * Copyright (c) 2005-2008 Analog Devices Inc. - * Copyright (c) 2010 Thomas Chou thomas@wytron.com.tw - * Copyright (c) 2010 Graeme Smecher graeme.smecher@mail.mcgill.ca - * Copyright (c) 2012 Stephan Linz linz@li-pro.net - * - * SPDX-License-Identifier: GPL-2.0+ - * - * [0]: http://www.xilinx.com/support/documentation - * - * [S]: [0]/ip_documentation/xps_spi.pdf - * [0]/ip_documentation/axi_spi_ds742.pdf - */ -#ifndef _XILINX_SPI_ -#define _XILINX_SPI_ - -#include <asm/types.h> -#include <asm/io.h> - -/* - * Xilinx SPI Register Definition - * - * [1]: [0]/ip_documentation/xps_spi.pdf - * page 8, Register Descriptions - * [2]: [0]/ip_documentation/axi_spi_ds742.pdf - * page 7, Register Overview Table - */ -struct xilinx_spi_reg { - u32 __space0__[7]; - u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */ - u32 ipisr; /* IP Interrupt Status Register (IPISR) */ - u32 __space1__; - u32 ipier; /* IP Interrupt Enable Register (IPIER) */ - u32 __space2__[5]; - u32 srr; /* Softare Reset Register (SRR) */ - u32 __space3__[7]; - u32 spicr; /* SPI Control Register (SPICR) */ - u32 spisr; /* SPI Status Register (SPISR) */ - u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */ - u32 spidrr; /* SPI Data Receive Register (SPIDRR) */ - u32 spissr; /* SPI Slave Select Register (SPISSR) */ - u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */ - u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */ -}; - -/* Device Global Interrupt Enable Register (dgier), [1] p15, [2] p15 */ -#define DGIER_GIE (1 << 31) - -/* IP Interrupt Status Register (ipisr), [1] p15, [2] p15 */ -#define IPISR_DRR_NOT_EMPTY (1 << 8) -#define IPISR_SLAVE_SELECT (1 << 7) -#define IPISR_TXF_HALF_EMPTY (1 << 6) -#define IPISR_DRR_OVERRUN (1 << 5) -#define IPISR_DRR_FULL (1 << 4) -#define IPISR_DTR_UNDERRUN (1 << 3) -#define IPISR_DTR_EMPTY (1 << 2) -#define IPISR_SLAVE_MODF (1 << 1) -#define IPISR_MODF (1 << 0) - -/* IP Interrupt Enable Register (ipier), [1] p17, [2] p18 */ -#define IPIER_DRR_NOT_EMPTY (1 << 8) -#define IPIER_SLAVE_SELECT (1 << 7) -#define IPIER_TXF_HALF_EMPTY (1 << 6) -#define IPIER_DRR_OVERRUN (1 << 5) -#define IPIER_DRR_FULL (1 << 4) -#define IPIER_DTR_UNDERRUN (1 << 3) -#define IPIER_DTR_EMPTY (1 << 2) -#define IPIER_SLAVE_MODF (1 << 1) -#define IPIER_MODF (1 << 0) - -/* Softare Reset Register (srr), [1] p9, [2] p8 */ -#define SRR_RESET_CODE 0x0000000A - -/* SPI Control Register (spicr), [1] p9, [2] p8 */ -#define SPICR_LSB_FIRST (1 << 9) -#define SPICR_MASTER_INHIBIT (1 << 8) -#define SPICR_MANUAL_SS (1 << 7) -#define SPICR_RXFIFO_RESEST (1 << 6) -#define SPICR_TXFIFO_RESEST (1 << 5) -#define SPICR_CPHA (1 << 4) -#define SPICR_CPOL (1 << 3) -#define SPICR_MASTER_MODE (1 << 2) -#define SPICR_SPE (1 << 1) -#define SPICR_LOOP (1 << 0) - -/* SPI Status Register (spisr), [1] p11, [2] p10 */ -#define SPISR_SLAVE_MODE_SELECT (1 << 5) -#define SPISR_MODF (1 << 4) -#define SPISR_TX_FULL (1 << 3) -#define SPISR_TX_EMPTY (1 << 2) -#define SPISR_RX_FULL (1 << 1) -#define SPISR_RX_EMPTY (1 << 0) - -/* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */ -#define SPIDTR_8BIT_MASK (0xff << 0) -#define SPIDTR_16BIT_MASK (0xffff << 0) -#define SPIDTR_32BIT_MASK (0xffffffff << 0) - -/* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */ -#define SPIDRR_8BIT_MASK (0xff << 0) -#define SPIDRR_16BIT_MASK (0xffff << 0) -#define SPIDRR_32BIT_MASK (0xffffffff << 0) - -/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */ -#define SPISSR_MASK(cs) (1 << (cs)) -#define SPISSR_ACT(cs) ~SPISSR_MASK(cs) -#define SPISSR_OFF ~0UL - -/* SPI Transmit FIFO Occupancy Register (spitfor), [1] p13, [2] p14 */ -#define SPITFOR_OCYVAL_POS 0 -#define SPITFOR_OCYVAL_MASK (0xf << SPITFOR_OCYVAL_POS) - -/* SPI Receive FIFO Occupancy Register (spirfor), [1] p14, [2] p14 */ -#define SPIRFOR_OCYVAL_POS 0 -#define SPIRFOR_OCYVAL_MASK (0xf << SPIRFOR_OCYVAL_POS) - -/* SPI Software Reset Register (ssr) */ -#define SPISSR_RESET_VALUE 0x0a - -struct xilinx_spi_slave { - struct spi_slave slave; - struct xilinx_spi_reg *regs; - unsigned int freq; - unsigned int mode; -}; - -static inline struct xilinx_spi_slave *to_xilinx_spi_slave( - struct spi_slave *slave) -{ - return container_of(slave, struct xilinx_spi_slave, slave); -} - -#endif /* _XILINX_SPI_ */

- Zap unneeded macros - Re-arrange the code - Removed __attribute__((weak)) - Replace __func__ macro with func names to save macro transition. - Re-arranged comment lines. - Arrange driver code in more readable format[1]

[1] http://lists.denx.de/pipermail/u-boot/2013-August/160473.html

Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com Cc: Michal Simek michal.simek@xilinx.com --- drivers/spi/xilinx_spi.c | 164 ++++++++++++++++------------------------------- 1 file changed, 57 insertions(+), 107 deletions(-)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 8073edc..650e494 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -1,79 +1,31 @@ /* * Xilinx SPI driver * - * supports 8 bit SPI transfers only, with or w/o FIFO + * Supports 8 bit SPI transfers only, with or w/o FIFO * - * based on bfin_spi.c, by way of altera_spi.c - * Copyright (c) 2005-2008 Analog Devices Inc. - * Copyright (c) 2010 Thomas Chou thomas@wytron.com.tw - * Copyright (c) 2010 Graeme Smecher graeme.smecher@mail.mcgill.ca + * Based on bfin_spi.c, by way of altera_spi.c * Copyright (c) 2012 Stephan Linz linz@li-pro.net + * Copyright (c) 2010 Graeme Smecher graeme.smecher@mail.mcgill.ca + * Copyright (c) 2010 Thomas Chou thomas@wytron.com.tw + * Copyright (c) 2005-2008 Analog Devices Inc. * * SPDX-License-Identifier: GPL-2.0+ - * - * [0]: http://www.xilinx.com/support/documentation - * - * [S]: [0]/ip_documentation/xps_spi.pdf - * [0]/ip_documentation/axi_spi_ds742.pdf */ + #include <config.h> #include <common.h> #include <malloc.h> #include <spi.h>

/* - * Xilinx SPI Register Definition + * [0]: http://www.xilinx.com/support/documentation * + * Xilinx SPI Register Definitions * [1]: [0]/ip_documentation/xps_spi.pdf * page 8, Register Descriptions * [2]: [0]/ip_documentation/axi_spi_ds742.pdf * page 7, Register Overview Table */ -struct xilinx_spi_reg { - u32 __space0__[7]; - u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */ - u32 ipisr; /* IP Interrupt Status Register (IPISR) */ - u32 __space1__; - u32 ipier; /* IP Interrupt Enable Register (IPIER) */ - u32 __space2__[5]; - u32 srr; /* Softare Reset Register (SRR) */ - u32 __space3__[7]; - u32 spicr; /* SPI Control Register (SPICR) */ - u32 spisr; /* SPI Status Register (SPISR) */ - u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */ - u32 spidrr; /* SPI Data Receive Register (SPIDRR) */ - u32 spissr; /* SPI Slave Select Register (SPISSR) */ - u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */ - u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */ -}; - -/* Device Global Interrupt Enable Register (dgier), [1] p15, [2] p15 */ -#define DGIER_GIE (1 << 31) - -/* IP Interrupt Status Register (ipisr), [1] p15, [2] p15 */ -#define IPISR_DRR_NOT_EMPTY (1 << 8) -#define IPISR_SLAVE_SELECT (1 << 7) -#define IPISR_TXF_HALF_EMPTY (1 << 6) -#define IPISR_DRR_OVERRUN (1 << 5) -#define IPISR_DRR_FULL (1 << 4) -#define IPISR_DTR_UNDERRUN (1 << 3) -#define IPISR_DTR_EMPTY (1 << 2) -#define IPISR_SLAVE_MODF (1 << 1) -#define IPISR_MODF (1 << 0) - -/* IP Interrupt Enable Register (ipier), [1] p17, [2] p18 */ -#define IPIER_DRR_NOT_EMPTY (1 << 8) -#define IPIER_SLAVE_SELECT (1 << 7) -#define IPIER_TXF_HALF_EMPTY (1 << 6) -#define IPIER_DRR_OVERRUN (1 << 5) -#define IPIER_DRR_FULL (1 << 4) -#define IPIER_DTR_UNDERRUN (1 << 3) -#define IPIER_DTR_EMPTY (1 << 2) -#define IPIER_SLAVE_MODF (1 << 1) -#define IPIER_MODF (1 << 0) - -/* Softare Reset Register (srr), [1] p9, [2] p8 */ -#define SRR_RESET_CODE 0x0000000A

/* SPI Control Register (spicr), [1] p9, [2] p8 */ #define SPICR_LSB_FIRST (1 << 9) @@ -110,17 +62,42 @@ struct xilinx_spi_reg { #define SPISSR_ACT(cs) ~SPISSR_MASK(cs) #define SPISSR_OFF ~0UL

-/* SPI Transmit FIFO Occupancy Register (spitfor), [1] p13, [2] p14 */ -#define SPITFOR_OCYVAL_POS 0 -#define SPITFOR_OCYVAL_MASK (0xf << SPITFOR_OCYVAL_POS) - -/* SPI Receive FIFO Occupancy Register (spirfor), [1] p14, [2] p14 */ -#define SPIRFOR_OCYVAL_POS 0 -#define SPIRFOR_OCYVAL_MASK (0xf << SPIRFOR_OCYVAL_POS) - /* SPI Software Reset Register (ssr) */ #define SPISSR_RESET_VALUE 0x0a

+#define XILSPI_MAX_XFER_BITS 8 +#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | SPICR_MASTER_MODE | \ + SPICR_SPE) +#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS) + +#ifndef CONFIG_XILINX_SPI_IDLE_VAL +#define CONFIG_XILINX_SPI_IDLE_VAL 0xff +#endif + +#ifndef CONFIG_SYS_XILINX_SPI_LIST +#define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE } +#endif + +/* xilinx spi register set */ +struct xilinx_spi_reg { + u32 __space0__[7]; + u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */ + u32 ipisr; /* IP Interrupt Status Register (IPISR) */ + u32 __space1__; + u32 ipier; /* IP Interrupt Enable Register (IPIER) */ + u32 __space2__[5]; + u32 srr; /* Softare Reset Register (SRR) */ + u32 __space3__[7]; + u32 spicr; /* SPI Control Register (SPICR) */ + u32 spisr; /* SPI Status Register (SPISR) */ + u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */ + u32 spidrr; /* SPI Data Receive Register (SPIDRR) */ + u32 spissr; /* SPI Slave Select Register (SPISSR) */ + u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */ + u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */ +}; + +/* xilinx spi slave */ struct xilinx_spi_slave { struct spi_slave slave; struct xilinx_spi_reg *regs; @@ -129,37 +106,17 @@ struct xilinx_spi_slave { };

static inline struct xilinx_spi_slave *to_xilinx_spi_slave( - struct spi_slave *slave) + struct spi_slave *slave) { return container_of(slave, struct xilinx_spi_slave, slave); }

-#ifndef CONFIG_SYS_XILINX_SPI_LIST -#define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE } -#endif - -#ifndef CONFIG_XILINX_SPI_IDLE_VAL -#define CONFIG_XILINX_SPI_IDLE_VAL 0xff -#endif - -#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | \ - SPICR_MASTER_MODE | \ - SPICR_SPE) - -#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | \ - SPICR_MANUAL_SS) - -#define XILSPI_MAX_XFER_BITS 8 - static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST; - -__attribute__((weak)) int spi_cs_is_valid(unsigned int bus, unsigned int cs) { return bus < ARRAY_SIZE(xilinx_spi_base_list) && cs < 32; }

-__attribute__((weak)) void spi_cs_activate(struct spi_slave *slave) { struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); @@ -167,7 +124,6 @@ void spi_cs_activate(struct spi_slave *slave) writel(SPISSR_ACT(slave->cs), &xilspi->regs->spissr); }

-__attribute__((weak)) void spi_cs_deactivate(struct spi_slave *slave) { struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); @@ -180,33 +136,26 @@ void spi_init(void) /* do nothing */ }

-void spi_set_speed(struct spi_slave *slave, uint hz) -{ - /* xilinx spi core does not support programmable speed */ -} - struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { struct xilinx_spi_slave *xilspi;

if (!spi_cs_is_valid(bus, cs)) { - printf("XILSPI error: %s: unsupported bus %d / cs %d\n", - __func__, bus, cs); + printf("XILSPI error: unsupported bus %d / cs %d\n", bus, cs); return NULL; }

xilspi = spi_alloc_slave(struct xilinx_spi_slave, bus, cs); if (!xilspi) { - printf("XILSPI error: %s: malloc of SPI structure failed\n", - __func__); + printf("XILSPI error: malloc of SPI structure failed\n"); return NULL; } xilspi->regs = (struct xilinx_spi_reg *)xilinx_spi_base_list[bus]; xilspi->freq = max_hz; xilspi->mode = mode; - debug("%s: bus:%i cs:%i base:%p mode:%x max_hz:%d\n", __func__, - bus, cs, xilspi->regs, xilspi->mode, xilspi->freq); + debug("spi_setup_slave: bus:%i cs:%i base:%p mode:%x max_hz:%d\n", + bus, cs, xilspi->regs, xilspi->mode, xilspi->freq);

writel(SPISSR_RESET_VALUE, &xilspi->regs->srr);

@@ -225,7 +174,7 @@ int spi_claim_bus(struct spi_slave *slave) struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); u32 spicr;

- debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); + debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs); writel(SPISSR_OFF, &xilspi->regs->spissr);

spicr = XILSPI_SPICR_DFLT_ON; @@ -246,7 +195,7 @@ void spi_release_bus(struct spi_slave *slave) { struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);

- debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); + debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs); writel(SPISSR_OFF, &xilspi->regs->spissr); writel(XILSPI_SPICR_DFLT_OFF, &xilspi->regs->spicr); } @@ -262,14 +211,15 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, unsigned rxecount = 17; /* max. 16 elements in FIFO, leftover 1 */ unsigned global_timeout;

- debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__, - slave->bus, slave->cs, bitlen, bytes, flags); + debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", + slave->bus, slave->cs, bitlen, bytes, flags); + if (bitlen == 0) goto done;

if (bitlen % XILSPI_MAX_XFER_BITS) { - printf("XILSPI warning: %s: Not a multiple of %d bits\n", - __func__, XILSPI_MAX_XFER_BITS); + printf("XILSPI warning: Not a multiple of %d bits\n", + XILSPI_MAX_XFER_BITS); flags |= SPI_XFER_END; goto done; } @@ -281,7 +231,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, }

if (!rxecount) { - printf("XILSPI error: %s: Rx buffer not empty\n", __func__); + printf("XILSPI error: Rx buffer not empty\n"); return -1; }

@@ -296,7 +246,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, unsigned timeout = global_timeout; /* get Tx element from data out buffer and count up */ unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL; - debug("%s: tx:%x ", __func__, d); + debug("spi_xfer: tx:%x ", d);

/* write out and wait for processing (receive data) */ writel(d & SPIDTR_8BIT_MASK, &xilspi->regs->spidtr); @@ -307,7 +257,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, }

if (!timeout) { - printf("XILSPI error: %s: Xfer timeout\n", __func__); + printf("XILSPI error: Xfer timeout\n"); return -1; }

@@ -315,7 +265,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, d = readl(&xilspi->regs->spidrr) & SPIDRR_8BIT_MASK; if (rxp) *rxp++ = d; - debug("rx:%x\n", d); + debug("spi_xfer: rx:%x\n", d); }

done:

Arrange driver code in more readable format[1] for easy accessing and readable. [1] http://lists.denx.de/pipermail/u-boot/2013-August/160473.html

Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com Cc: Rex Chang rchang@ti.com Cc: Murali Karicheri m-karicheri2@ti.com --- drivers/spi/davinci_spi.c | 343 +++++++++++++++++++++++----------------------- 1 file changed, 173 insertions(+), 170 deletions(-)

diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index e0ecf99..0a036cc 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -8,39 +8,13 @@ * * SPDX-License-Identifier: GPL-2.0+ */ + #include <common.h> #include <spi.h> #include <malloc.h> #include <asm/io.h> #include <asm/arch/hardware.h>

-struct davinci_spi_regs { - dv_reg gcr0; /* 0x00 */ - dv_reg gcr1; /* 0x04 */ - dv_reg int0; /* 0x08 */ - dv_reg lvl; /* 0x0c */ - dv_reg flg; /* 0x10 */ - dv_reg pc0; /* 0x14 */ - dv_reg pc1; /* 0x18 */ - dv_reg pc2; /* 0x1c */ - dv_reg pc3; /* 0x20 */ - dv_reg pc4; /* 0x24 */ - dv_reg pc5; /* 0x28 */ - dv_reg rsvd[3]; - dv_reg dat0; /* 0x38 */ - dv_reg dat1; /* 0x3c */ - dv_reg buf; /* 0x40 */ - dv_reg emu; /* 0x44 */ - dv_reg delay; /* 0x48 */ - dv_reg def; /* 0x4c */ - dv_reg fmt0; /* 0x50 */ - dv_reg fmt1; /* 0x54 */ - dv_reg fmt2; /* 0x58 */ - dv_reg fmt3; /* 0x5c */ - dv_reg intvec0; /* 0x60 */ - dv_reg intvec1; /* 0x64 */ -}; - #define BIT(x) (1 << (x))

/* SPIGCR0 */ @@ -112,6 +86,35 @@ struct davinci_spi_regs { #define SPI2_BASE CONFIG_SYS_SPI2_BASE #endif

+/* davinci spi register set */ +struct davinci_spi_regs { + dv_reg gcr0; /* 0x00 */ + dv_reg gcr1; /* 0x04 */ + dv_reg int0; /* 0x08 */ + dv_reg lvl; /* 0x0c */ + dv_reg flg; /* 0x10 */ + dv_reg pc0; /* 0x14 */ + dv_reg pc1; /* 0x18 */ + dv_reg pc2; /* 0x1c */ + dv_reg pc3; /* 0x20 */ + dv_reg pc4; /* 0x24 */ + dv_reg pc5; /* 0x28 */ + dv_reg rsvd[3]; + dv_reg dat0; /* 0x38 */ + dv_reg dat1; /* 0x3c */ + dv_reg buf; /* 0x40 */ + dv_reg emu; /* 0x44 */ + dv_reg delay; /* 0x48 */ + dv_reg def; /* 0x4c */ + dv_reg fmt0; /* 0x50 */ + dv_reg fmt1; /* 0x54 */ + dv_reg fmt2; /* 0x58 */ + dv_reg fmt3; /* 0x5c */ + dv_reg intvec0; /* 0x60 */ + dv_reg intvec1; /* 0x64 */ +}; + +/* davinci spi slave */ struct davinci_spi_slave { struct spi_slave slave; struct davinci_spi_regs *regs; @@ -123,111 +126,6 @@ static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave) return container_of(slave, struct davinci_spi_slave, slave); }

-void spi_init() -{ - /* do nothing */ -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct davinci_spi_slave *ds; - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs); - if (!ds) - return NULL; - - switch (bus) { - case SPI0_BUS: - ds->regs = (struct davinci_spi_regs *)SPI0_BASE; - break; -#ifdef CONFIG_SYS_SPI1 - case SPI1_BUS: - ds->regs = (struct davinci_spi_regs *)SPI1_BASE; - break; -#endif -#ifdef CONFIG_SYS_SPI2 - case SPI2_BUS: - ds->regs = (struct davinci_spi_regs *)SPI2_BASE; - break; -#endif - default: /* Invalid bus number */ - return NULL; - } - - ds->freq = max_hz; - - return &ds->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct davinci_spi_slave *ds = to_davinci_spi(slave); - - free(ds); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - struct davinci_spi_slave *ds = to_davinci_spi(slave); - unsigned int scalar; - - /* Enable the SPI hardware */ - writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); - udelay(1000); - writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0); - - /* Set master mode, powered up and not activated */ - writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1); - - /* CS, CLK, SIMO and SOMI are functional pins */ - writel(((1 << slave->cs) | SPIPC0_CLKFUN_MASK | - SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0); - - /* setup format */ - scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF; - - /* - * Use following format: - * character length = 8, - * clock signal delayed by half clk cycle, - * clock low in idle state - Mode 0, - * MSB shifted out first - */ - writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) | - (1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0); - - /* - * Including a minor delay. No science here. Should be good even with - * no delay - */ - writel((50 << SPI_C2TDELAY_SHIFT) | - (50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay); - - /* default chip select register */ - writel(SPIDEF_CSDEF0_MASK, &ds->regs->def); - - /* no interrupts */ - writel(0, &ds->regs->int0); - writel(0, &ds->regs->lvl); - - /* enable SPI */ - writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1); - - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ - struct davinci_spi_slave *ds = to_davinci_spi(slave); - - /* Disable the SPI hardware */ - writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); -} - /* * This functions needs to act like a macro to avoid pipeline reloads in the * loops below. Use always_inline. This gains us about 160KiB/s and the bloat @@ -343,6 +241,149 @@ static int davinci_spi_read_write(struct spi_slave *slave, unsigned int len, } #endif

+int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + int ret = 0; + + switch (bus) { + case SPI0_BUS: + if (cs < SPI0_NUM_CS) + ret = 1; + break; +#ifdef CONFIG_SYS_SPI1 + case SPI1_BUS: + if (cs < SPI1_NUM_CS) + ret = 1; + break; +#endif +#ifdef CONFIG_SYS_SPI2 + case SPI2_BUS: + if (cs < SPI2_NUM_CS) + ret = 1; + break; +#endif + default: + /* Invalid bus number. Do nothing */ + break; + } + return ret; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + /* do nothing */ +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + /* do nothing */ +} + +void spi_init(void) +{ + /* do nothing */ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct davinci_spi_slave *ds; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs); + if (!ds) + return NULL; + + switch (bus) { + case SPI0_BUS: + ds->regs = (struct davinci_spi_regs *)SPI0_BASE; + break; +#ifdef CONFIG_SYS_SPI1 + case SPI1_BUS: + ds->regs = (struct davinci_spi_regs *)SPI1_BASE; + break; +#endif +#ifdef CONFIG_SYS_SPI2 + case SPI2_BUS: + ds->regs = (struct davinci_spi_regs *)SPI2_BASE; + break; +#endif + default: /* Invalid bus number */ + return NULL; + } + + ds->freq = max_hz; + + return &ds->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct davinci_spi_slave *ds = to_davinci_spi(slave); + + free(ds); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct davinci_spi_slave *ds = to_davinci_spi(slave); + unsigned int scalar; + + /* Enable the SPI hardware */ + writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); + udelay(1000); + writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0); + + /* Set master mode, powered up and not activated */ + writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1); + + /* CS, CLK, SIMO and SOMI are functional pins */ + writel(((1 << slave->cs) | SPIPC0_CLKFUN_MASK | + SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0); + + /* setup format */ + scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF; + + /* + * Use following format: + * character length = 8, + * clock signal delayed by half clk cycle, + * clock low in idle state - Mode 0, + * MSB shifted out first + */ + writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) | + (1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0); + + /* + * Including a minor delay. No science here. Should be good even with + * no delay + */ + writel((50 << SPI_C2TDELAY_SHIFT) | + (50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay); + + /* default chip select register */ + writel(SPIDEF_CSDEF0_MASK, &ds->regs->def); + + /* no interrupts */ + writel(0, &ds->regs->int0); + writel(0, &ds->regs->lvl); + + /* enable SPI */ + writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct davinci_spi_slave *ds = to_davinci_spi(slave); + + /* Disable the SPI hardware */ + writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); +} + int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { @@ -386,41 +427,3 @@ out: } return 0; } - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - int ret = 0; - - switch (bus) { - case SPI0_BUS: - if (cs < SPI0_NUM_CS) - ret = 1; - break; -#ifdef CONFIG_SYS_SPI1 - case SPI1_BUS: - if (cs < SPI1_NUM_CS) - ret = 1; - break; -#endif -#ifdef CONFIG_SYS_SPI2 - case SPI2_BUS: - if (cs < SPI2_NUM_CS) - ret = 1; - break; -#endif - default: - /* Invalid bus number. Do nothing */ - break; - } - return ret; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - /* do nothing */ -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - /* do nothing */ -}