This patch simplifies the 4xx MII PHY init code by introducing the define CONFIG_PPC4xx_EMAC for EMAC enabled SoC's.

Signed-off-by: Stefan Roese sr@denx.de --- This is post 1.3.4 material.

cpu/ppc4xx/4xx_enet.c | 7 ++----- include/ppc4xx.h | 8 ++++++++ 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 8a38335..62a3be8 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -1969,12 +1969,9 @@ int eth_rx(void) return (ppc_4xx_eth_rx(emac0_dev)); }

-int emac4xx_miiphy_initialize (bd_t * bis) +int emac4xx_miiphy_initialize(bd_t * bis) { -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register ("ppc_4xx_eth0", - emac4xx_miiphy_read, emac4xx_miiphy_write); -#endif + miiphy_register("ppc_4xx_eth0", emac4xx_miiphy_read, emac4xx_miiphy_write);

return 0; } diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 5a6b855..732f4dd 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -46,6 +46,14 @@ #define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ #endif

+/* + * Configure if SoC is equipped with one or multiple EMAC's + */ +#if !defined(CONFIG_405) && !defined(CONFIG_405CR) && \ + !defined(CONFIG_IOP480) && !defined(CONFIG_XILINX_440) +#define CONFIG_PPC4xx_EMAC +#endif + #if defined(CONFIG_440) #include <ppc440.h> #else