[U-Boot] [PATCH 00/12] arm: socfpga: Arria V support and fixes
This series brings in a couple of minor fixes (mostly coding style and sync with rocketboards u-boot) and improvements (USB UMS and DFU support for Cyclone V SoC DK). There are also fixes for DT properties in this series to make those compatible with Linux.
This series also adds Arria V SoC DK support. By adding the Arria V support, the pieces of code which are specific to a particular CPU model are now clearly isolated by an #ifdef. These #ifdef mark code which should be easy to dissolve and migrate into DT in the next step.
While at this, the SoCFPGA platform is made dependent on having a proper Device Tree available (attached at the end of U-Boot binary). The board name is no longer hard-coded into the U-Boot binary, but is instead extracted from the DT ; this is the first step toward moving to DT altogether. At this point, no new SoCFPGA platform without DT is accepted anymore.
Note: The DT files imported in this series come from Linux 3.18 mainline.
Marek Vasut (12): arm: socfpga: Minor coding style fix arm: socfpga: Sync Cyclone V DK pinmux configuration arm: socfpga: Sync Cyclone V DK PLL configuration arm: socfpga: Add USB and UDC support for Cyclone V DK arm: socfpga: Drop cyclone5 suffix from board file name arm: socfpga: Add Altera Arria V DK support dt: socfpga: Rename snps,dw-spi-mmio to snps,dw-apb-ssi dt: socfpga: Replace num-chipselect with num-cs dt: socfpga: Import and enable Cyclone V DK DTS dt: socfpga: Import and enable Arria V DK DTS arm: socfpga: Zap checkboard() arm: socfpga: Zap board_early_init_f()
arch/arm/Kconfig | 5 + arch/arm/dts/Makefile | 5 +- arch/arm/dts/socfpga.dtsi | 10 +- arch/arm/dts/socfpga_arria5.dtsi | 34 + arch/arm/dts/socfpga_arria5_socdk.dts | 74 +++ arch/arm/dts/socfpga_cyclone5_socdk.dts | 79 +++ board/altera/socfpga/Kconfig | 16 + board/altera/socfpga/Makefile | 2 +- board/altera/socfpga/iocsr_config.c | 688 +++++++++++++++++++++ board/altera/socfpga/iocsr_config.h | 17 +- board/altera/socfpga/pinmux_config.c | 403 +++++++++--- board/altera/socfpga/pinmux_config.h | 14 +- board/altera/socfpga/pll_config.h | 34 +- .../socfpga/{socfpga_cyclone5.c => socfpga.c} | 17 - configs/socfpga_arria5_defconfig | 5 + configs/socfpga_cyclone5_defconfig | 2 + drivers/spi/designware_spi.c | 2 +- include/configs/socfpga_arria5.h | 107 ++++ include/configs/socfpga_common.h | 3 +- include/configs/socfpga_cyclone5.h | 9 + 20 files changed, 1371 insertions(+), 155 deletions(-) create mode 100644 arch/arm/dts/socfpga_arria5.dtsi create mode 100644 arch/arm/dts/socfpga_arria5_socdk.dts create mode 100644 arch/arm/dts/socfpga_cyclone5_socdk.dts rename board/altera/socfpga/{socfpga_cyclone5.c => socfpga.c} (86%) create mode 100644 configs/socfpga_arria5_defconfig create mode 100644 include/configs/socfpga_arria5.h
Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
Replace multiple spaces with a single tab.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com --- board/altera/socfpga/iocsr_config.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/altera/socfpga/iocsr_config.h b/board/altera/socfpga/iocsr_config.h index 490f109..4a7ed46 100644 --- a/board/altera/socfpga/iocsr_config.h +++ b/board/altera/socfpga/iocsr_config.h @@ -9,9 +9,9 @@ #ifndef _PRELOADER_IOCSR_CONFIG_H_ #define _PRELOADER_IOCSR_CONFIG_H_
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764) -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955) -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766) +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764) +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955) +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
#endif /*_PRELOADER_IOCSR_CONFIG_H_*/
On Wed 2014-12-31 20:14:49, Marek Vasut wrote:
Replace multiple spaces with a single tab.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com
Acked-by: Pavel Machek pavel@denx.de
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764) +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955) +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
Removing ()s would be nice, too.
But this is autogenerated file, so we'd need to get altera to fix their tools...? Pavel
On Friday, January 02, 2015 at 06:10:56 AM, Pavel Machek wrote:
On Wed 2014-12-31 20:14:49, Marek Vasut wrote:
Replace multiple spaces with a single tab.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com
Acked-by: Pavel Machek pavel@denx.de
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764) +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955) +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
Removing ()s would be nice, too.
But this is autogenerated file, so we'd need to get altera to fix their tools...?
Hi!
No, we need to get this information into DT and zap this file altogether. While this might take a bit more time, that's the ultimate goal here.
Best regards, Marek Vasut
On 31.12.2014 20:14, Marek Vasut wrote:
Replace multiple spaces with a single tab.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
On 12/31/14 1:14 PM, Marek Vasut wrote:
Replace multiple spaces with a single tab.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
board/altera/socfpga/iocsr_config.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/altera/socfpga/iocsr_config.h b/board/altera/socfpga/iocsr_config.h index 490f109..4a7ed46 100644 --- a/board/altera/socfpga/iocsr_config.h +++ b/board/altera/socfpga/iocsr_config.h @@ -9,9 +9,9 @@ #ifndef _PRELOADER_IOCSR_CONFIG_H_ #define _PRELOADER_IOCSR_CONFIG_H_
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764) -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955) -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766) +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764) +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955) +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
#endif /*_PRELOADER_IOCSR_CONFIG_H_*/
Acked-by: Dinh Nguyen dinguyen@opensource.altera.com
Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com --- board/altera/socfpga/pinmux_config.c | 188 +++++++++++++++++------------------ board/altera/socfpga/pinmux_config.h | 14 +-- 2 files changed, 101 insertions(+), 101 deletions(-)
diff --git a/board/altera/socfpga/pinmux_config.c b/board/altera/socfpga/pinmux_config.c index 8b09005..b124768 100644 --- a/board/altera/socfpga/pinmux_config.c +++ b/board/altera/socfpga/pinmux_config.c @@ -4,100 +4,100 @@
/* pin mux configuration data */ unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = { - 0, /* EMACIO0 - Unused */ - 2, /* EMACIO1 - USB */ - 2, /* EMACIO2 - USB */ - 2, /* EMACIO3 - USB */ - 2, /* EMACIO4 - USB */ - 2, /* EMACIO5 - USB */ - 2, /* EMACIO6 - USB */ - 2, /* EMACIO7 - USB */ - 2, /* EMACIO8 - USB */ - 0, /* EMACIO9 - Unused */ - 2, /* EMACIO10 - USB */ - 2, /* EMACIO11 - USB */ - 2, /* EMACIO12 - USB */ - 2, /* EMACIO13 - USB */ - 0, /* EMACIO14 - N/A */ - 0, /* EMACIO15 - N/A */ - 0, /* EMACIO16 - N/A */ - 0, /* EMACIO17 - N/A */ - 0, /* EMACIO18 - N/A */ - 0, /* EMACIO19 - N/A */ - 3, /* FLASHIO0 - SDMMC */ - 3, /* FLASHIO1 - SDMMC */ - 3, /* FLASHIO2 - SDMMC */ - 3, /* FLASHIO3 - SDMMC */ - 0, /* FLASHIO4 - SDMMC */ - 0, /* FLASHIO5 - SDMMC */ - 0, /* FLASHIO6 - SDMMC */ - 0, /* FLASHIO7 - SDMMC */ - 0, /* FLASHIO8 - SDMMC */ - 3, /* FLASHIO9 - SDMMC */ - 3, /* FLASHIO10 - SDMMC */ - 3, /* FLASHIO11 - SDMMC */ - 3, /* GENERALIO0 - TRACE */ - 3, /* GENERALIO1 - TRACE */ - 3, /* GENERALIO2 - TRACE */ - 3, /* GENERALIO3 - TRACE */ - 3, /* GENERALIO4 - TRACE */ - 3, /* GENERALIO5 - TRACE */ - 3, /* GENERALIO6 - TRACE */ - 3, /* GENERALIO7 - TRACE */ - 3, /* GENERALIO8 - TRACE */ - 3, /* GENERALIO9 - SPIM0 */ - 3, /* GENERALIO10 - SPIM0 */ - 3, /* GENERALIO11 - SPIM0 */ - 3, /* GENERALIO12 - SPIM0 */ - 2, /* GENERALIO13 - CAN0 */ - 2, /* GENERALIO14 - CAN0 */ - 3, /* GENERALIO15 - I2C0 */ - 3, /* GENERALIO16 - I2C0 */ - 2, /* GENERALIO17 - UART0 */ - 2, /* GENERALIO18 - UART0 */ - 0, /* GENERALIO19 - N/A */ - 0, /* GENERALIO20 - N/A */ - 0, /* GENERALIO21 - N/A */ - 0, /* GENERALIO22 - N/A */ - 0, /* GENERALIO23 - N/A */ - 0, /* GENERALIO24 - N/A */ - 0, /* GENERALIO25 - N/A */ - 0, /* GENERALIO26 - N/A */ - 0, /* GENERALIO27 - N/A */ - 0, /* GENERALIO28 - N/A */ - 0, /* GENERALIO29 - N/A */ - 0, /* GENERALIO30 - N/A */ - 0, /* GENERALIO31 - N/A */ - 2, /* MIXED1IO0 - EMAC */ - 2, /* MIXED1IO1 - EMAC */ - 2, /* MIXED1IO2 - EMAC */ - 2, /* MIXED1IO3 - EMAC */ - 2, /* MIXED1IO4 - EMAC */ - 2, /* MIXED1IO5 - EMAC */ - 2, /* MIXED1IO6 - EMAC */ - 2, /* MIXED1IO7 - EMAC */ - 2, /* MIXED1IO8 - EMAC */ - 2, /* MIXED1IO9 - EMAC */ - 2, /* MIXED1IO10 - EMAC */ - 2, /* MIXED1IO11 - EMAC */ - 2, /* MIXED1IO12 - EMAC */ - 2, /* MIXED1IO13 - EMAC */ - 0, /* MIXED1IO14 - Unused */ - 3, /* MIXED1IO15 - QSPI */ - 3, /* MIXED1IO16 - QSPI */ - 3, /* MIXED1IO17 - QSPI */ - 3, /* MIXED1IO18 - QSPI */ - 3, /* MIXED1IO19 - QSPI */ - 3, /* MIXED1IO20 - QSPI */ - 0, /* MIXED1IO21 - GPIO */ - 0, /* MIXED2IO0 - N/A */ - 0, /* MIXED2IO1 - N/A */ - 0, /* MIXED2IO2 - N/A */ - 0, /* MIXED2IO3 - N/A */ - 0, /* MIXED2IO4 - N/A */ - 0, /* MIXED2IO5 - N/A */ - 0, /* MIXED2IO6 - N/A */ - 0, /* MIXED2IO7 - N/A */ + 3, /* EMACIO0 */ + 3, /* EMACIO1 */ + 3, /* EMACIO2 */ + 3, /* EMACIO3 */ + 3, /* EMACIO4 */ + 3, /* EMACIO5 */ + 3, /* EMACIO6 */ + 3, /* EMACIO7 */ + 3, /* EMACIO8 */ + 3, /* EMACIO9 */ + 3, /* EMACIO10 */ + 3, /* EMACIO11 */ + 3, /* EMACIO12 */ + 3, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 3, /* FLASHIO4 */ + 3, /* FLASHIO5 */ + 3, /* FLASHIO6 */ + 3, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 0, /* GENERALIO3 */ + 0, /* GENERALIO4 */ + 1, /* GENERALIO5 */ + 1, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 0, /* GENERALIO9 */ + 0, /* GENERALIO10 */ + 0, /* GENERALIO11 */ + 0, /* GENERALIO12 */ + 2, /* GENERALIO13 */ + 2, /* GENERALIO14 */ + 0, /* GENERALIO15 */ + 0, /* GENERALIO16 */ + 0, /* GENERALIO17 */ + 0, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 0, /* MIXED1IO0 */ + 1, /* MIXED1IO1 */ + 1, /* MIXED1IO2 */ + 1, /* MIXED1IO3 */ + 1, /* MIXED1IO4 */ + 0, /* MIXED1IO5 */ + 0, /* MIXED1IO6 */ + 0, /* MIXED1IO7 */ + 1, /* MIXED1IO8 */ + 1, /* MIXED1IO9 */ + 1, /* MIXED1IO10 */ + 1, /* MIXED1IO11 */ + 0, /* MIXED1IO12 */ + 0, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 1, /* MIXED1IO15 */ + 1, /* MIXED1IO16 */ + 1, /* MIXED1IO17 */ + 1, /* MIXED1IO18 */ + 0, /* MIXED1IO19 */ + 0, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ 0, /* GPLINMUX48 */ 0, /* GPLINMUX49 */ 0, /* GPLINMUX50 */ diff --git a/board/altera/socfpga/pinmux_config.h b/board/altera/socfpga/pinmux_config.h index f278f2b..21fabb0 100644 --- a/board/altera/socfpga/pinmux_config.h +++ b/board/altera/socfpga/pinmux_config.h @@ -7,21 +7,21 @@ * State of enabling for which IP connected out through the muxing. * Value 1 mean the IP connection is muxed out */ -#define CONFIG_HPS_EMAC0 (0) -#define CONFIG_HPS_EMAC1 (1) +#define CONFIG_HPS_EMAC0 (1) +#define CONFIG_HPS_EMAC1 (0) #define CONFIG_HPS_USB0 (0) #define CONFIG_HPS_USB1 (1) #define CONFIG_HPS_NAND (0) #define CONFIG_HPS_SDMMC (1) -#define CONFIG_HPS_QSPI (1) +#define CONFIG_HPS_QSPI (0) #define CONFIG_HPS_UART0 (1) #define CONFIG_HPS_UART1 (0) -#define CONFIG_HPS_TRACE (1) +#define CONFIG_HPS_TRACE (0) #define CONFIG_HPS_I2C0 (1) #define CONFIG_HPS_I2C1 (0) #define CONFIG_HPS_I2C2 (0) #define CONFIG_HPS_I2C3 (0) -#define CONFIG_HPS_SPIM0 (1) +#define CONFIG_HPS_SPIM0 (0) #define CONFIG_HPS_SPIM1 (0) #define CONFIG_HPS_SPIS0 (0) #define CONFIG_HPS_SPIS1 (0) @@ -29,10 +29,10 @@ #define CONFIG_HPS_CAN1 (0)
/* IP attribute value (which affected by pin muxing configuration) */ -#define CONFIG_HPS_SDMMC_BUSWIDTH (4) +#define CONFIG_HPS_SDMMC_BUSWIDTH (8)
/* 1 if the pins are connected out */ -#define CONFIG_HPS_QSPI_CS0 (1) +#define CONFIG_HPS_QSPI_CS0 (0) #define CONFIG_HPS_QSPI_CS1 (0) #define CONFIG_HPS_QSPI_CS2 (0) #define CONFIG_HPS_QSPI_CS3 (0)
On Wed 2014-12-31 20:14:50, Marek Vasut wrote:
Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
Will this break the other socfpga targets? Because tables are completely different... Pavel
board/altera/socfpga/pinmux_config.c | 188 +++++++++++++++++------------------ board/altera/socfpga/pinmux_config.h | 14 +-- 2 files changed, 101 insertions(+), 101 deletions(-)
diff --git a/board/altera/socfpga/pinmux_config.c b/board/altera/socfpga/pinmux_config.c index 8b09005..b124768 100644 --- a/board/altera/socfpga/pinmux_config.c +++ b/board/altera/socfpga/pinmux_config.c @@ -4,100 +4,100 @@
/* pin mux configuration data */ unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
- 0, /* EMACIO0 - Unused */
- 2, /* EMACIO1 - USB */
- 2, /* EMACIO2 - USB */
- 2, /* EMACIO3 - USB */
- 2, /* EMACIO4 - USB */
- 2, /* EMACIO5 - USB */
- 2, /* EMACIO6 - USB */
- 2, /* EMACIO7 - USB */
- 2, /* EMACIO8 - USB */
- 0, /* EMACIO9 - Unused */
- 2, /* EMACIO10 - USB */
- 2, /* EMACIO11 - USB */
- 2, /* EMACIO12 - USB */
- 2, /* EMACIO13 - USB */
- 0, /* EMACIO14 - N/A */
- 0, /* EMACIO15 - N/A */
- 0, /* EMACIO16 - N/A */
- 0, /* EMACIO17 - N/A */
- 0, /* EMACIO18 - N/A */
- 0, /* EMACIO19 - N/A */
- 3, /* FLASHIO0 - SDMMC */
- 3, /* FLASHIO1 - SDMMC */
- 3, /* FLASHIO2 - SDMMC */
- 3, /* FLASHIO3 - SDMMC */
- 0, /* FLASHIO4 - SDMMC */
- 0, /* FLASHIO5 - SDMMC */
- 0, /* FLASHIO6 - SDMMC */
- 0, /* FLASHIO7 - SDMMC */
- 0, /* FLASHIO8 - SDMMC */
- 3, /* FLASHIO9 - SDMMC */
- 3, /* FLASHIO10 - SDMMC */
- 3, /* FLASHIO11 - SDMMC */
- 3, /* GENERALIO0 - TRACE */
- 3, /* GENERALIO1 - TRACE */
- 3, /* GENERALIO2 - TRACE */
- 3, /* GENERALIO3 - TRACE */
- 3, /* GENERALIO4 - TRACE */
- 3, /* GENERALIO5 - TRACE */
- 3, /* GENERALIO6 - TRACE */
- 3, /* GENERALIO7 - TRACE */
- 3, /* GENERALIO8 - TRACE */
- 3, /* GENERALIO9 - SPIM0 */
- 3, /* GENERALIO10 - SPIM0 */
- 3, /* GENERALIO11 - SPIM0 */
- 3, /* GENERALIO12 - SPIM0 */
- 2, /* GENERALIO13 - CAN0 */
- 2, /* GENERALIO14 - CAN0 */
- 3, /* GENERALIO15 - I2C0 */
- 3, /* GENERALIO16 - I2C0 */
- 2, /* GENERALIO17 - UART0 */
- 2, /* GENERALIO18 - UART0 */
- 0, /* GENERALIO19 - N/A */
- 0, /* GENERALIO20 - N/A */
- 0, /* GENERALIO21 - N/A */
- 0, /* GENERALIO22 - N/A */
- 0, /* GENERALIO23 - N/A */
- 0, /* GENERALIO24 - N/A */
- 0, /* GENERALIO25 - N/A */
- 0, /* GENERALIO26 - N/A */
- 0, /* GENERALIO27 - N/A */
- 0, /* GENERALIO28 - N/A */
- 0, /* GENERALIO29 - N/A */
- 0, /* GENERALIO30 - N/A */
- 0, /* GENERALIO31 - N/A */
- 2, /* MIXED1IO0 - EMAC */
- 2, /* MIXED1IO1 - EMAC */
- 2, /* MIXED1IO2 - EMAC */
- 2, /* MIXED1IO3 - EMAC */
- 2, /* MIXED1IO4 - EMAC */
- 2, /* MIXED1IO5 - EMAC */
- 2, /* MIXED1IO6 - EMAC */
- 2, /* MIXED1IO7 - EMAC */
- 2, /* MIXED1IO8 - EMAC */
- 2, /* MIXED1IO9 - EMAC */
- 2, /* MIXED1IO10 - EMAC */
- 2, /* MIXED1IO11 - EMAC */
- 2, /* MIXED1IO12 - EMAC */
- 2, /* MIXED1IO13 - EMAC */
- 0, /* MIXED1IO14 - Unused */
- 3, /* MIXED1IO15 - QSPI */
- 3, /* MIXED1IO16 - QSPI */
- 3, /* MIXED1IO17 - QSPI */
- 3, /* MIXED1IO18 - QSPI */
- 3, /* MIXED1IO19 - QSPI */
- 3, /* MIXED1IO20 - QSPI */
- 0, /* MIXED1IO21 - GPIO */
- 0, /* MIXED2IO0 - N/A */
- 0, /* MIXED2IO1 - N/A */
- 0, /* MIXED2IO2 - N/A */
- 0, /* MIXED2IO3 - N/A */
- 0, /* MIXED2IO4 - N/A */
- 0, /* MIXED2IO5 - N/A */
- 0, /* MIXED2IO6 - N/A */
- 0, /* MIXED2IO7 - N/A */
- 3, /* EMACIO0 */
- 3, /* EMACIO1 */
- 3, /* EMACIO2 */
- 3, /* EMACIO3 */
- 3, /* EMACIO4 */
- 3, /* EMACIO5 */
- 3, /* EMACIO6 */
- 3, /* EMACIO7 */
- 3, /* EMACIO8 */
- 3, /* EMACIO9 */
- 3, /* EMACIO10 */
- 3, /* EMACIO11 */
- 3, /* EMACIO12 */
- 3, /* EMACIO13 */
- 0, /* EMACIO14 */
- 0, /* EMACIO15 */
- 0, /* EMACIO16 */
- 0, /* EMACIO17 */
- 0, /* EMACIO18 */
- 0, /* EMACIO19 */
- 3, /* FLASHIO0 */
- 0, /* FLASHIO1 */
- 3, /* FLASHIO2 */
- 3, /* FLASHIO3 */
- 3, /* FLASHIO4 */
- 3, /* FLASHIO5 */
- 3, /* FLASHIO6 */
- 3, /* FLASHIO7 */
- 0, /* FLASHIO8 */
- 3, /* FLASHIO9 */
- 3, /* FLASHIO10 */
- 3, /* FLASHIO11 */
- 0, /* GENERALIO0 */
- 1, /* GENERALIO1 */
- 1, /* GENERALIO2 */
- 0, /* GENERALIO3 */
- 0, /* GENERALIO4 */
- 1, /* GENERALIO5 */
- 1, /* GENERALIO6 */
- 1, /* GENERALIO7 */
- 1, /* GENERALIO8 */
- 0, /* GENERALIO9 */
- 0, /* GENERALIO10 */
- 0, /* GENERALIO11 */
- 0, /* GENERALIO12 */
- 2, /* GENERALIO13 */
- 2, /* GENERALIO14 */
- 0, /* GENERALIO15 */
- 0, /* GENERALIO16 */
- 0, /* GENERALIO17 */
- 0, /* GENERALIO18 */
- 0, /* GENERALIO19 */
- 0, /* GENERALIO20 */
- 0, /* GENERALIO21 */
- 0, /* GENERALIO22 */
- 0, /* GENERALIO23 */
- 0, /* GENERALIO24 */
- 0, /* GENERALIO25 */
- 0, /* GENERALIO26 */
- 0, /* GENERALIO27 */
- 0, /* GENERALIO28 */
- 0, /* GENERALIO29 */
- 0, /* GENERALIO30 */
- 0, /* GENERALIO31 */
- 0, /* MIXED1IO0 */
- 1, /* MIXED1IO1 */
- 1, /* MIXED1IO2 */
- 1, /* MIXED1IO3 */
- 1, /* MIXED1IO4 */
- 0, /* MIXED1IO5 */
- 0, /* MIXED1IO6 */
- 0, /* MIXED1IO7 */
- 1, /* MIXED1IO8 */
- 1, /* MIXED1IO9 */
- 1, /* MIXED1IO10 */
- 1, /* MIXED1IO11 */
- 0, /* MIXED1IO12 */
- 0, /* MIXED1IO13 */
- 0, /* MIXED1IO14 */
- 1, /* MIXED1IO15 */
- 1, /* MIXED1IO16 */
- 1, /* MIXED1IO17 */
- 1, /* MIXED1IO18 */
- 0, /* MIXED1IO19 */
- 0, /* MIXED1IO20 */
- 0, /* MIXED1IO21 */
- 0, /* MIXED2IO0 */
- 0, /* MIXED2IO1 */
- 0, /* MIXED2IO2 */
- 0, /* MIXED2IO3 */
- 0, /* MIXED2IO4 */
- 0, /* MIXED2IO5 */
- 0, /* MIXED2IO6 */
- 0, /* MIXED2IO7 */ 0, /* GPLINMUX48 */ 0, /* GPLINMUX49 */ 0, /* GPLINMUX50 */
diff --git a/board/altera/socfpga/pinmux_config.h b/board/altera/socfpga/pinmux_config.h index f278f2b..21fabb0 100644 --- a/board/altera/socfpga/pinmux_config.h +++ b/board/altera/socfpga/pinmux_config.h @@ -7,21 +7,21 @@
- State of enabling for which IP connected out through the muxing.
- Value 1 mean the IP connection is muxed out
*/ -#define CONFIG_HPS_EMAC0 (0) -#define CONFIG_HPS_EMAC1 (1) +#define CONFIG_HPS_EMAC0 (1) +#define CONFIG_HPS_EMAC1 (0) #define CONFIG_HPS_USB0 (0) #define CONFIG_HPS_USB1 (1) #define CONFIG_HPS_NAND (0) #define CONFIG_HPS_SDMMC (1) -#define CONFIG_HPS_QSPI (1) +#define CONFIG_HPS_QSPI (0) #define CONFIG_HPS_UART0 (1) #define CONFIG_HPS_UART1 (0) -#define CONFIG_HPS_TRACE (1) +#define CONFIG_HPS_TRACE (0) #define CONFIG_HPS_I2C0 (1) #define CONFIG_HPS_I2C1 (0) #define CONFIG_HPS_I2C2 (0) #define CONFIG_HPS_I2C3 (0) -#define CONFIG_HPS_SPIM0 (1) +#define CONFIG_HPS_SPIM0 (0) #define CONFIG_HPS_SPIM1 (0) #define CONFIG_HPS_SPIS0 (0) #define CONFIG_HPS_SPIS1 (0) @@ -29,10 +29,10 @@ #define CONFIG_HPS_CAN1 (0)
/* IP attribute value (which affected by pin muxing configuration) */ -#define CONFIG_HPS_SDMMC_BUSWIDTH (4) +#define CONFIG_HPS_SDMMC_BUSWIDTH (8)
/* 1 if the pins are connected out */ -#define CONFIG_HPS_QSPI_CS0 (1) +#define CONFIG_HPS_QSPI_CS0 (0) #define CONFIG_HPS_QSPI_CS1 (0) #define CONFIG_HPS_QSPI_CS2 (0) #define CONFIG_HPS_QSPI_CS3 (0)
On Friday, January 02, 2015 at 06:13:43 AM, Pavel Machek wrote:
On Wed 2014-12-31 20:14:50, Marek Vasut wrote:
Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
Will this break the other socfpga targets? Because tables are completely different...
Mainline only supports socdk and socrates, which do work with this patch. In case this did break some out-of-mainline boards, that cannot really be helped at this point.
Still, this is only used in (already broken) SPL, so there's really nothing much to be worried about there. The ultimate goal is to use pinmux from the DT and zap this file.
Best regards, Marek Vasut
On 31.12.2014 20:14, Marek Vasut wrote:
Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
This is all for SPL only, right? Not sure if we should change these defines / values now even though its not really used in mainline. But it doesn't hurt. So:
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
On Saturday, January 03, 2015 at 12:08:04 PM, Stefan Roese wrote:
On 31.12.2014 20:14, Marek Vasut wrote:
Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
This is all for SPL only, right?
Yes.
Not sure if we should change these defines / values now even though its not really used in mainline. But it doesn't hurt. So:
It doesn't hurt keeping closer to RocketBoards for the time being I guess.
Reviewed-by: Stefan Roese sr@denx.de
Thanks!
Best regards, Marek Vasut
On 12/31/14 1:14 PM, Marek Vasut wrote:
Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
board/altera/socfpga/pinmux_config.c | 188 +++++++++++++++++------------------ board/altera/socfpga/pinmux_config.h | 14 +-- 2 files changed, 101 insertions(+), 101 deletions(-)
diff --git a/board/altera/socfpga/pinmux_config.c b/board/altera/socfpga/pinmux_config.c index 8b09005..b124768 100644 --- a/board/altera/socfpga/pinmux_config.c +++ b/board/altera/socfpga/pinmux_config.c @@ -4,100 +4,100 @@
/* pin mux configuration data */
Acked-by: Dinh Nguyen dinguyen@opensource.altera.com
Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).
NOTE: This change is useless until we get proper SPL support, at which point this will likely need further rework.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com --- board/altera/socfpga/pll_config.h | 34 +++++++++++----------------------- 1 file changed, 11 insertions(+), 23 deletions(-)
diff --git a/board/altera/socfpga/pll_config.h b/board/altera/socfpga/pll_config.h index f0f59a9..8130fa4 100644 --- a/board/altera/socfpga/pll_config.h +++ b/board/altera/socfpga/pll_config.h @@ -16,9 +16,9 @@ #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0) #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3) -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3) -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (12) +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (511) +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511) +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15) #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1) #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) @@ -36,7 +36,7 @@
/* Peripheral PLL */ #define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1) -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79) +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39) /* * To tell where is the VCOs source: * 0 = EOSC1 @@ -45,13 +45,13 @@ */ #define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0) #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3) -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3) -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1) +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511) #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4) #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4) -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9) +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511) #define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0) -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (4) #define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1) #define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1) #define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) @@ -66,15 +66,8 @@ #define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1)
/* SDRAM PLL */ -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* Arria V SDRAM will run at 533MHz while Cyclone V still at 400MHz - * This if..else... is not required if generated by tools */ #define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2) -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (127) -#else -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0) -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31) -#endif /* CONFIG_SOCFPGA_ARRIA5 */ +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (79)
/* * To tell where is the VCOs source: @@ -94,17 +87,12 @@
/* Info for driver */ #define CONFIG_HPS_CLK_OSC1_HZ (25000000) -#define CONFIG_HPS_CLK_OSC2_HZ 0 +#define CONFIG_HPS_CLK_OSC2_HZ (25000000) #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 #define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) #define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define CONFIG_HPS_CLK_SDRVCO_HZ (1066000000) -#else -#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000) -#endif +#define CONFIG_HPS_CLK_SDRVCO_HZ (666666666) #define CONFIG_HPS_CLK_EMAC0_HZ (250000000) #define CONFIG_HPS_CLK_EMAC1_HZ (250000000) #define CONFIG_HPS_CLK_USBCLK_HZ (200000000)
On Wed 2014-12-31 20:14:51, Marek Vasut wrote:
Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).
NOTE: This change is useless until we get proper SPL support, at which point this will likely need further rework.
Ok, so can we wait for SPL support before doing this? (And same is true for previous patch, no?) Pavel
On Friday, January 02, 2015 at 06:19:24 AM, Pavel Machek wrote:
On Wed 2014-12-31 20:14:51, Marek Vasut wrote:
Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).
NOTE: This change is useless until we get proper SPL support, at
which point this will likely need further rework.Ok, so can we wait for SPL support before doing this? (And same is true for previous patch, no?)
I prefer to keep in sync with rocketboards code, is that a problem for you in any way please?
Best regards, Marek Vasut
On Sat 2015-01-03 21:30:56, Marek Vasut wrote:
On Friday, January 02, 2015 at 06:19:24 AM, Pavel Machek wrote:
On Wed 2014-12-31 20:14:51, Marek Vasut wrote:
Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).
NOTE: This change is useless until we get proper SPL support, at
which point this will likely need further rework.Ok, so can we wait for SPL support before doing this? (And same is true for previous patch, no?)
I prefer to keep in sync with rocketboards code, is that a problem for you in any way please?
No problem for me, but it is strange to update files that are not used. Does it solve any problem for you?
Pavel
On Wednesday, January 07, 2015 at 12:08:13 AM, Pavel Machek wrote:
On Sat 2015-01-03 21:30:56, Marek Vasut wrote:
On Friday, January 02, 2015 at 06:19:24 AM, Pavel Machek wrote:
On Wed 2014-12-31 20:14:51, Marek Vasut wrote:
Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).
NOTE: This change is useless until we get proper SPL support, at
which point this will likely need further rework.Ok, so can we wait for SPL support before doing this? (And same is true for previous patch, no?)
I prefer to keep in sync with rocketboards code, is that a problem for you in any way please?
No problem for me, but it is strange to update files that are not used. Does it solve any problem for you?
No, it's just less divergence between the codebases, which I believe is always an improvement.
Best regards, Marek Vasut
On 31.12.2014 20:14, Marek Vasut wrote:
Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).
NOTE: This change is useless until we get proper SPL support, at which point this will likely need further rework.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
Same comment as on the patch before. Not sure if we should change these defines / values now even though its not really used in mainline. But it doesn't hurt. So:
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
On 12/31/14 1:14 PM, Marek Vasut wrote:
Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).
NOTE: This change is useless until we get proper SPL support, at which point this will likely need further rework.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
board/altera/socfpga/pll_config.h | 34 +++++++++++----------------------- 1 file changed, 11 insertions(+), 23 deletions(-)
Acked-by: Dinh Nguyen dinguyen@opensource.altera.com
Add support for USB host mode and USB device mode for the Cyclone V development kit and enable support for UMS (to export SD card as USB mass storage). The UMS is activated via 'ums 0 mmc 0' command, the system must be connected to a host PC via HPS USB port and SD card must be installed for this to work.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com --- include/configs/socfpga_cyclone5.h | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index c3d958c..676144a 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -21,6 +21,7 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_BOOTZ #define CONFIG_CMD_CACHE +#define CONFIG_CMD_DFU #define CONFIG_CMD_DHCP #define CONFIG_CMD_EXT4 #define CONFIG_CMD_EXT4_WRITE @@ -33,6 +34,8 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_PING #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_USB +#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_REGEX /* Enable regular expression support */
@@ -66,6 +69,12 @@
#endif
+/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS +#endif +#define CONFIG_G_DNL_MANUFACTURER "Altera" + /* Extra Environment */ #define CONFIG_HOSTNAME socfpga_cyclone5
On Wed 2014-12-31 20:14:52, Marek Vasut wrote:
Add support for USB host mode and USB device mode for the Cyclone V development kit and enable support for UMS (to export SD card as USB mass storage). The UMS is activated via 'ums 0 mmc 0' command, the system must be connected to a host PC via HPS USB port and SD card must be installed for this to work.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com
Acked-by: Pavel Machek pavel@denx.de
On 31.12.2014 20:14, Marek Vasut wrote:
Add support for USB host mode and USB device mode for the Cyclone V development kit and enable support for UMS (to export SD card as USB mass storage). The UMS is activated via 'ums 0 mmc 0' command, the system must be connected to a host PC via HPS USB port and SD card must be installed for this to work.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
On 12/31/14 1:14 PM, Marek Vasut wrote:
Add support for USB host mode and USB device mode for the Cyclone V development kit and enable support for UMS (to export SD card as USB mass storage). The UMS is activated via 'ums 0 mmc 0' command, the system must be connected to a host PC via HPS USB port and SD card must be installed for this to work.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
include/configs/socfpga_cyclone5.h | 9 +++++++++ 1 file changed, 9 insertions(+)
Acked-by: Dinh Nguyen dinguyen@opensource.altera.com
Drop the _cyclone5 suffix from socfpga_cyclone5.c since this file will contain Arria 5 support as well.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com --- board/altera/socfpga/Makefile | 2 +- board/altera/socfpga/{socfpga_cyclone5.c => socfpga.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename board/altera/socfpga/{socfpga_cyclone5.c => socfpga.c} (100%)
diff --git a/board/altera/socfpga/Makefile b/board/altera/socfpga/Makefile index 44baa00..c867f73 100644 --- a/board/altera/socfpga/Makefile +++ b/board/altera/socfpga/Makefile @@ -6,5 +6,5 @@ # SPDX-License-Identifier: GPL-2.0+ #
-obj-y := socfpga_cyclone5.o +obj-y := socfpga.o obj-$(CONFIG_SPL_BUILD) += pinmux_config.o iocsr_config.o diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga.c similarity index 100% rename from board/altera/socfpga/socfpga_cyclone5.c rename to board/altera/socfpga/socfpga.c
On Wed 2014-12-31 20:14:53, Marek Vasut wrote:
Drop the _cyclone5 suffix from socfpga_cyclone5.c since this file will contain Arria 5 support as well.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com
Acked-by: Pavel Machek pavel@denx.de
On 31.12.2014 20:14, Marek Vasut wrote:
Drop the _cyclone5 suffix from socfpga_cyclone5.c since this file will contain Arria 5 support as well.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
On 12/31/14 1:14 PM, Marek Vasut wrote:
Drop the _cyclone5 suffix from socfpga_cyclone5.c since this file will contain Arria 5 support as well.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
board/altera/socfpga/Makefile | 2 +- board/altera/socfpga/{socfpga_cyclone5.c => socfpga.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename board/altera/socfpga/{socfpga_cyclone5.c => socfpga.c} (100%)
diff --git a/board/altera/socfpga/Makefile b/board/altera/socfpga/Makefile index 44baa00..c867f73 100644 --- a/board/altera/socfpga/Makefile +++ b/board/altera/socfpga/Makefile @@ -6,5 +6,5 @@ # SPDX-License-Identifier: GPL-2.0+ #
-obj-y := socfpga_cyclone5.o +obj-y := socfpga.o obj-$(CONFIG_SPL_BUILD) += pinmux_config.o iocsr_config.o diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga.c similarity index 100% rename from board/altera/socfpga/socfpga_cyclone5.c rename to board/altera/socfpga/socfpga.c
Acked-by: Dinh Nguyen dinguyen@opensource.altera.com
Add support for the Altera Arria V development kit.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com --- arch/arm/Kconfig | 5 + board/altera/socfpga/Kconfig | 16 + board/altera/socfpga/iocsr_config.c | 688 +++++++++++++++++++++++++++++++++++ board/altera/socfpga/iocsr_config.h | 9 + board/altera/socfpga/pinmux_config.c | 215 +++++++++++ board/altera/socfpga/socfpga.c | 7 + configs/socfpga_arria5_defconfig | 3 + include/configs/socfpga_arria5.h | 107 ++++++ 8 files changed, 1050 insertions(+) create mode 100644 configs/socfpga_arria5_defconfig create mode 100644 include/configs/socfpga_arria5.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5eb1d03..0a04cca 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -687,6 +687,11 @@ config TARGET_CM_FX6 select CPU_V7 select SUPPORT_SPL
+config TARGET_SOCFPGA_ARRIA5 + bool "Support socfpga_arria5" + select CPU_V7 + select SUPPORT_SPL + config TARGET_SOCFPGA_CYCLONE5 bool "Support socfpga_cyclone5" select CPU_V7 diff --git a/board/altera/socfpga/Kconfig b/board/altera/socfpga/Kconfig index fc42185..cbed8d6 100644 --- a/board/altera/socfpga/Kconfig +++ b/board/altera/socfpga/Kconfig @@ -13,3 +13,19 @@ config SYS_CONFIG_NAME default "socfpga_cyclone5"
endif + +if TARGET_SOCFPGA_ARRIA5 + +config SYS_BOARD + default "socfpga" + +config SYS_VENDOR + default "altera" + +config SYS_SOC + default "socfpga" + +config SYS_CONFIG_NAME + default "socfpga_arria5" + +endif diff --git a/board/altera/socfpga/iocsr_config.c b/board/altera/socfpga/iocsr_config.c index b4b5ff8..c79aa6d 100644 --- a/board/altera/socfpga/iocsr_config.c +++ b/board/altera/socfpga/iocsr_config.c @@ -8,6 +8,7 @@
#include <iocsr_config.h>
+#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5 const unsigned long iocsr_scan_chain0_table[(( CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { 0x00000000, @@ -655,3 +656,690 @@ const unsigned long iocsr_scan_chain3_table[(( 0x0000001F, 0x00004100, }; +#endif /* CONFIG_TARGET_SOCFPGA_CYCLONE5 */ + +#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5 +const unsigned long iocsr_scan_chain0_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000060, + 0x00018060, + 0x06018060, + 0x00004000, + 0x0C0300C0, + 0x0C030000, + 0x00000030, + 0x00000000, + 0x00000000, + 0x00002000, + 0x00000000, + 0x00000000, + 0x06000000, + 0x00006018, + 0x01806018, + 0x00001000, + 0x0000C030, + 0x04000000, + 0x03000000, + 0x0000300C, + 0x00000000, + 0x00000800, + 0x00006018, + 0x01806000, + 0x01800000, + 0x00000006, + 0x00001806, + 0x00000400, + 0x0000300C, + 0x00C03000, + 0x00C00000, + 0x00000003, + 0x00000C03, + 0x00000200, +}; + +const unsigned long iocsr_scan_chain1_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { + 0x00100000, + 0x300C0000, + 0x300000C0, + 0x000000C0, + 0x000300C0, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00000060, + 0x00018060, + 0x00004000, + 0x000300C0, + 0x10000000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x06018060, + 0x06018000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x0000C030, + 0x0300C000, + 0x03000000, + 0x0000300C, + 0x0000300C, + 0x00000800, + 0x00006018, + 0x01806000, + 0x01800000, + 0x00000006, + 0x00002000, + 0x00000400, + 0x0000300C, + 0x01000000, + 0x00000000, + 0x00000004, + 0x00000C03, + 0x00000200, + 0x00001806, + 0x00800000, + 0x00000000, + 0x00000002, + 0x00000800, + 0x00000100, + 0x00001000, + 0x00400000, + 0xC0300000, + 0x00000000, + 0x00000400, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { + 0x00100000, + 0x40000000, + 0x00000000, + 0x00000100, + 0x00040000, + 0x00008000, + 0x18060180, + 0x20000000, + 0x00000000, + 0x00000080, + 0x00020000, + 0x00004000, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000000, + 0x00010000, + 0x00002000, + 0x10038060, + 0x00000000, + 0x00000000, + 0x00000020, + 0x01806018, + 0x00001000, + 0x00010000, + 0x04000000, + 0x03000000, + 0x0000801C, + 0x00004000, + 0x00000800, + 0x01806018, + 0x02000000, + 0x00000000, + 0x00000008, + 0x00002000, + 0x00000400, + 0x00C0300C, + 0x00C03000, + 0x00C00003, + 0x00000C03, + 0x00300C03, + 0x00000200, + 0x00601806, + 0x80601800, + 0x80600001, + 0x80000601, + 0x00180601, + 0x00000100, +}; + +const unsigned long iocsr_scan_chain3_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { + 0x2C820D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000050, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x906808A2, + 0xA2834024, + 0x05141A00, + 0x808A20D0, + 0x34024906, + 0x01A00A28, + 0xA20D0000, + 0x24906808, + 0x00A28340, + 0xD000001A, + 0x06808A20, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000050, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x906808A2, + 0xA2834024, + 0x05141A00, + 0x808A20D0, + 0x34024906, + 0x01A00040, + 0xA20D0002, + 0x24906808, + 0x00A28340, + 0xD005141A, + 0x06808A20, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC055F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x04510680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC055F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x8341D348, + 0x821A0124, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC055F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC055F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00481800, + 0x001A1A1A, + 0x085506A0, + 0x0000E1D4, + 0x045506A0, + 0x0000E1D4, + 0x085506A0, + 0x8000E1D4, + 0x00000200, + 0x00000004, + 0x04000000, + 0x00000009, + 0x00002410, + 0x00000040, + 0x41000000, + 0x00002082, + 0x00000350, + 0x000000DA, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x022A8350, + 0x000070EA, + 0x86000000, + 0x08000004, + 0x00000000, + 0x00482000, + 0x21800000, + 0x00101061, + 0x021541A8, + 0x00003875, + 0x011541A8, + 0x00003875, + 0x021541A8, + 0x20003875, + 0x00000080, + 0x00000001, + 0x41000000, + 0x00000002, + 0x00FF0904, + 0x00000000, + 0x90400000, + 0x00000820, + 0xC0000001, + 0xFFD602AF, + 0x86FFFFFF, + 0x0A0A78B4, + 0x000D020A, + 0x00006800, + 0x028A4320, + 0xEC2CB23D, + 0x8F5D1451, + 0xA47A88A2, + 0x0001A0E9, + 0x00410D00, + 0x40000068, + 0x3D000003, + 0x51EC2CB2, + 0xA28F5D14, + 0xE9A47A88, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000540, + 0x000003A8, + 0x08AA0D40, + 0x8001C3A8, + 0x0000007F, + 0x00000000, + 0x00004060, + 0xE1208000, + 0x0000001F, + 0x00004100, +}; +#endif /* CONFIG_TARGET_SOCFPGA_ARRIA5 */ diff --git a/board/altera/socfpga/iocsr_config.h b/board/altera/socfpga/iocsr_config.h index 4a7ed46..d1c9b0d 100644 --- a/board/altera/socfpga/iocsr_config.h +++ b/board/altera/socfpga/iocsr_config.h @@ -9,9 +9,18 @@ #ifndef _PRELOADER_IOCSR_CONFIG_H_ #define _PRELOADER_IOCSR_CONFIG_H_
+#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5 #define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764) #define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) #define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955) #define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766) +#endif + +#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5 +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (1337) +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (1528) +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766) +#endif
#endif /*_PRELOADER_IOCSR_CONFIG_H_*/ diff --git a/board/altera/socfpga/pinmux_config.c b/board/altera/socfpga/pinmux_config.c index b124768..61cdc73 100644 --- a/board/altera/socfpga/pinmux_config.c +++ b/board/altera/socfpga/pinmux_config.c @@ -2,6 +2,7 @@
#include "pinmux_config.h"
+#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5 /* pin mux configuration data */ unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = { 3, /* EMACIO0 */ @@ -212,3 +213,217 @@ unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = { 0, /* USB0USEFPGA */ 0 /* SPIM0USEFPGA */ }; +#endif /* CONFIG_TARGET_SOCFPGA_CYCLONE5 */ + +#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5 +/* pin mux configuration data */ +unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 3, /* EMACIO14 */ + 3, /* EMACIO15 */ + 3, /* EMACIO16 */ + 3, /* EMACIO17 */ + 3, /* EMACIO18 */ + 3, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 3, /* GENERALIO0 */ + 3, /* GENERALIO1 */ + 3, /* GENERALIO2 */ + 3, /* GENERALIO3 */ + 3, /* GENERALIO4 */ + 3, /* GENERALIO5 */ + 3, /* GENERALIO6 */ + 3, /* GENERALIO7 */ + 3, /* GENERALIO8 */ + 0, /* GENERALIO9 */ + 0, /* GENERALIO10 */ + 0, /* GENERALIO11 */ + 0, /* GENERALIO12 */ + 0, /* GENERALIO13 */ + 0, /* GENERALIO14 */ + 3, /* GENERALIO15 */ + 3, /* GENERALIO16 */ + 2, /* GENERALIO17 */ + 2, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 3, /* GENERALIO23 */ + 3, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 0, /* MIXED1IO0 */ + 0, /* MIXED1IO1 */ + 0, /* MIXED1IO2 */ + 0, /* MIXED1IO3 */ + 0, /* MIXED1IO4 */ + 0, /* MIXED1IO5 */ + 0, /* MIXED1IO6 */ + 0, /* MIXED1IO7 */ + 0, /* MIXED1IO8 */ + 0, /* MIXED1IO9 */ + 0, /* MIXED1IO10 */ + 0, /* MIXED1IO11 */ + 0, /* MIXED1IO12 */ + 0, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 3, /* MIXED2IO0 */ + 3, /* MIXED2IO1 */ + 3, /* MIXED2IO2 */ + 3, /* MIXED2IO3 */ + 3, /* MIXED2IO4 */ + 3, /* MIXED2IO5 */ + 3, /* MIXED2IO6 */ + 3, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* CONFIG_TARGET_SOCFPGA_ARRIA5 */ diff --git a/board/altera/socfpga/socfpga.c b/board/altera/socfpga/socfpga.c index 459d82f..a9c330d 100644 --- a/board/altera/socfpga/socfpga.c +++ b/board/altera/socfpga/socfpga.c @@ -23,7 +23,14 @@ DECLARE_GLOBAL_DATA_PTR; */ int checkboard(void) { +#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5 puts("BOARD: Altera SoCFPGA Cyclone5 Board\n"); +#endif + +#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5 + puts("BOARD: Altera SoCFPGA Arria5 Board\n"); +#endif + return 0; }
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig new file mode 100644 index 0000000..f290042 --- /dev/null +++ b/configs/socfpga_arria5_defconfig @@ -0,0 +1,3 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SOCFPGA_ARRIA5=y diff --git a/include/configs/socfpga_arria5.h b/include/configs/socfpga_arria5.h new file mode 100644 index 0000000..668a91e --- /dev/null +++ b/include/configs/socfpga_arria5.h @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2014 Marek Vasut marex@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_SOCFPGA_ARRIA5_H__ +#define __CONFIG_SOCFPGA_ARRIA5_H__ + +#include <asm/arch/socfpga_base_addrs.h> +#include "../../board/altera/socfpga/pinmux_config.h" +#include "../../board/altera/socfpga/iocsr_config.h" +#include "../../board/altera/socfpga/pll_config.h" + +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#include <config_cmd_default.h> +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DFU +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_USB +#define CONFIG_CMD_USB_MASS_STORAGE + +#define CONFIG_REGEX /* Enable regular expression support */ + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "zImage" +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_BOOTCOMMAND "run ramboot" +#else +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" +#endif +#define CONFIG_LOADADDR 0x8000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS +#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII + +/* PHY */ +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" +#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 +#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" +#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 + +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS +#endif +#define CONFIG_G_DNL_MANUFACTURER "Altera" + +/* Extra Environment */ +#define CONFIG_HOSTNAME socfpga_arria5 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=zImage\0" \ + "fdt_addr=100\0" \ + "fdtimage=socfpga.dtb\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootimage};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" + +/* The rest of the configuration is shared */ +#include <configs/socfpga_common.h> + +#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */
On Wed 2014-12-31 20:14:54, Marek Vasut wrote:
Add support for the Altera Arria V development kit.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
arch/arm/Kconfig | 5 +
board/altera/socfpga/iocsr_config.c | 688 +++++++++++++++++++++++++++++++++++ board/altera/socfpga/iocsr_config.h | 9 + board/altera/socfpga/pinmux_config.c | 215 +++++++++++
These are normally autogenerated, how does that work?
board/altera/socfpga/socfpga.c | 7 + configs/socfpga_arria5_defconfig | 3 + include/configs/socfpga_arria5.h | 107 ++++++
These look better. Can more defines be moved to common socfpga.h.
Thanks, Pavel
diff --git a/include/configs/socfpga_arria5.h b/include/configs/socfpga_arria5.h new file mode 100644 index 0000000..668a91e --- /dev/null +++ b/include/configs/socfpga_arria5.h @@ -0,0 +1,107 @@ +/*
- Copyright (C) 2014 Marek Vasut marex@denx.de
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_SOCFPGA_ARRIA5_H__ +#define __CONFIG_SOCFPGA_ARRIA5_H__
+#include <asm/arch/socfpga_base_addrs.h> +#include "../../board/altera/socfpga/pinmux_config.h" +#include "../../board/altera/socfpga/iocsr_config.h" +#include "../../board/altera/socfpga/pll_config.h"
+/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#include <config_cmd_default.h> +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG
+#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DFU +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_USB +#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_REGEX /* Enable regular expression support */
+/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
+/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "zImage" +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_BOOTCOMMAND "run ramboot" +#else +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" +#endif +#define CONFIG_LOADADDR 0x8000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS +#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
+/* PHY */ +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" +#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 +#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" +#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
+#endif
+/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS +#endif +#define CONFIG_G_DNL_MANUFACTURER "Altera"
+/* Extra Environment */ +#define CONFIG_HOSTNAME socfpga_arria5
+#define CONFIG_EXTRA_ENV_SETTINGS \
- "verify=n\0" \
- "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
- "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
"bootm ${loadaddr} - ${fdt_addr}\0" \- "bootimage=zImage\0" \
- "fdt_addr=100\0" \
- "fdtimage=socfpga.dtb\0" \
"fsloadcmd=ext2load\0" \- "bootm ${loadaddr} - ${fdt_addr}\0" \
- "mmcroot=/dev/mmcblk0p2\0" \
- "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
" root=${mmcroot} rw rootwait;" \"bootz ${loadaddr} - ${fdt_addr}\0" \- "mmcload=mmc rescan;" \
"load mmc 0:1 ${loadaddr} ${bootimage};" \"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \- "qspiroot=/dev/mtdblock0\0" \
- "qspirootfstype=jffs2\0" \
- "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
" root=${qspiroot} rw rootfstype=${qspirootfstype};"\"bootm ${loadaddr} - ${fdt_addr}\0"+/* The rest of the configuration is shared */ +#include <configs/socfpga_common.h>
+#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */
On Saturday, January 03, 2015 at 04:44:21 PM, Pavel Machek wrote:
On Wed 2014-12-31 20:14:54, Marek Vasut wrote:
Add support for the Altera Arria V development kit.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
arch/arm/Kconfig | 5 +
board/altera/socfpga/iocsr_config.c | 688 +++++++++++++++++++++++++++++++++++ board/altera/socfpga/iocsr_config.h | 9 + board/altera/socfpga/pinmux_config.c | 215 +++++++++++
These are normally autogenerated, how does that work?
I just pulled the default from rocketboards source.
board/altera/socfpga/socfpga.c | 7 + configs/socfpga_arria5_defconfig | 3 + include/configs/socfpga_arria5.h | 107 ++++++
These look better. Can more defines be moved to common socfpga.h.
I'd be much happier to move toward DT. The pinmux should be a particularly low hanging fruit.
The defines here are added really only so the build would not complain until we move to DT. Basic sketch of that is already further down in the series, though for now that's U-Boot (not SPL) only.
Best regards, Marek Vasut
On 12/31/14 1:14 PM, Marek Vasut wrote:
Add support for the Altera Arria V development kit.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
arch/arm/Kconfig | 5 + board/altera/socfpga/Kconfig | 16 + board/altera/socfpga/iocsr_config.c | 688 +++++++++++++++++++++++++++++++++++ board/altera/socfpga/iocsr_config.h | 9 + board/altera/socfpga/pinmux_config.c | 215 +++++++++++ board/altera/socfpga/socfpga.c | 7 + configs/socfpga_arria5_defconfig | 3 + include/configs/socfpga_arria5.h | 107 ++++++ 8 files changed, 1050 insertions(+) create mode 100644 configs/socfpga_arria5_defconfig create mode 100644 include/configs/socfpga_arria5.h
<snip>
diff --git a/board/altera/socfpga/socfpga.c b/board/altera/socfpga/socfpga.c index 459d82f..a9c330d 100644 --- a/board/altera/socfpga/socfpga.c +++ b/board/altera/socfpga/socfpga.c @@ -23,7 +23,14 @@ DECLARE_GLOBAL_DATA_PTR; */ int checkboard(void) { +#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5 puts("BOARD: Altera SoCFPGA Cyclone5 Board\n"); +#endif
+#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
- puts("BOARD: Altera SoCFPGA Arria5 Board\n");
+#endif
- return 0;
}
Do you need this change here only to get zapped in patch 11/12. No objections really, just an observation.
Acked-by: Dinh Nguyen dinguyen@opensource.altera.com
On Sunday, January 18, 2015 at 07:19:40 AM, Dinh Nguyen wrote:
On 12/31/14 1:14 PM, Marek Vasut wrote:
Hi!
diff --git a/board/altera/socfpga/socfpga.c b/board/altera/socfpga/socfpga.c index 459d82f..a9c330d 100644 --- a/board/altera/socfpga/socfpga.c +++ b/board/altera/socfpga/socfpga.c @@ -23,7 +23,14 @@ DECLARE_GLOBAL_DATA_PTR;
*/
int checkboard(void) {
+#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
puts("BOARD: Altera SoCFPGA Cyclone5 Board\n");
+#endif
+#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
- puts("BOARD: Altera SoCFPGA Arria5 Board\n");
+#endif
return 0;
}
Do you need this change here only to get zapped in patch 11/12. No objections really, just an observation.
You're right, I re-ordered the patches to cater for this. Thanks!
Best regards, Marek Vasut
Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'. Fix the naming before we have to support both names.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com --- arch/arm/dts/socfpga.dtsi | 4 ++-- drivers/spi/designware_spi.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 969e5ad..93d3776 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -644,7 +644,7 @@ };
spi0: spi@fff00000 { - compatible = "snps,dw-spi-mmio"; + compatible = "snps,dw-apb-ssi"; #address-cells = <1>; #size-cells = <0>; reg = <0xfff00000 0x1000>; @@ -658,7 +658,7 @@ };
spi1: spi@fff01000 { - compatible = "snps,dw-spi-mmio"; + compatible = "snps,dw-apb-ssi"; #address-cells = <1>; #size-cells = <0>; reg = <0xfff01000 0x1000>; diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 98c9f03..a42c0af 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -409,7 +409,7 @@ static const struct dm_spi_ops dw_spi_ops = { };
static const struct udevice_id dw_spi_ids[] = { - { .compatible = "snps,dw-spi-mmio" }, + { .compatible = "snps,dw-apb-ssi" }, { } };
On 31.12.2014 20:14, Marek Vasut wrote:
Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'. Fix the naming before we have to support both names.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
On Wed 2014-12-31 20:14:55, Marek Vasut wrote:
Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'. Fix the naming before we have to support both names.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com
Acked-by: Pavel Machek pavel@denx.de
On 3 January 2015 at 21:15, Pavel Machek pavel@denx.de wrote:
On Wed 2014-12-31 20:14:55, Marek Vasut wrote:
Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'. Fix the naming before we have to support both names.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com
Acked-by: Pavel Machek pavel@denx.de
-- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Applied to u-boot-spi/master
thanks!
On Tuesday, January 06, 2015 at 11:37:22 AM, Jagan Teki wrote:
On 3 January 2015 at 21:15, Pavel Machek pavel@denx.de wrote:
On Wed 2014-12-31 20:14:55, Marek Vasut wrote:
Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'. Fix the naming before we have to support both names.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com
Acked-by: Pavel Machek pavel@denx.de
-- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Applied to u-boot-spi/master
Do you plan to submit this for current release ? If that's the case, please also pick 08/12 .
Thanks!
Best regards, Marek Vasut
On 6 January 2015 at 21:11, Marek Vasut marex@denx.de wrote:
On Tuesday, January 06, 2015 at 11:37:22 AM, Jagan Teki wrote:
On 3 January 2015 at 21:15, Pavel Machek pavel@denx.de wrote:
On Wed 2014-12-31 20:14:55, Marek Vasut wrote:
Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'. Fix the naming before we have to support both names.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com
Acked-by: Pavel Machek pavel@denx.de
-- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Applied to u-boot-spi/master
Do you plan to submit this for current release ? If that's the case, please also pick 08/12 .
Yes - pls confirm this is 08/12 "[PATCH 08/12] dt: socfpga: Replace num-chipselect with num-cs"
thanks!
On Tuesday, January 06, 2015 at 05:43:28 PM, Jagan Teki wrote:
On 6 January 2015 at 21:11, Marek Vasut marex@denx.de wrote:
On Tuesday, January 06, 2015 at 11:37:22 AM, Jagan Teki wrote:
On 3 January 2015 at 21:15, Pavel Machek pavel@denx.de wrote:
On Wed 2014-12-31 20:14:55, Marek Vasut wrote:
Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'. Fix the naming before we have to support both names.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com
Acked-by: Pavel Machek pavel@denx.de
-- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Applied to u-boot-spi/master
Do you plan to submit this for current release ? If that's the case, please also pick 08/12 .
Yes - pls confirm this is 08/12 "[PATCH 08/12] dt: socfpga: Replace num-chipselect with num-cs"
Yes it is ^^^^^ ;-)
Please make sure these two land in current release then, since we don't want to introduce incompatible DT props. Thanks!
Best regards, Marek Vasut
This optional DT property is called 'num-cs', so repair the misnomers.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com --- arch/arm/dts/socfpga.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 93d3776..bf791c5 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -637,7 +637,7 @@ interrupts = <0 151 4>; clocks = <&qspi_clk>; ext-decoder = <0>; /* external decoder */ - num-chipselect = <4>; + num-cs = <4>; fifo-depth = <128>; bus-num = <2>; status = "disabled"; @@ -649,7 +649,7 @@ #size-cells = <0>; reg = <0xfff00000 0x1000>; interrupts = <0 154 4>; - num-chipselect = <4>; + num-cs = <4>; bus-num = <0>; tx-dma-channel = <&pdma 16>; rx-dma-channel = <&pdma 17>; @@ -663,7 +663,7 @@ #size-cells = <0>; reg = <0xfff01000 0x1000>; interrupts = <0 156 4>; - num-chipselect = <4>; + num-cs = <4>; bus-num = <1>; tx-dma-channel = <&pdma 20>; rx-dma-channel = <&pdma 21>;
On Wed 2014-12-31 20:14:56, Marek Vasut wrote:
This optional DT property is called 'num-cs', so repair the misnomers.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com
Acked-by: Pavel Machek pavel@denx.de
On 3 January 2015 at 21:15, Pavel Machek pavel@denx.de wrote:
On Wed 2014-12-31 20:14:56, Marek Vasut wrote:
This optional DT property is called 'num-cs', so repair the misnomers.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com
Acked-by: Pavel Machek pavel@denx.de
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
Applied to u-boot-spi/master
thanks!
Import DTS for Cyclone V development kit and enable support for DT. The DT is imported from Linux 3.19-rc1 as of commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672 .
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com --- arch/arm/dts/Makefile | 4 +- arch/arm/dts/socfpga_cyclone5_socdk.dts | 79 +++++++++++++++++++++++++++++++++ configs/socfpga_cyclone5_defconfig | 2 + 3 files changed, 84 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/socfpga_cyclone5_socdk.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e6a495c..c851d65 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -48,7 +48,9 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \ zynq-zc770-xm013.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
-dtb-$(CONFIG_SOCFPGA) += socfpga_cyclone5_socrates.dtb +dtb-$(CONFIG_SOCFPGA) += \ + socfpga_cyclone5_socdk.dtb \ + socfpga_cyclone5_socrates.dtb
targets += $(dtb-y)
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts new file mode 100644 index 0000000..8e1f88c --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Altera SOCFPGA Cyclone V SoC Development Kit"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + aliases { + /* this allow the ethaddr uboot environmnet variable contents + * to be added to the gmac1 device tree blob. + */ + ethernet0 = &gmac1; + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&mmc0 { + cd-gpios = <&portb 18 0>; + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; +}; + +&usb1 { + status = "okay"; +}; diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 4b2ede4..2d3dd47 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -1,3 +1,5 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
On 31.12.2014 20:14, Marek Vasut wrote:
Import DTS for Cyclone V development kit and enable support for DT. The DT is imported from Linux 3.19-rc1 as of commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672 .
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
On Wed 2014-12-31 20:14:57, Marek Vasut wrote:
Import DTS for Cyclone V development kit and enable support for DT. The DT is imported from Linux 3.19-rc1 as of commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672 .
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com
Acked-by: Pavel Machek pavel@denx.de
Import DTS for Arria V development kit and enable support for DT. The DT is imported from Linux 3.19-rc1 as of commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672 .
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com --- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_arria5.dtsi | 34 ++++++++++++++++ arch/arm/dts/socfpga_arria5_socdk.dts | 74 +++++++++++++++++++++++++++++++++++ configs/socfpga_arria5_defconfig | 2 + 4 files changed, 111 insertions(+) create mode 100644 arch/arm/dts/socfpga_arria5.dtsi create mode 100644 arch/arm/dts/socfpga_arria5_socdk.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c851d65..2a84323 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -49,6 +49,7 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \ dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
dtb-$(CONFIG_SOCFPGA) += \ + socfpga_arria5_socdk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_socrates.dtb
diff --git a/arch/arm/dts/socfpga_arria5.dtsi b/arch/arm/dts/socfpga_arria5.dtsi new file mode 100644 index 0000000..5175f03 --- /dev/null +++ b/arch/arm/dts/socfpga_arria5.dtsi @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/* First 4KB has trampoline code for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; +#include "socfpga.dtsi" + +/ { + soc { + clkmgr@ffd04000 { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; + + mmc0: dwmmc0@ff704000 { + num-slots = <1>; + broken-cd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + }; + + sysmgr@ffd08000 { + cpu1-start-addr = <0xffd080c4>; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts new file mode 100644 index 0000000..4e529a1 --- /dev/null +++ b/arch/arm/dts/socfpga_arria5_socdk.dts @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "socfpga_arria5.dtsi" + +/ { + model = "Altera SOCFPGA Arria V SoC Development Kit"; + compatible = "altr,socfpga-arria5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + aliases { + /* this allow the ethaddr uboot environmnet variable contents + * to be added to the gmac1 device tree blob. + */ + ethernet0 = &gmac1; + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; +}; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; +}; + +&usb1 { + status = "okay"; +}; diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index f290042..f152e9d 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -1,3 +1,5 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_TARGET_SOCFPGA_ARRIA5=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
On 31.12.2014 20:14, Marek Vasut wrote:
Import DTS for Arria V development kit and enable support for DT. The DT is imported from Linux 3.19-rc1 as of commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672 .
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
On Wed 2014-12-31 20:14:58, Marek Vasut wrote:
Import DTS for Arria V development kit and enable support for DT. The DT is imported from Linux 3.19-rc1 as of commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672 .
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com
Acked-by: Pavel Machek pavel@denx.de
On 12/31/14 1:14 PM, Marek Vasut wrote:
Import DTS for Arria V development kit and enable support for DT. The DT is imported from Linux 3.19-rc1 as of commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672 .
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_arria5.dtsi | 34 ++++++++++++++++ arch/arm/dts/socfpga_arria5_socdk.dts | 74 +++++++++++++++++++++++++++++++++++ configs/socfpga_arria5_defconfig | 2 + 4 files changed, 111 insertions(+) create mode 100644 arch/arm/dts/socfpga_arria5.dtsi create mode 100644 arch/arm/dts/socfpga_arria5_socdk.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c851d65..2a84323 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -49,6 +49,7 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \ dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
dtb-$(CONFIG_SOCFPGA) += \
- socfpga_arria5_socdk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_socrates.dtb
diff --git a/arch/arm/dts/socfpga_arria5.dtsi b/arch/arm/dts/socfpga_arria5.dtsi new file mode 100644 index 0000000..5175f03 --- /dev/null +++ b/arch/arm/dts/socfpga_arria5.dtsi @@ -0,0 +1,34 @@ +/*
- Copyright (C) 2013 Altera Corporation <www.altera.com>
Nit: extra space before "Copyright".
- SPDX-License-Identifier: GPL-2.0+
- */
+/dts-v1/; +/* First 4KB has trampoline code for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; +#include "socfpga.dtsi"
+/ {
- soc {
clkmgr@ffd04000 {clocks {osc1 {clock-frequency = <25000000>;};};};mmc0: dwmmc0@ff704000 {num-slots = <1>;broken-cd;bus-width = <4>;cap-mmc-highspeed;cap-sd-highspeed;};sysmgr@ffd08000 {cpu1-start-addr = <0xffd080c4>;};- };
+}; diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts new file mode 100644 index 0000000..4e529a1 --- /dev/null +++ b/arch/arm/dts/socfpga_arria5_socdk.dts @@ -0,0 +1,74 @@ +/*
- Copyright (C) 2013 Altera Corporation <www.altera.com>
Same nit
Dinh
On Sunday, January 18, 2015 at 07:21:34 AM, Dinh Nguyen wrote:
On 12/31/14 1:14 PM, Marek Vasut wrote:
[...]
diff --git a/arch/arm/dts/socfpga_arria5.dtsi b/arch/arm/dts/socfpga_arria5.dtsi new file mode 100644 index 0000000..5175f03 --- /dev/null +++ b/arch/arm/dts/socfpga_arria5.dtsi @@ -0,0 +1,34 @@ +/*
- Copyright (C) 2013 Altera Corporation <www.altera.com>
Nit: extra space before "Copyright".
Hi!
Sorry for the late reply. This DTS comes from mainline Linux, so I wonder if it makes sense to diverge here, especially since this is just a comment. Diverging in the DTS files would make it more annoying in the long run, since checking the differences between Linux and U-Boot would spit this one false positive.
What do you think please ?
Best regards, Marek Vasut
Since all boards now have a DT, instead of hard-coding the board name into the U-Boot binary, read the board name from DT "model" property.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com --- board/altera/socfpga/socfpga.c | 16 ---------------- include/configs/socfpga_common.h | 2 +- 2 files changed, 1 insertion(+), 17 deletions(-)
diff --git a/board/altera/socfpga/socfpga.c b/board/altera/socfpga/socfpga.c index a9c330d..2b2b63d 100644 --- a/board/altera/socfpga/socfpga.c +++ b/board/altera/socfpga/socfpga.c @@ -19,22 +19,6 @@ DECLARE_GLOBAL_DATA_PTR;
/* - * Print Board information - */ -int checkboard(void) -{ -#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5 - puts("BOARD: Altera SoCFPGA Cyclone5 Board\n"); -#endif - -#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5 - puts("BOARD: Altera SoCFPGA Arria5 Board\n"); -#endif - - return 0; -} - -/* * Initialization function which happen at early stage of c code */ int board_early_init_f(void) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 6b1f967..c2a4c72 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -19,7 +19,7 @@ * High level configuration */ #define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_DISPLAY_BOARDINFO_LATE #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_SYS_NO_FLASH
On 31.12.2014 20:14, Marek Vasut wrote:
Since all boards now have a DT, instead of hard-coding the board name into the U-Boot binary, read the board name from DT "model" property.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
On Wed 2014-12-31 20:14:59, Marek Vasut wrote:
Since all boards now have a DT, instead of hard-coding the board name into the U-Boot binary, read the board name from DT "model" property.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com
Acked-by: Pavel Machek pavel@denx.de
On 12/31/14 1:14 PM, Marek Vasut wrote:
Since all boards now have a DT, instead of hard-coding the board name into the U-Boot binary, read the board name from DT "model" property.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
board/altera/socfpga/socfpga.c | 16 ---------------- include/configs/socfpga_common.h | 2 +- 2 files changed, 1 insertion(+), 17 deletions(-)
Acked-by: Dinh Nguyen dinguyen@opensource.altera.com
Zap this unused empty function, no point in having it.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com --- board/altera/socfpga/socfpga.c | 8 -------- include/configs/socfpga_common.h | 1 - 2 files changed, 9 deletions(-)
diff --git a/board/altera/socfpga/socfpga.c b/board/altera/socfpga/socfpga.c index 2b2b63d..20d2216 100644 --- a/board/altera/socfpga/socfpga.c +++ b/board/altera/socfpga/socfpga.c @@ -19,14 +19,6 @@ DECLARE_GLOBAL_DATA_PTR;
/* - * Initialization function which happen at early stage of c code - */ -int board_early_init_f(void) -{ - return 0; -} - -/* * Miscellaneous platform dependent initialisations */ int board_init(void) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index c2a4c72..5254e9b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -20,7 +20,6 @@ */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO_LATE -#define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_SYS_NO_FLASH #define CONFIG_CLOCKS
On 31.12.2014 20:15, Marek Vasut wrote:
Zap this unused empty function, no point in having it.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
On Wed 2014-12-31 20:15:00, Marek Vasut wrote:
Zap this unused empty function, no point in having it.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com
Acked-by: Pavel Machek pavel@denx.de
On 12/31/14 1:15 PM, Marek Vasut wrote:
Zap this unused empty function, no point in having it.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See clsee@opensource.altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Pavel Machek pavel@denx.de Cc: Stefan Roese sr@denx.de Cc: Vince Bridgers vbridger@opensource.altera.com
board/altera/socfpga/socfpga.c | 8 -------- include/configs/socfpga_common.h | 1 - 2 files changed, 9 deletions(-)
Acked-by: Dinh Nguyen dinguyen@opensource.altera.com
participants (5)
-
Dinh Nguyen -
Jagan Teki -
Marek Vasut -
Pavel Machek -
Stefan Roese