[U-Boot] [PATCH v2 0/6] rockchip: spl: rk3399: prepare to have SPI config per-board
To support SPI flashes (via the device model) and enable loading of later-stage images from SPI in SPL, we need a few adjustments to the common configuration header for the RK3399: - enable SPL_SPI_LOAD if SPI is enabled for SPL (in rk3399_common) - move CONFIG_SPI and CONFIG_SPI_FLASH (from rk3399_common) to defconfig
Changes in v2: - fixes a wrong macro usage, which caused the SPI module input clock frequency to be significantly higher than intended - frequencies have now been validated using an oscilloscope (keep in mind that all frequencies are derived from a 99MHz module input clock) at the following measurement points: * 1 MHz ... 0.99 MHz * 5 MHz ... 4.95 MHz * 10 MHz ... 9.9 MHz * 30 MHz ... 33 MHz * 50 MHz ... 49.5 MHz - fixes an off-by-one for the RK3399 that cause the SPI module input clock to be misstated as 84MHz (even though it was running at 99MHz)
Jakob Unterwurzacher (2): rockchip: spi: enable support for the rk_spi driver for the RK3399 rockchip: spi: rk3399: move CONFIG_SPI and CONFIG_SPI_FLASH to defconfig
Philipp Tomsich (4): rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5 clk: rk3399: fix off-by one during rate calculation in i2c/spi_set_rate rockchip: pinctrl: rk3399: add support for the SPI5 controller rockchip: spl: rk3399: enable SPL_SPI_LOAD if SPI is enabled for SPL
arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 12 +++++ arch/arm/include/asm/arch-rockchip/periph.h | 3 ++ drivers/clk/rockchip/clk_rk3399.c | 71 ++++++++++++++++++++++++- drivers/pinctrl/rockchip/pinctrl_rk3399.c | 17 ++++++ drivers/spi/rk_spi.c | 1 + include/configs/rk3399_common.h | 5 +- 6 files changed, 106 insertions(+), 3 deletions(-)
This change adds support for configuring the module clocks for SPI1 and SPI5 from the 594MHz GPLL.
Note that the driver (rk_spi.c) always sets this to 99MHz, but the implemented functionality is more general and will also support different clock configurations.
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Tested-by: Jakob Unterwurzacher jakob.unterwurzacher@theobroma-systems.com Tested-by: Klaus Goger klaus.goger@theobroma-systems.com
---
Changes in v2: - fixes a wrong macro usage, which caused the SPI module input clock frequency to be significantly higher than intended - frequencies have now been validated using an oscilloscope (keep in mind that all frequencies are derived from a 99MHz module input clock) at the following measurement points (assuming the other fix for the usage of DIV_RATE from the series): * 1 MHz ... 0.99 MHz * 5 MHz ... 4.95 MHz * 10 MHz ... 9.9 MHz * 30 MHz ... 33 MHz * 50 MHz ... 49.5 MHz
drivers/clk/rockchip/clk_rk3399.c | 69 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index f778ddf..9150183 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -605,6 +605,67 @@ static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) return DIV_TO_RATE(GPLL_HZ, src_clk_div); }
+#define SPI_CLK_REG_MASK(bus) \ + (CLK_SPI_PLL_DIV_CON_MASK << \ + CLK_SPI ##bus## _PLL_DIV_CON_SHIFT | \ + CLK_SPI_PLL_SEL_MASK << \ + CLK_SPI ##bus## _PLL_SEL_SHIFT) + +#define SPI_CLK_REG_VALUE(bus, clk_div) \ + ((clk_div - 1) << \ + CLK_SPI ##bus## _PLL_DIV_CON_SHIFT | \ + CLK_SPI_PLL_SEL_GPLL << \ + CLK_SPI ##bus## _PLL_SEL_SHIFT) + +#define SPI_CLK_DIV_VALUE(con, bus) \ + (con >> CLK_SPI ##bus## _PLL_DIV_CON_SHIFT) & \ + CLK_SPI_PLL_DIV_CON_MASK; + +static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) +{ + u32 div, con; + + switch (clk_id) { + case SCLK_SPI1: + con = readl(&cru->clksel_con[59]); + div = SPI_CLK_DIV_VALUE(con, 1); + break; + case SCLK_SPI5: + con = readl(&cru->clksel_con[58]); + div = SPI_CLK_DIV_VALUE(con, 5); + break; + default: + error("%s: SPI clk-id %ld not supported\n", __func__, clk_id); + return -EINVAL; + } + + return DIV_TO_RATE(GPLL_HZ, div); +} + +static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) +{ + int src_clk_div; + + src_clk_div = GPLL_HZ / hz; + assert((src_clk_div - 1) < 127); + + switch (clk_id) { + case SCLK_SPI1: + rk_clrsetreg(&cru->clksel_con[59], SPI_CLK_REG_MASK(1), + SPI_CLK_REG_VALUE(1, src_clk_div)); + break; + case SCLK_SPI5: + rk_clrsetreg(&cru->clksel_con[58], SPI_CLK_REG_MASK(5), + SPI_CLK_REG_VALUE(5, src_clk_div)); + break; + default: + error("%s: SPI clk-id %ld not supported\n", __func__, clk_id); + return -EINVAL; + } + + return DIV_TO_RATE(GPLL_HZ, src_clk_div); +} + static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) { struct pll_div vpll_config = {0}; @@ -780,6 +841,10 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case SCLK_I2C7: rate = rk3399_i2c_get_clk(priv->cru, clk->id); break; + case SCLK_SPI1: + case SCLK_SPI5: + rate = rk3399_spi_get_clk(priv->cru, clk->id); + break; case SCLK_UART0: case SCLK_UART2: return 24000000; @@ -818,6 +883,10 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case SCLK_I2C7: ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate); break; + case SCLK_SPI1: + case SCLK_SPI5: + ret = rk3399_spi_set_clk(priv->cru, clk->id, rate); + break; case DCLK_VOP0: case DCLK_VOP1: ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
For the RK3399, i2c_set_rate (and by extension: our spi_set_rate, which had been mindlessly following the template of the i2c_set_rate implementation) miscalculates the rate returned due to a off-by-one error resulting from the following sequence of events: 1. calculates 'src_div := src_freq / target_freq' 2. stores 'src_div - 1' into the register (the actual divider applied in hardware is biased by adding 1) 3. returns the result of the DIV_RATE(src_freq, src_div) macro, which expects the (decremented) divider from the hardware-register and implictly adds 1 (i.e. 'DIV_RATE(freq, div) := freq / (div + 1)')
This can be observed with the SPI driver, which sets a rate of 99MHz based on the GPLL frequency of 594MHz: the hardware generates a clock of 99MHz (src_div is 6, the bitfield in the register correctly reads 5), but reports a frequency of 84MHz (594 / 7) on return.
To fix, we have two options: * either we bias (i.e. "DIV_RATE(GPLL, src_div - 1)"), which doesn't make for a particularily nice read * we simply call the i2c/spi_get_rate function (introducing additional overhead for the additional register-read), which reads the divider from the register and then passes it through the DIV_RATE macro
Given that this code is not time-critical, the more readable solution (i.e. calling the appropriate get_rate function) is implemented in this change.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Tested-by: Klaus Goger klaus.goger@theobroma-systems.com
---
Changes in v2: - fixes an off-by-one for the RK3399 that cause the SPI module input clock to be misstated as 84MHz (even though it was running at 99MHz)
drivers/clk/rockchip/clk_rk3399.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 9150183..8e0d5af 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -602,7 +602,7 @@ static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) return -EINVAL; }
- return DIV_TO_RATE(GPLL_HZ, src_clk_div); + return rk3399_i2c_get_clk(cru, clk_id); }
#define SPI_CLK_REG_MASK(bus) \ @@ -663,7 +663,7 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) return -EINVAL; }
- return DIV_TO_RATE(GPLL_HZ, src_clk_div); + return rk3399_spi_get_clk(cru, clk_id); }
static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
On 29 March 2017 at 05:31, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
For the RK3399, i2c_set_rate (and by extension: our spi_set_rate, which had been mindlessly following the template of the i2c_set_rate implementation) miscalculates the rate returned due to a off-by-one error resulting from the following sequence of events:
- calculates 'src_div := src_freq / target_freq'
- stores 'src_div - 1' into the register (the actual divider applied in hardware is biased by adding 1)
- returns the result of the DIV_RATE(src_freq, src_div) macro, which expects the (decremented) divider from the hardware-register and implictly adds 1 (i.e. 'DIV_RATE(freq, div) := freq / (div + 1)')
This can be observed with the SPI driver, which sets a rate of 99MHz based on the GPLL frequency of 594MHz: the hardware generates a clock of 99MHz (src_div is 6, the bitfield in the register correctly reads 5), but reports a frequency of 84MHz (594 / 7) on return.
To fix, we have two options:
- either we bias (i.e. "DIV_RATE(GPLL, src_div - 1)"), which doesn't make for a particularily nice read
- we simply call the i2c/spi_get_rate function (introducing additional overhead for the additional register-read), which reads the divider from the register and then passes it through the DIV_RATE macro
Given that this code is not time-critical, the more readable solution (i.e. calling the appropriate get_rate function) is implemented in this change.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Tested-by: Klaus Goger klaus.goger@theobroma-systems.com
Changes in v2:
- fixes an off-by-one for the RK3399 that cause the SPI module input clock to be misstated as 84MHz (even though it was running at 99MHz)
drivers/clk/rockchip/clk_rk3399.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
This commit adds support for the pin-configuration of the SPI5 controller of the RK3399 through the following changes: * grf_rk3399.h: adds definition for configuring the SPI5 pins in the GPIO2C group * periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5 * pinctrl_rk3399.c: adds the reverse-mapping from the IRQ# to PERIPH_ID_SPI5; dispatches PERIPH_ID_SPI3 through SPI5 to the appropriate pin-config function; implements the pin-configuration for PERIPH_ID_SPI5 using the GPIO2C group
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Tested-by: Jakob Unterwurzacher jakob.unterwurzacher@theobroma-systems.com ---
Changes in v2: None
arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 12 ++++++++++++ arch/arm/include/asm/arch-rockchip/periph.h | 3 +++ drivers/pinctrl/rockchip/pinctrl_rk3399.c | 17 +++++++++++++++++ 3 files changed, 32 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index c424753..cbcff2e 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -344,6 +344,18 @@ enum { GRF_GPIO2C1_SEL_SHIFT = 2, GRF_GPIO2C1_SEL_MASK = 3 << GRF_GPIO2C1_SEL_SHIFT, GRF_UART0BT_SOUT = 1, + GRF_GPIO2C4_SEL_SHIFT = 8, + GRF_GPIO2C4_SEL_MASK = 3 << GRF_GPIO2C4_SEL_SHIFT, + GRF_SPI5EXPPLUS_RXD = 2, + GRF_GPIO2C5_SEL_SHIFT = 10, + GRF_GPIO2C5_SEL_MASK = 3 << GRF_GPIO2C5_SEL_SHIFT, + GRF_SPI5EXPPLUS_TXD = 2, + GRF_GPIO2C6_SEL_SHIFT = 12, + GRF_GPIO2C6_SEL_MASK = 3 << GRF_GPIO2C6_SEL_SHIFT, + GRF_SPI5EXPPLUS_CLK = 2, + GRF_GPIO2C7_SEL_SHIFT = 14, + GRF_GPIO2C7_SEL_MASK = 3 << GRF_GPIO2C7_SEL_SHIFT, + GRF_SPI5EXPPLUS_CSN0 = 2,
/* GRF_GPIO3A_IOMUX */ GRF_GPIO3A0_SEL_SHIFT = 0, diff --git a/arch/arm/include/asm/arch-rockchip/periph.h b/arch/arm/include/asm/arch-rockchip/periph.h index 239a274..8018d47 100644 --- a/arch/arm/include/asm/arch-rockchip/periph.h +++ b/arch/arm/include/asm/arch-rockchip/periph.h @@ -27,6 +27,9 @@ enum periph_id { PERIPH_ID_SPI0, PERIPH_ID_SPI1, PERIPH_ID_SPI2, + PERIPH_ID_SPI3, + PERIPH_ID_SPI4, + PERIPH_ID_SPI5, PERIPH_ID_UART0, PERIPH_ID_UART1, PERIPH_ID_UART2, diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c index 507bec4..6eb657f 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c @@ -145,7 +145,19 @@ static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf, | GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT | GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT); break; + case PERIPH_ID_SPI5: + if (cs != 0) + goto err; + rk_clrsetreg(&grf->gpio2c_iomux, + GRF_GPIO2C4_SEL_MASK | GRF_GPIO2C5_SEL_MASK + | GRF_GPIO2C6_SEL_MASK | GRF_GPIO2C7_SEL_MASK, + GRF_SPI5EXPPLUS_RXD << GRF_GPIO2C4_SEL_SHIFT + | GRF_SPI5EXPPLUS_TXD << GRF_GPIO2C5_SEL_SHIFT + | GRF_SPI5EXPPLUS_CLK << GRF_GPIO2C6_SEL_SHIFT + | GRF_SPI5EXPPLUS_CSN0 << GRF_GPIO2C7_SEL_SHIFT); + break; default: + printf("%s: spi_id %d is not supported.\n", __func__, spi_id); goto err; }
@@ -259,6 +271,9 @@ static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags) case PERIPH_ID_SPI0: case PERIPH_ID_SPI1: case PERIPH_ID_SPI2: + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + case PERIPH_ID_SPI5: pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags); break; case PERIPH_ID_UART0: @@ -307,6 +322,8 @@ static int rk3399_pinctrl_get_periph_id(struct udevice *dev, return PERIPH_ID_SPI1; case 52: return PERIPH_ID_SPI2; + case 132: + return PERIPH_ID_SPI5; case 57: return PERIPH_ID_I2C0; case 59: /* Note strange order */
On 29 March 2017 at 05:31, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
This commit adds support for the pin-configuration of the SPI5 controller of the RK3399 through the following changes:
- grf_rk3399.h: adds definition for configuring the SPI5 pins in the GPIO2C group
- periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5
- pinctrl_rk3399.c: adds the reverse-mapping from the IRQ# to PERIPH_ID_SPI5; dispatches PERIPH_ID_SPI3 through SPI5 to the appropriate pin-config function; implements the pin-configuration for PERIPH_ID_SPI5 using the GPIO2C group
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Tested-by: Jakob Unterwurzacher jakob.unterwurzacher@theobroma-systems.com
Changes in v2: None
arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 12 ++++++++++++ arch/arm/include/asm/arch-rockchip/periph.h | 3 +++ drivers/pinctrl/rockchip/pinctrl_rk3399.c | 17 +++++++++++++++++ 3 files changed, 32 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
From: Jakob Unterwurzacher jakob.unterwurzacher@theobroma-systems.com
The existing Rockchip SPI (rk_spi.c) driver also matches the hardware block found in the RK3399. This has been confirmed both with SPI NOR flashes and general SPI transfers on the RK3399-Q7 for SPI1 and SPI5.
This change adds the 'rockchip,rk3399-spi' string to its compatible list to allow reuse of the existing driver.
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Tested-by: Jakob Unterwurzacher jakob.unterwurzacher@theobroma-systems.com ---
Changes in v2: None
drivers/spi/rk_spi.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index 3e44f17..91e169c 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -403,6 +403,7 @@ static const struct dm_spi_ops rockchip_spi_ops = {
static const struct udevice_id rockchip_spi_ids[] = { { .compatible = "rockchip,rk3288-spi" }, + { .compatible = "rockchip,rk3399-spi" }, { } };
On 29 March 2017 at 05:31, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
From: Jakob Unterwurzacher jakob.unterwurzacher@theobroma-systems.com
The existing Rockchip SPI (rk_spi.c) driver also matches the hardware block found in the RK3399. This has been confirmed both with SPI NOR flashes and general SPI transfers on the RK3399-Q7 for SPI1 and SPI5.
This change adds the 'rockchip,rk3399-spi' string to its compatible list to allow reuse of the existing driver.
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Tested-by: Jakob Unterwurzacher jakob.unterwurzacher@theobroma-systems.com
Changes in v2: None
drivers/spi/rk_spi.c | 1 + 1 file changed, 1 insertion(+)
Acked-by: Simon Glass sjg@chromium.org
From: Jakob Unterwurzacher jakob.unterwurzacher@theobroma-systems.com
On the RK3399-Q7 we need to enable a number of configuration options (e.g. CONFIG_SPI_FLASH_WINBND) dependent on Kconfig seeing CONFIG_SPI and CONFIG_SPI_FLASH active.
To allow for these being defined in Kconfig (e.g. via defconfig) and to avoid a warning on having the macro defined multiple times, we remove them from the common header file.
Note that the rk3399-evb does not currently have the rk_spi.c driver active (i.e. CONFIG_ROCKCHIP_SPI), so there's no change to the evb-rk3399_defconfig as part of this change.
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Tested-by: Jakob Unterwurzacher jakob.unterwurzacher@theobroma-systems.com ---
Changes in v2: None
include/configs/rk3399_common.h | 2 -- 1 file changed, 2 deletions(-)
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index a36725c..db3125e 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -54,8 +54,6 @@ #define CONFIG_SYS_SDRAM_BASE 0 #define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SPI_FLASH -#define CONFIG_SPI #define CONFIG_SF_DEFAULT_SPEED 20000000
#ifndef CONFIG_SPL_BUILD
On 29 March 2017 at 05:31, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
From: Jakob Unterwurzacher jakob.unterwurzacher@theobroma-systems.com
On the RK3399-Q7 we need to enable a number of configuration options (e.g. CONFIG_SPI_FLASH_WINBND) dependent on Kconfig seeing CONFIG_SPI and CONFIG_SPI_FLASH active.
To allow for these being defined in Kconfig (e.g. via defconfig) and to avoid a warning on having the macro defined multiple times, we remove them from the common header file.
Note that the rk3399-evb does not currently have the rk_spi.c driver active (i.e. CONFIG_ROCKCHIP_SPI), so there's no change to the evb-rk3399_defconfig as part of this change.
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Tested-by: Jakob Unterwurzacher jakob.unterwurzacher@theobroma-systems.com
Changes in v2: None
include/configs/rk3399_common.h | 2 -- 1 file changed, 2 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
On 31 March 2017 at 22:23, Simon Glass sjg@chromium.org wrote:
On 29 March 2017 at 05:31, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
From: Jakob Unterwurzacher jakob.unterwurzacher@theobroma-systems.com
On the RK3399-Q7 we need to enable a number of configuration options (e.g. CONFIG_SPI_FLASH_WINBND) dependent on Kconfig seeing CONFIG_SPI and CONFIG_SPI_FLASH active.
To allow for these being defined in Kconfig (e.g. via defconfig) and to avoid a warning on having the macro defined multiple times, we remove them from the common header file.
Note that the rk3399-evb does not currently have the rk_spi.c driver active (i.e. CONFIG_ROCKCHIP_SPI), so there's no change to the evb-rk3399_defconfig as part of this change.
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Tested-by: Jakob Unterwurzacher jakob.unterwurzacher@theobroma-systems.com
Changes in v2: None
include/configs/rk3399_common.h | 2 -- 1 file changed, 2 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-rockchip, thanks!
To include the ability to load from an SPI flash in SPL, it's not sufficient to define SPL_SPI_SUPPORT and SPL_SPI_FLASH_SUPPORT via Kconfig... so we conditionally define SPL_SPI_LOAD if SPI support is already enabled for SPL via Kconfig.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
---
Changes in v2: None
include/configs/rk3399_common.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index db3125e..629318f 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -20,6 +20,9 @@ #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#if defined(CONFIG_SPL_SPI_SUPPORT) +#define CONFIG_SPL_SPI_LOAD +#endif
#define COUNTER_FREQUENCY 24000000
On 29 March 2017 at 05:31, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
To include the ability to load from an SPI flash in SPL, it's not sufficient to define SPL_SPI_SUPPORT and SPL_SPI_FLASH_SUPPORT via Kconfig... so we conditionally define SPL_SPI_LOAD if SPI support is already enabled for SPL via Kconfig.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Changes in v2: None
include/configs/rk3399_common.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index db3125e..629318f 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -20,6 +20,9 @@ #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#if defined(CONFIG_SPL_SPI_SUPPORT) +#define CONFIG_SPL_SPI_LOAD +#endif
#define COUNTER_FREQUENCY 24000000
This has all moved to Kconfig now - can you tidy this up and do this there?
Regards, Simon
participants (2)
-
Philipp Tomsich -
Simon Glass