[U-Boot] [PATCH 0/7] x86: coral: Add support for Cr50
This series adds a driver for the Cr50 security chip and enables it on coral. This supports the 'tpm' command.
This series is built on the pending 'apollolake' series.
Simon Glass (7): coral: Update i2c and rtc status tpm: Add more TPM2 definitions tpm: Add a driver for H1/Cr50 pci: i2c: designware: Add compatible string coral: Add I2C and TPM device-tree definitions i2c: designware: Drop invalid debugging x86: coral: Enable TPM
arch/x86/dts/chromebook_coral.dts | 25 ++ configs/chromebook_coral_defconfig | 5 +- doc/board/google/chromebook_coral.rst | 2 - drivers/i2c/designware_i2c.c | 1 - drivers/i2c/dw_i2c_pci.c | 6 + drivers/tpm/Kconfig | 10 + drivers/tpm/Makefile | 1 + drivers/tpm/cr50_i2c.c | 568 ++++++++++++++++++++++++++ include/tpm-v2.h | 31 ++ 9 files changed, 643 insertions(+), 6 deletions(-) create mode 100644 drivers/tpm/cr50_i2c.c
These are actually working correctly, so update the status.
Signed-off-by: Simon Glass sjg@chromium.org ---
doc/board/google/chromebook_coral.rst | 2 -- 1 file changed, 2 deletions(-)
diff --git a/doc/board/google/chromebook_coral.rst b/doc/board/google/chromebook_coral.rst index c583ac2b27..b010cc1ded 100644 --- a/doc/board/google/chromebook_coral.rst +++ b/doc/board/google/chromebook_coral.rst @@ -208,9 +208,7 @@ To do - left-side USB - USB-C - Cr50 (security chip: a basic driver is running but not included here) - - I2C (driver exists but not enabled in device tree) - Sound (Intel I2S support exists, but need da7219 driver) - - RTC (driver exists but not enabled in device tree) - Various minor features supported by LPC, etc. - Booting Chrome OS, e.g. with verified boot - Integrate with Chrome OS vboot
Add definitions for access and status.
Need to drop the mixed case.
Signed-off-by: Simon Glass sjg@chromium.org ---
include/tpm-v2.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)
diff --git a/include/tpm-v2.h b/include/tpm-v2.h index ae00803f6d..d53d2e4023 100644 --- a/include/tpm-v2.h +++ b/include/tpm-v2.h @@ -161,6 +161,37 @@ enum tpm_index_attrs { TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE, };
+enum { + TPM_ACCESS_VALID = 1 << 7, + TPM_ACCESS_ACTIVE_LOCALITY = 1 << 5, + TPM_ACCESS_REQUEST_PENDING = 1 << 2, + TPM_ACCESS_REQUEST_USE = 1 << 1, + TPM_ACCESS_ESTABLISHMENT = 1 << 0, +}; + +enum { + TPM_STS_FAMILY_SHIFT = 26, + TPM_STS_FAMILY_MASK = 0x3 << TPM_STS_FAMILY_SHIFT, + TPM_STS_FAMILY_TPM2 = 1 << TPM_STS_FAMILY_SHIFT, + TPM_STS_RESE_TESTABLISMENT_BIT = 1 << 25, + TPM_STS_COMMAND_CANCEL = 1 << 24, + TPM_STS_BURST_COUNT_SHIFT = 8, + TPM_STS_BURST_COUNT_MASK = 0xffff << TPM_STS_BURST_COUNT_SHIFT, + TPM_STS_VALID = 1 << 7, + TPM_STS_COMMAND_READY = 1 << 6, + TPM_STS_GO = 1 << 5, + TPM_STS_DATA_AVAIL = 1 << 4, + TPM_STS_DATA_EXPECT = 1 << 3, + TPM_STS_SELF_TEST_DONE = 1 << 2, + TPM_STS_RESPONSE_RETRY = 1 << 1, +}; + +enum { + TPM_CMD_COUNT_OFFSET = 2, + TPM_CMD_ORDINAL_OFFSET = 6, + TPM_MAX_BUF_SIZE = 1260, +}; + /** * Issue a TPM2_Startup command. *
H1 is a Google security chip present in recent Chromebooks, Pixel phones and other devices. Cr50 is the name of the software that runs on H1 in Chromebooks.
This chip is used to handle TPM-like functionality and also has quite a few additional features.
Add a driver for this.
Signed-off-by: Simon Glass sjg@chromium.org ---
drivers/tpm/Kconfig | 10 + drivers/tpm/Makefile | 1 + drivers/tpm/cr50_i2c.c | 568 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 579 insertions(+) create mode 100644 drivers/tpm/cr50_i2c.c
diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig index 94629dffd2..00d7dc8e48 100644 --- a/drivers/tpm/Kconfig +++ b/drivers/tpm/Kconfig @@ -127,6 +127,16 @@ config TPM_V2
if TPM_V2
+config TPM2_CR50_I2C + bool "Enable support for Google cr50 TPM" + depends on DM_I2C + help + Cr50 is an implementation of a TPM on Google's H1 security chip. + This uses the same open-source firmware as the Chromium OS EC. + While Cr50 has other features, its primary role is as the root of + trust for a devuce, It operates like a TPM and can be used with + verified boot. Cr50 is used on recent Chromebooks (since 2017). + config TPM2_TIS_SANDBOX bool "Enable sandbox TPMv2.x driver" depends on TPM_V2 && SANDBOX diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile index 94c337b8ed..4c866b37c5 100644 --- a/drivers/tpm/Makefile +++ b/drivers/tpm/Makefile @@ -10,5 +10,6 @@ obj-$(CONFIG_TPM_TIS_SANDBOX) += tpm_tis_sandbox.o obj-$(CONFIG_TPM_ST33ZP24_I2C) += tpm_tis_st33zp24_i2c.o obj-$(CONFIG_TPM_ST33ZP24_SPI) += tpm_tis_st33zp24_spi.o
+obj-$(CONFIG_TPM2_CR50_I2C) += cr50_i2c.o obj-$(CONFIG_TPM2_TIS_SANDBOX) += tpm2_tis_sandbox.o obj-$(CONFIG_TPM2_TIS_SPI) += tpm2_tis_spi.o diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c new file mode 100644 index 0000000000..5328c102f6 --- /dev/null +++ b/drivers/tpm/cr50_i2c.c @@ -0,0 +1,568 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Cr50 / H1 TPM support + * + * Copyright 2018 Google LLC + */ + +#define LOG_CATEGORY UCLASS_TPM +#define LOG_DEBUG + +#include <common.h> +#include <dm.h> +#include <i2c.h> +#include <tpm-v2.h> +#include <asm/gpio.h> + +enum { + TIMEOUT_LONG_US = 2 * 1000 * 1000, + TIMEOUT_SHORT_US = 2 * 1000, + TIMEOUT_NO_IRQ_US = 20 * 1000, + TIMEOUT_IRQ_US = 100 * 1000, +}; + +enum { + CR50_DID_VID = 0x00281ae0L +}; + +enum { + CR50_MAX_BUF_SIZE = 63, +}; + +struct cr50_priv { + struct gpio_desc ready_gpio; + int locality; + uint vendor; +}; + +/* Wait for interrupt to indicate TPM is ready */ +static int cr50_i2c_wait_tpm_ready(struct udevice *dev) +{ + struct cr50_priv *priv = dev_get_priv(dev); + ulong timeout; + int i; + + if (!dm_gpio_is_valid(&priv->ready_gpio)) { + /* Fixed delay if interrupt not supported */ + udelay(TIMEOUT_NO_IRQ_US); + return 0; + } + + timeout = timer_get_us() + TIMEOUT_IRQ_US; + + i = 0; + while (!dm_gpio_get_value(&priv->ready_gpio)) { + i++; + if (timer_get_us() > timeout) { + printf("Timeout\n"); + /* + * Use this instead of -ETIMEDOUT which is used by i2c + */ + return -ETIME; + } + } + + return 0; +} + +/* Clear pending interrupts */ +static void cr50_i2c_clear_tpm_irq(struct udevice *dev) +{ + /* This is not really an interrupt, just a GPIO, so we can't clear it */ +} + +/* + * cr50_i2c_read() - read from TPM register + * + * @tpm: TPM chip information + * @addr: register address to read from + * @buffer: provided by caller + * @len: number of bytes to read + * + * 1) send register address byte 'addr' to the TPM + * 2) wait for TPM to indicate it is ready + * 3) read 'len' bytes of TPM response into the provided 'buffer' + * + * Return 0 on success. -ve on error + */ +static int cr50_i2c_read(struct udevice *dev, u8 addr, u8 *buffer, + size_t len) +{ + int ret; + + /* Clear interrupt before starting transaction */ + cr50_i2c_clear_tpm_irq(dev); + + /* Send the register address byte to the TPM */ + ret = dm_i2c_write(dev, 0, &addr, 1); + if (ret) { + log_err("Address write failed (err=%d)\n", ret); + return ret; + } + + /* Wait for TPM to be ready with response data */ + ret = cr50_i2c_wait_tpm_ready(dev); + if (ret) + return ret; + + /* Read response data frrom the TPM */ + ret = dm_i2c_read(dev, 0, buffer, len); + if (ret) { + log_err("Read response failed (err=%d)\n", ret); + return ret; + } + + return 0; +} + +/* + * cr50_i2c_write() - write to TPM register + * + * @tpm: TPM chip information + * @addr: register address to write to + * @buffer: data to write + * @len: number of bytes to write + * + * 1) prepend the provided address to the provided data + * 2) send the address+data to the TPM + * 3) wait for TPM to indicate it is done writing + * + * Returns -1 on error, 0 on success. + */ +static int cr50_i2c_write(struct udevice *dev, u8 addr, const u8 *buffer, + size_t len) +{ + u8 buf[len + 1]; + int ret; + + if (len > CR50_MAX_BUF_SIZE) { + log_err("Length %zd is too large\n", len); + return -E2BIG; + } + + /* Prepend the 'register address' to the buffer */ + buf[0] = addr; + memcpy(buf + 1, buffer, len); + + /* Clear interrupt before starting transaction */ + cr50_i2c_clear_tpm_irq(dev); + + /* Send write request buffer with address */ + ret = dm_i2c_write(dev, 0, buf, len + 1); + if (ret) { + log_err("Error writing to TPM (err=%d)\n", ret); + return ret; + } + + /* Wait for TPM to be ready */ + return cr50_i2c_wait_tpm_ready(dev); +} + +#define TPM_HEADER_SIZE 10 + +static inline u8 tpm_access(u8 locality) +{ + return 0x0 | (locality << 4); +} + +static inline u8 tpm_sts(u8 locality) +{ + return 0x1 | (locality << 4); +} + +static inline u8 tpm_data_fifo(u8 locality) +{ + return 0x5 | (locality << 4); +} + +static inline u8 tpm_did_vid(u8 locality) +{ + return 0x6 | (locality << 4); +} + +static int check_locality(struct udevice *dev, int loc) +{ + u8 mask = TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY; + int ret; + u8 buf; + + ret = cr50_i2c_read(dev, tpm_access(loc), &buf, 1); + if (ret) + return ret; + + if ((buf & mask) == mask) + return loc; + + return -EPERM; +} + +static int release_locality(struct udevice *dev, int force) +{ + struct cr50_priv *priv = dev_get_priv(dev); + u8 mask = TPM_ACCESS_VALID | TPM_ACCESS_REQUEST_PENDING; + u8 addr = tpm_access(priv->locality); + int ret; + u8 buf; + + ret = cr50_i2c_read(dev, addr, &buf, 1); + if (ret) + return ret; + + if (force || (buf & mask) == mask) { + buf = TPM_ACCESS_ACTIVE_LOCALITY; + cr50_i2c_write(dev, addr, &buf, 1); + } + + priv->locality = 0; + + return 0; +} + +static int request_locality(struct udevice *dev, int loc) +{ + struct cr50_priv *priv = dev_get_priv(dev); + u8 buf = TPM_ACCESS_REQUEST_USE; + ulong timeout; + int ret; + + ret = check_locality(dev, loc); + if (ret < 0) + return ret; + else if (ret == loc) + return loc; + + ret = cr50_i2c_write(dev, tpm_access(loc), &buf, 1); + if (ret) + return ret; + + timeout = timer_get_us() + TIMEOUT_LONG_US; + while (timer_get_us() < timeout) { + ret = check_locality(dev, loc); + if (ret < 0) + return ret; + if (ret == loc) { + priv->locality = loc; + log_debug("Set locality to %x\n", loc); + return loc; + } + udelay(TIMEOUT_SHORT_US); + } + printf("Request locality failed\n"); + + return -ETIMEDOUT; +} + +/* cr50 requires all 4 bytes of status register to be read */ +static int cr50_i2c_status(struct udevice *dev) +{ + struct cr50_priv *priv = dev_get_priv(dev); + u8 buf[4]; + int ret; + + ret = cr50_i2c_read(dev, tpm_sts(priv->locality), buf, sizeof(buf)); + if (ret) + return ret; + + return buf[0]; +} + +/* cr50 requires all 4 bytes of status register to be written */ +static int cr50_i2c_ready(struct udevice *dev) +{ + struct cr50_priv *priv = dev_get_priv(dev); + u8 buf[4] = { TPM_STS_COMMAND_READY }; + int ret; + + ret = cr50_i2c_write(dev, tpm_sts(priv->locality), buf, sizeof(buf)); + if (ret) + return ret; + + udelay(TIMEOUT_SHORT_US); + + return 0; +} + +static int cr50_i2c_wait_burststs(struct udevice *dev, u8 mask, + size_t *burst, int *status) +{ + struct cr50_priv *priv = dev_get_priv(dev); + ulong timeout; + u32 buf; + + timeout = timer_get_us() + TIMEOUT_LONG_US; + while (timer_get_us() < timeout) { + if (cr50_i2c_read(dev, tpm_sts(priv->locality), + (u8 *)&buf, sizeof(buf)) < 0) { + udelay(TIMEOUT_SHORT_US); + continue; + } + + *status = buf & 0xff; + *burst = le16_to_cpu((buf >> 8) & 0xffff); + + if ((*status & mask) == mask && + *burst > 0 && *burst <= CR50_MAX_BUF_SIZE) + return 0; + + udelay(TIMEOUT_SHORT_US); + } + + printf("Timeout reading burst and status\n"); + + return -ETIMEDOUT; +} + +static int cr50_i2c_recv(struct udevice *dev, u8 *buf, size_t buf_len) +{ + struct cr50_priv *priv = dev_get_priv(dev); + size_t burstcnt, expected, current, len; + u8 addr = tpm_data_fifo(priv->locality); + u8 mask = TPM_STS_VALID | TPM_STS_DATA_AVAIL; + u32 expected_buf; + int status; + int ret; + + if (buf_len < TPM_HEADER_SIZE) + return -E2BIG; + + if (cr50_i2c_wait_burststs(dev, mask, &burstcnt, &status) < 0) { + printf("First chunk not available\n"); + goto out_err; + } + + /* Read first chunk of burstcnt bytes */ + if (cr50_i2c_read(dev, addr, buf, burstcnt) < 0) { + printf("Read failed\n"); + goto out_err; + } + + /* Determine expected data in the return buffer */ + memcpy(&expected_buf, buf + TPM_CMD_COUNT_OFFSET, sizeof(expected_buf)); + expected = be32_to_cpu(expected_buf); + if (expected > buf_len) { + printf("Too much data: %zu > %zu\n", + expected, buf_len); + goto out_err; + } + + /* Now read the rest of the data */ + current = burstcnt; + while (current < expected) { + /* Read updated burst count and check status */ + if (cr50_i2c_wait_burststs(dev, mask, &burstcnt, &status) < 0) + goto out_err; + + len = min(burstcnt, expected - current); + if (cr50_i2c_read(dev, addr, buf + current, len) != 0) { + printf("Read failed\n"); + goto out_err; + } + + current += len; + } + + if (cr50_i2c_wait_burststs(dev, TPM_STS_VALID, &burstcnt, &status) < 0) + goto out_err; + if (status & TPM_STS_DATA_AVAIL) { + printf("Data still available\n"); + goto out_err; + } + + return current; + +out_err: + /* Abort current transaction if still pending */ + ret = cr50_i2c_status(dev); + if (ret) + return ret; + if (ret & TPM_STS_COMMAND_READY) { + ret = cr50_i2c_ready(dev); + if (ret) + return ret; + } + + return -EIO; +} + +static int cr50_i2c_send(struct udevice *dev, const u8 *buf, size_t len) +{ + struct cr50_priv *priv = dev_get_priv(dev); + + int status; + size_t burstcnt, limit, sent = 0; + u8 tpm_go[4] = { TPM_STS_GO }; + ulong timeout; + int ret; + + timeout = timer_get_us() + TIMEOUT_LONG_US; + do { + ret = cr50_i2c_status(dev); + if (ret) + goto out_err; + if (!(ret & TPM_STS_COMMAND_READY)) + break; + + if (timer_get_us() > timeout) + goto out_err; + + ret = cr50_i2c_ready(dev); + if (ret) + goto out_err; + } while (1); + + while (len > 0) { + u8 mask = TPM_STS_VALID; + + /* Wait for data if this is not the first chunk */ + if (sent > 0) + mask |= TPM_STS_DATA_EXPECT; + + if (cr50_i2c_wait_burststs(dev, mask, &burstcnt, &status) < 0) + goto out_err; + + /* + * Use burstcnt - 1 to account for the address byte + * that is inserted by cr50_i2c_write() + */ + limit = min(burstcnt - 1, len); + if (cr50_i2c_write(dev, tpm_data_fifo(priv->locality), + &buf[sent], limit) != 0) { + printf("Write failed\n"); + goto out_err; + } + + sent += limit; + len -= limit; + } + + /* Ensure TPM is not expecting more data */ + if (cr50_i2c_wait_burststs(dev, TPM_STS_VALID, &burstcnt, &status) < 0) + goto out_err; + if (status & TPM_STS_DATA_EXPECT) { + printf("Data still expected\n"); + goto out_err; + } + + /* Start the TPM command */ + ret = cr50_i2c_write(dev, tpm_sts(priv->locality), tpm_go, + sizeof(tpm_go)); + if (ret) { + printf("Start command failed\n"); + goto out_err; + } + return sent; + +out_err: + /* Abort current transaction if still pending */ + ret = cr50_i2c_status(dev); + if (ret) + return ret; + + if (ret & TPM_STS_COMMAND_READY) { + ret = cr50_i2c_ready(dev); + if (ret) + return ret; + } + + return -EIO; +} + +static int cr50_i2c_get_desc(struct udevice *dev, char *buf, int size) +{ + struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); + struct cr50_priv *priv = dev_get_priv(dev); + + return snprintf(buf, size, "cr50 TPM 2.0 (i2c %02x id %x)", + chip->chip_addr, priv->vendor >> 16); +} + +static int cr50_i2c_open(struct udevice *dev) +{ + struct cr50_priv *priv = dev_get_priv(dev); + char buf[80]; + u32 vendor; + int ret; + + ret = request_locality(dev, 0); + if (ret) + return ret; + + /* Read four bytes from DID_VID register */ + ret = cr50_i2c_read(dev, tpm_did_vid(0), (u8 *)&vendor, 4); + if (ret) { + release_locality(dev, 1); + return ret; + } + + if (vendor != CR50_DID_VID) { + printf("Vendor ID 0x%08x not recognized.\n", vendor); + release_locality(dev, 1); + return -EXDEV; + } + + priv->vendor = vendor; + cr50_i2c_get_desc(dev, buf, sizeof(buf)); + log_debug("%s\n", buf); + + return 0; +} + +static int cr50_i2c_cleanup(struct udevice *dev) +{ + release_locality(dev, 1); + + return 0; +} + +enum { + TPM_TIMEOUT_MS = 5, + SHORT_TIMEOUT_MS = 750, + LONG_TIMEOUT_MS = 2000, +}; + +static int cr50_i2c_probe(struct udevice *dev) +{ + struct tpm_chip_priv *upriv = dev_get_uclass_priv(dev); + struct cr50_priv *priv = dev_get_priv(dev); + int ret; + + upriv->version = TPM_V2; + upriv->duration_ms[TPM_SHORT] = SHORT_TIMEOUT_MS; + upriv->duration_ms[TPM_MEDIUM] = LONG_TIMEOUT_MS; + upriv->duration_ms[TPM_LONG] = LONG_TIMEOUT_MS; + upriv->retry_time_ms = TPM_TIMEOUT_MS; + + upriv->pcr_count = 32; + upriv->pcr_select_min = 2; + + /* Optional GPIO to track when cr50 is ready */ + ret = gpio_request_by_name(dev, "ready-gpio", 0, &priv->ready_gpio, + GPIOD_IS_IN); + if (ret) + debug("Warning: Cr50 does not have a ready-gpio (err=%d)\n", + ret); + + return 0; +} + +static const struct tpm_ops cr50_i2c_ops = { + .open = cr50_i2c_open, + .get_desc = cr50_i2c_get_desc, + .send = cr50_i2c_send, + .recv = cr50_i2c_recv, + .cleanup = cr50_i2c_cleanup, +}; + +static const struct udevice_id cr50_i2c_ids[] = { + { .compatible = "google,cr50" }, + { } +}; + +U_BOOT_DRIVER(cr50_i2c) = { + .name = "cr50_i2c", + .id = UCLASS_TPM, + .of_match = cr50_i2c_ids, + .ops = &cr50_i2c_ops, + .probe = cr50_i2c_probe, + .priv_auto_alloc_size = sizeof(struct cr50_priv), +};
On Sat, Nov 2, 2019 at 4:01 PM Simon Glass sjg@chromium.org wrote:
H1 is a Google security chip present in recent Chromebooks, Pixel phones and other devices. Cr50 is the name of the software that runs on H1 in Chromebooks.
This chip is used to handle TPM-like functionality and also has quite a few additional features.
Add a driver for this.
+/* Wait for interrupt to indicate TPM is ready */ +static int cr50_i2c_wait_tpm_ready(struct udevice *dev) +{
struct cr50_priv *priv = dev_get_priv(dev);ulong timeout;int i;if (!dm_gpio_is_valid(&priv->ready_gpio)) {/* Fixed delay if interrupt not supported */udelay(TIMEOUT_NO_IRQ_US);return 0;}timeout = timer_get_us() + TIMEOUT_IRQ_US;i = 0;while (!dm_gpio_get_value(&priv->ready_gpio)) {i++;if (timer_get_us() > timeout) {printf("Timeout\n");/** Use this instead of -ETIMEDOUT which is used by i2c*/return -ETIME;}}return 0;+}
Timeout loops look more naturally if they are done as do {} while. See:
i = 0; do { if (dm_gpio_get_value(&priv->ready_gpio)) return 0;
i++; /* What is this for? */ } while (timeout >= timer_get_us());
printf("Timeout\n"); /* * Use this instead of -ETIMEDOUT which is used by i2c */ return -ETIME; }
+static int cr50_i2c_write(struct udevice *dev, u8 addr, const u8 *buffer,
size_t len)+{
u8 buf[len + 1];
VLA?!
int ret;if (len > CR50_MAX_BUF_SIZE) {log_err("Length %zd is too large\n", len);return -E2BIG;}
+}
+static int request_locality(struct udevice *dev, int loc) +{
struct cr50_priv *priv = dev_get_priv(dev);u8 buf = TPM_ACCESS_REQUEST_USE;ulong timeout;int ret;ret = check_locality(dev, loc);if (ret < 0)return ret;
else if (ret == loc)
Here 'else' is redundant.
return loc;
timeout = timer_get_us() + TIMEOUT_LONG_US;while (timer_get_us() < timeout) {
Same comment for timeout loops (btw, there is a chance in a while {} loop that it won't do even first iteretation).
ret = check_locality(dev, loc);if (ret < 0)return ret;if (ret == loc) {priv->locality = loc;log_debug("Set locality to %x\n", loc);return loc;}udelay(TIMEOUT_SHORT_US);}printf("Request locality failed\n");return -ETIMEDOUT;+}
timeout = timer_get_us() + TIMEOUT_LONG_US;while (timer_get_us() < timeout) {
Ditto for all timeout loop related comments.
if (cr50_i2c_read(dev, tpm_sts(priv->locality),(u8 *)&buf, sizeof(buf)) < 0) {udelay(TIMEOUT_SHORT_US);continue;}
timeout = timer_get_us() + TIMEOUT_LONG_US;do {ret = cr50_i2c_status(dev);if (ret)goto out_err;if (!(ret & TPM_STS_COMMAND_READY))break;if (timer_get_us() > timeout)goto out_err;ret = cr50_i2c_ready(dev);if (ret)goto out_err;
} while (1);
Better to have non-infinite loops (i.o.w. loops with understandable exit conditional).
Add a compatible string for this driver so that it can have children.
Signed-off-by: Simon Glass sjg@chromium.org ---
drivers/i2c/dw_i2c_pci.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/i2c/dw_i2c_pci.c b/drivers/i2c/dw_i2c_pci.c index 34cdc7bf59..193ad5225f 100644 --- a/drivers/i2c/dw_i2c_pci.c +++ b/drivers/i2c/dw_i2c_pci.c @@ -64,9 +64,15 @@ static int designware_i2c_pci_bind(struct udevice *dev) return 0; }
+static const struct udevice_id designware_i2c_pci_ids[] = { + { .compatible = "snps,designware-i2c-pci" }, + { } +}; + U_BOOT_DRIVER(i2c_designware_pci) = { .name = "i2c_designware_pci", .id = UCLASS_I2C, + .of_match = designware_i2c_pci_ids, .bind = designware_i2c_pci_bind, .probe = designware_i2c_pci_probe, .priv_auto_alloc_size = sizeof(struct dw_i2c),
Hello Simon,
Am 02.11.2019 um 14:59 schrieb Simon Glass:
Add a compatible string for this driver so that it can have children.
Signed-off-by: Simon Glass sjg@chromium.org
drivers/i2c/dw_i2c_pci.c | 6 ++++++ 1 file changed, 6 insertions(+)
Reviewed-by: Heiko Schocher hs@denx.de
bye, Heiko
Add a node to the device tree for Cr50. We want this to be on i2c port 2 so add 0 and 1 as well to make this work.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/x86/dts/chromebook_coral.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 79b3e60db4..1e6e0e182f 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -28,6 +28,9 @@ cros-ec0 = &cros_ec; fsp = &fsp_s; spi0 = &spi; + i2c0 = &i2c_0; + i2c1 = &i2c_1; + i2c2 = &i2c_2; };
config { @@ -213,6 +216,28 @@ }; };
+ i2c_0: i2c2@16,0 { + compatible = "snps,designware-i2c-pci"; + reg = <0x0200b010 0 0 0 0>; + }; + + i2c_1: i2c2@16,1 { + compatible = "snps,designware-i2c-pci"; + reg = <0x0200b110 0 0 0 0>; + }; + + i2c_2: i2c2@16,2 { + compatible = "snps,designware-i2c-pci"; + reg = <0x0200b210 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + tpm@50 { + reg = <0x50>; + compatible = "google,cr50"; + u-boot,i2c-offset-len = <0>; + }; + }; + serial: serial@18,2 { reg = <0x0200c210 0 0 0 0>; u-boot,dm-pre-reloc;
This printf() should not be there.
Signed-off-by: Simon Glass sjg@chromium.org ---
drivers/i2c/designware_i2c.c | 1 - 1 file changed, 1 deletion(-)
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 54e4a70c74..b12ad02a43 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -540,7 +540,6 @@ static int designware_i2c_ofdata_to_platdata(struct udevice *bus) { struct dw_i2c *priv = dev_get_priv(bus);
- printf("bad\n"); priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
return 0;
Hello Simon,
Am 02.11.2019 um 14:59 schrieb Simon Glass:
This printf() should not be there.
Signed-off-by: Simon Glass sjg@chromium.org
drivers/i2c/designware_i2c.c | 1 - 1 file changed, 1 deletion(-)
Thanks!
Reviewed-by: Heiko Schocher hs@denx.de
bye, Heiko
Enable TPM2 so that we can use cr50.
Signed-off-by: Simon Glass sjg@chromium.org ---
configs/chromebook_coral_defconfig | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig index 6b586ef3c7..43fb94458b 100644 --- a/configs/chromebook_coral_defconfig +++ b/configs/chromebook_coral_defconfig @@ -53,7 +53,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_SOUND=y CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_TPM=y -CONFIG_CMD_TPM_TEST=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -76,7 +75,6 @@ CONFIG_SYS_I2C_DW=y CONFIG_TPL_MISC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y -CONFIG_SPI_FLASH_INTEL_FAST=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_X86_PCH7 is not set # CONFIG_X86_PCH9 is not set @@ -89,7 +87,8 @@ CONFIG_SPI=y CONFIG_ICH_SPI=y CONFIG_TPL_SYSRESET=y CONFIG_X86_TSC_ZERO_BASE=y -CONFIG_TPM_TIS_LPC=y +# CONFIG_TPM_V1 is not set +CONFIG_TPM2_CR50_I2C=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y
participants (3)
-
Andy Shevchenko -
Heiko Schocher -
Simon Glass