[U-Boot] [PATCH v3 3/7] [REPOST-2] gpio: Add Multi-Function-Pin configuration driver for Marvell SoCs
Most of the Marvell SoCs has Multi Function Pin (MFP) configuration registers For ex. ARMADA100.
These registers are programmed to expose the specific functionality associated with respective SoC Pins
This driver provides configuration APIs, using them, configuration need to be done in board specific code
for ex- following code configures MFPs 107 and 108 for UART_TX/RX functionality
int board_early_init_f(void) { u32 mfp_cfg[] = { /* Console on UART1 */ MFP107_UART1_RXD, MFP108_UART1_TXD, MFP_EOC /*End of configureation*/ }; /* configure MFP's */ mfp_config(mfp_cfg); return 0; }
Signed-off-by: Prafulla Wadaskar prafulla@marvell.com --- Please Ignore earlier patch, below bufix is added to this patch
Change log v3: Fixed: Read-modify-Write a mfg register as per configuration ANDed with MASK value before ORing for each configuration
REPOST-V1: I am sorry for the repost-V1 :-( MASK values changed to relevent (copy paste mistake)
Change log v3-repost-2 Soc specific pointer updation code is replaced by a macro MFPR_PTR_UPDATE, will be put in asm/arch/mfp.c
Regards.. Prafulla . .
drivers/gpio/Makefile | 1 + drivers/gpio/mfp.c | 103 +++++++++++++++++++++++++++++++++++++++++++++++++ include/mfp.h | 97 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 201 insertions(+), 0 deletions(-) create mode 100644 drivers/gpio/mfp.c create mode 100644 include/mfp.h
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 398024c..f6903d5 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libgpio.o
COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o +COBJS-$(CONFIG_MFP) += mfp.o COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o COBJS-$(CONFIG_PCA953X) += pca953x.o COBJS-$(CONFIG_S5P) += s5p_gpio.o diff --git a/drivers/gpio/mfp.c b/drivers/gpio/mfp.c new file mode 100644 index 0000000..db71a74 --- /dev/null +++ b/drivers/gpio/mfp.c @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <mfp.h> +#include <asm/arch/mfp.h> +#ifdef CONFIG_ARMADA100 +#include <asm/arch/armada100.h> +#define MFPR_BASE ARMD1_MFPR_BASE; +#else +#error Unsupported SoC... +#endif + +/* + * mfp_config + * + * On most of Marvell SoCs (ex. ARMADA100) there is Multi-Funtion-Pin + * configuration registers to configure each GPIO/Function pin on the + * SoC. + * + * This function reads the array of values for + * MFPR_X registers and programms them into respective + * Multi-Function Pin registers. + * It supports - Alternate Function Selection programming. + * + * Whereas, + * The Configureation value is constructed using ARMD_MFP() + * array consists of 32bit values as- + * Bits 31-16 : Mfp instance number (i.e. MFPR no. to be programmed) + * Bits 15-13 : PULL_UP/PULL_DOWN selection + * Bits 11:10 : Pin Driver strength + * Bits 6-4 : Edge detection configuration + * Bits 2-0 : Alternate Function Selection + * + * For more details please refer respective Product Software Manual + */ +void mfp_config(u32 *mfp_cfgs) +{ + u32 *p_mfpr = NULL; + u32 val, cfg_val, mfpr_no; + + do { + cfg_val = *mfp_cfgs++; + /* exit if End of configuration table detected */ + if (cfg_val == MFP_EOC) + break; + /* abstract mfpr tobe programmed from configuration value */ + mfpr_no = (cfg_val & MFP_PINNO_MASK) >> 16; + BUG_ON(mfpr_no >= MFP_PIN_MAX); + + p_mfpr = (u32 *)MFPR_BASE; + MFPR_PTR_UPDATE(p_mfpr, mfpr_no); + /*p_mfpr contains address of register to be programmed */ + + /* Read-modify-Write a mfg register as per configuration */ + val = readl(p_mfpr); + if (cfg_val & MFP_CFG_AF) { + /* Abstract and program Afternate-Func Selection */ + val &= ~MFP_AF_MASK; + val |= cfg_val & MFP_AF_MASK; + } if (cfg_val & MFP_CFG_EDGE) { + /* Abstract and program Edge configuration */ + val &= ~MFP_LPM_EDGE_MASK; + val |= cfg_val & MFP_LPM_EDGE_MASK; + } if (cfg_val & MFP_CFG_DRIVE) { + /* Abstract and program Drive configuration */ + val &= ~MFP_DRIVE_MASK; + val |= cfg_val & MFP_DRIVE_MASK; + } if (cfg_val & MFP_CFG_PULL) { + /* Abstract and program Pullup/down configuration */ + val &= ~MFP_PULL_MASK; + val |= cfg_val & MFP_PULL_MASK; + } + writel(val, p_mfpr); + } while (1); + /* + * perform a read-back of any MFPR register to make sure the + * previous writings are finished + */ + readl(p_mfpr); +} diff --git a/include/mfp.h b/include/mfp.h new file mode 100644 index 0000000..176acda --- /dev/null +++ b/include/mfp.h @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __MFP_H +#define __MFP_H + +/* + * Header file for MultiFunctionPin (MFP) Configururation framework + * + * Processors Supported: + * 1. Marvell ARMADA100 Processors + * + * processor to be supported should be added here + */ + +#define MFP_EOC 0xffffffff /* flag to indicate end-of-configuration */ + +/* + * Possible MFP configuration is represented by a 32-bit unsigned integer + * + * bit 0.. 2 - Alternate Function Selection + * bit 4.. 6 - Edge Detection + * bit 7.. 9 - Type of configuration + * bit 10..11 - Drive Strength + * bit 13..15 - Run Mode Pull State + * bit 16..31 - Used to hold MFP number to be configured + * + * to facilitate the definition, the following macros are provided + */ + +#define MFP_AF0 (0x0 << 0) +#define MFP_AF1 (0x1 << 0) +#define MFP_AF2 (0x2 << 0) +#define MFP_AF3 (0x3 << 0) +#define MFP_AF4 (0x4 << 0) +#define MFP_AF5 (0x5 << 0) +#define MFP_AF6 (0x6 << 0) +#define MFP_AF7 (0x7 << 0) +#define MFP_AF_MASK (0x7 << 0) + +#define MFP_LPM_EDGE_NONE (0x0 << 4) +#define MFP_LPM_EDGE_RISE (0x1 << 4) +#define MFP_LPM_EDGE_FALL (0x2 << 4) +#define MFP_LPM_EDGE_BOTH (0x3 << 4) +#define MFP_LPM_EDGE_MASK (0x3 << 4) + +/* unused bits are used to identify config type */ +#define MFP_CFG_AF (0x1 << 7) +#define MFP_CFG_DRIVE (0x1 << 8) +#define MFP_CFG_EDGE (0x1 << 9) +#define MFP_CFG_PULL (0x1 << 3) + +#define MFP_DRIVE_VERY_SLOW (0x0 << 10) +#define MFP_DRIVE_SLOW (0x1 << 10) +#define MFP_DRIVE_MEDIUM (0x2 << 10) +#define MFP_DRIVE_FAST (0x3 << 10) +#define MFP_DRIVE_MASK (0x3 << 10) + +#define MFP_PULL_NONE (0x0 << 13) +#define MFP_PULL_LOW (0x1 << 13) +#define MFP_PULL_HIGH (0x2 << 13) +#define MFP_PULL_BOTH (0x3 << 13) +#define MFP_PULL_FLOAT (0x4 << 13) +#define MFP_PULL_MASK (0x7 << 13) + +#define MFP_PINNO_MASK (0xffff << 16) + +#define MFP_AF(af) (MFP_CFG_AF | MFP_AF##af) +#define MFP_DRIVE(drv) (MFP_CFG_DRIVE | MFP_DRIVE_##drv) +#define MFP_EDGE(edge) (MFP_CFG_EDGE | MFP_LPM_EDGE_##edge) +#define MFP_PULL(pull) (MFP_CFG_PULL | MFP_PULL_##pull) +#define MFP(pin) (MFP_PINNO_MASK & (pin << 16)) + +void mfp_config(u32 *mfp_cfgs); + +#endif /* __MFP_H */
Dear Prafulla Wadaskar,
In message 1291302695-15561-1-git-send-email-prafulla@marvell.com you wrote:
Most of the Marvell SoCs has Multi Function Pin (MFP) configuration registers For ex. ARMADA100.
These registers are programmed to expose the specific functionality associated with respective SoC Pins
This driver provides configuration APIs, using them, configuration need to be done in board specific code
for ex- following code configures MFPs 107 and 108 for UART_TX/RX functionality
int board_early_init_f(void) { u32 mfp_cfg[] = { /* Console on UART1 */ MFP107_UART1_RXD, MFP108_UART1_TXD, MFP_EOC /*End of configureation*/ }; /* configure MFP's */ mfp_config(mfp_cfg); return 0; }
This smells as if it needs a ton of #defines in header files, covering all possible pin configurations. Is there not a way to implemtn this less expensively?
For example, check how such configurations are done in PowerPC land - see for example the I/O configuration tables qe_iop_conf_tab[] in board/freescale/mpc8360erdk/mpc8360erdk.c or in board/freescale/mpc8568mds/mpc8568mds.c etc.
Best regards,
Wolfgang Denk
This patch adds the support MFP support for Marvell ARMADA100 SoCs
Signed-off-by: Prafulla Wadaskar prafulla@marvell.com --- Change log v3 REPOST: macro MFPR_PTR_UPDATE added
arch/arm/include/asm/arch-armada100/mfp.h | 231 +++++++++++++++++++++++++++++ 1 files changed, 231 insertions(+), 0 deletions(-) create mode 100755 arch/arm/include/asm/arch-armada100/mfp.h
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h new file mode 100755 index 0000000..f77055c --- /dev/null +++ b/arch/arm/include/asm/arch-armada100/mfp.h @@ -0,0 +1,231 @@ +/* + * Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h + * (C) Copyright 2007 + * Marvell Semiconductor <www.marvell.com> + * 2007-08-21: eric miao eric.miao@marvell.com + * + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * Contributor: Mahavir Jain mjain@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __ARMADA100_MFP_H +#define __ARMADA100_MFP_H + +/* + * On ARMADA100, (Ref: Specs: A1.1) + * the offset address are divided in three regions and are not + * consecutive, this macro updates the same + */ +#define MFPR_PTR_UPDATE(ptr, no) \ + if (no < 37) \ + ptr += (0x004c / 4) + no; \ + else if ( no >= 56) \ + ptr += (0x00e0 / 4) + (no - 56);\ + else \ + ptr += (no - 37); + +/* By default Pin Drive is set to medium */ +#define MFPD(x) MFP(x) | MFP_DRIVE(MEDIUM) + +/* GPIOs */ +#define GPIOAF(x) (if (x <= 15) ? 5 : \ + if (x == 16) ? 0 : \ + if (x == 17) ? 5 : \ + if (x == 18) ? 0 : \ + if (x == 19) ? 5 : \ + if (x == 20) ? 0 : \ + if (x <= 25) ? 5 : \ + if (x == 26) ? 0 : \ + if (x == 33) ? 5 : 0) + +#define MFP_GPIO(x) MFPD(x) | MFP_AF(GPIOAF(x)) + +/* UART2 */ +#define MFP47_UART2_RXD MFPD(47) | MFP_AF(6) +#define MFP48_UART2_TXD MFPD(48) | MFP_AF(6) +#define MFP88_UART2_RXD MFPD(88) | MFP_AF(2) +#define MFP89_UART2_TXD MFPD(89) | MFP_AF(2) + +/* UART3 */ +#define GPIO8_UART3_RXD MFPD(8) | MFP_AF(2) +#define GPIO9_UART3_TXD MFPD(9) | MFP_AF(2) + +/* MFU */ +#define MFP86_TX_CLK MFPD(86) | MFP_AF(5) +#define MFP87_TX_EN MFPD(87) | MFP_AF(5) +#define MFP88_TX_DQ3 MFPD(88) | MFP_AF(5) +#define MFP89_TX_DQ2 MFPD(89) | MFP_AF(5) +#define MFP90_TX_DQ1 MFPD(90) | MFP_AF(5) +#define MFP91_TX_DQ0 MFPD(91) | MFP_AF(5) +#define MFP92_MII_CRS MFPD(92) | MFP_AF(5) +#define MFP93_MII_COL MFPD(93) | MFP_AF(5) +#define MFP94_RX_CLK MFPD(94) | MFP_AF(5) +#define MFP95_RX_ER MFPD(95) | MFP_AF(5) +#define MFP96_RX_DQ3 MFPD(96) | MFP_AF(5) +#define MFP97_RX_DQ2 MFPD(97) | MFP_AF(5) +#define MFP98_RX_DQ1 MFPD(98) | MFP_AF(5) +#define MFP99_RX_DQ0 MFPD(99) | MFP_AF(5) +#define MFP100_MII_MDC MFPD(100) | MFP_AF(5) +#define MFP101_MII_MDIO MFPD(101) | MFP_AF(5) +#define MFP103_RX_DV MFPD(103) | MFP_AF(5) + +/* SSP2*/ +#define MFP107_SPI_NOR_RXD MFPD(107) | MFP_AF(4) +#define MFP108_SPI_NOR_TXD MFPD(108) | MFP_AF(4) +#define MFP109_SPI_NOR_SYSCLK MFPD(109) | MFP_AF(4) +#define MFP111_SPI_NOR_CLK MFPD(111) | MFP_AF(4) + +/* DFI */ +#define MFP0_DFI_D15 MFPD(0) | MFP_AF(0) +#define MFP1_DFI_D14 MFPD(1) | MFP_AF(0) +#define MFP2_DFI_D13 MFPD(2) | MFP_AF(0) +#define MFP3_DFI_D12 MFPD(3) | MFP_AF(0) +#define MFP4_DFI_D11 MFPD(4) | MFP_AF(0) +#define MFP5_DFI_D10 MFPD(5) | MFP_AF(0) +#define MFP6_DFI_D9 MFPD(6) | MFP_AF(0) +#define MFP7_DFI_D8 MFPD(7) | MFP_AF(0) +#define MFP8_DFI_D7 MFPD(8) | MFP_AF(0) +#define MFP9_DFI_D6 MFPD(9) | MFP_AF(0) +#define MFP10_DFI_D5 MFPD(10) | MFP_AF(0) +#define MFP11_DFI_D4 MFPD(11) | MFP_AF(0) +#define MFP12_DFI_D3 MFPD(12) | MFP_AF(0) +#define MFP13_DFI_D2 MFPD(13) | MFP_AF(0) +#define MFP14_DFI_D1 MFPD(14) | MFP_AF(0) +#define MFP15_DFI_D0 MFPD(15) | MFP_AF(0) + +#define MFP30_DFI_ADDR0 MFPD(30) | MFP_AF(0) +#define MFP31_DFI_ADDR1 MFPD(31) | MFP_AF(0) +#define MFP32_DFI_ADDR2 MFPD(32) | MFP_AF(0) +#define MFP33_DFI_ADDR3 MFPD(33) | MFP_AF(0) + +/* NAND */ +#define MFP16_ND_nCS0 MFPD(16) | MFP_AF(1) +#define MFP17_ND_nWE MFPD(17) | MFP_AF(0) +#define MFP21_ND_ALE MFPD(21) | MFP_AF(0) +#define MFP22_ND_CLE MFPD(22) | MFP_AF(0) +#define MFP24_ND_nRE MFPD(24) | MFP_AF(0) +#define MFP26_ND_RnB1 MFPD(26) | MFP_AF(1) +#define MFP27_ND_RnB2 MFPD(27) | MFP_AF(1) + +/* Static Memory Controller */ +#define MFP18_SMC_nCS0 MFPD(18) | MFP_AF(3) +#define MFP18_SMC_nCS1 MFPD(18) | MFP_AF(2) +#define MFP16_SMC_nCS0 MFPD(16) | MFP_AF(2) +#define MFP16_SMC_nCS1 MFPD(16) | MFP_AF(3) +#define MFP19_SMC_nCS0 MFPD(19) | MFP_AF(0) +#define MFP20_SMC_nCS1 MFPD(20) | MFP_AF(2) +#define MFP23_SMC_nLUA MFPD(23) | MFP_AF(0) +#define MFP25_SMC_nLLA MFPD(25) | MFP_AF(0) +#define MFP27_SMC_IRQ MFPD(27) | MFP_AF(0) +#define MFP28_SMC_RDY MFPD(28) | MFP_AF(0) +#define MFP29_SMC_SCLK MFPD(29) | MFP_AF(0) +#define MFP34_SMC_nCS1 MFPD(34) | MFP_AF(2) +#define MFP35_SMC_BE1 MFPD(35) | MFP_AF(2) +#define MFP36_SMC_BE2 MFPD(36) | MFP_AF(2) + +/* Compact Flash */ +#define MFP19_CF_nCE1 MFPD(19) | MFP_AF(3) +#define MFP20_CF_nCE2 MFPD(20) | MFP_AF(3) +#define MFP23_CF_nALE MFPD(23) | MFP_AF(3) +#define MFP25_CF_nRESET MFPD(25) | MFP_AF(3) +#define MFP28_CF_RDY MFPD(28) | MFP_AF(3) +#define MFP29_CF_STSCH MFPD(29) | MFP_AF(3) +#define MFP30_CF_nREG MFPD(30) | MFP_AF(3) +#define MFP31_CF_nIOIS16 MFPD(31) | MFP_AF(3) +#define MFP32_CF_nCD1 MFPD(32) | MFP_AF(3) +#define MFP33_CF_nCD2 MFPD(33) | MFP_AF(3) + +/* UART1 */ +#define MFP107_UART1_TXD MFP(107) | MFP_AF(1) | MFP_DRIVE(FAST) +#define MFP107_UART1_RXD MFP(107) | MFP_AF(2) | MFP_DRIVE(FAST) +#define MFP108_UART1_RXD MFP(108) | MFP_AF(1) | MFP_DRIVE(FAST) +#define MFP108_UART1_TXD MFP(108) | MFP_AF(2) | MFP_DRIVE(FAST) +#define MFP109_UART1_CTS MFPD(109) | MFP_AF(1) +#define MFP109_UART1_RTS MFPD(109) | MFP_AF(2) +#define MFP110_UART1_RTS MFPD(110) | MFP_AF(1) +#define MFP110_UART1_CTS MFPD(110) | MFP_AF(2) +#define MFP111_UART1_RI MFPD(111) | MFP_AF(1) +#define MFP111_UART1_DSR MFPD(111) | MFP_AF(2) +#define MFP112_UART1_DTR MFPD(111) | MFP_AF(1) +#define MFP112_UART1_DCD MFPD(112) | MFP_AF(2) + +/* MMC1 */ +#define MFP37_MMC1_DAT7 MFPD(37) | MFP_AF(1) +#define MFP38_MMC1_DAT6 MFPD(38) | MFP_AF(1) +#define MFP54_MMC1_DAT5 MFPD(54) | MFP_AF(1) +#define MFP48_MMC1_DAT4 MFPD(48) | MFP_AF(1) +#define MFP51_MMC1_DAT3 MFPD(51) | MFP_AF(1) +#define MFP52_MMC1_DAT2 MFPD(52) | MFP_AF(1) +#define MFP40_MMC1_DAT1 MFPD(40) | MFP_AF(1) +#define MFP41_MMC1_DAT0 MFPD(41) | MFP_AF(1) +#define MFP49_MMC1_CMD MFPD(49) | MFP_AF(1) +#define MFP43_MMC1_CLK MFPD(43) | MFP_AF(1) +#define MFP53_MMC1_CD MFPD(53) | MFP_AF(1) +#define MFP46_MMC1_WP MFPD(46) | MFP_AF(1) + +/* LCD */ +#define MFP84_LCD_CS MFPD(84) | MFP_AF(1) +#define MFP60_LCD_DD0 MFPD(60) | MFP_AF(1) +#define MFP61_LCD_DD1 MFPD(61) | MFP_AF(1) +#define MFP70_LCD_DD10 MFPD(70) | MFP_AF(1) +#define MFP71_LCD_DD11 MFPD(71) | MFP_AF(1) +#define MFP72_LCD_DD12 MFPD(72) | MFP_AF(1) +#define MFP73_LCD_DD13 MFPD(73) | MFP_AF(1) +#define MFP74_LCD_DD14 MFPD(74) | MFP_AF(1) +#define MFP75_LCD_DD15 MFPD(75) | MFP_AF(1) +#define MFP76_LCD_DD16 MFPD(76) | MFP_AF(1) +#define MFP77_LCD_DD17 MFPD(77) | MFP_AF(1) +#define MFP78_LCD_DD18 MFPD(78) | MFP_AF(1) +#define MFP79_LCD_DD19 MFPD(79) | MFP_AF(1) +#define MFP62_LCD_DD2 MFPD(62) | MFP_AF(1) +#define MFP80_LCD_DD20 MFPD(80) | MFP_AF(1) +#define MFP81_LCD_DD21 MFPD(81) | MFP_AF(1) +#define MFP82_LCD_DD22 MFPD(82) | MFP_AF(1) +#define MFP83_LCD_DD23 MFPD(83) | MFP_AF(1) +#define MFP63_LCD_DD3 MFPD(63) | MFP_AF(1) +#define MFP64_LCD_DD4 MFPD(64) | MFP_AF(1) +#define MFP65_LCD_DD5 MFPD(65) | MFP_AF(1) +#define MFP66_LCD_DD6 MFPD(66) | MFP_AF(1) +#define MFP67_LCD_DD7 MFPD(67) | MFP_AF(1) +#define MFP68_LCD_DD8 MFPD(68) | MFP_AF(1) +#define MFP69_LCD_DD9 MFPD(69) | MFP_AF(1) +#define MFP59_LCD_DENA_BIAS MFPD(59) | MFP_AF(1) +#define MFP56_LCD_FCLK_RD MFPD(56) | MFP_AF(1) +#define MFP57_LCD_LCLK_A0 MFPD(57) | MFP_AF(1) +#define MFP58_LCD_PCLK_WR MFPD(58) | MFP_AF(1) +#define MFP85_LCD_VSYNC MFPD(85) | MFP_AF(1) + +/* I2C */ +#define MFP105_CI2C_SDA MFPD(105) | MFP_AF(1) +#define MFP106_CI2C_SCL MFPD(106) | MFP_AF(1) + +/* I2S */ +#define MFP113_I2S_MCLK MFPD(113), MFP_AF(6) +#define MFP114_I2S_FRM MFPD(114), MFP_AF(1) +#define MFP115_I2S_BCLK MFPD(115), MFP_AF(1) +#define MFP116_I2S_RXD MFPD(116), MFP_AF(2) +#define MFP117_I2S_TXD MFPD(117), MFP_AF(2) + +#define MFP_PIN_MAX 117 + +#endif /* __ARMADA100_MFP_H */
Dear Prafulla Wadaskar,
In message 1291302695-15561-2-git-send-email-prafulla@marvell.com you wrote:
This patch adds the support MFP support for Marvell ARMADA100 SoCs
Signed-off-by: Prafulla Wadaskar prafulla@marvell.com
Change log v3 REPOST: macro MFPR_PTR_UPDATE added
arch/arm/include/asm/arch-armada100/mfp.h | 231 +++++++++++++++++++++++++++++ 1 files changed, 231 insertions(+), 0 deletions(-) create mode 100755 arch/arm/include/asm/arch-armada100/mfp.h
...
+/* GPIOs */ +#define GPIOAF(x) (if (x <= 15) ? 5 : \
if (x == 16) ? 0 : \if (x == 17) ? 5 : \if (x == 18) ? 0 : \if (x == 19) ? 5 : \if (x == 20) ? 0 : \if (x <= 25) ? 5 : \if (x == 26) ? 0 : \if (x == 33) ? 5 : 0)
Does this code actually compile?
Best regards,
Wolfgang Denk
Hi Prafulla,
On Thu, Dec 2, 2010 at 11:11 PM, Prafulla Wadaskar prafulla@marvell.com wrote:
This patch adds the support MFP support for Marvell ARMADA100 SoCs
Signed-off-by: Prafulla Wadaskar prafulla@marvell.com
Change log v3 REPOST: macro MFPR_PTR_UPDATE added
arch/arm/include/asm/arch-armada100/mfp.h | 231 +++++++++++++++++++++++++++++ 1 files changed, 231 insertions(+), 0 deletions(-) create mode 100755 arch/arm/include/asm/arch-armada100/mfp.h
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h new file mode 100755 index 0000000..f77055c --- /dev/null +++ b/arch/arm/include/asm/arch-armada100/mfp.h @@ -0,0 +1,231 @@ +/*
- Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h
- (C) Copyright 2007
- Marvell Semiconductor <www.marvell.com>
- 2007-08-21: eric miao eric.miao@marvell.com
- (C) Copyright 2010
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- Contributor: Mahavir Jain mjain@marvell.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- MA 02110-1301 USA
- */
+#ifndef __ARMADA100_MFP_H +#define __ARMADA100_MFP_H
+/*
- On ARMADA100, (Ref: Specs: A1.1)
- the offset address are divided in three regions and are not
- consecutive, this macro updates the same
- */
+#define MFPR_PTR_UPDATE(ptr, no) \
- if (no < 37) \
- ptr += (0x004c / 4) + no; \
- else if ( no >= 56) \
- ptr += (0x00e0 / 4) + (no - 56);\
- else \
- ptr += (no - 37);
+/* By default Pin Drive is set to medium */ +#define MFPD(x) MFP(x) | MFP_DRIVE(MEDIUM)
+/* GPIOs */ +#define GPIOAF(x) (if (x <= 15) ? 5 : \
- if (x == 16) ? 0 : \
- if (x == 17) ? 5 : \
- if (x == 18) ? 0 : \
- if (x == 19) ? 5 : \
- if (x == 20) ? 0 : \
- if (x <= 25) ? 5 : \
- if (x == 26) ? 0 : \
- if (x == 33) ? 5 : 0)
+#define MFP_GPIO(x) MFPD(x) | MFP_AF(GPIOAF(x))
Do we really need this? I think the better way to configure GPIO MFP is doing like below. That is create each GPIO name, and define its MFPD and MFP_AF.
+/* UART2 */ +#define MFP47_UART2_RXD MFPD(47) | MFP_AF(6) +#define MFP48_UART2_TXD MFPD(48) | MFP_AF(6) +#define MFP88_UART2_RXD MFPD(88) | MFP_AF(2) +#define MFP89_UART2_TXD MFPD(89) | MFP_AF(2)
+/* UART3 */ +#define GPIO8_UART3_RXD MFPD(8) | MFP_AF(2) +#define GPIO9_UART3_TXD MFPD(9) | MFP_AF(2)
+/* MFU */ +#define MFP86_TX_CLK MFPD(86) | MFP_AF(5) +#define MFP87_TX_EN MFPD(87) | MFP_AF(5) +#define MFP88_TX_DQ3 MFPD(88) | MFP_AF(5) +#define MFP89_TX_DQ2 MFPD(89) | MFP_AF(5) +#define MFP90_TX_DQ1 MFPD(90) | MFP_AF(5) +#define MFP91_TX_DQ0 MFPD(91) | MFP_AF(5) +#define MFP92_MII_CRS MFPD(92) | MFP_AF(5) +#define MFP93_MII_COL MFPD(93) | MFP_AF(5) +#define MFP94_RX_CLK MFPD(94) | MFP_AF(5) +#define MFP95_RX_ER MFPD(95) | MFP_AF(5) +#define MFP96_RX_DQ3 MFPD(96) | MFP_AF(5) +#define MFP97_RX_DQ2 MFPD(97) | MFP_AF(5) +#define MFP98_RX_DQ1 MFPD(98) | MFP_AF(5) +#define MFP99_RX_DQ0 MFPD(99) | MFP_AF(5) +#define MFP100_MII_MDC MFPD(100) | MFP_AF(5) +#define MFP101_MII_MDIO MFPD(101) | MFP_AF(5) +#define MFP103_RX_DV MFPD(103) | MFP_AF(5)
+/* SSP2*/ +#define MFP107_SPI_NOR_RXD MFPD(107) | MFP_AF(4) +#define MFP108_SPI_NOR_TXD MFPD(108) | MFP_AF(4) +#define MFP109_SPI_NOR_SYSCLK MFPD(109) | MFP_AF(4) +#define MFP111_SPI_NOR_CLK MFPD(111) | MFP_AF(4)
+/* DFI */ +#define MFP0_DFI_D15 MFPD(0) | MFP_AF(0) +#define MFP1_DFI_D14 MFPD(1) | MFP_AF(0) +#define MFP2_DFI_D13 MFPD(2) | MFP_AF(0) +#define MFP3_DFI_D12 MFPD(3) | MFP_AF(0) +#define MFP4_DFI_D11 MFPD(4) | MFP_AF(0) +#define MFP5_DFI_D10 MFPD(5) | MFP_AF(0) +#define MFP6_DFI_D9 MFPD(6) | MFP_AF(0) +#define MFP7_DFI_D8 MFPD(7) | MFP_AF(0) +#define MFP8_DFI_D7 MFPD(8) | MFP_AF(0) +#define MFP9_DFI_D6 MFPD(9) | MFP_AF(0) +#define MFP10_DFI_D5 MFPD(10) | MFP_AF(0) +#define MFP11_DFI_D4 MFPD(11) | MFP_AF(0) +#define MFP12_DFI_D3 MFPD(12) | MFP_AF(0) +#define MFP13_DFI_D2 MFPD(13) | MFP_AF(0) +#define MFP14_DFI_D1 MFPD(14) | MFP_AF(0) +#define MFP15_DFI_D0 MFPD(15) | MFP_AF(0)
+#define MFP30_DFI_ADDR0 MFPD(30) | MFP_AF(0) +#define MFP31_DFI_ADDR1 MFPD(31) | MFP_AF(0) +#define MFP32_DFI_ADDR2 MFPD(32) | MFP_AF(0) +#define MFP33_DFI_ADDR3 MFPD(33) | MFP_AF(0)
+/* NAND */ +#define MFP16_ND_nCS0 MFPD(16) | MFP_AF(1) +#define MFP17_ND_nWE MFPD(17) | MFP_AF(0) +#define MFP21_ND_ALE MFPD(21) | MFP_AF(0) +#define MFP22_ND_CLE MFPD(22) | MFP_AF(0) +#define MFP24_ND_nRE MFPD(24) | MFP_AF(0) +#define MFP26_ND_RnB1 MFPD(26) | MFP_AF(1) +#define MFP27_ND_RnB2 MFPD(27) | MFP_AF(1)
+/* Static Memory Controller */ +#define MFP18_SMC_nCS0 MFPD(18) | MFP_AF(3) +#define MFP18_SMC_nCS1 MFPD(18) | MFP_AF(2) +#define MFP16_SMC_nCS0 MFPD(16) | MFP_AF(2) +#define MFP16_SMC_nCS1 MFPD(16) | MFP_AF(3) +#define MFP19_SMC_nCS0 MFPD(19) | MFP_AF(0) +#define MFP20_SMC_nCS1 MFPD(20) | MFP_AF(2) +#define MFP23_SMC_nLUA MFPD(23) | MFP_AF(0) +#define MFP25_SMC_nLLA MFPD(25) | MFP_AF(0) +#define MFP27_SMC_IRQ MFPD(27) | MFP_AF(0) +#define MFP28_SMC_RDY MFPD(28) | MFP_AF(0) +#define MFP29_SMC_SCLK MFPD(29) | MFP_AF(0) +#define MFP34_SMC_nCS1 MFPD(34) | MFP_AF(2) +#define MFP35_SMC_BE1 MFPD(35) | MFP_AF(2) +#define MFP36_SMC_BE2 MFPD(36) | MFP_AF(2)
+/* Compact Flash */ +#define MFP19_CF_nCE1 MFPD(19) | MFP_AF(3) +#define MFP20_CF_nCE2 MFPD(20) | MFP_AF(3) +#define MFP23_CF_nALE MFPD(23) | MFP_AF(3) +#define MFP25_CF_nRESET MFPD(25) | MFP_AF(3) +#define MFP28_CF_RDY MFPD(28) | MFP_AF(3) +#define MFP29_CF_STSCH MFPD(29) | MFP_AF(3) +#define MFP30_CF_nREG MFPD(30) | MFP_AF(3) +#define MFP31_CF_nIOIS16 MFPD(31) | MFP_AF(3) +#define MFP32_CF_nCD1 MFPD(32) | MFP_AF(3) +#define MFP33_CF_nCD2 MFPD(33) | MFP_AF(3)
+/* UART1 */ +#define MFP107_UART1_TXD MFP(107) | MFP_AF(1) | MFP_DRIVE(FAST) +#define MFP107_UART1_RXD MFP(107) | MFP_AF(2) | MFP_DRIVE(FAST) +#define MFP108_UART1_RXD MFP(108) | MFP_AF(1) | MFP_DRIVE(FAST) +#define MFP108_UART1_TXD MFP(108) | MFP_AF(2) | MFP_DRIVE(FAST) +#define MFP109_UART1_CTS MFPD(109) | MFP_AF(1) +#define MFP109_UART1_RTS MFPD(109) | MFP_AF(2) +#define MFP110_UART1_RTS MFPD(110) | MFP_AF(1) +#define MFP110_UART1_CTS MFPD(110) | MFP_AF(2) +#define MFP111_UART1_RI MFPD(111) | MFP_AF(1) +#define MFP111_UART1_DSR MFPD(111) | MFP_AF(2) +#define MFP112_UART1_DTR MFPD(111) | MFP_AF(1) +#define MFP112_UART1_DCD MFPD(112) | MFP_AF(2)
+/* MMC1 */ +#define MFP37_MMC1_DAT7 MFPD(37) | MFP_AF(1) +#define MFP38_MMC1_DAT6 MFPD(38) | MFP_AF(1) +#define MFP54_MMC1_DAT5 MFPD(54) | MFP_AF(1) +#define MFP48_MMC1_DAT4 MFPD(48) | MFP_AF(1) +#define MFP51_MMC1_DAT3 MFPD(51) | MFP_AF(1) +#define MFP52_MMC1_DAT2 MFPD(52) | MFP_AF(1) +#define MFP40_MMC1_DAT1 MFPD(40) | MFP_AF(1) +#define MFP41_MMC1_DAT0 MFPD(41) | MFP_AF(1) +#define MFP49_MMC1_CMD MFPD(49) | MFP_AF(1) +#define MFP43_MMC1_CLK MFPD(43) | MFP_AF(1) +#define MFP53_MMC1_CD MFPD(53) | MFP_AF(1) +#define MFP46_MMC1_WP MFPD(46) | MFP_AF(1)
+/* LCD */ +#define MFP84_LCD_CS MFPD(84) | MFP_AF(1) +#define MFP60_LCD_DD0 MFPD(60) | MFP_AF(1) +#define MFP61_LCD_DD1 MFPD(61) | MFP_AF(1) +#define MFP70_LCD_DD10 MFPD(70) | MFP_AF(1) +#define MFP71_LCD_DD11 MFPD(71) | MFP_AF(1) +#define MFP72_LCD_DD12 MFPD(72) | MFP_AF(1) +#define MFP73_LCD_DD13 MFPD(73) | MFP_AF(1) +#define MFP74_LCD_DD14 MFPD(74) | MFP_AF(1) +#define MFP75_LCD_DD15 MFPD(75) | MFP_AF(1) +#define MFP76_LCD_DD16 MFPD(76) | MFP_AF(1) +#define MFP77_LCD_DD17 MFPD(77) | MFP_AF(1) +#define MFP78_LCD_DD18 MFPD(78) | MFP_AF(1) +#define MFP79_LCD_DD19 MFPD(79) | MFP_AF(1) +#define MFP62_LCD_DD2 MFPD(62) | MFP_AF(1) +#define MFP80_LCD_DD20 MFPD(80) | MFP_AF(1) +#define MFP81_LCD_DD21 MFPD(81) | MFP_AF(1) +#define MFP82_LCD_DD22 MFPD(82) | MFP_AF(1) +#define MFP83_LCD_DD23 MFPD(83) | MFP_AF(1) +#define MFP63_LCD_DD3 MFPD(63) | MFP_AF(1) +#define MFP64_LCD_DD4 MFPD(64) | MFP_AF(1) +#define MFP65_LCD_DD5 MFPD(65) | MFP_AF(1) +#define MFP66_LCD_DD6 MFPD(66) | MFP_AF(1) +#define MFP67_LCD_DD7 MFPD(67) | MFP_AF(1) +#define MFP68_LCD_DD8 MFPD(68) | MFP_AF(1) +#define MFP69_LCD_DD9 MFPD(69) | MFP_AF(1) +#define MFP59_LCD_DENA_BIAS MFPD(59) | MFP_AF(1) +#define MFP56_LCD_FCLK_RD MFPD(56) | MFP_AF(1) +#define MFP57_LCD_LCLK_A0 MFPD(57) | MFP_AF(1) +#define MFP58_LCD_PCLK_WR MFPD(58) | MFP_AF(1) +#define MFP85_LCD_VSYNC MFPD(85) | MFP_AF(1)
+/* I2C */ +#define MFP105_CI2C_SDA MFPD(105) | MFP_AF(1) +#define MFP106_CI2C_SCL MFPD(106) | MFP_AF(1)
+/* I2S */ +#define MFP113_I2S_MCLK MFPD(113), MFP_AF(6) +#define MFP114_I2S_FRM MFPD(114), MFP_AF(1) +#define MFP115_I2S_BCLK MFPD(115), MFP_AF(1) +#define MFP116_I2S_RXD MFPD(116), MFP_AF(2) +#define MFP117_I2S_TXD MFPD(117), MFP_AF(2)
+#define MFP_PIN_MAX 117
+#endif /* __ARMADA100_MFP_H */
1.5.3.4
Best regards, Lei
Dear Lei Wen,
In message AANLkTimZTFsmL0bzbTi+exRZJKg5JH9kXQZUKeVRcNmV@mail.gmail.com you wrote:
Do we really need this? I think the better way to configure GPIO MFP is doing like below. That is create each GPIO name, and define its MFPD and MFP_AF.
+/* UART2 */ +#define MFP47_UART2_RXD MFPD(47) | MFP_AF(6) +#define MFP48_UART2_TXD MFPD(48) | MFP_AF(6) +#define MFP88_UART2_RXD MFPD(88) | MFP_AF(2)
...
No. This is exactly what I do not want to see.
We will end up with zillions of #defines, and only a tiny percentage of them will ever be used.
Please use plain simple tables instead.
Best regards,
Wolfgang Denk
-----Original Message----- From: Wolfgang Denk [mailto:wd@denx.de] Sent: Thursday, December 02, 2010 5:05 PM To: Lei Wen Cc: Prafulla Wadaskar; Eric Miao; Manas Saksena; Lei Wen; Yu Tang; u- boot@lists.denx.de; Ashish Karkare; Kiran Vedere; Prabhanjan Sarnaik Subject: Re: [U-Boot] [PATCH v3 3/7] [REPOST] add Multi Function Pin configuration support for ARMADA100
Dear Lei Wen,
In message AANLkTimZTFsmL0bzbTi+exRZJKg5JH9kXQZUKeVRcNmV@mail.gmail.com you wrote:
Do we really need this? I think the better way to configure GPIO MFP is doing like below. That is create each GPIO name, and define its MFPD and MFP_AF.
There should be no issue defining as MFP_GPIO(16) or MFP16_GPIO, but it saves hundreds of lines in the code.
+/* UART2 */ +#define MFP47_UART2_RXD MFPD(47) | MFP_AF(6) +#define MFP48_UART2_TXD MFPD(48) | MFP_AF(6) +#define MFP88_UART2_RXD MFPD(88) | MFP_AF(2)
...
No. This is exactly what I do not want to see.
We will end up with zillions of #defines, and only a tiny percentage of them will ever be used.
I agree with Wolfgang, On armada168 there are 118 MFPs each can have several programming options, I have defined few of them which will be generally used.
Regards.. Prafulla ..
participants (3)
-
Lei Wen -
Prafulla Wadaskar -
Wolfgang Denk