[U-Boot] [U-boot][PATCH v3 00/14] Add support for sam9x60ek
From: Tudor Ambarus tudor.ambarus@microchip.com
Add support for sam9x60 SOC, sam9x60ek board, dts, NAND and QSPI. Add defconfigs for MMC, NAND and QSPI.
v3: - Enable MII utility commands and phy in qspi & nand defconfigs - Add sam9x60-sdhci and sam9x60-macb compatibility strings - nandflash_defconfig: Fix rootfs partition
v2: add maintainers for qspi & nand defconfigs
Nicolas Ferre (2): net: macb: Add sam9x60-macb compatibility string ARM: dts: at91: sam9x60: Add macb0 Ethernet controller
Sandeep Sheriker Mallikarjun (5): mmc: atmel_sdhci: Add sam9x60-sdhci compatibility string ARM: at91: Add sam9x60 soc ARM: dts: Add dts files for sam9x60ek board: atmel: Add sam9x60ek board configs: Add sam9x60ek_mmc_defconfig
Tudor Ambarus (7): ARM: at91: Rename sama5_sfr.h to at91_sfr.h ARM: at91: Add SFR definitions board: sam9x60ek: Add NAND flash support configs: Add sam9x60ek_nandflash_defconfig configs: sam9x60ek: Add QSPI_BOOT defines ARM: dts: at91: sam9x60ek: Enable qspi node configs: Add sam9x60ek_qspiflash_defconfig
arch/arm/dts/Makefile | 2 + arch/arm/dts/sam9x60.dtsi | 285 +++++++++++++++++++++ arch/arm/dts/sam9x60ek-u-boot.dtsi | 132 ++++++++++ arch/arm/dts/sam9x60ek.dts | 55 ++++ arch/arm/mach-at91/Kconfig | 11 + arch/arm/mach-at91/arm926ejs/Makefile | 1 + arch/arm/mach-at91/arm926ejs/sam9x60_devices.c | 125 +++++++++ arch/arm/mach-at91/armv7/sama5d4_devices.c | 2 +- arch/arm/mach-at91/atmel_sfr.c | 2 +- .../include/mach/{sama5_sfr.h => at91_sfr.h} | 52 +++- arch/arm/mach-at91/include/mach/hardware.h | 2 + arch/arm/mach-at91/include/mach/sam9x60.h | 169 ++++++++++++ board/atmel/sam9x60ek/Kconfig | 12 + board/atmel/sam9x60ek/MAINTAINERS | 9 + board/atmel/sam9x60ek/Makefile | 7 + board/atmel/sam9x60ek/sam9x60ek.c | 120 +++++++++ board/laird/wb50n/wb50n.c | 2 +- configs/sam9x60ek_mmc_defconfig | 52 ++++ configs/sam9x60ek_nandflash_defconfig | 53 ++++ configs/sam9x60ek_qspiflash_defconfig | 75 ++++++ drivers/clk/at91/clk-utmi.c | 2 +- drivers/mmc/atmel_sdhci.c | 1 + drivers/net/macb.c | 1 + include/configs/sam9x60ek.h | 95 +++++++ 24 files changed, 1258 insertions(+), 9 deletions(-) create mode 100644 arch/arm/dts/sam9x60.dtsi create mode 100644 arch/arm/dts/sam9x60ek-u-boot.dtsi create mode 100644 arch/arm/dts/sam9x60ek.dts create mode 100644 arch/arm/mach-at91/arm926ejs/sam9x60_devices.c rename arch/arm/mach-at91/include/mach/{sama5_sfr.h => at91_sfr.h} (53%) create mode 100644 arch/arm/mach-at91/include/mach/sam9x60.h create mode 100644 board/atmel/sam9x60ek/Kconfig create mode 100644 board/atmel/sam9x60ek/MAINTAINERS create mode 100644 board/atmel/sam9x60ek/Makefile create mode 100644 board/atmel/sam9x60ek/sam9x60ek.c create mode 100644 configs/sam9x60ek_mmc_defconfig create mode 100644 configs/sam9x60ek_nandflash_defconfig create mode 100644 configs/sam9x60ek_qspiflash_defconfig create mode 100644 include/configs/sam9x60ek.h
From: Nicolas Ferre nicolas.ferre@microchip.com
Add this new compatibility string for matching sam9x60 product macb.
Signed-off-by: Nicolas Ferre nicolas.ferre@microchip.com --- drivers/net/macb.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c index c99cf663a416..e0f7b2350b20 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -1319,6 +1319,7 @@ static const struct macb_config sifive_config = { static const struct udevice_id macb_eth_ids[] = { { .compatible = "cdns,macb" }, { .compatible = "cdns,at91sam9260-macb" }, + { .compatible = "cdns,sam9x60-macb" }, { .compatible = "atmel,sama5d2-gem" }, { .compatible = "atmel,sama5d3-gem" }, { .compatible = "atmel,sama5d4-gem", .data = (ulong)&sama5d4_config },
From: Sandeep Sheriker Mallikarjun sandeepsheriker.mallikarjun@microchip.com
Add new compatibility string for matching sam9x60 product.
Signed-off-by: Sandeep Sheriker Mallikarjun sandeepsheriker.mallikarjun@microchip.com --- drivers/mmc/atmel_sdhci.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c index d930ed8da0e2..2b797c9bd400 100644 --- a/drivers/mmc/atmel_sdhci.c +++ b/drivers/mmc/atmel_sdhci.c @@ -112,6 +112,7 @@ static int atmel_sdhci_bind(struct udevice *dev)
static const struct udevice_id atmel_sdhci_ids[] = { { .compatible = "atmel,sama5d2-sdhci" }, + { .compatible = "microchip,sam9x60-sdhci" }, { } };
From: Sandeep Sheriker Mallikarjun sandeepsheriker.mallikarjun@microchip.com
Add new Microchip sam9x60 SoC based on an ARM926.
Signed-off-by: Sandeep Sheriker Mallikarjun sandeepsheriker.mallikarjun@microchip.com [tudor.ambarus@microchip.com: fix SFR definition] Signed-off-by: Tudor Ambarus tudor.ambarus@microchip.com --- arch/arm/mach-at91/Kconfig | 4 + arch/arm/mach-at91/arm926ejs/Makefile | 1 + arch/arm/mach-at91/arm926ejs/sam9x60_devices.c | 125 ++++++++++++++++++ arch/arm/mach-at91/include/mach/hardware.h | 2 + arch/arm/mach-at91/include/mach/sam9x60.h | 169 +++++++++++++++++++++++++ 5 files changed, 301 insertions(+) create mode 100644 arch/arm/mach-at91/arm926ejs/sam9x60_devices.c create mode 100644 arch/arm/mach-at91/include/mach/sam9x60.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 14343280793b..3cf13042b7b4 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -43,6 +43,10 @@ config AT91SAM9X5 bool select CPU_ARM926EJS
+config SAM9X60 + bool + select CPU_ARM926EJS + config SAMA5D2 bool select CPU_V7A diff --git a/arch/arm/mach-at91/arm926ejs/Makefile b/arch/arm/mach-at91/arm926ejs/Makefile index 6b0b28957af5..8de6a2f9661e 100644 --- a/arch/arm/mach-at91/arm926ejs/Makefile +++ b/arch/arm/mach-at91/arm926ejs/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o obj-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o obj-$(CONFIG_AT91SAM9N12) += at91sam9n12_devices.o obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o +obj-$(CONFIG_SAM9X60) += sam9x60_devices.o obj-$(CONFIG_AT91_EFLASH) += eflash.o obj-$(CONFIG_AT91_LED) += led.o obj-y += clock.o diff --git a/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c b/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c new file mode 100644 index 000000000000..d463bbc78863 --- /dev/null +++ b/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries + */ + +#include <common.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/io.h> + +unsigned int get_chip_id(void) +{ + /* The 0x40 is the offset of cidr in DBGU */ + return readl(ATMEL_BASE_DBGU + 0x40) & ~ARCH_ID_VERSION_MASK; +} + +unsigned int get_extension_chip_id(void) +{ + /* The 0x44 is the offset of exid in DBGU */ + return readl(ATMEL_BASE_DBGU + 0x44); +} + +unsigned int has_emac1(void) +{ + return cpu_is_sam9x60(); +} + +unsigned int has_emac0(void) +{ + return cpu_is_sam9x60(); +} + +unsigned int has_lcdc(void) +{ + return cpu_is_sam9x60(); +} + +char *get_cpu_name(void) +{ + unsigned int extension_id = get_extension_chip_id(); + + if (cpu_is_sam9x60()) { + switch (extension_id) { + case ARCH_EXID_SAM9X60: + return "SAM9X60"; + default: + return "Unknown CPU type"; + } + } else { + return "Unknown CPU type"; + } +} + +void at91_seriald_hw_init(void) +{ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 1); /* DRXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ + + at91_periph_clk_enable(ATMEL_ID_DBGU); +} + +void at91_mci_hw_init(void) +{ + /* Initialize the SDMMC0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 1); /* CLK */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 1); /* CMD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 1); /* DAT0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 1); /* DAT1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 1); /* DAT2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 1); /* DAT3 */ + + at91_periph_clk_enable(ATMEL_ID_SDMMC0); +} + +#ifdef CONFIG_MACB +void at91_macb_hw_init(void) +{ + if (has_emac0()) { + /* Enable EMAC0 clock */ + at91_periph_clk_enable(ATMEL_ID_EMAC0); + /* EMAC0 pins setup */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */ + } + + if (has_emac1()) { + /* Enable EMAC1 clock */ + at91_periph_clk_enable(ATMEL_ID_EMAC1); + /* EMAC1 pins setup */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */ + } + +#ifndef CONFIG_RMII + /* Only emac0 support MII */ + if (has_emac0()) { + at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */ + } +#endif +} +#endif diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index 3a7752b999f6..88acca854998 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -22,6 +22,8 @@ # include <asm/arch/at91sam9g45.h> #elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5) # include <asm/arch/at91sam9x5.h> +#elif defined(CONFIG_SAM9X60) +# include <asm/arch/sam9x60.h> #elif defined(CONFIG_SAMA5D2) # include <asm/arch/sama5d2.h> #elif defined(CONFIG_SAMA5D3) diff --git a/arch/arm/mach-at91/include/mach/sam9x60.h b/arch/arm/mach-at91/include/mach/sam9x60.h new file mode 100644 index 000000000000..0f00a9ae871e --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sam9x60.h @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Chip-specific header file for the SAM9X60 SoC. + * + * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries + */ + +#ifndef __SAM9X60_H__ +#define __SAM9X60_H__ + +/* + * Peripheral identifiers/interrupts. + */ +#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller */ +#define ATMEL_ID_SYS 1 /* System Controller Interrupt */ +#define ATMEL_ID_PIOA 2 /* Parallel I/O Controller A */ +#define ATMEL_ID_PIOB 3 /* Parallel I/O Controller B */ +#define ATMEL_ID_PIOC 4 /* Parallel I/O Controller C */ +#define ATMEL_ID_FLEXCOM0 5 /* FLEXCOM 0 */ +#define ATMEL_ID_FLEXCOM1 6 /* FLEXCOM 1 */ +#define ATMEL_ID_FLEXCOM2 7 /* FLEXCOM 2 */ +#define ATMEL_ID_FLEXCOM3 8 /* FLEXCOM 3 */ +#define ATMEL_ID_FLEXCOM6 9 /* FLEXCOM 6 */ +#define ATMEL_ID_FLEXCOM7 10 /* FLEXCOM 7 */ +#define ATMEL_ID_FLEXCOM8 11 /* FLEXCOM 8 */ +#define ATMEL_ID_SDMMC0 12 /* SDMMC 0 */ +#define ATMEL_ID_FLEXCOM4 13 /* FLEXCOM 4 */ +#define ATMEL_ID_FLEXCOM5 14 /* FLEXCOM 5 */ +#define ATMEL_ID_FLEXCOM9 15 /* FLEXCOM 9 */ +#define ATMEL_ID_FLEXCOM10 16 /* FLEXCOM 10 */ +#define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ +#define ATMEL_ID_PWM 18 /* Pulse Width Modulation Controller */ +#define ATMEL_ID_ADC 19 /* ADC Controller */ +#define ATMEL_ID_XDMAC0 20 /* XDMA Controller 0 */ +#define ATMEL_ID_MATRIX 21 /* BUS Matrix */ +#define ATMEL_ID_UHPHS 22 /* USB Host High Speed */ +#define ATMEL_ID_UDPHS 23 /* USB Device High Speed */ +#define ATMEL_ID_EMAC0 24 /* Ethernet MAC 0 */ +#define ATMEL_ID_LCDC 25 /* LCD Controller */ +#define ATMEL_ID_SDMMC1 26 /* SDMMC 1 */ +#define ATMEL_ID_EMAC1 27 /* Ethernet MAC `1 */ +#define ATMEL_ID_SSC 28 /* Synchronous Serial Controller */ +#define ATMEL_ID_IRQ 31 /* Advanced Interrupt Controller */ +#define ATMEL_ID_TRNG 38 /* True Random Number Generator */ +#define ATMEL_ID_PIOD 44 /* Parallel I/O Controller D */ +#define ATMEL_ID_DBGU 47 /* Debug unit */ + +/* + * User Peripheral physical base addresses. + */ +#define ATMEL_BASE_FLEXCOM4 0xf0000000 +#define ATMEL_BASE_FLEXCOM5 0xf0004000 +#define ATMEL_BASE_XDMA0 0xf0008000 +#define ATMEL_BASE_SSC 0xf0010000 +#define ATMEL_BASE_QSPI 0xf0014000 +#define ATMEL_BASE_CAN0 0xf8000000 +#define ATMEL_BASE_CAN1 0xf8004000 +#define ATMEL_BASE_TC0 0xf8008000 +#define ATMEL_BASE_TC1 0xf8008040 +#define ATMEL_BASE_TC2 0xf8008080 +#define ATMEL_BASE_TC3 0xf800c000 +#define ATMEL_BASE_TC4 0xf800c040 +#define ATMEL_BASE_TC5 0xf800c080 +#define ATMEL_BASE_FLEXCOM6 0xf8010000 +#define ATMEL_BASE_FLEXCOM7 0xf8014000 +#define ATMEL_BASE_FLEXCOM8 0xf8018000 +#define ATMEL_BASE_FLEXCOM0 0xf801c000 +#define ATMEL_BASE_FLEXCOM1 0xf8020000 +#define ATMEL_BASE_FLEXCOM2 0xf8024000 +#define ATMEL_BASE_FLEXCOM3 0xf8028000 +#define ATMEL_BASE_EMAC0 0xf802c000 +#define ATMEL_BASE_EMAC1 0xf8030000 +#define ATMEL_BASE_PWM 0xf8034000 +#define ATMEL_BASE_LCDC 0xf8038000 +#define ATMEL_BASE_UDPHS 0xf803c000 +#define ATMEL_BASE_FLEXCOM9 0xf8040000 +#define ATMEL_BASE_FLEXCOM10 0xf8044000 +#define ATMEL_BASE_ISI 0xf8048000 +#define ATMEL_BASE_ADC 0xf804c000 +#define ATMEL_BASE_SFR 0xf8050000 +#define ATMEL_BASE_SYS 0xffffc000 + +/* + * System Peripherals + */ +#define ATMEL_BASE_MATRIX 0xffffde00 +#define ATMEL_BASE_PMECC 0xffffe000 +#define ATMEL_BASE_PMERRLOC 0xffffe600 +#define ATMEL_BASE_MPDDRC 0xffffe800 +#define ATMEL_BASE_SMC 0xffffea00 +#define ATMEL_BASE_SDRAMC 0xffffec00 +#define ATMEL_BASE_AIC 0xfffff100 +#define ATMEL_BASE_DBGU 0xfffff200 +#define ATMEL_BASE_PIOA 0xfffff400 +#define ATMEL_BASE_PIOB 0xfffff600 +#define ATMEL_BASE_PIOC 0xfffff800 +#define ATMEL_BASE_PIOD 0xfffffa00 +#define ATMEL_BASE_PMC 0xfffffc00 +#define ATMEL_BASE_RSTC 0xfffffe00 +#define ATMEL_BASE_SHDWC 0xfffffe10 +#define ATMEL_BASE_PIT 0xfffffe40 +#define ATMEL_BASE_GPBR 0xfffffe60 +#define ATMEL_BASE_RTC 0xfffffea8 +#define ATMEL_BASE_WDT 0xffffff80 + +/* + * Internal Memory. + */ +#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */ +#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ +#define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */ +#define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */ +#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */ + +/* + * External memory + */ +#define ATMEL_BASE_CS0 0x10000000 +#define ATMEL_BASE_CS1 0x20000000 +#define ATMEL_BASE_CS2 0x30000000 +#define ATMEL_BASE_CS3 0x40000000 +#define ATMEL_BASE_CS4 0x50000000 +#define ATMEL_BASE_CS5 0x60000000 +#define ATMEL_BASE_SDMMC0 0x80000000 +#define ATMEL_BASE_SDMMC1 0x90000000 + +/* 9x60 series chip id definitions */ +#define ARCH_ID_SAM9X60 0x819b35a0 +#define ARCH_ID_VERSION_MASK 0x1f +#define ARCH_EXID_SAM9X60 0x00000000 + +#define cpu_is_sam9x60() (get_chip_id() == ARCH_ID_SAM9X60) + +/* + * Cpu Name + */ +#define ATMEL_CPU_NAME get_cpu_name() + +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffe4c + +/* + * Other misc defines + */ +#define ATMEL_PIO_PORTS 4 +#define CPU_HAS_PCR +#define CPU_NO_PLLB +#define PLL_ID_PLLA 0 +#define PLL_ID_UPLL 1 + +/* + * PMECC table in ROM + */ +#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000 +#define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000 + +/* + * SAM9X60 specific prototypes + */ +#ifndef __ASSEMBLY__ +unsigned int get_chip_id(void); +unsigned int get_extension_chip_id(void); +unsigned int has_emac1(void); +unsigned int has_emac0(void); +unsigned int has_lcdc(void); +char *get_cpu_name(void); +#endif + +#endif
From: Sandeep Sheriker Mallikarjun sandeepsheriker.mallikarjun@microchip.com
add device tree files for sam9x60ek board with below changes.
- Add initial device nodes (pmc, pinctrl, sdhc, dbgu & pit) - Add the reg property for the pinctrl node. - Add the "u-boot,dm-pre-reloc" property to determine which nodes are used by the board_init_f stage.
Signed-off-by: Sandeep Sheriker Mallikarjun sandeepsheriker.mallikarjun@microchip.com [prasanthi.chellakumar@microchip.com: fix style/whitespace issues] Signed-off-by: Prasanthi Chellakumar prasanthi.chellakumar@microchip.com [nicolas.ferre@microchip.com: - fix gclk, - fix pio/pinctrl controller definition and allow to have more than only PIOA for this SoC, - removing pinctrl address] Signed-off-by: Nicolas Ferre nicolas.ferre@microchip.com [claudiu.beznea@microchip.com: - use SAM9X60's compatible for pinctrl - add drive strength and slew rate options for SDMMC0 pins.] Signed-off-by: Claudiu Beznea claudiu.beznea@microchip.com [tudor.ambarus@microchip.com: - u-boot,dm-pre-reloc property in dedicated file, - fix pit len, starts from 0xFFFFFE40 and it is of len 0x10] Signed-off-by: Tudor Ambarus tudor.ambarus@microchip.com --- arch/arm/dts/Makefile | 2 + arch/arm/dts/sam9x60.dtsi | 225 +++++++++++++++++++++++++++++++++++++ arch/arm/dts/sam9x60ek-u-boot.dtsi | 104 +++++++++++++++++ arch/arm/dts/sam9x60ek.dts | 19 ++++ 4 files changed, 350 insertions(+) create mode 100644 arch/arm/dts/sam9x60.dtsi create mode 100644 arch/arm/dts/sam9x60ek-u-boot.dtsi create mode 100644 arch/arm/dts/sam9x60ek.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 250b9ba505aa..52027786ef50 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -690,6 +690,8 @@ dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \ at91sam9x25ek.dtb \ at91sam9x35ek.dtb
+dtb-$(CONFIG_TARGET_SAM9X60EK) += sam9x60ek.dtb + dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
dtb-$(CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM) += \ diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi new file mode 100644 index 000000000000..e880dc0068df --- /dev/null +++ b/arch/arm/dts/sam9x60.dtsi @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC. + * + * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries + * + * Author: Sandeep Sheriker M sandeepsheriker.mallikarjun@microchip.com + */ + +#include "skeleton.dtsi" +#include <dt-bindings/dma/at91.h> +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/at91.h> + +/{ + model = "Microchip SAM9X60 SoC"; + compatible = "microchip,sam9x60"; + + aliases { + serial0 = &dbgu; + gpio0 = &pioA; + gpio1 = &pioB; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sdhci0: sdhci-host@80000000 { + compatible = "microchip,sam9x60-sdhci"; + reg = <0x80000000 0x300>; + clocks = <&sdhci0_clk>, <&sdhci0_gclk>, <&main>; + clock-names = "hclock", "multclk", "baseclk"; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0>; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&dbgu_clk>; + clock-names = "usart"; + }; + + pinctrl { + #address-cells = <1>; + #size-cells = <1>; + compatible = "microchip,sam9x60-pinctrl", "simple-bus"; + ranges = <0xfffff400 0xfffff400 0x800>; + reg = <0xfffff400 0x200 /* pioA */ + 0xfffff600 0x200 /* pioB */ + 0xfffff800 0x200 /* pioC */ + 0xfffffa00 0x200>; /* pioD */ + + /* shared pinctrl settings */ + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + sdhci0 { + pinctrl_sdhci0: sdhci0 { + atmel,pins = + <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT /* PA17 CK periph A with pullup */ + AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 CMD periph A with pullup */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA15 DAT0 periph A */ + AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 DAT1 periph A with pullup */ + AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 DAT2 periph A with pullup */ + AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 DAT3 periph A with pullup */ + }; + }; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + #gpio-cells = <2>; + gpio-controller; + clocks = <&pioA_clk>; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + #gpio-cells = <2>; + gpio-controller; + clocks = <&pioB_clk>; + }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91sam9x5-pmc"; + reg = <0xfffffc00 0x200>; + #address-cells = <1>; + #size-cells = <0>; + + main: mainck { + compatible = "atmel,at91sam9x5-clk-main"; + #clock-cells = <0>; + }; + + plla: pllack { + compatible = "microchip,sam9x60-clk-pll"; + #clock-cells = <0>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <8000000 24000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <140000000 1200000000 0 0>; + }; + + mck: masterck { + compatible = "atmel,at91sam9x5-clk-master"; + #clock-cells = <0>; + clocks = <&md_slck>, <&main>, <&plla>; + atmel,clk-output-range = <140000000 200000000>; + atmel,clk-divisors = <1 2 4 6>; + }; + + periph: periphck { + compatible = "microchip,sam9x60-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + + pioA_clk: pioA_clk { + #clock-cells = <0>; + reg = <2>; + }; + + pioB_clk: pioB_clk { + #clock-cells = <0>; + reg = <3>; + }; + + sdhci0_clk: sdhci0_clk { + #clock-cells = <0>; + reg = <12>; + }; + + dbgu_clk: dbgu_clk { + #clock-cells = <0>; + reg = <47>; + }; + }; + + generic: gck { + compatible = "microchip,sam9x60-clk-generated"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&md_slck>, <&td_slck>, <&main>, <&mck>, <&plla>; + + sdhci0_gclk: sdhci0_gclk { + #clock-cells = <0>; + reg = <12>; + }; + }; + }; + + pit: timer@fffffe40 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffe40 0x10>; + clocks = <&mck>; + }; + + slowckc: sckc@fffffe50 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfffffe50 0x4>; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + clocks = <&slow_xtal>; + }; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + td_slck: td_slck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc>, <&slow_osc>; + }; + + md_slck: md_slck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc>; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/sam9x60ek-u-boot.dtsi b/arch/arm/dts/sam9x60ek-u-boot.dtsi new file mode 100644 index 000000000000..68e220926e5e --- /dev/null +++ b/arch/arm/dts/sam9x60ek-u-boot.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sam9x60-u-boot.dts - Device Tree file for SAM9X60 SoC. + * + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + */ + +/ { + chosen { + u-boot,dm-pre-reloc; + }; + + ahb { + u-boot,dm-pre-reloc; + + apb { + u-boot,dm-pre-reloc; + + pinctrl { + u-boot,dm-pre-reloc; + }; + }; + }; +}; + +&sdhci0 { + u-boot,dm-pre-reloc; +}; + +&dbgu { + u-boot,dm-pre-reloc; +}; + +&pinctrl_dbgu { + u-boot,dm-pre-reloc; +}; + +&pinctrl_sdhci0 { + u-boot,dm-pre-reloc; +}; + +&pioA { + u-boot,dm-pre-reloc; +}; + +&pmc { + u-boot,dm-pre-reloc; +}; + +&main { + u-boot,dm-pre-reloc; +}; + +&plla { + u-boot,dm-pre-reloc; +}; + +&mck { + u-boot,dm-pre-reloc; +}; + +&periph { + u-boot,dm-pre-reloc; +}; + +&pioA_clk { + u-boot,dm-pre-reloc; +}; + +&sdhci0_clk { + u-boot,dm-pre-reloc; +}; + +&dbgu_clk { + u-boot,dm-pre-reloc; +}; + +&generic { + u-boot,dm-pre-reloc; +}; + +&sdhci0_gclk { + u-boot,dm-pre-reloc; +}; + +&slowckc { + u-boot,dm-pre-reloc; +}; + +&slow_osc { + u-boot,dm-pre-reloc; +}; + +&slow_rc_osc { + u-boot,dm-pre-reloc; +}; + +&td_slck { + u-boot,dm-pre-reloc; +}; + +&md_slck { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts new file mode 100644 index 000000000000..e64566ec8e58 --- /dev/null +++ b/arch/arm/dts/sam9x60ek.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sam9x60ek.dts - Device Tree file for SAM9X60 EK board + * + * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries + * + * Author: Sandeep Sheriker M Sandeepsheriker.mallikarjun@microchip.com + */ +/dts-v1/; +#include "sam9x60.dtsi" + +/ { + model = "Microchip SAM9X60-Ek"; + compatible = "microchip,sam9x60ek", "microchip,sam9x60", "atmel,at91sam9"; + + chosen { + stdout-path = &dbgu; + }; +};
From: Nicolas Ferre nicolas.ferre@microchip.com
Add Ethernet controller to dtsi file and enable it on sam9x60ek platform connected with rmii.
Signed-off-by: Nicolas Ferre nicolas.ferre@microchip.com --- arch/arm/dts/sam9x60.dtsi | 31 +++++++++++++++++++++++++++++++ arch/arm/dts/sam9x60ek.dts | 5 +++++ 2 files changed, 36 insertions(+)
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi index e880dc0068df..a66d0a278a87 100644 --- a/arch/arm/dts/sam9x60.dtsi +++ b/arch/arm/dts/sam9x60.dtsi @@ -60,6 +60,16 @@ #size-cells = <1>; ranges;
+ macb0: ethernet@f802c000 { + compatible = "cdns,sam9x60-macb", "cdns,macb"; + reg = <0xf802c000 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii>; + clock-names = "hclk", "pclk"; + clocks = <&macb0_clk>, <&macb0_clk>; + status = "disabled"; + }; + dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; @@ -88,6 +98,22 @@ }; };
+ macb0 { + pinctrl_macb0_rmii: macb0_rmii-0 { + atmel,pins = + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */ + AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ + AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */ + AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */ + }; + }; + sdhci0 { pinctrl_sdhci0: sdhci0 { atmel,pins = @@ -171,6 +197,11 @@ #clock-cells = <0>; reg = <47>; }; + + macb0_clk: macb0_clk { + #clock-cells = <0>; + reg = <24>; + }; };
generic: gck { diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts index e64566ec8e58..6fe9f19f0bc7 100644 --- a/arch/arm/dts/sam9x60ek.dts +++ b/arch/arm/dts/sam9x60ek.dts @@ -17,3 +17,8 @@ stdout-path = &dbgu; }; }; + +&macb0 { + phy-mode = "rmii"; + status = "okay"; +};
From: Sandeep Sheriker Mallikarjun sandeepsheriker.mallikarjun@microchip.com
Add new board SAM9X60-EK using the ARM926 SAM9X60 SoC.
Signed-off-by: Sandeep Sheriker Mallikarjun sandeepsheriker.mallikarjun@microchip.com [tudor.ambarus@microchip.com: - fix number of DRAM banks: One DDR2-SDRAM (W972GG6KB 2 Gbit = 16 Mbit x 16 x 8 banks] - drop SPL related macros - drop memtest macros - drop CONFIG_SPI_BOOT, CONFIG_SYS_USE_DATAFLASH related macros - drop inclusion of asm/arch/at91sam9_smc.h] Signed-off-by: Tudor Ambarus tudor.ambarus@microchip.com --- arch/arm/mach-at91/Kconfig | 7 +++++ board/atmel/sam9x60ek/Kconfig | 12 ++++++++ board/atmel/sam9x60ek/MAINTAINERS | 7 +++++ board/atmel/sam9x60ek/Makefile | 7 +++++ board/atmel/sam9x60ek/sam9x60ek.c | 59 ++++++++++++++++++++++++++++++++++++++ include/configs/sam9x60ek.h | 60 +++++++++++++++++++++++++++++++++++++++ 6 files changed, 152 insertions(+) create mode 100644 board/atmel/sam9x60ek/Kconfig create mode 100644 board/atmel/sam9x60ek/MAINTAINERS create mode 100644 board/atmel/sam9x60ek/Makefile create mode 100644 board/atmel/sam9x60ek/sam9x60ek.c create mode 100644 include/configs/sam9x60ek.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 3cf13042b7b4..85524004f9e4 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -160,6 +160,12 @@ config TARGET_GARDENA_SMART_GATEWAY_AT91SAM select BOARD_LATE_INIT select SUPPORT_SPL
+config TARGET_SAM9X60EK + bool "SAM9X60-EK board" + select SAM9X60 + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + config TARGET_SAMA5D2_PTC_EK bool "SAMA5D2 PTC EK board" select BOARD_EARLY_INIT_F @@ -316,6 +322,7 @@ source "board/atmel/at91sam9m10g45ek/Kconfig" source "board/atmel/at91sam9n12ek/Kconfig" source "board/atmel/at91sam9rlek/Kconfig" source "board/atmel/at91sam9x5ek/Kconfig" +source "board/atmel/sam9x60ek/Kconfig" source "board/atmel/sama5d2_ptc_ek/Kconfig" source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d27_som1_ek/Kconfig" diff --git a/board/atmel/sam9x60ek/Kconfig b/board/atmel/sam9x60ek/Kconfig new file mode 100644 index 000000000000..32fae2108e6e --- /dev/null +++ b/board/atmel/sam9x60ek/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SAM9X60EK + +config SYS_BOARD + default "sam9x60ek" + +config SYS_VENDOR + default "atmel" + +config SYS_CONFIG_NAME + default "sam9x60ek" + +endif diff --git a/board/atmel/sam9x60ek/MAINTAINERS b/board/atmel/sam9x60ek/MAINTAINERS new file mode 100644 index 000000000000..e8c1346863a3 --- /dev/null +++ b/board/atmel/sam9x60ek/MAINTAINERS @@ -0,0 +1,7 @@ +SAM9X60EK BOARD +M: Sandeep Sheriker M sandeep.sheriker@microchip.com +M: Eugen Hristev eugen.hristev@microchip.com +S: Maintained +F: board/atmel/sam9x60ek/ +F: include/configs/sam9x60ek.h +F: configs/sam9x60ek_mmc_defconfig diff --git a/board/atmel/sam9x60ek/Makefile b/board/atmel/sam9x60ek/Makefile new file mode 100644 index 000000000000..12a406a3bb5c --- /dev/null +++ b/board/atmel/sam9x60ek/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries +# +# Author: Sandeep Sheriker M sandeep.sheriker@microchip.com + +obj-y += sam9x60ek.o diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c new file mode 100644 index 000000000000..62938741ddd6 --- /dev/null +++ b/board/atmel/sam9x60ek/sam9x60ek.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries + * + * Author: Sandeep Sheriker M sandeep.sheriker@microchip.com + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <debug_uart.h> +#include <asm/mach-types.h> + +DECLARE_GLOBAL_DATA_PTR; + +void at91_prepare_cpu_var(void); + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + at91_prepare_cpu_var(); + return 0; +} +#endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + at91_seriald_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h new file mode 100644 index 000000000000..b778bd8e83eb --- /dev/null +++ b/include/configs/sam9x60ek.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the SAM9X60EK board. + * + * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries + * + * Author: Sandeep Sheriker M sandeep.sheriker@microchip.com + */ + +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID 0 /* ignored in arm */ + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0) + * NB: in this case, USB 1.1 devices won't be recognized. + */ + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#ifdef CONFIG_SD_BOOT +/* bootstrap + u-boot + env + linux in sd card */ +#define CONFIG_BOOTCOMMAND \ + "fatload mmc 0:1 0x21000000 at91-sam9x60ek.dtb;" \ + "fatload mmc 0:1 0x22000000 zImage;" \ + "bootz 0x22000000 - 0x21000000" +#endif + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) + +#endif
From: Sandeep Sheriker Mallikarjun sandeepsheriker.mallikarjun@microchip.com
add sam9x60ek_mmc_defconfig and for now only supports booting from sdcard.
Signed-off-by: Sandeep Sheriker Mallikarjun sandeepsheriker.mallikarjun@microchip.com Signed-off-by: Nicolas Ferre nicolas.ferre@microchip.com [nicolas.ferre@microchip.com: split patch, add Ethernet controller, phy and tools] [claudiu.beznea@microchip.com: add CONFIG_OF_LIBFDT_OVERLAY] Signed-off-by: Claudiu Beznea claudiu.beznea@microchip.com [tudor.ambarus@microchip.com: Fix number of DRAM banks: One DDR2-SDRAM (W972GG6KB 2 Gbit = 16 Mbit x 16 x 8 banks] Signed-off-by: Tudor Ambarus tudor.ambarus@microchip.com --- configs/sam9x60ek_mmc_defconfig | 52 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 configs/sam9x60ek_mmc_defconfig
diff --git a/configs/sam9x60ek_mmc_defconfig b/configs/sam9x60ek_mmc_defconfig new file mode 100644 index 000000000000..6cdc819a6793 --- /dev/null +++ b/configs/sam9x60ek_mmc_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x23f00000 +CONFIG_TARGET_SAM9X60EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_NR_DRAM_BANKS=8 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="mem=256M console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_OF_LIBFDT_OVERLAY=y
From: Tudor Ambarus tudor.ambarus@microchip.com
The Special Function Registers (SFR) are present in sam9x5 and sam9x60 too, rename sama5_sfr to at91_sfr.h.
Signed-off-by: Tudor Ambarus tudor.ambarus@microchip.com --- arch/arm/mach-at91/armv7/sama5d4_devices.c | 2 +- arch/arm/mach-at91/atmel_sfr.c | 2 +- arch/arm/mach-at91/include/mach/{sama5_sfr.h => at91_sfr.h} | 4 ++-- board/laird/wb50n/wb50n.c | 2 +- drivers/clk/at91/clk-utmi.c | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) rename arch/arm/mach-at91/include/mach/{sama5_sfr.h => at91_sfr.h} (97%)
diff --git a/arch/arm/mach-at91/armv7/sama5d4_devices.c b/arch/arm/mach-at91/armv7/sama5d4_devices.c index 5c693df2ecf0..e68ae9940788 100644 --- a/arch/arm/mach-at91/armv7/sama5d4_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d4_devices.c @@ -8,7 +8,7 @@ #include <asm/io.h> #include <asm/arch/at91_common.h> #include <asm/arch/clk.h> -#include <asm/arch/sama5_sfr.h> +#include <asm/arch/at91_sfr.h> #include <asm/arch/sama5d4.h>
char *get_cpu_name() diff --git a/arch/arm/mach-at91/atmel_sfr.c b/arch/arm/mach-at91/atmel_sfr.c index 13cfba0ba0c0..b14222460f3a 100644 --- a/arch/arm/mach-at91/atmel_sfr.c +++ b/arch/arm/mach-at91/atmel_sfr.c @@ -7,7 +7,7 @@ #include <common.h> #include <asm/hardware.h> #include <asm/io.h> -#include <asm/arch/sama5_sfr.h> +#include <asm/arch/at91_sfr.h>
#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D4) void redirect_int_from_saic_to_aic(void) diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h b/arch/arm/mach-at91/include/mach/at91_sfr.h similarity index 97% rename from arch/arm/mach-at91/include/mach/sama5_sfr.h rename to arch/arm/mach-at91/include/mach/at91_sfr.h index f9c412f9989a..dc259055cff6 100644 --- a/arch/arm/mach-at91/include/mach/sama5_sfr.h +++ b/arch/arm/mach-at91/include/mach/at91_sfr.h @@ -6,8 +6,8 @@ * Bo Shen voice.shen@atmel.com */
-#ifndef __SAMA5_SFR_H -#define __SAMA5_SFR_H +#ifndef __AT91_SFR_H +#define __AT91_SFR_H
struct atmel_sfr { u32 reserved1; /* 0x00 */ diff --git a/board/laird/wb50n/wb50n.c b/board/laird/wb50n/wb50n.c index ab1dbcd879ae..13563abb49ef 100644 --- a/board/laird/wb50n/wb50n.c +++ b/board/laird/wb50n/wb50n.c @@ -4,7 +4,7 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch/sama5_sfr.h> +#include <asm/arch/at91_sfr.h> #include <asm/arch/sama5d3_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c index e8506099fd32..18af0bfeaad1 100644 --- a/drivers/clk/at91/clk-utmi.c +++ b/drivers/clk/at91/clk-utmi.c @@ -10,7 +10,7 @@ #include <syscon.h> #include <linux/io.h> #include <mach/at91_pmc.h> -#include <mach/sama5_sfr.h> +#include <mach/at91_sfr.h> #include "pmc.h"
/*
From: Tudor Ambarus tudor.ambarus@microchip.com
sama5's SFR has at offset 0x04 the DDR Configuration Register, while sam9x60's SFR contains the EBI Chip Select Register. Add a union to reconcile both boards.
Signed-off-by: Tudor Ambarus tudor.ambarus@microchip.com --- arch/arm/mach-at91/include/mach/at91_sfr.h | 48 ++++++++++++++++++++++++++++-- 1 file changed, 45 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/at91_sfr.h b/arch/arm/mach-at91/include/mach/at91_sfr.h index dc259055cff6..0300c336dd81 100644 --- a/arch/arm/mach-at91/include/mach/at91_sfr.h +++ b/arch/arm/mach-at91/include/mach/at91_sfr.h @@ -11,7 +11,10 @@
struct atmel_sfr { u32 reserved1; /* 0x00 */ - u32 ddrcfg; /* 0x04: DDR Configuration Register */ + union { + u32 ddrcfg; /* 0x04: DDR Configuration Register */ + u32 ebicsa; /* 0x04: EBI Chip Select Register */ + }; u32 reserved2; /* 0x08 */ u32 reserved3; /* 0x0c */ u32 ohciicr; /* 0x10: OHCI Interrupt Configuration Register */ @@ -28,7 +31,16 @@ struct atmel_sfr { };
/* Register Mapping*/ +#define AT91_SFR_DDRCFG 0x04 /* DDR Configuration Register */ +#define AT91_SFR_CCFG_EBICSA 0x04 /* EBI Chip Select Register */ +/* 0x08 ~ 0x0c: Reserved */ +#define AT91_SFR_OHCIICR 0x10 /* OHCI INT Configuration Register */ +#define AT91_SFR_OHCIISR 0x14 /* OHCI INT Status Register */ #define AT91_SFR_UTMICKTRIM 0x30 /* UTMI Clock Trimming Register */ +#define AT91_SFR_UTMISWAP 0x3c /* UTMI DP/DM Pin Swapping Register */ +#define AT91_SFR_LS 0x7c /* Light Sleep Register */ +#define AT91_SFR_I2SCLKSEL 0x90 /* I2SC Register */ +#define AT91_SFR_WPMR 0xe4 /* Write Protection Mode Register */
/* Bit field in DDRCFG */ #define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000 @@ -58,9 +70,39 @@ struct atmel_sfr { #define AT91_SFR_EBICFG_SCH1_OFF (0x0 << 12) #define AT91_SFR_EBICFG_SCH1_ON (0x1 << 12)
-#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0) - /* Bit field in AICREDIR */ #define ATMEL_SFR_AICREDIR_NSAIC 0x00000001
+/* Bit field in DDRCFG */ +#define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000 +#define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000 + +#define AT91_SFR_CCFG_EBI_CSA(cs, val) ((val) << (cs)) +#define AT91_SFR_CCFG_EBI_DBPUC BIT(8) +#define AT91_SFR_CCFG_EBI_DBPDC BIT(9) +#define AT91_SFR_CCFG_EBI_DRIVE_SAM9X60 BIT(16) +#define AT91_SFR_CCFG_EBI_DRIVE BIT(17) +#define AT91_SFR_CCFG_DQIEN_F BIT(20) +#define AT91_SFR_CCFG_NFD0_ON_D16 BIT(24) +#define AT91_SFR_CCFG_DDR_MP_EN BIT(25) + +#define AT91_SFR_OHCIICR_RES(x) BIT(x) +#define AT91_SFR_OHCIICR_ARIE BIT(4) +#define AT91_SFR_OHCIICR_APPSTART BIT(5) +#define AT91_SFR_OHCIICR_USB_SUSP(x) BIT(8 + (x)) +#define AT91_SFR_OHCIICR_UDPPUDIS BIT(23) +#define AT91_OHCIICR_USB_SUSPEND GENMASK(10, 8) + +#define AT91_SFR_OHCIISR_RIS(x) BIT(x) + +#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0) + +#define AT91_SFR_UTMISWAP_PORT(x) BIT(x) + +#define AT91_SFR_LS_VALUE(x) BIT(x) +#define AT91_SFR_LS_MEM_POWER_GATING_ULP1_EN BIT(16) + +#define AT91_SFR_WPMR_WPEN BIT(0) +#define AT91_SFR_WPMR_WPKEY_MASK GENMASK(31, 8) + #endif
From: Tudor Ambarus tudor.ambarus@microchip.com
- EBI Chip Select Register is now in SFR, - the pins are set to default values, - timings are matching MT29F4G08BABWP's nand flash requirements.
Signed-off-by: Tudor Ambarus tudor.ambarus@microchip.com --- board/atmel/sam9x60ek/sam9x60ek.c | 61 +++++++++++++++++++++++++++++++++++++++ include/configs/sam9x60ek.h | 28 ++++++++++++++++++ 2 files changed, 89 insertions(+)
diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c index 62938741ddd6..e352afc67ed3 100644 --- a/board/atmel/sam9x60ek/sam9x60ek.c +++ b/board/atmel/sam9x60ek/sam9x60ek.c @@ -7,8 +7,10 @@
#include <common.h> #include <asm/io.h> +#include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_rstc.h> +#include <asm/arch/at91_sfr.h> #include <asm/arch/clk.h> #include <asm/arch/gpio.h> #include <debug_uart.h> @@ -18,6 +20,62 @@ DECLARE_GLOBAL_DATA_PTR;
void at91_prepare_cpu_var(void);
+#ifdef CONFIG_CMD_NAND +static void sam9x60ek_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; + unsigned int csa; + + at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* NAND ALE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* NAND CLE */ + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); + + at91_periph_clk_enable(ATMEL_ID_PIOD); + + /* Enable CS3 */ + csa = readl(&sfr->ebicsa); + csa |= AT91_SFR_CCFG_EBI_CSA(3, 1) | AT91_SFR_CCFG_NFD0_ON_D16; + + /* Configure IO drive */ + csa &= ~AT91_SFR_CCFG_EBI_DRIVE_SAM9X60; + + writel(csa, &sfr->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(4), &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(20) | + AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(20), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20), + &smc->cs[3].cycle); + + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_MODE_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_MODE_DBW_8 | +#endif + AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(15), + &smc->cs[3].mode); +} +#endif + #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { @@ -48,6 +106,9 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#ifdef CONFIG_CMD_NAND + sam9x60ek_nand_hw_init(); +#endif return 0; }
diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index b778bd8e83eb..dbcbce3a2b80 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -42,6 +42,26 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_MTD_DEVICE +#endif + +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC +#define CONFIG_ATMEL_NAND_HW_PMECC +#define CONFIG_PMECC_CAP 8 +#define CONFIG_PMECC_SECTOR_SIZE 512 + #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#ifdef CONFIG_SD_BOOT @@ -50,6 +70,14 @@ "fatload mmc 0:1 0x21000000 at91-sam9x60ek.dtb;" \ "fatload mmc 0:1 0x22000000 zImage;" \ "bootz 0x22000000 - 0x21000000" + +#elif defined(CONFIG_NAND_BOOT) +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_ENV_OFFSET_REDUND 0x100000 +#define CONFIG_BOOTCOMMAND "nand read " \ + "0x22000000 0x200000 0x600000; " \ + "nand read 0x21000000 0x180000 0x20000; " \ + "bootz 0x22000000 - 0x21000000" #endif
/*
From: Tudor Ambarus tudor.ambarus@microchip.com
Boot from nand flash.
Signed-off-by: Tudor Ambarus tudor.ambarus@microchip.com --- board/atmel/sam9x60ek/MAINTAINERS | 1 + configs/sam9x60ek_nandflash_defconfig | 53 +++++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 configs/sam9x60ek_nandflash_defconfig
diff --git a/board/atmel/sam9x60ek/MAINTAINERS b/board/atmel/sam9x60ek/MAINTAINERS index e8c1346863a3..ec5bed7479ba 100644 --- a/board/atmel/sam9x60ek/MAINTAINERS +++ b/board/atmel/sam9x60ek/MAINTAINERS @@ -5,3 +5,4 @@ S: Maintained F: board/atmel/sam9x60ek/ F: include/configs/sam9x60ek.h F: configs/sam9x60ek_mmc_defconfig +F: configs/sam9x60ek_nandflash_defconfig diff --git a/configs/sam9x60ek_nandflash_defconfig b/configs/sam9x60ek_nandflash_defconfig new file mode 100644 index 000000000000..948d7c7a7227 --- /dev/null +++ b/configs/sam9x60ek_nandflash_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x23f00000 +CONFIG_TARGET_SAM9X60EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=8 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_NAND_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=12 root=ubi0:rootfs rw" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek" +CONFIG_ENV_IS_IN_NAND=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_OF_LIBFDT_OVERLAY=y
From: Tudor Ambarus tudor.ambarus@microchip.com
Cope with the offsets defined at: https://www.at91.com/linux4sam/pub/Linux4SAM/SambaSubsections/demo_nandflash...
The environment starts at 0x140000 and it's of size 0x20000. The device tree starts at 0x180000 and it's of size 0x80000. The zImage starts at 0x200000 and it's of size 0x600000.
Signed-off-by: Tudor Ambarus tudor.ambarus@microchip.com --- include/configs/sam9x60ek.h | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index dbcbce3a2b80..5f89ae4a511a 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -78,6 +78,13 @@ "0x22000000 0x200000 0x600000; " \ "nand read 0x21000000 0x180000 0x20000; " \ "bootz 0x22000000 - 0x21000000" + +#elif defined(CONFIG_QSPI_BOOT) +/* bootstrap + u-boot + env + linux in SPI NOR flash */ +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x21000000 0x180000 0x80000; " \ + "sf read 0x22000000 0x200000 0x600000; " \ + "bootz 0x22000000 - 0x21000000" #endif
/*
From: Tudor Ambarus tudor.ambarus@microchip.com
The sam9x60 qspi controller uses 2 clocks, one for the peripheral register access, the other for the qspi core and phy. Both are mandatory.
Enable the qspi node together with the SST26VF064B qspi nor flash memory. Booting from the QSPI NOR flash is now possible.
Signed-off-by: Tudor Ambarus tudor.ambarus@microchip.com --- arch/arm/dts/sam9x60.dtsi | 29 +++++++++++++++++++++++++++++ arch/arm/dts/sam9x60ek-u-boot.dtsi | 28 ++++++++++++++++++++++++++++ arch/arm/dts/sam9x60ek.dts | 31 +++++++++++++++++++++++++++++++ 3 files changed, 88 insertions(+)
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi index a66d0a278a87..9c16ba1e6a87 100644 --- a/arch/arm/dts/sam9x60.dtsi +++ b/arch/arm/dts/sam9x60.dtsi @@ -22,6 +22,7 @@ serial0 = &dbgu; gpio0 = &pioA; gpio1 = &pioB; + spi0 = &qspi; };
clocks { @@ -60,6 +61,17 @@ #size-cells = <1>; ranges;
+ qspi: spi@f0014000 { + compatible = "microchip,sam9x60-qspi"; + reg = <0xf0014000 0x100>, <0x70000000 0x10000000>; + reg-names = "qspi_base", "qspi_mmap"; + clocks = <&qspi_clk>, <&qspick>; + clock-names = "pclk", "qspick"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + macb0: ethernet@f802c000 { compatible = "cdns,sam9x60-macb", "cdns,macb"; reg = <0xf802c000 0x100>; @@ -172,6 +184,18 @@ atmel,clk-divisors = <1 2 4 6>; };
+ system: systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + qspick: qspick { + #clock-cells = <0>; + reg = <19>; + clocks = <&mck>; + }; + }; + periph: periphck { compatible = "microchip,sam9x60-clk-peripheral"; #address-cells = <1>; @@ -202,6 +226,11 @@ #clock-cells = <0>; reg = <24>; }; + + qspi_clk: qspi_clk { + #clock-cells = <0>; + reg = <35>; + }; };
generic: gck { diff --git a/arch/arm/dts/sam9x60ek-u-boot.dtsi b/arch/arm/dts/sam9x60ek-u-boot.dtsi index 68e220926e5e..93cf1262f6fc 100644 --- a/arch/arm/dts/sam9x60ek-u-boot.dtsi +++ b/arch/arm/dts/sam9x60ek-u-boot.dtsi @@ -31,6 +31,10 @@ u-boot,dm-pre-reloc; };
+&qspi { + u-boot,dm-pre-reloc; +}; + &pinctrl_dbgu { u-boot,dm-pre-reloc; }; @@ -39,10 +43,18 @@ u-boot,dm-pre-reloc; };
+&pinctrl_qspi { + u-boot,dm-pre-reloc; +}; + &pioA { u-boot,dm-pre-reloc; };
+&pioB { + u-boot,dm-pre-reloc; +}; + &pmc { u-boot,dm-pre-reloc; }; @@ -59,6 +71,14 @@ u-boot,dm-pre-reloc; };
+&system { + u-boot,dm-pre-reloc; +}; + +&qspick { + u-boot,dm-pre-reloc; +}; + &periph { u-boot,dm-pre-reloc; }; @@ -67,6 +87,10 @@ u-boot,dm-pre-reloc; };
+&pioB_clk { + u-boot,dm-pre-reloc; +}; + &sdhci0_clk { u-boot,dm-pre-reloc; }; @@ -75,6 +99,10 @@ u-boot,dm-pre-reloc; };
+&qspi_clk { + u-boot,dm-pre-reloc; +}; + &generic { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts index 6fe9f19f0bc7..63904272f08f 100644 --- a/arch/arm/dts/sam9x60ek.dts +++ b/arch/arm/dts/sam9x60ek.dts @@ -16,6 +16,37 @@ chosen { stdout-path = &dbgu; }; + + ahb { + apb { + qspi: spi@f0014000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + nor_flash: sst26vf064@0 { + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; + }; + + pinctrl { + pinctrl_qspi: qspi { + atmel,pins = + <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE + AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE + AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; + }; + + }; + }; + }; };
&macb0 {
From: Tudor Ambarus tudor.ambarus@microchip.com
Boot from QSPI nor flash.
The at91bootstrap, u-boot, u-boot env redundant, u-boot env, device tree and kernel will reside in the QSPI nor flash. The rootfs will reside in the NAND flash.
Signed-off-by: Tudor Ambarus tudor.ambarus@microchip.com --- board/atmel/sam9x60ek/MAINTAINERS | 1 + configs/sam9x60ek_qspiflash_defconfig | 75 +++++++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) create mode 100644 configs/sam9x60ek_qspiflash_defconfig
diff --git a/board/atmel/sam9x60ek/MAINTAINERS b/board/atmel/sam9x60ek/MAINTAINERS index ec5bed7479ba..d209249c2eff 100644 --- a/board/atmel/sam9x60ek/MAINTAINERS +++ b/board/atmel/sam9x60ek/MAINTAINERS @@ -6,3 +6,4 @@ F: board/atmel/sam9x60ek/ F: include/configs/sam9x60ek.h F: configs/sam9x60ek_mmc_defconfig F: configs/sam9x60ek_nandflash_defconfig +F: configs/sam9x60ek_qspiflash_defconfig diff --git a/configs/sam9x60ek_qspiflash_defconfig b/configs/sam9x60ek_qspiflash_defconfig new file mode 100644 index 000000000000..0d0932bba3f8 --- /dev/null +++ b/configs/sam9x60ek_qspiflash_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x23f00000 +CONFIG_TARGET_SAM9X60EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=8 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_DEBUG_UART=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=12 root=ubi0:rootfs rw" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_SF=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_ENV_SPI_BUS=y +CONFIG_ENV_SPI_BUS=0 +CONFIG_USE_ENV_SPI_CS=y +CONFIG_ENV_SPI_CS=0 +CONFIG_USE_ENV_SPI_MAX_HZ=y +CONFIG_ENV_SPI_MAX_HZ=50000000 +CONFIG_USE_ENV_SPI_MODE=y +CONFIG_ENV_SPI_MODE=0x0 +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_OF_LIBFDT_OVERLAY=y
Applied this series to u-boot-atmel/next, thanks !
On 27.09.2019 16:08, Tudor Ambarus - M18064 wrote:
From: Tudor Ambarus tudor.ambarus@microchip.com
Add support for sam9x60 SOC, sam9x60ek board, dts, NAND and QSPI. Add defconfigs for MMC, NAND and QSPI.
v3:
- Enable MII utility commands and phy in qspi & nand defconfigs
- Add sam9x60-sdhci and sam9x60-macb compatibility strings
- nandflash_defconfig: Fix rootfs partition
v2: add maintainers for qspi & nand defconfigs
Nicolas Ferre (2): net: macb: Add sam9x60-macb compatibility string ARM: dts: at91: sam9x60: Add macb0 Ethernet controller
Sandeep Sheriker Mallikarjun (5): mmc: atmel_sdhci: Add sam9x60-sdhci compatibility string ARM: at91: Add sam9x60 soc ARM: dts: Add dts files for sam9x60ek board: atmel: Add sam9x60ek board configs: Add sam9x60ek_mmc_defconfig
Tudor Ambarus (7): ARM: at91: Rename sama5_sfr.h to at91_sfr.h ARM: at91: Add SFR definitions board: sam9x60ek: Add NAND flash support configs: Add sam9x60ek_nandflash_defconfig configs: sam9x60ek: Add QSPI_BOOT defines ARM: dts: at91: sam9x60ek: Enable qspi node configs: Add sam9x60ek_qspiflash_defconfig
arch/arm/dts/Makefile | 2 + arch/arm/dts/sam9x60.dtsi | 285 +++++++++++++++++++++ arch/arm/dts/sam9x60ek-u-boot.dtsi | 132 ++++++++++ arch/arm/dts/sam9x60ek.dts | 55 ++++ arch/arm/mach-at91/Kconfig | 11 + arch/arm/mach-at91/arm926ejs/Makefile | 1 + arch/arm/mach-at91/arm926ejs/sam9x60_devices.c | 125 +++++++++ arch/arm/mach-at91/armv7/sama5d4_devices.c | 2 +- arch/arm/mach-at91/atmel_sfr.c | 2 +- .../include/mach/{sama5_sfr.h => at91_sfr.h} | 52 +++- arch/arm/mach-at91/include/mach/hardware.h | 2 + arch/arm/mach-at91/include/mach/sam9x60.h | 169 ++++++++++++ board/atmel/sam9x60ek/Kconfig | 12 + board/atmel/sam9x60ek/MAINTAINERS | 9 + board/atmel/sam9x60ek/Makefile | 7 + board/atmel/sam9x60ek/sam9x60ek.c | 120 +++++++++ board/laird/wb50n/wb50n.c | 2 +- configs/sam9x60ek_mmc_defconfig | 52 ++++ configs/sam9x60ek_nandflash_defconfig | 53 ++++ configs/sam9x60ek_qspiflash_defconfig | 75 ++++++ drivers/clk/at91/clk-utmi.c | 2 +- drivers/mmc/atmel_sdhci.c | 1 + drivers/net/macb.c | 1 + include/configs/sam9x60ek.h | 95 +++++++ 24 files changed, 1258 insertions(+), 9 deletions(-) create mode 100644 arch/arm/dts/sam9x60.dtsi create mode 100644 arch/arm/dts/sam9x60ek-u-boot.dtsi create mode 100644 arch/arm/dts/sam9x60ek.dts create mode 100644 arch/arm/mach-at91/arm926ejs/sam9x60_devices.c rename arch/arm/mach-at91/include/mach/{sama5_sfr.h => at91_sfr.h} (53%) create mode 100644 arch/arm/mach-at91/include/mach/sam9x60.h create mode 100644 board/atmel/sam9x60ek/Kconfig create mode 100644 board/atmel/sam9x60ek/MAINTAINERS create mode 100644 board/atmel/sam9x60ek/Makefile create mode 100644 board/atmel/sam9x60ek/sam9x60ek.c create mode 100644 configs/sam9x60ek_mmc_defconfig create mode 100644 configs/sam9x60ek_nandflash_defconfig create mode 100644 configs/sam9x60ek_qspiflash_defconfig create mode 100644 include/configs/sam9x60ek.h
participants (2)
-
Eugen.Hristev＠microchip.com -
Tudor.Ambarus＠microchip.com