Generic Interface (GENI) Serial Engine (SE) based uart can be found on newer qualcomm SOCs, starting from SDM845. Tested on Samsung SM-G9600(starqltechn) by chain-loading u-boot with stock bootloader.

Signed-off-by: Dzmitry Sankouski dsankouski@gmail.com Cc: Ramon Fried rfried.dev@gmail.com Cc: Tom Rini trini@konsulko.com --- Changes for v2: - change functions return type to void, where possible - remove '.' from summary line Changes for v3: - move function open brace on new line - use tab between define name and value - define: wrap expression with braces, remove braces from constants Changes for v4: - add linux/delay.h header

MAINTAINERS | 1 + .../serial/msm-geni-serial.txt | 6 + drivers/serial/Kconfig | 17 + drivers/serial/Makefile | 1 + drivers/serial/serial_msm_geni.c | 603 ++++++++++++++++++ 5 files changed, 628 insertions(+) create mode 100644 doc/device-tree-bindings/serial/msm-geni-serial.txt create mode 100644 drivers/serial/serial_msm_geni.c

diff --git a/MAINTAINERS b/MAINTAINERS index 776ff703b9..52ddc99cda 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -390,6 +390,7 @@ F: drivers/gpio/msm_gpio.c F: drivers/mmc/msm_sdhci.c F: drivers/phy/msm8916-usbh-phy.c F: drivers/serial/serial_msm.c +F: drivers/serial/serial_msm_geni.c F: drivers/smem/msm_smem.c F: drivers/usb/host/ehci-msm.c

diff --git a/doc/device-tree-bindings/serial/msm-geni-serial.txt b/doc/device-tree-bindings/serial/msm-geni-serial.txt new file mode 100644 index 0000000000..9eadc2561b --- /dev/null +++ b/doc/device-tree-bindings/serial/msm-geni-serial.txt @@ -0,0 +1,6 @@ +Qualcomm GENI UART + +Required properties: +- compatible: must be "qcom,msm-geni-uart" +- reg: start address and size of the registers +- clock: interface clock (must accept baudrate as a frequency) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 93348c0929..b420a5720d 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -278,6 +278,14 @@ config DEBUG_UART_S5P will need to provide parameters to make this work. The driver will be available until the real driver-model serial is running.

+config DEBUG_UART_MSM_GENI + bool "Qualcomm snapdragon" + depends on ARCH_SNAPDRAGON + help + Select this to enable a debug UART using the serial_msm driver. You + will need to provide parameters to make this work. The driver will + be available until the real driver-model serial is running. + config DEBUG_UART_MESON bool "Amlogic Meson" depends on MESON_SERIAL @@ -783,6 +791,15 @@ config MSM_SERIAL for example APQ8016 and MSM8916. Single baudrate is supported in current implementation (115200).

+config MSM_GENI_SERIAL + bool "Qualcomm on-chip GENI UART" + help + Support UART based on Generic Interface (GENI) Serial Engine (SE), used on Qualcomm Snapdragon SoCs. + Should support all qualcomm SOCs with Qualcomm Universal Peripheral (QUP) Wrapper cores, + i.e. newer ones, starting from SDM845. + Driver works in FIFO mode. + Multiple baudrates supported. + config OCTEON_SERIAL_BOOTCMD bool "MIPS Octeon PCI remote bootcmd input" depends on ARCH_OCTEON diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 3cbea8156f..d44caf4ea2 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -62,6 +62,7 @@ obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o obj-$(CONFIG_BCM283X_PL011_SERIAL) += serial_bcm283x_pl011.o obj-$(CONFIG_MSM_SERIAL) += serial_msm.o +obj-$(CONFIG_MSM_GENI_SERIAL) += serial_msm_geni.o obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c new file mode 100644 index 0000000000..c656d54cbb --- /dev/null +++ b/drivers/serial/serial_msm_geni.c @@ -0,0 +1,603 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm GENI serial engine UART driver + * + * (C) Copyright 2021 Dzmitry Sankouski dsankouski@gmail.com + * + * Based on Linux driver. + */ + +#include <asm/io.h> +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <errno.h> +#include <linux/compiler.h> +#include <log.h> +#include <linux/delay.h> +#include <malloc.h> +#include <serial.h> +#include <watchdog.h> + +#define UART_OVERSAMPLING 32 +#define STALE_TIMEOUT 160 +#define SE_UART_RX_STALE_CNT 0x294 +#define S_GENI_CMD_ABORT (BIT(1)) + +#define SE_GENI_S_CMD_CTRL_REG 0x634 +#define SE_GENI_M_CMD_CTRL_REG 0x604 + +/* GENI_M_CMD_CTRL_REG */ +#define M_GENI_CMD_CANCEL (BIT(2)) +#define M_GENI_CMD_ABORT (BIT(1)) +#define M_GENI_DISABLE (BIT(0)) + +/* GENI_S_CMD0 fields */ +#define S_OPCODE_MSK (GENMASK(31, 27)) +#define S_OPCODE_SHFT 27 +#define S_PARAMS_MSK (GENMASK(26, 0)) + +/* GENI_STATUS fields */ +#define M_GENI_CMD_ACTIVE (BIT(0)) +#define S_GENI_CMD_ACTIVE (BIT(12)) +#define S_CMD_DONE_EN (BIT(0)) +#define M_CMD_DONE_EN (BIT(0)) + +#define USEC_PER_SEC 1000000L + +#define SE_GENI_STATUS 0x40 +#define GENI_SER_M_CLK_CFG 0x48 +#define GENI_SER_S_CLK_CFG 0x4C +#define SE_GENI_M_CMD0 0x600 +#define SE_GENI_M_IRQ_CLEAR 0x618 +#define SE_GENI_S_IRQ_STATUS 0x640 +#define SE_GENI_S_IRQ_CLEAR 0x648 +#define SE_GENI_S_IRQ_EN 0x644 +#define SE_GENI_M_IRQ_EN 0x614 +#define SE_GENI_TX_FIFOn 0x700 +#define SE_GENI_RX_FIFOn 0x780 +#define SE_GENI_TX_FIFO_STATUS 0x800 +#define SE_GENI_RX_FIFO_STATUS 0x804 +#define SE_GENI_TX_WATERMARK_REG 0x80C +#define M_TX_FIFO_WATERMARK_EN (BIT(30)) +#define DEF_TX_WM 2 +#define SE_UART_TX_TRANS_LEN 0x270 +#define SE_GENI_TX_PACKING_CFG0 0x260 +#define SE_GENI_TX_PACKING_CFG1 0x264 +#define SE_GENI_RX_PACKING_CFG0 0x284 +#define SE_GENI_RX_PACKING_CFG1 0x288 +#define SE_UART_TX_STOP_BIT_LEN 0x26c +#define SE_UART_TX_WORD_LEN 0x268 +#define SE_UART_RX_WORD_LEN 0x28c +#define SE_UART_RX_TRANS_CFG 0x280 +#define SE_UART_RX_PARITY_CFG 0x2a8 +#define SE_UART_TX_TRANS_CFG 0x25c +#define SE_UART_TX_PARITY_CFG 0x2a4 + +#define GENI_FORCE_DEFAULT_REG 0x20 +/* GENI_FORCE_DEFAULT_REG fields */ +#define FORCE_DEFAULT (BIT(0)) + +#define S_CMD_ABORT_EN (BIT(5)) + +#define SE_GENI_S_CMD0 0x630 +#define UART_START_READ 0x1 + +/* GENI_M_CMD_CTRL_REG */ +#define M_GENI_CMD_CANCEL (BIT(2)) +#define M_GENI_CMD_ABORT (BIT(1)) +#define M_GENI_DISABLE (BIT(0)) + +#define M_CMD_ABORT_EN (BIT(5)) + +#define M_CMD_DONE_EN (BIT(0)) +#define M_CMD_DONE_DISABLE_MASK (~M_CMD_DONE_EN) +#define SE_GENI_M_IRQ_STATUS 0x610 + +#define M_OPCODE_SHIFT 27 +#define S_OPCODE_SHIFT 27 +#define M_TX_FIFO_WATERMARK_EN (BIT(30)) +#define UART_START_TX 0x1 +#define UART_CTS_MASK (BIT(1)) +#define M_SEC_IRQ_EN (BIT(31)) +#define TX_FIFO_WC_MSK (GENMASK(27, 0)) +#define RX_FIFO_WC_MSK (GENMASK(24, 0)) + +#define S_RX_FIFO_WATERMARK_EN (BIT(26)) +#define S_RX_FIFO_LAST_EN (BIT(27)) +#define M_RX_FIFO_WATERMARK_EN (BIT(26)) +#define M_RX_FIFO_LAST_EN (BIT(27)) + +/* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */ +#define SER_CLK_EN (BIT(0)) +#define CLK_DIV_MSK (GENMASK(15, 4)) +#define CLK_DIV_SHFT 4 + +#define SE_HW_PARAM_0 0xE24 +/* SE_HW_PARAM_0 fields */ +#define TX_FIFO_WIDTH_MSK (GENMASK(29, 24)) +#define TX_FIFO_WIDTH_SHFT 24 +#define TX_FIFO_DEPTH_MSK (GENMASK(21, 16)) +#define TX_FIFO_DEPTH_SHFT 16 + +DECLARE_GLOBAL_DATA_PTR; + +struct msm_serial_data { + phys_addr_t base; + u32 baud; +}; + +static int get_clk_cfg(unsigned long clk_freq, unsigned long *ser_clk) +{ + unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200, + 32000000, 48000000, 64000000, 80000000, + 96000000, 100000000}; + int i; + int match = -1; + + for (i = 0; i < ARRAY_SIZE(root_freq); i++) { + if (clk_freq > root_freq[i]) + continue; + + if (!(root_freq[i] % clk_freq)) { + match = i; + break; + } + } + if (match != -1) + *ser_clk = root_freq[match]; + else + pr_err("clk_freq %ld\n", clk_freq); + return match; +} + +static int get_clk_div_rate(u32 baud, u64 *desired_clk_rate) +{ + unsigned long ser_clk; + int dfs_index; + int clk_div = 0; + + *desired_clk_rate = baud * UART_OVERSAMPLING; + dfs_index = get_clk_cfg(*desired_clk_rate, &ser_clk); + if (dfs_index < 0) { + pr_err("%s: Can't find matching DFS entry for baud %d\n", + __func__, baud); + clk_div = -EINVAL; + goto exit_get_clk_div_rate; + } + + clk_div = ser_clk / *desired_clk_rate; + *desired_clk_rate = ser_clk; +exit_get_clk_div_rate: + return clk_div; +} + +static int geni_serial_set_clock_rate(struct udevice *dev, u64 rate) +{ + struct clk *clk; + int ret; + + clk = devm_clk_get(dev, "se-clk"); + if (!clk) + return -EINVAL; + + ret = clk_set_rate(clk, rate); + return ret; +} + +/** + * geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine + * @base: Pointer to the concerned serial engine. + * + * This function is used to get the depth i.e. number of elements in the + * TX fifo of the serial engine. + * + * Return: TX fifo depth in units of FIFO words. + */ +static inline u32 geni_se_get_tx_fifo_depth(long base) +{ + u32 tx_fifo_depth; + + tx_fifo_depth = ((readl(base + SE_HW_PARAM_0) & TX_FIFO_DEPTH_MSK) >> + TX_FIFO_DEPTH_SHFT); + return tx_fifo_depth; +} + +/** + * geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine + * @base: Pointer to the concerned serial engine. + * + * This function is used to get the width i.e. word size per element in the + * TX fifo of the serial engine. + * + * Return: TX fifo width in bits + */ +static inline u32 geni_se_get_tx_fifo_width(long base) +{ + u32 tx_fifo_width; + + tx_fifo_width = ((readl(base + SE_HW_PARAM_0) & TX_FIFO_WIDTH_MSK) >> + TX_FIFO_WIDTH_SHFT); + return tx_fifo_width; +} + +static inline void geni_serial_baud(phys_addr_t base_address, u64 uclk, + int baud) +{ + u32 clk_div; + u32 s_clk_cfg = 0; + + clk_div = get_clk_div_rate(baud, &uclk); + + s_clk_cfg |= SER_CLK_EN; + s_clk_cfg |= (clk_div << CLK_DIV_SHFT); + + writel(s_clk_cfg, base_address + GENI_SER_M_CLK_CFG); + writel(s_clk_cfg, base_address + GENI_SER_S_CLK_CFG); +} + +int msm_serial_setbrg(struct udevice *dev, int baud) +{ + struct msm_serial_data *priv = dev_get_priv(dev); + + priv->baud = baud; + u32 clk_div; + u64 clk_rate; + + clk_div = get_clk_div_rate(baud, &clk_rate); + geni_serial_set_clock_rate(dev, clk_rate); + geni_serial_baud(priv->base, clk_rate, baud); + + return 0; +} + +static bool qcom_geni_serial_poll_bit(const struct udevice *dev, int offset, + int field, bool set) +{ + u32 reg; + struct msm_serial_data *priv = dev_get_priv(dev); + unsigned int baud; + unsigned int tx_fifo_depth; + unsigned int tx_fifo_width; + unsigned int fifo_bits; + unsigned long timeout_us = 10000; + + baud = 115200; + + if (priv) { + baud = priv->baud; + if (!baud) + baud = 115200; + tx_fifo_depth = geni_se_get_tx_fifo_depth(priv->base); + tx_fifo_width = geni_se_get_tx_fifo_width(priv->base); + fifo_bits = tx_fifo_depth * tx_fifo_width; + /* + * Total polling iterations based on FIFO worth of bytes to be + * sent at current baud. Add a little fluff to the wait. + */ + timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500; + } + + /* + * Use custom implementation instead of readl_poll_atomic since ktimer + * is not ready at the time of early console. + */ + timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; + while (timeout_us) { + reg = readl(priv->base + offset); + if ((bool)(reg & field) == set) + return true; + udelay(10); + timeout_us -= 10; + } + return false; +} + +static void qcom_geni_serial_setup_tx(u64 base, u32 xmit_size) +{ + u32 m_cmd; + + writel(xmit_size, base + SE_UART_TX_TRANS_LEN); + m_cmd = UART_START_TX << M_OPCODE_SHIFT; + writel(m_cmd, base + SE_GENI_M_CMD0); +} + +static inline void qcom_geni_serial_poll_tx_done(const struct udevice *dev) +{ + struct msm_serial_data *priv = dev_get_priv(dev); + int done = 0; + u32 irq_clear = M_CMD_DONE_EN; + + done = qcom_geni_serial_poll_bit(dev, SE_GENI_M_IRQ_STATUS, + M_CMD_DONE_EN, true); + if (!done) { + writel(M_GENI_CMD_ABORT, priv->base + SE_GENI_M_CMD_CTRL_REG); + irq_clear |= M_CMD_ABORT_EN; + qcom_geni_serial_poll_bit(dev, SE_GENI_M_IRQ_STATUS, + M_CMD_ABORT_EN, true); + } + writel(irq_clear, priv->base + SE_GENI_M_IRQ_CLEAR); +} + +static u32 qcom_geni_serial_tx_empty(u64 base) +{ + return !readl(base + SE_GENI_TX_FIFO_STATUS); +} + +/** + * geni_se_setup_s_cmd() - Setup the secondary sequencer + * @se: Pointer to the concerned serial engine. + * @cmd: Command/Operation to setup in the secondary sequencer. + * @params: Parameter for the sequencer command. + * + * This function is used to configure the secondary sequencer with the + * command and its associated parameters. + */ +static inline void geni_se_setup_s_cmd(u64 base, u32 cmd, u32 params) +{ + u32 s_cmd; + + s_cmd = readl(base + SE_GENI_S_CMD0); + s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK); + s_cmd |= (cmd << S_OPCODE_SHFT); + s_cmd |= (params & S_PARAMS_MSK); + writel(s_cmd, base + SE_GENI_S_CMD0); +} + +static void qcom_geni_serial_start_tx(u64 base) +{ + u32 irq_en; + u32 status; + + status = readl(base + SE_GENI_STATUS); + if (status & M_GENI_CMD_ACTIVE) + return; + + if (!qcom_geni_serial_tx_empty(base)) + return; + + irq_en = readl(base + SE_GENI_M_IRQ_EN); + irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN; + + writel(DEF_TX_WM, base + SE_GENI_TX_WATERMARK_REG); + writel(irq_en, base + SE_GENI_M_IRQ_EN); +} + +static void qcom_geni_serial_start_rx(struct udevice *dev) +{ + u32 irq_en; + u32 status; + struct msm_serial_data *priv = dev_get_priv(dev); + + status = readl(priv->base + SE_GENI_STATUS); + + geni_se_setup_s_cmd(priv->base, UART_START_READ, 0); + + irq_en = readl(priv->base + SE_GENI_S_IRQ_EN); + irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; + writel(irq_en, priv->base + SE_GENI_S_IRQ_EN); + + irq_en = readl(priv->base + SE_GENI_M_IRQ_EN); + irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; + writel(irq_en, priv->base + SE_GENI_M_IRQ_EN); +} + +static void msm_geni_serial_setup_rx(struct udevice *dev) +{ + u32 irq_clear = S_CMD_DONE_EN; + u32 geni_s_irq_en; + u32 geni_m_irq_en; + u32 cfg0; + u32 cfg1; + struct msm_serial_data *priv = dev_get_priv(dev); + + irq_clear |= S_CMD_ABORT_EN; + + writel(S_GENI_CMD_ABORT, priv->base + SE_GENI_S_CMD_CTRL_REG); + qcom_geni_serial_poll_bit(dev, SE_GENI_S_CMD_CTRL_REG, S_GENI_CMD_ABORT, + false); + writel(irq_clear, priv->base + SE_GENI_S_IRQ_CLEAR); + writel(FORCE_DEFAULT, priv->base + GENI_FORCE_DEFAULT_REG); + + cfg0 = 0xf; + cfg1 = 0x0; + writel(cfg0, priv->base + SE_GENI_RX_PACKING_CFG0); + writel(cfg1, priv->base + SE_GENI_RX_PACKING_CFG1); + + geni_se_setup_s_cmd(priv->base, UART_START_READ, 0); + + geni_s_irq_en = readl(priv->base + SE_GENI_S_IRQ_EN); + geni_m_irq_en = readl(priv->base + SE_GENI_M_IRQ_EN); + + geni_s_irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; + geni_m_irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; + + writel(geni_s_irq_en, priv->base + SE_GENI_S_IRQ_EN); + writel(geni_m_irq_en, priv->base + SE_GENI_M_IRQ_EN); +} + +static int msm_serial_putc(struct udevice *dev, const char ch) +{ + struct msm_serial_data *priv = dev_get_priv(dev); + + writel(DEF_TX_WM, priv->base + SE_GENI_TX_WATERMARK_REG); + qcom_geni_serial_setup_tx(priv->base, 1); + + qcom_geni_serial_poll_bit(dev, SE_GENI_M_IRQ_STATUS, + M_TX_FIFO_WATERMARK_EN, true); + + writel(ch, priv->base + SE_GENI_TX_FIFOn); + writel(M_TX_FIFO_WATERMARK_EN, priv->base + SE_GENI_M_IRQ_CLEAR); + + qcom_geni_serial_poll_tx_done(dev); + + return 0; +} + +static int msm_serial_getc(struct udevice *dev) +{ + struct msm_serial_data *priv = dev_get_priv(dev); + u32 rx_fifo; + u32 m_irq_status; + u32 s_irq_status; + + writel(1 << S_OPCODE_SHIFT, priv->base + SE_GENI_S_CMD0); + + qcom_geni_serial_poll_bit(dev, SE_GENI_M_IRQ_STATUS, M_SEC_IRQ_EN, + true); + + m_irq_status = readl(priv->base + SE_GENI_M_IRQ_STATUS); + s_irq_status = readl(priv->base + SE_GENI_S_IRQ_STATUS); + writel(m_irq_status, priv->base + SE_GENI_M_IRQ_CLEAR); + writel(s_irq_status, priv->base + SE_GENI_S_IRQ_CLEAR); + qcom_geni_serial_poll_bit(dev, SE_GENI_RX_FIFO_STATUS, RX_FIFO_WC_MSK, + true); + + if (!readl(priv->base + SE_GENI_RX_FIFO_STATUS)) + return 0; + + rx_fifo = readl(priv->base + SE_GENI_RX_FIFOn); + return rx_fifo & 0xff; +} + +static int msm_serial_pending(struct udevice *dev, bool input) +{ + struct msm_serial_data *priv = dev_get_priv(dev); + + if (input) + return readl(priv->base + SE_GENI_RX_FIFO_STATUS) & + RX_FIFO_WC_MSK; + else + return readl(priv->base + SE_GENI_TX_FIFO_STATUS) & + TX_FIFO_WC_MSK; + + return 0; +} + +static const struct dm_serial_ops msm_serial_ops = { + .putc = msm_serial_putc, + .pending = msm_serial_pending, + .getc = msm_serial_getc, + .setbrg = msm_serial_setbrg, +}; + +static inline void geni_serial_init(phys_addr_t base_address) +{ + u32 tx_trans_cfg; + u32 tx_parity_cfg = 0; /* Disable Tx Parity */ + u32 rx_trans_cfg = 0; + u32 rx_parity_cfg = 0; /* Disable Rx Parity */ + u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ + u32 bits_per_char; + + /* + * Ignore Flow control. + * n = 8. + */ + tx_trans_cfg = UART_CTS_MASK; + bits_per_char = BITS_PER_BYTE; + + u32 cfg0 = 0xf; + + u32 cfg1 = 0x0; + + /* + * Make an unconditional cancel on the main sequencer to reset + * it else we could end up in data loss scenarios. + */ + writel(cfg0, base_address + SE_GENI_TX_PACKING_CFG0); + writel(cfg1, base_address + SE_GENI_TX_PACKING_CFG1); + writel(cfg0, base_address + SE_GENI_RX_PACKING_CFG0); + writel(cfg1, base_address + SE_GENI_RX_PACKING_CFG1); + + writel(tx_trans_cfg, base_address + SE_UART_TX_TRANS_CFG); + writel(tx_parity_cfg, base_address + SE_UART_TX_PARITY_CFG); + writel(rx_trans_cfg, base_address + SE_UART_RX_TRANS_CFG); + writel(rx_parity_cfg, base_address + SE_UART_RX_PARITY_CFG); + writel(bits_per_char, base_address + SE_UART_TX_WORD_LEN); + writel(bits_per_char, base_address + SE_UART_RX_WORD_LEN); + writel(stop_bit_len, base_address + SE_UART_TX_STOP_BIT_LEN); +} + +static int msm_serial_probe(struct udevice *dev) +{ + struct msm_serial_data *priv = dev_get_priv(dev); + + /* No need to reinitialize the UART after relocation */ + if (gd->flags & GD_FLG_RELOC) + return 0; + + geni_serial_init(priv->base); + msm_geni_serial_setup_rx(dev); + qcom_geni_serial_start_rx(dev); + qcom_geni_serial_start_tx(priv->base); + + pinctrl_select_state(dev, "uart"); + + return 0; +} + +static int msm_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct msm_serial_data *priv = dev_get_priv(dev); + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + return 0; +} + +static const struct udevice_id msm_serial_ids[] = { + {.compatible = "qcom,msm-geni-uart"}, {}}; + +U_BOOT_DRIVER(serial_msm_geni) = { + .name = "serial_msm_geni", + .id = UCLASS_SERIAL, + .of_match = msm_serial_ids, + .of_to_plat = msm_serial_ofdata_to_platdata, + .priv_auto = sizeof(struct msm_serial_data), + .probe = msm_serial_probe, + .ops = &msm_serial_ops, +}; + +#ifdef CONFIG_DEBUG_UART_MSM_GENI + +static struct msm_serial_data init_serial_data = { + .base = CONFIG_DEBUG_UART_BASE +}; + +/* Serial dumb device, to reuse driver code */ +static struct udevice init_dev = { + .priv_ = &init_serial_data, +}; + +#include <debug_uart.h> + +static inline void _debug_uart_init(void) +{ + phys_addr_t base = CONFIG_DEBUG_UART_BASE; + + geni_serial_init(base); + geni_serial_baud(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); + qcom_geni_serial_start_tx(base); +} + +static inline void _debug_uart_putc(int ch) +{ + phys_addr_t base = CONFIG_DEBUG_UART_BASE; + + writel(DEF_TX_WM, base + SE_GENI_TX_WATERMARK_REG); + qcom_geni_serial_setup_tx(base, 1); + qcom_geni_serial_poll_bit(&init_dev, SE_GENI_M_IRQ_STATUS, + M_TX_FIFO_WATERMARK_EN, true); + + writel(ch, base + SE_GENI_TX_FIFOn); + writel(M_TX_FIFO_WATERMARK_EN, base + SE_GENI_M_IRQ_CLEAR); + qcom_geni_serial_poll_tx_done(&init_dev); +} + +DEBUG_UART_FUNCS + +#endif

Signed-off-by: Dzmitry Sankouski dsankouski@gmail.com Cc: Ramon Fried rfried.dev@gmail.com Cc: Tom Rini trini@konsulko.com Cc: Stephan Gerhold stephan@gerhold.net --- Changes for v2: - Add __section(".data") for pin_name variable.

arch/arm/mach-snapdragon/pinctrl-sdm845.c | 44 +++++++++++++++++++ arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 1 + arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 1 + drivers/gpio/msm_gpio.c | 1 + drivers/gpio/pm8916_gpio.c | 8 ++-- 5 files changed, 52 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-snapdragon/pinctrl-sdm845.c

diff --git a/arch/arm/mach-snapdragon/pinctrl-sdm845.c b/arch/arm/mach-snapdragon/pinctrl-sdm845.c new file mode 100644 index 0000000000..40f2f012fa --- /dev/null +++ b/arch/arm/mach-snapdragon/pinctrl-sdm845.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm SDM845 pinctrl + * + * (C) Copyright 2021 Dzmitry Sankouski dsankouski@gmail.com + * + */ + +#include "pinctrl-snapdragon.h" +#include <common.h> + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { + {"qup9", 1}, + {"gpio", 0}, +}; + +static const char *sdm845_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *sdm845_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector); + return pin_name; +} + +static unsigned int sdm845_get_function_mux(unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +struct msm_pinctrl_data sdm845_data = { + .pin_count = 150, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = sdm845_get_function_name, + .get_function_mux = sdm845_get_function_mux, + .get_pin_name = sdm845_get_pin_name, +}; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c index e6b87c3573..c0ed943036 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -116,6 +116,7 @@ static struct pinctrl_ops msm_pinctrl_ops = { static const struct udevice_id msm_pinctrl_ids[] = { { .compatible = "qcom,tlmm-apq8016", .data = (ulong)&apq8016_data }, { .compatible = "qcom,tlmm-apq8096", .data = (ulong)&apq8096_data }, + { .compatible = "qcom,tlmm-sdm845", .data = (ulong)&sdm845_data }, { } };

diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h index 61d466f4d8..ea524312a0 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h @@ -27,5 +27,6 @@ struct pinctrl_function {

extern struct msm_pinctrl_data apq8016_data; extern struct msm_pinctrl_data apq8096_data; +extern struct msm_pinctrl_data sdm845_data;

#endif diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index e1ff84c1c0..a3c3cd7824 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -120,6 +120,7 @@ static const struct udevice_id msm_gpio_ids[] = { { .compatible = "qcom,msm8916-pinctrl" }, { .compatible = "qcom,apq8016-pinctrl" }, { .compatible = "qcom,ipq4019-pinctrl" }, + { .compatible = "qcom,sdm845-pinctrl" }, { } };

diff --git a/drivers/gpio/pm8916_gpio.c b/drivers/gpio/pm8916_gpio.c index 40b0f2578b..7ad95784a8 100644 --- a/drivers/gpio/pm8916_gpio.c +++ b/drivers/gpio/pm8916_gpio.c @@ -202,6 +202,7 @@ static int pm8916_gpio_of_to_plat(struct udevice *dev) static const struct udevice_id pm8916_gpio_ids[] = { { .compatible = "qcom,pm8916-gpio" }, { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ + { .compatible = "qcom,pm8998-gpio" }, { } };

@@ -266,7 +267,7 @@ static int pm8941_pwrkey_probe(struct udevice *dev) return log_msg_ret("bad type", -ENXIO);

reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE); - if (reg != 0x1) + if ((reg & 0x5) == 0) return log_msg_ret("bad subtype", -ENXIO);

return 0; @@ -287,11 +288,12 @@ static int pm8941_pwrkey_of_to_plat(struct udevice *dev) static const struct udevice_id pm8941_pwrkey_ids[] = { { .compatible = "qcom,pm8916-pwrkey" }, { .compatible = "qcom,pm8994-pwrkey" }, + { .compatible = "qcom,pm8998-pwrkey" }, { } };

-U_BOOT_DRIVER(pwrkey_pm8941) = { - .name = "pwrkey_pm8916", +U_BOOT_DRIVER(pwrkey_pm89xx) = { + .name = "pwrkey_pm89xx", .id = UCLASS_GPIO, .of_match = pm8941_pwrkey_ids, .of_to_plat = pm8941_pwrkey_of_to_plat,

Hi-end qualcomm chip, introduced in late 2017. Mostly used in flagship phones and tablets of 2018. Features: - arm64 arch - total of 8 Kryo 385 Gold / Silver cores - Hexagon 685 DSP - Adreno 630 GPU

Tested only as second-stage bootloader.

Signed-off-by: Dzmitry Sankouski dsankouski@gmail.com Cc: Ramon Fried rfried.dev@gmail.com Cc: Tom Rini trini@konsulko.com Cc: Stephan Gerhold stephan@gerhold.net --- Changes for v2: - refactor sdm845.dtsi.

arch/arm/dts/sdm845.dtsi | 116 ++++++++++++++++++ arch/arm/mach-snapdragon/Kconfig | 4 + arch/arm/mach-snapdragon/Makefile | 4 + .../include/mach/sysmap-sdm845.h | 42 +++++++ arch/arm/mach-snapdragon/init_sdm845.c | 82 +++++++++++++ arch/arm/mach-snapdragon/sysmap-sdm845.c | 31 +++++ include/configs/sdm845.h | 33 +++++ 7 files changed, 312 insertions(+) create mode 100644 arch/arm/dts/sdm845.dtsi create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h create mode 100644 arch/arm/mach-snapdragon/init_sdm845.c create mode 100644 arch/arm/mach-snapdragon/sysmap-sdm845.c create mode 100644 include/configs/sdm845.h

diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi new file mode 100644 index 0000000000..1185b71216 --- /dev/null +++ b/arch/arm/dts/sdm845.dtsi @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm SDM845 chip device tree source + * + * (C) Copyright 2021 Dzmitry Sankouski dsankouski@gmail.com + * + */ + +/dts-v1/; + +#include "skeleton64.dtsi" + +/ { + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + u-boot,dm-pre-reloc; + compatible = "qcom,gcc-sdm845"; + reg = <0x100000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + gpio_north: gpio_north@3900000 { + u-boot,dm-pre-reloc; + #gpio-cells = <2>; + compatible = "qcom,sdm845-pinctrl"; + reg = <0x3900000 0x400000>; + gpio-count = <150>; + gpio-controller; + gpio-ranges = <&gpio_north 0 0 150>; + gpio-bank-name = "soc_north."; + }; + + tlmm_north: pinctrl_north@3900000 { + u-boot,dm-pre-reloc; + compatible = "qcom,tlmm-sdm845"; + reg = <0x3900000 0x400000>; + gpio-count = <150>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm_north 0 0 150>; + + /* DEBUG UART */ + qup_uart9: qup-uart9-default { + pinmux { + pins = "GPIO_4", "GPIO_5"; + function = "qup9"; + }; + }; + }; + + debug_uart: serial@a84000 { + compatible = "qcom,msm-geni-uart"; + reg = <0xa84000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk"; + clocks = <&gcc 0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart9>; + qcom,wrapper-core = <0x8a>; + status = "disabled"; + }; + + spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1100>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>; + reg-names = "cnfg", "core", "obsrvr"; + #address-cells = <0x1>; + #size-cells = <0x1>; + + qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + pmic0: pm8998@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 0x1>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + pm8998_pon: pm8998_pon@800 { + compatible = "qcom,pm8998-pwrkey"; + reg = <0x800 0x100>; + #gpio-cells = <2>; + gpio-controller; + gpio-bank-name = "pm8998_key."; + }; + + pm8998_gpios: pm8998_gpios@c000 { + compatible = "qcom,pm8998-gpio"; + reg = <0xc000 0x1a00>; + gpio-controller; + gpio-count = <21>; + #gpio-cells = <2>; + gpio-bank-name = "pm8998."; + }; + }; + + pmic1: pm8998@1 { + compatible = "qcom,spmi-pmic"; + reg = <0x1 0x0>; + #address-cells = <0x2>; + #size-cells = <0x0>; + }; + }; + }; +}; diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index 0ec74fa5d3..1a6a608967 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -9,6 +9,10 @@ config SYS_MALLOC_F_LEN config SPL_SYS_MALLOC_F_LEN default 0x2000

+config SDM845 + bool "Qualcomm Snapdragon 845 SoC" + default n + choice prompt "Snapdragon board select"

diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 709919fce4..962855eb8c 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -2,6 +2,9 @@ # # (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com

+obj-$(CONFIG_SDM845) += clock-sdm845.o +obj-$(CONFIG_SDM845) += sysmap-sdm845.o +obj-$(CONFIG_SDM845) += init_sdm845.o obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o @@ -12,3 +15,4 @@ obj-y += dram.o obj-y += pinctrl-snapdragon.o obj-y += pinctrl-apq8016.o obj-y += pinctrl-apq8096.o +obj-$(CONFIG_SDM845) += pinctrl-sdm845.o diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h b/arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h new file mode 100644 index 0000000000..7165985bcd --- /dev/null +++ b/arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Qualcomm SDM845 sysmap + * + * (C) Copyright 2021 Dzmitry Sankouski dsankouski@gmail.com + */ +#ifndef _MACH_SYSMAP_SDM845_H +#define _MACH_SYSMAP_SDM845_H + +#define TLMM_BASE_ADDR (0x1010000) + +/* Strength (sdc1) */ +#define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000) + +/* Clocks: (from CLK_CTL_BASE) */ +#define GPLL0_STATUS (0x0000) +#define APCS_GPLL_ENA_VOTE (0x52000) +#define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004) + +#define SDCC2_BCR (0x14000) /* block reset */ +#define SDCC2_APPS_CBCR (0x14004) /* branch control */ +#define SDCC2_AHB_CBCR (0x14008) +#define SDCC2_CMD_RCGR (0x1400c) +#define SDCC2_CFG_RCGR (0x14010) +#define SDCC2_M (0x14014) +#define SDCC2_N (0x14018) +#define SDCC2_D (0x1401C) + +#define RCG2_CFG_REG 0x4 +#define M_REG 0x8 +#define N_REG 0xc +#define D_REG 0x10 + +#define SE9_AHB_CBCR (0x25004) +#define SE9_UART_APPS_CBCR (0x29004) +#define SE9_UART_APPS_CMD_RCGR (0x18148) +#define SE9_UART_APPS_CFG_RCGR (0x1814C) +#define SE9_UART_APPS_M (0x18150) +#define SE9_UART_APPS_N (0x18154) +#define SE9_UART_APPS_D (0x18158) + +#endif diff --git a/arch/arm/mach-snapdragon/init_sdm845.c b/arch/arm/mach-snapdragon/init_sdm845.c new file mode 100644 index 0000000000..5f53c21947 --- /dev/null +++ b/arch/arm/mach-snapdragon/init_sdm845.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Common init part for boards based on SDM845 + * + * (C) Copyright 2021 Dzmitry Sankouski dsankouski@gmail.com + */ + +#include <init.h> +#include <env.h> +#include <common.h> +#include <asm/system.h> +#include <asm/gpio.h> +#include <dm.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +void reset_cpu(void) +{ + psci_system_reset(); +} + +__weak int board_init(void) +{ + return 0; +} + +/* Check for vol- and power buttons */ +__weak int misc_init_r(void) +{ + struct udevice *pon; + struct gpio_desc resin; + int node, ret; + + ret = uclass_get_device_by_name(UCLASS_GPIO, "pm8998_pon@800", &pon); + if (ret < 0) { + printf("Failed to find PMIC pon node. Check device tree\n"); + return 0; + } + + node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon), + "key_vol_down"); + if (node < 0) { + printf("Failed to find key_vol_down node. Check device tree\n"); + return 0; + } + if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0, + &resin, 0)) { + printf("Failed to request key_vol_down button.\n"); + return 0; + } + if (dm_gpio_get_value(&resin)) { + env_set("key_vol_down", "1"); + printf("Volume down button pressed\n"); + } else { + env_set("key_vol_down", "0"); + } + + node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon), + "key_power"); + if (node < 0) { + printf("Failed to find key_power node. Check device tree\n"); + return 0; + } + if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0, + &resin, 0)) { + printf("Failed to request key_power button.\n"); + return 0; + } + if (dm_gpio_get_value(&resin)) { + env_set("key_power", "1"); + printf("Power button pressed\n"); + } else { + env_set("key_power", "0"); + } + + return 0; +} diff --git a/arch/arm/mach-snapdragon/sysmap-sdm845.c b/arch/arm/mach-snapdragon/sysmap-sdm845.c new file mode 100644 index 0000000000..721ac41166 --- /dev/null +++ b/arch/arm/mach-snapdragon/sysmap-sdm845.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm SDM845 memory map + * + * (C) Copyright 2021 Dzmitry Sankouski dsankousk@gmail.com + */ + +#include <common.h> +#include <asm/armv8/mmu.h> + +static struct mm_region sdm845_mem_map[] = { + { + .virt = 0x0UL, /* Peripheral block */ + .phys = 0x0UL, /* Peripheral block */ + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x80000000UL, /* DDR */ + .phys = 0x80000000UL, /* DDR */ + .size = 0x200000000UL, /* 8GiB - maximum allowed memory */ + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = sdm845_mem_map; diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h new file mode 100644 index 0000000000..c77d0acac6 --- /dev/null +++ b/include/configs/sdm845.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for boards, based on Qualcomm SDM845 chip + * + * (C) Copyright 2021 Dzmitry Sankouski dsankouski@gmail.com + */ + +#ifndef __CONFIGS_SDM845_H +#define __CONFIGS_SDM845_H + +#include <linux/sizes.h> +#include <asm/arch/sysmap-sdm845.h> + +#define CONFIG_SYS_LOAD_ADDR 0x80000000 +#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 19000000 + +#define EXTRA_ENV_SETTINGS \ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80000000\0" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_MAXARGS 64 + +#endif