On 03/01/2019 13:26, Amit Singh Tomar wrote:

This adds common arch owl support that drives both s700 and s900, 64-bits SoCs from Actions Semiconductor.

Nice cleanup.

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

arch/arm/Kconfig | 2 -- arch/arm/mach-owl/Kconfig | 31 +++++++++++------------ arch/arm/mach-owl/Makefile | 2 +- arch/arm/mach-owl/soc.c | 56 ++++++++++++++++++++++++++++++++++++++++++ configs/bubblegum_96_defconfig | 3 +-- include/configs/bubblegum_96.h | 42 ------------------------------- include/configs/owl-common.h | 42 +++++++++++++++++++++++++++++++ include/configs/s700.h | 15 +++++++++++ include/configs/s900.h | 18 ++++++++++++++ 9 files changed, 147 insertions(+), 64 deletions(-) create mode 100644 arch/arm/mach-owl/soc.c delete mode 100644 include/configs/bubblegum_96.h create mode 100644 include/configs/owl-common.h create mode 100644 include/configs/s700.h create mode 100644 include/configs/s900.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b5952ad..b478096 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -760,7 +760,6 @@ config ARCH_MX5

config ARCH_OWL bool "Actions Semi OWL SoCs"

• select ARM64 select DM select DM_SERIAL select OF_CONTROL

@@ -1555,7 +1554,6 @@ source "board/spear/spear600/Kconfig" source "board/spear/x600/Kconfig" source "board/st/stv0991/Kconfig" source "board/tcl/sl50/Kconfig" -source "board/ucRobotics/bubblegum_96/Kconfig" source "board/birdland/bav335x/Kconfig" source "board/toradex/colibri_pxa270/Kconfig" source "board/vscom/baltos/Kconfig" diff --git a/arch/arm/mach-owl/Kconfig b/arch/arm/mach-owl/Kconfig index 199e772..3143782 100644 --- a/arch/arm/mach-owl/Kconfig +++ b/arch/arm/mach-owl/Kconfig @@ -1,27 +1,24 @@ if ARCH_OWL

-config SYS_SOC

• default "owl"

choice

•    prompt "Actions Semi OWL SoCs board select"
  

•    prompt "SemiActions SoC Variant"
  

Even after refactoring the company is still called Actions Semi ;-)

     optional

-config TARGET_BUBBLEGUM_96

• bool "96Boards Bubblegum-96"
• help

•  Support for 96Boards Bubblegum-96. This board complies with
  

•  96Board Consumer Edition Specification. Features:
  

•  - Actions Semi S900 SoC (4xCortex A53, Power VR G6230 GPU)
  

•  - 2GiB RAM
  

•  - 8GiB eMMC, uSD slot
  

•  - WiFi, Bluetooth and GPS module
  

•  - 2x Host, 1x Device USB port
  

•  - HDMI
  

•  - 20-pin low speed and 40-pin high speed expanders, 6 LED, 3 buttons
  

+config MACH_S700

•    bool "SemiActions S700"
  

•    select ARM64
  

It's probably a bit premature to introduce S700 here already. Just move that to a later patch.

+config MACH_S900

•    bool "SemiActions S900"
  

•    select ARM64
  
  

endchoice

-source "board/ucRobotics/bubblegum_96/Kconfig" +config SYS_CONFIG_NAME

•    default "s900" if MACH_S900
  

•    default "s700" if MACH_S700
  

Same here.

+config SYS_SOC

•    default "owl"
  
  

endif diff --git a/arch/arm/mach-owl/Makefile b/arch/arm/mach-owl/Makefile index 1b43dc2..2a76ee0 100644 --- a/arch/arm/mach-owl/Makefile +++ b/arch/arm/mach-owl/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+

-obj-y += sysmap-s900.o

That breaks Bubblegum compilation. Just keep it in for now and remove it in the next patch.

+obj-y += soc.o diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c new file mode 100644 index 0000000..a4c202d --- /dev/null +++ b/arch/arm/mach-owl/soc.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Bubblegum-96 Boards Support

That line should be changed to reflect the new generic nature of that file.

• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

+#include <linux/arm-smccc.h> +#include <linux/psci.h> +#include <common.h> +#include <asm/io.h> +#include <asm/mach-types.h> +#include <asm/psci.h>

+DECLARE_GLOBAL_DATA_PTR;

+/*

• • dram_init - sets uboots idea of sdram size
• */

+int dram_init(void) +{

• gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
• return 0;

+}

+/* This is called after dram_init() so use get_ram_size result */ +int dram_init_banksize(void) +{

• gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
• gd->bd->bi_dram[0].size = gd->ram_size;
• return 0;

+}

+static void show_psci_version(void) +{

• struct arm_smccc_res res;
• arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
• printf("PSCI: v%ld.%ld\n",

•       PSCI_VERSION_MAJOR(res.a0),
  

• PSCI_VERSION_MINOR(res.a0));
  

looks like a whitespace issue

+}

+int board_init(void) +{

• show_psci_version();
• return 0;

+}

+void reset_cpu(ulong addr) +{

• psci_system_reset();

+} diff --git a/configs/bubblegum_96_defconfig b/configs/bubblegum_96_defconfig index 4b00a17..6c31b1c 100644 --- a/configs/bubblegum_96_defconfig +++ b/configs/bubblegum_96_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARM_SMCCC=y CONFIG_ARCH_OWL=y CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_TARGET_BUBBLEGUM_96=y +CONFIG_MACH_S900=y CONFIG_IDENT_STRING="\nBubblegum-96" CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=1 @@ -19,5 +19,4 @@ CONFIG_CMD_TIMER=y CONFIG_DEFAULT_DEVICE_TREE="bubblegum_96" CONFIG_CLK=y CONFIG_CLK_OWL=y -CONFIG_CLK_S900=y CONFIG_OWL_SERIAL=y diff --git a/include/configs/bubblegum_96.h b/include/configs/bubblegum_96.h deleted file mode 100644 index e1dc37b..0000000 --- a/include/configs/bubblegum_96.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*

• • Board configuration file for Bubblegum-96
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

-#ifndef _BUBBLEGUM_96_H_ -#define _BUGGLEGUM_96_H_

-/* SDRAM Definitions */ -#define CONFIG_SYS_SDRAM_BASE 0x0 -#define CONFIG_SYS_SDRAM_SIZE 0x80000000

-/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY (24000000) /* 24MHz */

-#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)

-/* Some commands use this as the default load address */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7ffc0)

-/*

• • This is the initial SP which is used only briefly for relocating the u-boot
• • image to the top of SDRAM. After relocation u-boot moves the stack to the
• • proper place.
• */

-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7ff00)

-/* UART Definitions */ -#define CONFIG_BAUDRATE 115200

-#define CONFIG_ENV_SIZE 0x2000

-/* Console configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE

-#endif diff --git a/include/configs/owl-common.h b/include/configs/owl-common.h new file mode 100644 index 0000000..a980681 --- /dev/null +++ b/include/configs/owl-common.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Board configuration file for Bubblegum-96
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

+#ifndef _OWL_COMMON_CONFIG_H_ +#define _OWL_COMMON_CONFIG_H_

+/* SDRAM Definitions */ +#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CONFIG_SYS_SDRAM_SIZE 0x80000000

+/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (24000000) /* 24MHz */

+#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)

+/* Some commands use this as the default load address */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7ffc0)

+/*

• • This is the initial SP which is used only briefly for relocating the u-boot
• • image to the top of SDRAM. After relocation u-boot moves the stack to the
• • proper place.
• */

+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7ff00)

+/* UART Definitions */ +#define CONFIG_BAUDRATE 115200

+#define CONFIG_ENV_SIZE 0x2000

+/* Console configuration */ +#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE

+#endif diff --git a/include/configs/s700.h b/include/configs/s700.h new file mode 100644 index 0000000..84f9174 --- /dev/null +++ b/include/configs/s700.h

Same comment about S700 support. Just leave it out of this patch.

Cheers, Andre.

@@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Board configuration file for Action semi s700
• */

+#ifndef _CONFIG_S700_H_ +#define _CONFIG_S700_H_

+/*

• • Include common owl configuration where most the settings are
• */

+#include <configs/owl-common.h>

+#endif diff --git a/include/configs/s900.h b/include/configs/s900.h new file mode 100644 index 0000000..fe5cfb5 --- /dev/null +++ b/include/configs/s900.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Board configuration file for Bubblegum-96
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

+#ifndef _CONFIG_S900_H_ +#define _CONFIG_S900_H_

+/*

• • Include common owl configuration where most the settings are
• */

+#include <configs/owl-common.h>

+#endif

On Thu, Jan 03, 2019 at 06:56:17PM +0530, Amit Singh Tomar wrote:

This adds memory regions needed to setup MMU for actions S900 and S700 SoCs.

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

arch/arm/mach-owl/Makefile | 1 + arch/arm/mach-owl/sysmap-owl.c | 32 ++++++++++++++++++++++++++++++++ arch/arm/mach-owl/sysmap-s900.c | 32 -------------------------------- 3 files changed, 33 insertions(+), 32 deletions(-) create mode 100644 arch/arm/mach-owl/sysmap-owl.c delete mode 100644 arch/arm/mach-owl/sysmap-s900.c

diff --git a/arch/arm/mach-owl/Makefile b/arch/arm/mach-owl/Makefile index 2a76ee0..417c859 100644 --- a/arch/arm/mach-owl/Makefile +++ b/arch/arm/mach-owl/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+

obj-y += soc.o +obj-y += sysmap-owl.o diff --git a/arch/arm/mach-owl/sysmap-owl.c b/arch/arm/mach-owl/sysmap-owl.c new file mode 100644 index 0000000..9dc4a05 --- /dev/null +++ b/arch/arm/mach-owl/sysmap-owl.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Actions Semi S900/S700 Memory map
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

+#include <common.h>

You might want to wrap the below contents with CONFIG_ARM64 since S500 has different memory map and it is an ARMv7 SoC.

Thanks, Mani

+#include <asm/armv8/mmu.h>

+static struct mm_region owl_mem_map[] = {

• {

• .virt = 0x0UL, /* DDR */
  

• .phys = 0x0UL, /* DDR */
  

• .size = 0x80000000UL,
  

• .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  

• 	 PTE_BLOCK_INNER_SHARE
  

• }, {

• .virt = 0xE0000000UL, /* Peripheral block */
  

• .phys = 0xE0000000UL, /* Peripheral block */
  

• .size = 0x08000000UL,
  

• .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  

• 	 PTE_BLOCK_NON_SHARE |
  

• 	 PTE_BLOCK_PXN | PTE_BLOCK_UXN
  

• }, {

• /* List terminator */
  

• 0,
  

• }

+};

+struct mm_region *mem_map = owl_mem_map; diff --git a/arch/arm/mach-owl/sysmap-s900.c b/arch/arm/mach-owl/sysmap-s900.c deleted file mode 100644 index f78b639..0000000 --- a/arch/arm/mach-owl/sysmap-s900.c +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*

• • Actions Semi S900 Memory map
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

-#include <common.h> -#include <asm/armv8/mmu.h>

-static struct mm_region s900_mem_map[] = {

• {

• .virt = 0x0UL, /* DDR */
  

• .phys = 0x0UL, /* DDR */
  

• .size = 0x80000000UL,
  

• .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  

• 	 PTE_BLOCK_INNER_SHARE
  

• }, {

• .virt = 0xE0000000UL, /* Peripheral block */
  

• .phys = 0xE0000000UL, /* Peripheral block */
  

• .size = 0x08000000UL,
  

• .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  

• 	 PTE_BLOCK_NON_SHARE |
  

• 	 PTE_BLOCK_PXN | PTE_BLOCK_UXN
  

• }, {

• /* List terminator */
  

• 0,
  

• }

-};

-struct mm_region *mem_map = s900_mem_map;

2.7.4

On Sun, Jan 06, 2019 at 01:16:43AM +0000, André Przywara wrote:

On 05/01/2019 18:27, Manivannan Sadhasivam wrote:

Hi,

...

On Thu, Jan 03, 2019 at 06:56:17PM +0530, Amit Singh Tomar wrote:

...

This adds memory regions needed to setup MMU for actions S900 and S700 SoCs.

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

arch/arm/mach-owl/Makefile | 1 + arch/arm/mach-owl/sysmap-owl.c | 32 ++++++++++++++++++++++++++++++++ arch/arm/mach-owl/sysmap-s900.c | 32 -------------------------------- 3 files changed, 33 insertions(+), 32 deletions(-) create mode 100644 arch/arm/mach-owl/sysmap-owl.c delete mode 100644 arch/arm/mach-owl/sysmap-s900.c

diff --git a/arch/arm/mach-owl/Makefile b/arch/arm/mach-owl/Makefile index 2a76ee0..417c859 100644 --- a/arch/arm/mach-owl/Makefile +++ b/arch/arm/mach-owl/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+

obj-y += soc.o +obj-y += sysmap-owl.o diff --git a/arch/arm/mach-owl/sysmap-owl.c b/arch/arm/mach-owl/sysmap-owl.c new file mode 100644 index 0000000..9dc4a05 --- /dev/null +++ b/arch/arm/mach-owl/sysmap-owl.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Actions Semi S900/S700 Memory map
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

+#include <common.h>

You might want to wrap the below contents with CONFIG_ARM64 since S500 has different memory map and it is an ARMv7 SoC.

If I am not mistaken, we need that struct mm_region only for v8 parts. So that would be better handled in the Makefile instead?

obj-$(CONFIG_ARM64) += sysmap-owl.o

Yes, this makes sense!

Thanks, Mani

Cheers, Andre.

...

...

+#include <asm/armv8/mmu.h>

+static struct mm_region owl_mem_map[] = {

• {

• .virt = 0x0UL, /* DDR */
  

• .phys = 0x0UL, /* DDR */
  

• .size = 0x80000000UL,
  

• .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  

• 	 PTE_BLOCK_INNER_SHARE
  

• }, {

• .virt = 0xE0000000UL, /* Peripheral block */
  

• .phys = 0xE0000000UL, /* Peripheral block */
  

• .size = 0x08000000UL,
  

• .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  

• 	 PTE_BLOCK_NON_SHARE |
  

• 	 PTE_BLOCK_PXN | PTE_BLOCK_UXN
  

• }, {

• /* List terminator */
  

• 0,
  

• }

+};

+struct mm_region *mem_map = owl_mem_map; diff --git a/arch/arm/mach-owl/sysmap-s900.c b/arch/arm/mach-owl/sysmap-s900.c deleted file mode 100644 index f78b639..0000000 --- a/arch/arm/mach-owl/sysmap-s900.c +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*

• • Actions Semi S900 Memory map
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

-#include <common.h> -#include <asm/armv8/mmu.h>

-static struct mm_region s900_mem_map[] = {

• {

• .virt = 0x0UL, /* DDR */
  

• .phys = 0x0UL, /* DDR */
  

• .size = 0x80000000UL,
  

• .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  

• 	 PTE_BLOCK_INNER_SHARE
  

• }, {

• .virt = 0xE0000000UL, /* Peripheral block */
  

• .phys = 0xE0000000UL, /* Peripheral block */
  

• .size = 0x08000000UL,
  

• .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  

• 	 PTE_BLOCK_NON_SHARE |
  

• 	 PTE_BLOCK_PXN | PTE_BLOCK_UXN
  

• }, {

• /* List terminator */
  

• 0,
  

• }

-};

-struct mm_region *mem_map = s900_mem_map;

2.7.4

On Thu, Jan 03, 2019 at 06:56:18PM +0530, Amit Singh Tomar wrote:

CMU block on most of the actions SoC seems to be identical(S900, S700 and S500)?

No :-) S500 is slightly different from S900/S700 but I will tackle this later.

This patch converts S900 clock driver to something common that can be used for other SoCs, for instance S700(most of clk registres are same).

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

arch/arm/include/asm/arch-owl/clk_owl.h | 61 +++++++++++++ arch/arm/include/asm/arch-owl/clk_s900.h | 57 ------------- arch/arm/include/asm/arch-owl/regs_s700.h | 56 ++++++++++++ drivers/clk/owl/Kconfig | 8 +- drivers/clk/owl/Makefile | 2 +- drivers/clk/owl/clk_owl.c | 132 ++++++++++++++++++++++++++++ drivers/clk/owl/clk_s900.c | 137 ------------------------------ 7 files changed, 252 insertions(+), 201 deletions(-) create mode 100644 arch/arm/include/asm/arch-owl/clk_owl.h delete mode 100644 arch/arm/include/asm/arch-owl/clk_s900.h create mode 100644 arch/arm/include/asm/arch-owl/regs_s700.h create mode 100644 drivers/clk/owl/clk_owl.c delete mode 100644 drivers/clk/owl/clk_s900.c

diff --git a/arch/arm/include/asm/arch-owl/clk_owl.h b/arch/arm/include/asm/arch-owl/clk_owl.h new file mode 100644 index 0000000..8ff7537 --- /dev/null +++ b/arch/arm/include/asm/arch-owl/clk_owl.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Actions Semi S900 Clock Definitions
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

+#ifndef _OWL_CLK_H_ +#define _OWL_CLK_H_

+#include <clk-uclass.h>

+struct owl_clk_priv {

• phys_addr_t base;

+};

+/* BUSCLK register definitions */ +#define CMU_PDBGDIV_8 7 +#define CMU_PDBGDIV_SHIFT 26 +#define CMU_PDBGDIV_DIV (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT) +#define CMU_PERDIV_8 7 +#define CMU_PERDIV_SHIFT 20 +#define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT) +#define CMU_NOCDIV_2 1 +#define CMU_NOCDIV_SHIFT 19 +#define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT) +#define CMU_DMMCLK_SRC_APLL 2 +#define CMU_DMMCLK_SRC_SHIFT 10 +#define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT) +#define CMU_APBCLK_DIV BIT(8) +#define CMU_NOCCLK_SRC BIT(7) +#define CMU_AHBCLK_DIV BIT(4) +#define CMU_CORECLK_MASK 3 +#define CMU_CORECLK_CPLL BIT(1) +#define CMU_CORECLK_HOSC BIT(0)

+/* COREPLL register definitions */ +#define CMU_COREPLL_EN BIT(9) +#define CMU_COREPLL_HOSC_EN BIT(8) +#define CMU_COREPLL_OUT (1104 / 24)

+/* DEVPLL register definitions */ +#define CMU_DEVPLL_CLK BIT(12) +#define CMU_DEVPLL_EN BIT(8) +#define CMU_DEVPLL_OUT (660 / 6)

+/* UARTCLK register definitions */ +#define CMU_UARTCLK_SRC_DEVPLL BIT(16)

+/* DEVCLKEN1 register definitions */ +#if defined(CONFIG_MACH_S900) +#define CMU_DEVCLKEN1_UART5 BIT(21) +#elif defined(CONFIG_MACH_S700) +#define CMU_DEVCLKEN1_UART3 BIT(11) +#endif

+#define PLL_STABILITY_WAIT_US 50

+#endif diff --git a/arch/arm/include/asm/arch-owl/clk_s900.h b/arch/arm/include/asm/arch-owl/clk_s900.h deleted file mode 100644 index 88e88f7..0000000 --- a/arch/arm/include/asm/arch-owl/clk_s900.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*

• • Actions Semi S900 Clock Definitions
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

-#ifndef _OWL_CLK_S900_H_ -#define _OWL_CLK_S900_H_

-#include <clk-uclass.h>

-struct owl_clk_priv {

• phys_addr_t base;

-};

-/* BUSCLK register definitions */ -#define CMU_PDBGDIV_8 7 -#define CMU_PDBGDIV_SHIFT 26 -#define CMU_PDBGDIV_DIV (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT) -#define CMU_PERDIV_8 7 -#define CMU_PERDIV_SHIFT 20 -#define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT) -#define CMU_NOCDIV_2 1 -#define CMU_NOCDIV_SHIFT 19 -#define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT) -#define CMU_DMMCLK_SRC_APLL 2 -#define CMU_DMMCLK_SRC_SHIFT 10 -#define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT) -#define CMU_APBCLK_DIV BIT(8) -#define CMU_NOCCLK_SRC BIT(7) -#define CMU_AHBCLK_DIV BIT(4) -#define CMU_CORECLK_MASK 3 -#define CMU_CORECLK_CPLL BIT(1) -#define CMU_CORECLK_HOSC BIT(0)

-/* COREPLL register definitions */ -#define CMU_COREPLL_EN BIT(9) -#define CMU_COREPLL_HOSC_EN BIT(8) -#define CMU_COREPLL_OUT (1104 / 24)

-/* DEVPLL register definitions */ -#define CMU_DEVPLL_CLK BIT(12) -#define CMU_DEVPLL_EN BIT(8) -#define CMU_DEVPLL_OUT (660 / 6)

-/* UARTCLK register definitions */ -#define CMU_UARTCLK_SRC_DEVPLL BIT(16)

-/* DEVCLKEN1 register definitions */ -#define CMU_DEVCLKEN1_UART5 BIT(21)

-#define PLL_STABILITY_WAIT_US 50

-#endif diff --git a/arch/arm/include/asm/arch-owl/regs_s700.h b/arch/arm/include/asm/arch-owl/regs_s700.h new file mode 100644 index 0000000..a0bd737 --- /dev/null +++ b/arch/arm/include/asm/arch-owl/regs_s700.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Actions Semi S700 Register Definitions
• */

+#ifndef _OWL_REGS_S700_H_ +#define _OWL_REGS_S700_H_

+#define CMU_COREPLL (0x0000) +#define CMU_DEVPLL (0x0004) +#define CMU_DDRPLL (0x0008) +#define CMU_NANDPLL (0x000C) +#define CMU_DISPLAYPLL (0x0010) +#define CMU_AUDIOPLL (0x0014) +#define CMU_TVOUTPLL (0x0018) +#define CMU_BUSCLK (0x001C) +#define CMU_SENSORCLK (0x0020) +#define CMU_LCDCLK (0x0024) +#define CMU_DSIPLLCLK (0x0028) +#define CMU_CSICLK (0x002C) +#define CMU_DECLK (0x0030) +#define CMU_SICLK (0x0034) +#define CMU_BUSCLK1 (0x0038) +#define CMU_HDECLK (0x003C) +#define CMU_VDECLK (0x0040) +#define CMU_VCECLK (0x0044) +#define CMU_NANDCCLK (0x004C) +#define CMU_SD0CLK (0x0050) +#define CMU_SD1CLK (0x0054) +#define CMU_SD2CLK (0x0058) +#define CMU_UART0CLK (0x005C) +#define CMU_UART1CLK (0x0060) +#define CMU_UART2CLK (0x0064) +#define CMU_UART3CLK (0x0068) +#define CMU_UART4CLK (0x006C) +#define CMU_UART5CLK (0x0070) +#define CMU_UART6CLK (0x0074) +#define CMU_PWM0CLK (0x0078) +#define CMU_PWM1CLK (0x007C) +#define CMU_PWM2CLK (0x0080) +#define CMU_PWM3CLK (0x0084) +#define CMU_PWM4CLK (0x0088) +#define CMU_PWM5CLK (0x008C) +#define CMU_GPU3DCLK (0x0090) +#define CMU_CORECTL (0x009C) +#define CMU_DEVCLKEN0 (0x00A0) +#define CMU_DEVCLKEN1 (0x00A4) +#define CMU_DEVRST0 (0x00A8) +#define CMU_DEVRST1 (0x00AC) +#define CMU_USBPLL (0x00B0) +#define CMU_ETHERNETPLL (0x00B4) +#define CMU_CVBSPLL (0x00B8) +#define CMU_SSTSCLK (0x00C0)

+#endif diff --git a/drivers/clk/owl/Kconfig b/drivers/clk/owl/Kconfig index 661f198..3adbda0 100644 --- a/drivers/clk/owl/Kconfig +++ b/drivers/clk/owl/Kconfig @@ -1,12 +1,8 @@ config CLK_OWL bool "Actions Semi OWL clock drivers"

•    depends on CLK && ARCH_OWL
  

•    depends on CLK && ARCH_OWL && ARM64
     help
       Enable support for clock managemet unit present in Actions Semi
  

  OWL SoCs.

Mention S700 and S900 here.

-config CLK_S900

•    bool "Actions Semi S900 clock driver"
  

•    depends on CLK_OWL && ARM64
  

•    help
  

•      Enable support for the clocks in Actions Semi S900 SoC.
  

diff --git a/drivers/clk/owl/Makefile b/drivers/clk/owl/Makefile index 63ab573..5218b6b 100644 --- a/drivers/clk/owl/Makefile +++ b/drivers/clk/owl/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+

-obj-$(CONFIG_CLK_S900) += clk_s900.o +obj-$(CONFIG_CLK_OWL) += clk_owl.o diff --git a/drivers/clk/owl/clk_owl.c b/drivers/clk/owl/clk_owl.c new file mode 100644 index 0000000..9d5befc --- /dev/null +++ b/drivers/clk/owl/clk_owl.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Actions Semi S900 clock driver

This needs to be updated.

• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

+#include <common.h> +#include <dm.h> +#include <asm/arch-owl/clk_owl.h> +#include <asm/io.h> +#if defined(CONFIG_MACH_S900) +#include <asm/arch-owl/regs_s900.h> +#elif defined(CONFIG_MACH_S700) +#include <asm/arch-owl/regs_s700.h> +#endif

+void owl_clk_init(struct owl_clk_priv *priv) +{

• u32 bus_clk = 0, core_pll, dev_pll;

+#if defined(CONFIG_MACH_S900)

• /* Enable ASSIST_PLL */
• setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
• udelay(PLL_STABILITY_WAIT_US);

+#endif

• /* Source HOSC to DEV_CLK */
• clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
• /* Configure BUS_CLK */
• bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV | CMU_NOCDIV_DIV |

• 	CMU_DMMCLK_SRC | CMU_APBCLK_DIV | CMU_AHBCLK_DIV |
  

• 	CMU_NOCCLK_SRC | CMU_CORECLK_HOSC);
  

• writel(bus_clk, priv->base + CMU_BUSCLK);
• udelay(PLL_STABILITY_WAIT_US);
• /* Configure CORE_PLL */
• core_pll = readl(priv->base + CMU_COREPLL);
• core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN | CMU_COREPLL_OUT);
• writel(core_pll, priv->base + CMU_COREPLL);
• udelay(PLL_STABILITY_WAIT_US);
• /* Configure DEV_PLL */
• dev_pll = readl(priv->base + CMU_DEVPLL);
• dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT);
• writel(dev_pll, priv->base + CMU_DEVPLL);
• udelay(PLL_STABILITY_WAIT_US);
• /* Source CORE_PLL for CORE_CLK */
• clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,

• 	CMU_CORECLK_CPLL);
  

• /* Source DEV_PLL for DEV_CLK */
• setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
• udelay(PLL_STABILITY_WAIT_US);

+}

+int owl_clk_enable(struct clk *clk) +{

• struct owl_clk_priv *priv = dev_get_priv(clk->dev);

+#if defined(CONFIG_MACH_S900)

• /* Source HOSC for UART5 interface */

•    clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
  

•    /* Enable UART5 interface clock */
  

•    setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
  

+#elif defined(CONFIG_MACH_S700)

•    /* Source HOSC for UART3 interface */
  

•    clrbits_le32(priv->base + CMU_UART3CLK, CMU_UARTCLK_SRC_DEVPLL);
  

•    /* Enable UART3 interface clock */
  

•    setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
  

+#endif

• return 0;

+}

+int owl_clk_disable(struct clk *clk) +{

• struct owl_clk_priv *priv = dev_get_priv(clk->dev);

+#if defined(CONFIG_MACH_S900)

•    /* Disable UART5 interface clock */
  

•    clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
  

+#elif defined(CONFIG_MACH_S700)

• /* Disable UART3 interface clock */
• clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);

+#endif

• return 0;

+}

+static int owl_clk_probe(struct udevice *dev) +{

• struct owl_clk_priv *priv = dev_get_priv(dev);
• priv->base = dev_read_addr(dev);
• if (priv->base == FDT_ADDR_T_NONE)

• return -EINVAL;
  

• /* setup necessary clocks */
• owl_clk_init(priv);
• return 0;

+}

+static struct clk_ops owl_clk_ops = {

• .enable = owl_clk_enable,
• .disable = owl_clk_disable,

+};

+static const struct udevice_id owl_clk_ids[] = {

• { .compatible = "actions,s900-cmu" },
• { .compatible = "actions,s700-cmu" },
• { }

+};

+U_BOOT_DRIVER(clk_owl) = {

• .name = "clk_s900",
• .id = UCLASS_CLK,
• .of_match = owl_clk_ids,
• .ops = &owl_clk_ops,
• .priv_auto_alloc_size = sizeof(struct owl_clk_priv),
• .probe = owl_clk_probe,

+};

We can live with this driver for now, but soon this needs to be reworked to support rest of the peripherals.

Thanks, Mani

diff --git a/drivers/clk/owl/clk_s900.c b/drivers/clk/owl/clk_s900.c deleted file mode 100644 index a7c15d2..0000000 --- a/drivers/clk/owl/clk_s900.c +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*

• • Actions Semi S900 clock driver
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

-#include <common.h> -#include <dm.h> -#include <asm/arch-owl/clk_s900.h> -#include <asm/arch-owl/regs_s900.h> -#include <asm/io.h>

-#include <dt-bindings/clock/s900_cmu.h>

-void owl_clk_init(struct owl_clk_priv *priv) -{

• u32 bus_clk = 0, core_pll, dev_pll;
• /* Enable ASSIST_PLL */
• setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
• udelay(PLL_STABILITY_WAIT_US);
• /* Source HOSC to DEV_CLK */
• clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
• /* Configure BUS_CLK */
• bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV | CMU_NOCDIV_DIV |

• 	CMU_DMMCLK_SRC | CMU_APBCLK_DIV | CMU_AHBCLK_DIV |
  

• 	CMU_NOCCLK_SRC | CMU_CORECLK_HOSC);
  

• writel(bus_clk, priv->base + CMU_BUSCLK);
• udelay(PLL_STABILITY_WAIT_US);
• /* Configure CORE_PLL */
• core_pll = readl(priv->base + CMU_COREPLL);
• core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN | CMU_COREPLL_OUT);
• writel(core_pll, priv->base + CMU_COREPLL);
• udelay(PLL_STABILITY_WAIT_US);
• /* Configure DEV_PLL */
• dev_pll = readl(priv->base + CMU_DEVPLL);
• dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT);
• writel(dev_pll, priv->base + CMU_DEVPLL);
• udelay(PLL_STABILITY_WAIT_US);
• /* Source CORE_PLL for CORE_CLK */
• clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,

• 	CMU_CORECLK_CPLL);
  

• /* Source DEV_PLL for DEV_CLK */
• setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
• udelay(PLL_STABILITY_WAIT_US);

-}

-void owl_uart_clk_enable(struct owl_clk_priv *priv) -{

• /* Source HOSC for UART5 interface */
• clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
• /* Enable UART5 interface clock */
• setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);

-}

-void owl_uart_clk_disable(struct owl_clk_priv *priv) -{

• /* Disable UART5 interface clock */
• clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);

-}

-int owl_clk_enable(struct clk *clk) -{

• struct owl_clk_priv *priv = dev_get_priv(clk->dev);
• switch (clk->id) {
• case CLOCK_UART5:

• owl_uart_clk_enable(priv);
  

• break;
  

• default:

• return 0;
  

• }
• return 0;

-}

-int owl_clk_disable(struct clk *clk) -{

• struct owl_clk_priv *priv = dev_get_priv(clk->dev);
• switch (clk->id) {
• case CLOCK_UART5:

• owl_uart_clk_disable(priv);
  

• break;
  

• default:

• return 0;
  

• }
• return 0;

-}

-static int owl_clk_probe(struct udevice *dev) -{

• struct owl_clk_priv *priv = dev_get_priv(dev);
• priv->base = dev_read_addr(dev);
• if (priv->base == FDT_ADDR_T_NONE)

• return -EINVAL;
  

• /* setup necessary clocks */
• owl_clk_init(priv);
• return 0;

-}

-static struct clk_ops owl_clk_ops = {

• .enable = owl_clk_enable,
• .disable = owl_clk_disable,

-};

-static const struct udevice_id owl_clk_ids[] = {

• { .compatible = "actions,s900-cmu" },
• { }

-};

-U_BOOT_DRIVER(clk_owl) = {

• .name = "clk_s900",
• .id = UCLASS_CLK,
• .of_match = owl_clk_ids,
• .ops = &owl_clk_ops,
• .priv_auto_alloc_size = sizeof(struct owl_clk_priv),
• .probe = owl_clk_probe,

-};

2.7.4

On 03/01/2019 13:26, Amit Singh Tomar wrote:

Bubblegum board now gets driven from common owl framework, so let's remove the respected board files.

I think this patch could be split and merged into other patches, mostly 1/8.

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

board/ucRobotics/bubblegum_96/Kconfig | 15 -------- board/ucRobotics/bubblegum_96/MAINTAINERS | 6 --- board/ucRobotics/bubblegum_96/Makefile | 3 -- board/ucRobotics/bubblegum_96/bubblegum_96.c | 56 ---------------------------- 4 files changed, 80 deletions(-) delete mode 100644 board/ucRobotics/bubblegum_96/Kconfig delete mode 100644 board/ucRobotics/bubblegum_96/MAINTAINERS delete mode 100644 board/ucRobotics/bubblegum_96/Makefile delete mode 100644 board/ucRobotics/bubblegum_96/bubblegum_96.c

diff --git a/board/ucRobotics/bubblegum_96/Kconfig b/board/ucRobotics/bubblegum_96/Kconfig deleted file mode 100644 index 2dd40d9..0000000 --- a/board/ucRobotics/bubblegum_96/Kconfig +++ /dev/null

That should be part of patch 1/8, where you remove the inclusion of that file.

@@ -1,15 +0,0 @@ -if TARGET_BUBBLEGUM_96

-config SYS_BOARD

• default "bubblegum_96"

-config SYS_VENDOR

• default "ucRobotics"

-config SYS_SOC

• default "s900"

-config SYS_CONFIG_NAME

• default "bubblegum_96"

-endif diff --git a/board/ucRobotics/bubblegum_96/MAINTAINERS b/board/ucRobotics/bubblegum_96/MAINTAINERS deleted file mode 100644 index d0cb727..0000000 --- a/board/ucRobotics/bubblegum_96/MAINTAINERS +++ /dev/null

Can you please adjust the paths in /MAINTAINERS? board/ucRobotics will be gone after this patch, that should be reflected there. This could be the only thing left in this patch or merged into 1/8.

@@ -1,6 +0,0 @@ -BUBBLEGUM_96 BOARD -M: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org -S: Maintained -F: board/ucRobotics/bubblegum_96/ -F: include/configs/bubblegum_96.h -F: configs/bubblegum_96_defconfig diff --git a/board/ucRobotics/bubblegum_96/Makefile b/board/ucRobotics/bubblegum_96/Makefile deleted file mode 100644 index c4b524d..0000000 --- a/board/ucRobotics/bubblegum_96/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+

-obj-y := bubblegum_96.o diff --git a/board/ucRobotics/bubblegum_96/bubblegum_96.c b/board/ucRobotics/bubblegum_96/bubblegum_96.c deleted file mode 100644 index a4c202d..0000000 --- a/board/ucRobotics/bubblegum_96/bubblegum_96.c +++ /dev/null

That should be part of 1/8 as well, where you more or less rename that file here. That helps git to detect this and show this accordingly.

Cheers, Andre.

@@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*

• • Bubblegum-96 Boards Support
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

-#include <linux/arm-smccc.h> -#include <linux/psci.h> -#include <common.h> -#include <asm/io.h> -#include <asm/mach-types.h> -#include <asm/psci.h>

-DECLARE_GLOBAL_DATA_PTR;

-/*

• • dram_init - sets uboots idea of sdram size
• */

-int dram_init(void) -{

• gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
• return 0;

-}

-/* This is called after dram_init() so use get_ram_size result */ -int dram_init_banksize(void) -{

• gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
• gd->bd->bi_dram[0].size = gd->ram_size;
• return 0;

-}

-static void show_psci_version(void) -{

• struct arm_smccc_res res;
• arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
• printf("PSCI: v%ld.%ld\n",

•       PSCI_VERSION_MAJOR(res.a0),
  

• PSCI_VERSION_MINOR(res.a0));
  

-}

-int board_init(void) -{

• show_psci_version();
• return 0;

-}

-void reset_cpu(ulong addr) -{

• psci_system_reset();

-}

On Thu, Jan 03, 2019 at 06:56:20PM +0530, Amit Singh Tomar wrote:

This patch adds .dtsi file(sync with Linux 4.20) and required binding for S700 SoC that is a 64-bit Quad-core ARM Cortex-A53 cores.

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

arch/arm/dts/s700.dtsi | 193 +++++++++++++++++++++++++++ include/dt-bindings/clock/actions,s700-cmu.h | 118 ++++++++++++++++ 2 files changed, 311 insertions(+) create mode 100644 arch/arm/dts/s700.dtsi create mode 100644 include/dt-bindings/clock/actions,s700-cmu.h

diff --git a/arch/arm/dts/s700.dtsi b/arch/arm/dts/s700.dtsi new file mode 100644 index 0000000..a74c75a --- /dev/null +++ b/arch/arm/dts/s700.dtsi @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*

• • Copyright (c) 2017 Andreas Färber
• */

+#include <dt-bindings/clock/actions,s700-cmu.h> +#include <dt-bindings/interrupt-controller/arm-gic.h>

+/ {

• compatible = "actions,s700";
• interrupt-parent = <&gic>;
• #address-cells = <2>;
• #size-cells = <2>;
• cpus {

• #address-cells = <2>;
  

• #size-cells = <0>;
  

• cpu0: cpu@0 {
  

• 	device_type = "cpu";
  

• 	compatible = "arm,cortex-a53", "arm,armv8";
  

• 	reg = <0x0 0x0>;
  

• 	enable-method = "psci";
  

• };
  

• cpu1: cpu@1 {
  

• 	device_type = "cpu";
  

• 	compatible = "arm,cortex-a53", "arm,armv8";
  

• 	reg = <0x0 0x1>;
  

• 	enable-method = "psci";
  

• };
  

• cpu2: cpu@2 {
  

• 	device_type = "cpu";
  

• 	compatible = "arm,cortex-a53", "arm,armv8";
  

• 	reg = <0x0 0x2>;
  

• 	enable-method = "psci";
  

• };
  

• cpu3: cpu@3 {
  

• 	device_type = "cpu";
  

• 	compatible = "arm,cortex-a53", "arm,armv8";
  

• 	reg = <0x0 0x3>;
  

• 	enable-method = "psci";
  

• };
  

• };
• reserved-memory {

• #address-cells = <2>;
  

• #size-cells = <2>;
  

• ranges;
  

• secmon@1f000000 {
  

• 	reg = <0x0 0x1f000000 0x0 0x1000000>;
  

• 	no-map;
  

• };
  

• };
• psci {

• compatible = "arm,psci-0.2";
  

• method = "smc";
  

• };
• arm-pmu {

• compatible = "arm,cortex-a53-pmu";
  

• interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  

•              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
  

•              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  

•              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  

• interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  

• };
• timer {

• compatible = "arm,armv8-timer";
  

• interrupts = <GIC_PPI 13
  

• 	(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  

• 	     <GIC_PPI 14
  

• 	(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  

• 	     <GIC_PPI 11
  

• 	(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  

• 	     <GIC_PPI 10
  

• 	(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  

• };
• hosc: hosc {

• compatible = "fixed-clock";
  

• clock-frequency = <24000000>;
  

• #clock-cells = <0>;
  

• };
• losc: losc {

• compatible = "fixed-clock";
  

• clock-frequency = <32768>;
  

• #clock-cells = <0>;
  

• };
• soc {

• u-boot,dm-pre-reloc;
  

• compatible = "simple-bus";
  

• #address-cells = <2>;
  

• #size-cells = <2>;
  

• ranges;
  

• gic: interrupt-controller@e00f1000 {
  

• 	compatible = "arm,gic-400";
  

• 	reg = <0x0 0xe00f1000 0x0 0x1000>,
  

• 	      <0x0 0xe00f2000 0x0 0x2000>,
  

• 	      <0x0 0xe00f4000 0x0 0x2000>,
  

• 	      <0x0 0xe00f6000 0x0 0x2000>;
  

• 	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  

• 	interrupt-controller;
  

• 	#interrupt-cells = <3>;
  

• };
  

• uart0: serial@e0120000 {
  

• 	compatible = "actions,s900-uart", "actions,owl-uart";
  

• 	reg = <0x0 0xe0120000 0x0 0x2000>;
  

• 	clocks = <&cmu CLK_UART0>;
  

• 	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  

• 	status = "disabled";
  

• };
  

• uart1: serial@e0122000 {
  

• 	compatible = "actions,s900-uart", "actions,owl-uart";
  

• 	reg = <0x0 0xe0122000 0x0 0x2000>;
  

• 	clocks = <&cmu CLK_UART1>;
  

• 	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  

• 	status = "disabled";
  

• };
  

• uart2: serial@e0124000 {
  

• 	compatible = "actions,s900-uart", "actions,owl-uart";
  

• 	reg = <0x0 0xe0124000 0x0 0x2000>;
  

• 	clocks = <&cmu CLK_UART2>;
  

• 	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  

• 	status = "disabled";
  

• };
  

• uart3: serial@e0126000 {
  

• 	u-boot,dm-pre-reloc;
  

It would be best to keep this DTS unchanged with Linux and add the u-boot specific bits in -u-boot.dtsi.

• 	compatible = "actions,s900-uart", "actions,owl-uart";
  

• 	reg = <0x0 0xe0126000 0x0 0x2000>;
  

• 	clocks = <&cmu CLK_UART3>;
  

• 	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  

• 	status = "disabled";
  

• };
  

• uart4: serial@e0128000 {
  

• 	compatible = "actions,s900-uart", "actions,owl-uart";
  

• 	reg = <0x0 0xe0128000 0x0 0x2000>;
  

• 	clocks = <&cmu CLK_UART4>;
  

• 	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  

• 	status = "disabled";
  

• };
  

• uart5: serial@e012a000 {
  

• 	compatible = "actions,s900-uart", "actions,owl-uart";
  

• 	reg = <0x0 0xe012a000 0x0 0x2000>;
  

• 	clocks = <&cmu CLK_UART5>;
  

• 	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  

• 	status = "disabled";
  

• };
  

• uart6: serial@e012c000 {
  

• 	compatible = "actions,s900-uart", "actions,owl-uart";
  

• 	reg = <0x0 0xe012c000 0x0 0x2000>;
  

• 	clocks = <&cmu CLK_UART6>;
  

• 	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  

• 	status = "disabled";
  

• };
  

• cmu: clock-controller@e0168000 {
  

• 	u-boot,dm-pre-reloc;
  

Same as above comment.

Thanks, Mani

• 	compatible = "actions,s700-cmu";
  

• 	reg = <0x0 0xe0168000 0x0 0x1000>;
  

• 	clocks = <&hosc>, <&losc>;
  

• 	#clock-cells = <1>;
  

• };
  

• sps: power-controller@e01b0100 {
  

• 	compatible = "actions,s700-sps";
  

• 	reg = <0x0 0xe01b0100 0x0 0x100>;
  

• 	#power-domain-cells = <1>;
  

• };
  

• timer: timer@e024c000 {
  

• 	compatible = "actions,s700-timer";
  

• 	reg = <0x0 0xe024c000 0x0 0x4000>;
  

• 	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  

• 	interrupt-names = "timer1";
  

• };
  

• };

+}; diff --git a/include/dt-bindings/clock/actions,s700-cmu.h b/include/dt-bindings/clock/actions,s700-cmu.h new file mode 100644 index 0000000..3e19429 --- /dev/null +++ b/include/dt-bindings/clock/actions,s700-cmu.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0

• • Device Tree binding constants for Actions Semi S700 Clock Management Unit
• • Copyright (c) 2014 Actions Semi Inc.
• • Author: David Liu liuwei@actions-semi.com
• • Author: Pathiban Nallathambi pn@denx.de
• • Author: Saravanan Sekar sravanhome@gmail.com
• */

+#ifndef __DT_BINDINGS_CLOCK_S700_H +#define __DT_BINDINGS_CLOCK_S700_H

+#define CLK_NONE 0

+/* pll clocks */ +#define CLK_CORE_PLL 1 +#define CLK_DEV_PLL 2 +#define CLK_DDR_PLL 3 +#define CLK_NAND_PLL 4 +#define CLK_DISPLAY_PLL 5 +#define CLK_TVOUT_PLL 6 +#define CLK_CVBS_PLL 7 +#define CLK_AUDIO_PLL 8 +#define CLK_ETHERNET_PLL 9

+/* system clock */ +#define CLK_CPU 10 +#define CLK_DEV 11 +#define CLK_AHB 12 +#define CLK_APB 13 +#define CLK_DMAC 14 +#define CLK_NOC0_CLK_MUX 15 +#define CLK_NOC1_CLK_MUX 16 +#define CLK_HP_CLK_MUX 17 +#define CLK_HP_CLK_DIV 18 +#define CLK_NOC1_CLK_DIV 19 +#define CLK_NOC0 20 +#define CLK_NOC1 21 +#define CLK_SENOR_SRC 22

+/* peripheral device clock */ +#define CLK_GPIO 23 +#define CLK_TIMER 24 +#define CLK_DSI 25 +#define CLK_CSI 26 +#define CLK_SI 27 +#define CLK_DE 28 +#define CLK_HDE 29 +#define CLK_VDE 30 +#define CLK_VCE 31 +#define CLK_NAND 32 +#define CLK_SD0 33 +#define CLK_SD1 34 +#define CLK_SD2 35

+#define CLK_UART0 36 +#define CLK_UART1 37 +#define CLK_UART2 38 +#define CLK_UART3 39 +#define CLK_UART4 40 +#define CLK_UART5 41 +#define CLK_UART6 42

+#define CLK_PWM0 43 +#define CLK_PWM1 44 +#define CLK_PWM2 45 +#define CLK_PWM3 46 +#define CLK_PWM4 47 +#define CLK_PWM5 48 +#define CLK_GPU3D 49

+#define CLK_I2C0 50 +#define CLK_I2C1 51 +#define CLK_I2C2 52 +#define CLK_I2C3 53

+#define CLK_SPI0 54 +#define CLK_SPI1 55 +#define CLK_SPI2 56 +#define CLK_SPI3 57

+#define CLK_USB3_480MPLL0 58 +#define CLK_USB3_480MPHY0 59 +#define CLK_USB3_5GPHY 60 +#define CLK_USB3_CCE 61 +#define CLK_USB3_MAC 62

+#define CLK_LCD 63 +#define CLK_HDMI_AUDIO 64 +#define CLK_I2SRX 65 +#define CLK_I2STX 66

+#define CLK_SENSOR0 67 +#define CLK_SENSOR1 68

+#define CLK_HDMI_DEV 69

+#define CLK_ETHERNET 70 +#define CLK_RMII_REF 71

+#define CLK_USB2H0_PLLEN 72 +#define CLK_USB2H0_PHY 73 +#define CLK_USB2H0_CCE 74 +#define CLK_USB2H1_PLLEN 75 +#define CLK_USB2H1_PHY 76 +#define CLK_USB2H1_CCE 77

+#define CLK_TVOUT 78

+#define CLK_THERMAL_SENSOR 79

+#define CLK_IRC_SWITCH 80 +#define CLK_PCM1 81 +#define CLK_NR_CLKS (CLK_PCM1 + 1)

+#endif /* __DT_BINDINGS_CLOCK_S700_H */

2.7.4

On 03/01/2019 13:26, Amit Singh Tomar wrote:

Hi,

The Cubieboard is a single board computer containing a Actions S700 SoC(with 4 ARMv8 Cortex-A53 cores).

This patch adds respective defconfig alongwith device tree(sync with Linux 4.20).

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

arch/arm/dts/s700-cubieboard7.dts | 39 +++++++++++++++++++++++++++++++++++++++ configs/cubieboard7_defconfig | 22 ++++++++++++++++++++++ 2 files changed, 61 insertions(+) create mode 100644 arch/arm/dts/s700-cubieboard7.dts create mode 100644 configs/cubieboard7_defconfig

diff --git a/arch/arm/dts/s700-cubieboard7.dts b/arch/arm/dts/s700-cubieboard7.dts new file mode 100644 index 0000000..28f3f4a --- /dev/null +++ b/arch/arm/dts/s700-cubieboard7.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*

• • Copyright (c) 2017 Andreas Färber
• */

+/dts-v1/;

+#include "s700.dtsi"

+/ {

• compatible = "cubietech,cubieboard7", "actions,s700";
• model = "CubieBoard7";
• aliases {

• serial3 = &uart3;
  

• };
• chosen {

• stdout-path = "serial3:115200n8";
  

• };
• memory@0 {

• device_type = "memory";
  

• reg = <0x0 0x0 0x0 0x80000000>;
  

• };
• memory@1,e0000000 {

• device_type = "memory";
  

• reg = <0x1 0xe0000000 0x0 0x0>;
  

• };

+};

+&timer {

• clocks = <&hosc>;

+};

+&uart3 {

• status = "okay";

+}; diff --git a/configs/cubieboard7_defconfig b/configs/cubieboard7_defconfig new file mode 100644 index 0000000..f870839 --- /dev/null +++ b/configs/cubieboard7_defconfig

This is copied from the Bubblegum, right? It contains a lot of symbols that are required by the platform, so should be tackled in the Kconfig instead of here. This applies to the bubblegum config as well, so maybe these comments are more for Mani ;-)

@@ -0,0 +1,22 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y

Sounds like a generic OWL 64 bit requirement.

+CONFIG_ARCH_OWL=y +CONFIG_SYS_TEXT_BASE=0x11000000

This is also a platform decision, to be handled generically.

+CONFIG_MACH_S700=y +CONFIG_IDENT_STRING="\ncubieboard7" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyOWL3,115200n8" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="U-Boot => " +CONFIG_CMD_MD5SUM=y

What is this for? If it is required by something, it should be already selected automatically.

+CONFIG_CMD_MEMINFO=y +CONFIG_CMD_CACHE=y

Why is this? Disabling the cache on the U-Boot command line sounds dodgy.

+CONFIG_CMD_TIMER=y

Is this needed by some boot script? Then it should be set somewhere generic.

+CONFIG_DEFAULT_DEVICE_TREE="s700-cubieboard7" +CONFIG_CLK=y +CONFIG_CLK_OWL=y +CONFIG_OWL_SERIAL=y

Those last three should also be set in the Kconfig.

Cheers, Andre.

On Thu, Jan 03, 2019 at 06:56:22PM +0530, Amit Singh Tomar wrote:

UART controller present on S700 is compatible with existing S900 UART, this patch simply adds a proper compatible string so that S900 uart driver can be reused for S700.

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

drivers/serial/serial_owl.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/serial/serial_owl.c b/drivers/serial/serial_owl.c index 7ead73e..76995bf 100644 --- a/drivers/serial/serial_owl.c +++ b/drivers/serial/serial_owl.c @@ -121,6 +121,7 @@ static const struct dm_serial_ops owl_serial_ops = {

static const struct udevice_id owl_serial_ids[] = { { .compatible = "actions,s900-serial" },

• { .compatible = "actions,owl-uart" },

"owl" is the family name for S series SoCs from Actions Semi. There are 3 SoCs so far, S500, S700 and S900. Reason for naming s900-serial was that there are hw difference between S500 (ARMv7) and S900/S700 (ARMv8). So, this should be "actions,s700-serial".

Thanks, Mani

{ } };

-- 2.7.4

On Sun, Jan 06, 2019 at 01:12:53AM +0000, André Przywara wrote:

On 05/01/2019 18:20, Manivannan Sadhasivam wrote:

...

On Thu, Jan 03, 2019 at 06:56:22PM +0530, Amit Singh Tomar wrote:

...

UART controller present on S700 is compatible with existing S900 UART, this patch simply adds a proper compatible string so that S900 uart driver can be reused for S700.

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

drivers/serial/serial_owl.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/serial/serial_owl.c b/drivers/serial/serial_owl.c index 7ead73e..76995bf 100644 --- a/drivers/serial/serial_owl.c +++ b/drivers/serial/serial_owl.c @@ -121,6 +121,7 @@ static const struct dm_serial_ops owl_serial_ops = {

static const struct udevice_id owl_serial_ids[] = { { .compatible = "actions,s900-serial" },

• { .compatible = "actions,owl-uart" },

"owl" is the family name for S series SoCs from Actions Semi. There are 3 SoCs so far, S500, S700 and S900. Reason for naming s900-serial was that there are hw difference between S500 (ARMv7) and S900/S700 (ARMv8). So, this should be "actions,s700-serial".

Huh, how so? The Linux DT bindings, which should be authoritative, do not describe a s700 device. Also the Linux DTs use the s900 name. The only difference between the S500 and S900 type seems to be the FIFO size, which U-Boot doesn't care about. As all the DTs I see in the Linux tree have owl-uart in their compatible list, it would actually be sufficient to list just that. This is what Linux' earlycon relies on. But to play safe we could list both here, maybe even add s500-serial, for the sake of completeness.

My argument above was based on the fact that Amit didn't remove "actions,s900-serial" compatible but added "actions,owl-serial". I'm okay with having "actions,owl-serial" for _all_ S series boards.

Thanks, Mani

But we should not invent a new compatible string here.

Cheers, Andre.

...

Thanks, Mani

...

{ } };

-- 2.7.4