[U-Boot] [PATCH] arm: imx-common: init: extend init_aips to support imx7
Extend init_aips to support imx7 SoC, use is_soc_type and is_cpu_type to resolve at run time aips3 settings
Signed-off-by: Adrian Alonso aalonso@freescale.com --- arch/arm/imx-common/init.c | 44 ++++++++++++++++++++------------------------ 1 file changed, 20 insertions(+), 24 deletions(-)
diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c index f7ed038..c3ac98f 100644 --- a/arch/arm/imx-common/init.c +++ b/arch/arm/imx-common/init.c @@ -13,16 +13,11 @@
void init_aips(void) { - struct aipstz_regs *aips1, *aips2; -#ifdef CONFIG_MX6SX - struct aipstz_regs *aips3; -#endif + struct aipstz_regs *aips1, *aips2, *aips3;
aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR; aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR; -#ifdef CONFIG_MX6SX aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR; -#endif
/* * Set all MPROTx to be non-bufferable, trusted for R/W, @@ -49,25 +44,26 @@ void init_aips(void) writel(0x00000000, &aips2->opacr3); writel(0x00000000, &aips2->opacr4);
-#ifdef CONFIG_MX6SX - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - writel(0x77777777, &aips3->mprot0); - writel(0x77777777, &aips3->mprot1); + if (is_soc_type(MXC_SOC_MX7) || is_cpu_type(MXC_CPU_MX6SX)) + { + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, &aips3->mprot0); + writel(0x77777777, &aips3->mprot1);
- /* - * Set all OPACRx to be non-bufferable, not require - * supervisor privilege level for access,allow for - * write access and untrusted master access. - */ - writel(0x00000000, &aips3->opacr0); - writel(0x00000000, &aips3->opacr1); - writel(0x00000000, &aips3->opacr2); - writel(0x00000000, &aips3->opacr3); - writel(0x00000000, &aips3->opacr4); -#endif + /* + * Set all OPACRx to be non-bufferable, not require + * supervisor privilege level for access,allow for + * write access and untrusted master access. + */ + writel(0x00000000, &aips3->opacr0); + writel(0x00000000, &aips3->opacr1); + writel(0x00000000, &aips3->opacr2); + writel(0x00000000, &aips3->opacr3); + writel(0x00000000, &aips3->opacr4); + } }
#define SRC_SCR_WARM_RESET_ENABLE 0
Hi Adrian,
On 29/08/2015 01:06, Adrian Alonso wrote:
Extend init_aips to support imx7 SoC, use is_soc_type and is_cpu_type to resolve at run time aips3 settings
Signed-off-by: Adrian Alonso aalonso@freescale.com
arch/arm/imx-common/init.c | 44 ++++++++++++++++++++------------------------ 1 file changed, 20 insertions(+), 24 deletions(-)
diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c index f7ed038..c3ac98f 100644 --- a/arch/arm/imx-common/init.c +++ b/arch/arm/imx-common/init.c @@ -13,16 +13,11 @@
void init_aips(void) {
- struct aipstz_regs *aips1, *aips2;
-#ifdef CONFIG_MX6SX
- struct aipstz_regs *aips3;
-#endif
struct aipstz_regs *aips1, *aips2, *aips3;
aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR; aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
-#ifdef CONFIG_MX6SX aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR; -#endif
/* * Set all MPROTx to be non-bufferable, trusted for R/W, @@ -49,25 +44,26 @@ void init_aips(void) writel(0x00000000, &aips2->opacr3); writel(0x00000000, &aips2->opacr4);
-#ifdef CONFIG_MX6SX
- /*
* Set all MPROTx to be non-bufferable, trusted for R/W,* not forced to user-mode.*/- writel(0x77777777, &aips3->mprot0);
- writel(0x77777777, &aips3->mprot1);
- if (is_soc_type(MXC_SOC_MX7) || is_cpu_type(MXC_CPU_MX6SX))
- {
/** Set all MPROTx to be non-bufferable, trusted for R/W,* not forced to user-mode.*/writel(0x77777777, &aips3->mprot0);writel(0x77777777, &aips3->mprot1);
- /*
* Set all OPACRx to be non-bufferable, not require* supervisor privilege level for access,allow for* write access and untrusted master access.*/- writel(0x00000000, &aips3->opacr0);
- writel(0x00000000, &aips3->opacr1);
- writel(0x00000000, &aips3->opacr2);
- writel(0x00000000, &aips3->opacr3);
- writel(0x00000000, &aips3->opacr4);
-#endif
/** Set all OPACRx to be non-bufferable, not require* supervisor privilege level for access,allow for* write access and untrusted master access.*/writel(0x00000000, &aips3->opacr0);writel(0x00000000, &aips3->opacr1);writel(0x00000000, &aips3->opacr2);writel(0x00000000, &aips3->opacr3);writel(0x00000000, &aips3->opacr4);- }
}
#define SRC_SCR_WARM_RESET_ENABLE 0
This looks ok to me. By the way, I see you sent single patches for i.MXv7 support. I guess the order to apply them is important, isn't it ?
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
Hi Stefano,
-----Original Message----- From: Stefano Babic [mailto:sbabic@denx.de] Sent: Monday, August 31, 2015 10:46 AM To: Alonso Lazcano Adrian-B38018 aalonso@freescale.com; u- boot@lists.denx.de; sbabic@denx.de Cc: otavio@ossystems.com.br; Estevam Fabio-R49496 Fabio.Estevam@freescale.com; Li Frank-B20596 Frank.Li@freescale.com; Garg Nitin-B37173 nitin.garg@freescale.com Subject: Re: [PATCH] arm: imx-common: init: extend init_aips to support imx7
Hi Adrian,
On 29/08/2015 01:06, Adrian Alonso wrote:
Extend init_aips to support imx7 SoC, use is_soc_type and is_cpu_type to resolve at run time aips3 settings
Signed-off-by: Adrian Alonso aalonso@freescale.com
arch/arm/imx-common/init.c | 44 ++++++++++++++++++++------------------------ 1 file changed, 20 insertions(+), 24 deletions(-)
diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c index f7ed038..c3ac98f 100644 --- a/arch/arm/imx-common/init.c +++ b/arch/arm/imx-common/init.c @@ -13,16 +13,11 @@
void init_aips(void) {
- struct aipstz_regs *aips1, *aips2;
-#ifdef CONFIG_MX6SX
- struct aipstz_regs *aips3;
-#endif
struct aipstz_regs *aips1, *aips2, *aips3;
aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR; aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR; -#ifdef
CONFIG_MX6SX
aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR; -#endif
/* * Set all MPROTx to be non-bufferable, trusted for R/W, @@ -49,25 +44,26 @@ void init_aips(void) writel(0x00000000, &aips2->opacr3); writel(0x00000000, &aips2->opacr4);
-#ifdef CONFIG_MX6SX
- /*
* Set all MPROTx to be non-bufferable, trusted for R/W,* not forced to user-mode.*/- writel(0x77777777, &aips3->mprot0);
- writel(0x77777777, &aips3->mprot1);
- if (is_soc_type(MXC_SOC_MX7) || is_cpu_type(MXC_CPU_MX6SX))
- {
/** Set all MPROTx to be non-bufferable, trusted for R/W,* not forced to user-mode.*/writel(0x77777777, &aips3->mprot0);writel(0x77777777, &aips3->mprot1);
- /*
* Set all OPACRx to be non-bufferable, not require* supervisor privilege level for access,allow for* write access and untrusted master access.*/- writel(0x00000000, &aips3->opacr0);
- writel(0x00000000, &aips3->opacr1);
- writel(0x00000000, &aips3->opacr2);
- writel(0x00000000, &aips3->opacr3);
- writel(0x00000000, &aips3->opacr4);
-#endif
/** Set all OPACRx to be non-bufferable, not require* supervisor privilege level for access,allow for* write access and untrusted master access.*/writel(0x00000000, &aips3->opacr0);writel(0x00000000, &aips3->opacr1);writel(0x00000000, &aips3->opacr2);writel(0x00000000, &aips3->opacr3);writel(0x00000000, &aips3->opacr4);- }
}
#define SRC_SCR_WARM_RESET_ENABLE 0
This looks ok to me. By the way, I see you sent single patches for i.MXv7 support. I guess the order to apply them is important, isn't it ?
[Adrian] Yes, they are several patch's acked and other that have sent new version The order to apply them is: power: pmic: add pfuze3000 support imx: iomux-v3: add imx7d support for iomuxc imx: mxc_gpio: add support for imx7d SoC imx: ocotp: mxc add i.MX7D support imx: arch-mx6: add is_soc_type helper macro thermal: imx_thermal: rework driver to be reused arm: imx: common rework cache settings for imx6 arm: imx: imx-common: init: move arch init common setup arm: imx-common: init: extend init_aips to support imx7 arm: imx-common: init: rework wdog settings for imx6/imx7 imx: system counter driver for imx7d and mx6ul imx: imx7d: initial arch level support imx: imx7d: clock control module support imx: imx7d: Add SoC system support imx: imx7d: add timer support for imx7d imx: imx7d: add imx-common cpu support for imx7d imx: mx7dsabresd: Add support for MX7D SABRESD board thermal: imx: add imx7d soc thermal support
Sorry for the mess :P
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
--
========= DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de ============================================================ =========
participants (3)
-
Adrian Alonso -
Alonso Adrian
-
Stefano Babic