[PATCH 01/30] clk: renesas: Synchronize RZ/G2 tables with Linux 5.12
Synchronize RZ/G2 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- drivers/clk/renesas/r8a774a1-cpg-mssr.c | 14 +++++++++----- drivers/clk/renesas/r8a774b1-cpg-mssr.c | 8 ++++++++ drivers/clk/renesas/r8a774c0-cpg-mssr.c | 9 +++++++++ 3 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index 1c54eca6c0..ef2bb6d777 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -68,13 +68,18 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), - DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), + + DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC, + CLK_RPCSRC), + DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, + R8A774A1_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */ - DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), - DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), + DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), + DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), @@ -99,7 +104,6 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = { DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078), DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268), DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c), - DEF_GEN3_RPC("rpc", R8A774A1_CLK_RPC, CLK_RPCSRC, 0x238),
DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1), @@ -203,7 +207,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] = { DEF_MOD("can-fd", 914, R8A774A1_CLK_S3D2), DEF_MOD("can-if1", 915, R8A774A1_CLK_S3D4), DEF_MOD("can-if0", 916, R8A774A1_CLK_S3D4), - DEF_MOD("rpc", 917, R8A774A1_CLK_RPC), + DEF_MOD("rpc-if", 917, R8A774A1_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6), DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6), DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP), diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c index 03851d0b5a..a8b242dc47 100644 --- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c @@ -39,6 +39,7 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC, + CLK_RPCSRC, CLK_RINT,
/* Module Clocks */ @@ -64,6 +65,12 @@ static const struct cpg_core_clk r8a774b1_core_clks[] = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), + + DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC, + CLK_RPCSRC), + DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, + R8A774B1_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
@@ -195,6 +202,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] = { DEF_MOD("can-fd", 914, R8A774B1_CLK_S3D2), DEF_MOD("can-if1", 915, R8A774B1_CLK_S3D4), DEF_MOD("can-if0", 916, R8A774B1_CLK_S3D4), + DEF_MOD("rpc-if", 917, R8A774B1_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6), DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6), DEF_MOD("i2c-dvfs", 926, R8A774B1_CLK_CP), diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c index 37a7123f73..6e9558a107 100644 --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c @@ -44,6 +44,7 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC, + CLK_RPCSRC, CLK_RINT, CLK_OCO,
@@ -74,6 +75,13 @@ static const struct cpg_core_clk r8a774c0_core_clks[] = { DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
+ DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1), + + DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC, + CLK_RPCSRC), + DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, + R8A774C0_CLK_RPC), + DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000), @@ -199,6 +207,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] = { DEF_MOD("can-fd", 914, R8A774C0_CLK_S3D2), DEF_MOD("can-if1", 915, R8A774C0_CLK_S3D4), DEF_MOD("can-if0", 916, R8A774C0_CLK_S3D4), + DEF_MOD("rpc-if", 917, R8A774C0_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2), DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2), DEF_MOD("i2c-dvfs", 926, R8A774C0_CLK_CP),
Synchronize R-Car Gen2 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- drivers/clk/renesas/r8a7790-cpg-mssr.c | 4 ++-- drivers/clk/renesas/r8a7791-cpg-mssr.c | 2 +- drivers/clk/renesas/r8a7792-cpg-mssr.c | 2 +- drivers/clk/renesas/r8a7794-cpg-mssr.c | 2 +- drivers/clk/renesas/rcar-gen2-cpg.h | 5 +---- 5 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c b/drivers/clk/renesas/r8a7790-cpg-mssr.c index d5079da3ff..8d616476c7 100644 --- a/drivers/clk/renesas/r8a7790-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c @@ -108,8 +108,8 @@ static const struct mssr_mod_clk r8a7790_mod_clks[] = { DEF_MOD("tmu0", 125, R8A7790_CLK_CP), DEF_MOD("vsp1du1", 127, R8A7790_CLK_ZS), DEF_MOD("vsp1du0", 128, R8A7790_CLK_ZS), - DEF_MOD("vsp1-rt", 130, R8A7790_CLK_ZS), - DEF_MOD("vsp1-sy", 131, R8A7790_CLK_ZS), + DEF_MOD("vspr", 130, R8A7790_CLK_ZS), + DEF_MOD("vsps", 131, R8A7790_CLK_ZS), DEF_MOD("scifa2", 202, R8A7790_CLK_MP), DEF_MOD("scifa1", 203, R8A7790_CLK_MP), DEF_MOD("scifa0", 204, R8A7790_CLK_MP), diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c b/drivers/clk/renesas/r8a7791-cpg-mssr.c index fa0e275afd..7a89613b32 100644 --- a/drivers/clk/renesas/r8a7791-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c @@ -106,7 +106,7 @@ static const struct mssr_mod_clk r8a7791_mod_clks[] = { DEF_MOD("tmu0", 125, R8A7791_CLK_CP), DEF_MOD("vsp1du1", 127, R8A7791_CLK_ZS), DEF_MOD("vsp1du0", 128, R8A7791_CLK_ZS), - DEF_MOD("vsp1-sy", 131, R8A7791_CLK_ZS), + DEF_MOD("vsps", 131, R8A7791_CLK_ZS), DEF_MOD("scifa2", 202, R8A7791_CLK_MP), DEF_MOD("scifa1", 203, R8A7791_CLK_MP), DEF_MOD("scifa0", 204, R8A7791_CLK_MP), diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c index d2225a3ff5..e18774dae4 100644 --- a/drivers/clk/renesas/r8a7792-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c @@ -88,7 +88,7 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] = { DEF_MOD("tmu0", 125, R8A7792_CLK_CP), DEF_MOD("vsp1du1", 127, R8A7792_CLK_ZS), DEF_MOD("vsp1du0", 128, R8A7792_CLK_ZS), - DEF_MOD("vsp1-sy", 131, R8A7792_CLK_ZS), + DEF_MOD("vsps", 131, R8A7792_CLK_ZS), DEF_MOD("msiof1", 208, R8A7792_CLK_MP), DEF_MOD("sys-dmac1", 218, R8A7792_CLK_ZS), DEF_MOD("sys-dmac0", 219, R8A7792_CLK_ZS), diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c index d05f89deb1..790bc1bbd9 100644 --- a/drivers/clk/renesas/r8a7794-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c @@ -97,7 +97,7 @@ static const struct mssr_mod_clk r8a7794_mod_clks[] = { DEF_MOD("cmt0", 124, R8A7794_CLK_R), DEF_MOD("tmu0", 125, R8A7794_CLK_CP), DEF_MOD("vsp1du0", 128, R8A7794_CLK_ZS), - DEF_MOD("vsp1-sy", 131, R8A7794_CLK_ZS), + DEF_MOD("vsps", 131, R8A7794_CLK_ZS), DEF_MOD("scifa2", 202, R8A7794_CLK_MP), DEF_MOD("scifa1", 203, R8A7794_CLK_MP), DEF_MOD("scifa0", 204, R8A7794_CLK_MP), diff --git a/drivers/clk/renesas/rcar-gen2-cpg.h b/drivers/clk/renesas/rcar-gen2-cpg.h index 913c932620..2739480dad 100644 --- a/drivers/clk/renesas/rcar-gen2-cpg.h +++ b/drivers/clk/renesas/rcar-gen2-cpg.h @@ -1,11 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * R-Car Gen2 Clock Pulse Generator * * Copyright (C) 2016 Cogent Embedded Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation; version 2 of the License. */
#ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__
Synchronize R-Car Gen3 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- drivers/clk/renesas/r8a7795-cpg-mssr.c | 58 ++++++----- drivers/clk/renesas/r8a7796-cpg-mssr.c | 58 +++++++---- drivers/clk/renesas/r8a77965-cpg-mssr.c | 58 +++++++---- drivers/clk/renesas/r8a77970-cpg-mssr.c | 132 ++++++++++++------------ drivers/clk/renesas/r8a77990-cpg-mssr.c | 37 ++++--- drivers/clk/renesas/r8a77995-cpg-mssr.c | 16 +-- drivers/clk/renesas/rcar-gen3-cpg.h | 16 +-- 7 files changed, 212 insertions(+), 163 deletions(-)
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index b137564962..ca74250276 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -41,8 +41,8 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC, - CLK_RPCSRC, CLK_SSPSRC, + CLK_RPCSRC, CLK_RINT,
/* Module Clocks */ @@ -69,13 +69,18 @@ static const struct cpg_core_clk r8a7795_core_clks[] = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), - DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), + + DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC, + CLK_RPCSRC), + DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, + R8A7795_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */ - DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), - DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), + DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), + DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), @@ -102,8 +107,6 @@ static const struct cpg_core_clk r8a7795_core_clks[] = { DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268), DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
- DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238), - DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1), DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1), @@ -132,14 +135,15 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = { DEF_MOD("msiof2", 209, R8A7795_CLK_MSO), DEF_MOD("msiof1", 210, R8A7795_CLK_MSO), DEF_MOD("msiof0", 211, R8A7795_CLK_MSO), - DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3), - DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3), + DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1), + DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1), DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3), DEF_MOD("sceg-pub", 229, R8A7795_CLK_CR), DEF_MOD("cmt3", 300, R8A7795_CLK_R), DEF_MOD("cmt2", 301, R8A7795_CLK_R), DEF_MOD("cmt1", 302, R8A7795_CLK_R), DEF_MOD("cmt0", 303, R8A7795_CLK_R), + DEF_MOD("tpu0", 304, R8A7795_CLK_S3D4), DEF_MOD("scif2", 310, R8A7795_CLK_S3D4), DEF_MOD("sdif3", 311, R8A7795_CLK_SD3), DEF_MOD("sdif2", 312, R8A7795_CLK_SD2), @@ -156,16 +160,16 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = { DEF_MOD("rwdt", 402, R8A7795_CLK_R), DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3), - DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3), - DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3), - DEF_MOD("drif7", 508, R8A7795_CLK_S3D2), - DEF_MOD("drif6", 509, R8A7795_CLK_S3D2), - DEF_MOD("drif5", 510, R8A7795_CLK_S3D2), - DEF_MOD("drif4", 511, R8A7795_CLK_S3D2), - DEF_MOD("drif3", 512, R8A7795_CLK_S3D2), - DEF_MOD("drif2", 513, R8A7795_CLK_S3D2), - DEF_MOD("drif1", 514, R8A7795_CLK_S3D2), - DEF_MOD("drif0", 515, R8A7795_CLK_S3D2), + DEF_MOD("audmac1", 501, R8A7795_CLK_S1D2), + DEF_MOD("audmac0", 502, R8A7795_CLK_S1D2), + DEF_MOD("drif31", 508, R8A7795_CLK_S3D2), + DEF_MOD("drif30", 509, R8A7795_CLK_S3D2), + DEF_MOD("drif21", 510, R8A7795_CLK_S3D2), + DEF_MOD("drif20", 511, R8A7795_CLK_S3D2), + DEF_MOD("drif11", 512, R8A7795_CLK_S3D2), + DEF_MOD("drif10", 513, R8A7795_CLK_S3D2), + DEF_MOD("drif01", 514, R8A7795_CLK_S3D2), + DEF_MOD("drif00", 515, R8A7795_CLK_S3D2), DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1), DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1), DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1), @@ -197,12 +201,16 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = { DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */ DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1), DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1), - DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4), - DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4), - DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4), - DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4), - DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4), - DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4), + DEF_MOD("ehci3", 700, R8A7795_CLK_S3D2), + DEF_MOD("ehci2", 701, R8A7795_CLK_S3D2), + DEF_MOD("ehci1", 702, R8A7795_CLK_S3D2), + DEF_MOD("ehci0", 703, R8A7795_CLK_S3D2), + DEF_MOD("hsusb", 704, R8A7795_CLK_S3D2), + DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D2), + DEF_MOD("cmm3", 708, R8A7795_CLK_S2D1), + DEF_MOD("cmm2", 709, R8A7795_CLK_S2D1), + DEF_MOD("cmm1", 710, R8A7795_CLK_S2D1), + DEF_MOD("cmm0", 711, R8A7795_CLK_S2D1), DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */ DEF_MOD("csi20", 714, R8A7795_CLK_CSI0), DEF_MOD("csi41", 715, R8A7795_CLK_CSI0), @@ -239,7 +247,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = { DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2), DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4), DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4), - DEF_MOD("rpc", 917, R8A7795_CLK_RPC), + DEF_MOD("rpc-if", 917, R8A7795_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6), DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6), DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP), diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 6745305a59..2e9a8b6448 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -47,8 +47,8 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC, - CLK_RPCSRC, CLK_SSPSRC, + CLK_RPCSRC, CLK_RINT,
/* Module Clocks */ @@ -75,13 +75,18 @@ static const struct cpg_core_clk r8a7796_core_clks[] = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), - DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), + + DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC, + CLK_RPCSRC), + DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, + R8A7796_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */ - DEF_BASE("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), - DEF_BASE("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), + DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), + DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1), @@ -108,9 +113,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] = { DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268), DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
- DEF_GEN3_RPC("rpc", R8A7796_CLK_RPC, CLK_RPCSRC, 0x238), - DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1), + DEF_FIXED("cr", R8A7796_CLK_CR, CLK_PLL1_DIV4, 2, 1), DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cpex", R8A7796_CLK_CPEX, CLK_EXTAL, 2, 1),
@@ -126,6 +130,11 @@ static const struct cpg_core_clk r8a7796_core_clks[] = {
static const struct mssr_mod_clk r8a7796_mod_clks[] = { DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1), + DEF_MOD("tmu4", 121, R8A7796_CLK_S0D6), + DEF_MOD("tmu3", 122, R8A7796_CLK_S3D2), + DEF_MOD("tmu2", 123, R8A7796_CLK_S3D2), + DEF_MOD("tmu1", 124, R8A7796_CLK_S3D2), + DEF_MOD("tmu0", 125, R8A7796_CLK_CP), DEF_MOD("scif5", 202, R8A7796_CLK_S3D4), DEF_MOD("scif4", 203, R8A7796_CLK_S3D4), DEF_MOD("scif3", 204, R8A7796_CLK_S3D4), @@ -135,13 +144,15 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = { DEF_MOD("msiof2", 209, R8A7796_CLK_MSO), DEF_MOD("msiof1", 210, R8A7796_CLK_MSO), DEF_MOD("msiof0", 211, R8A7796_CLK_MSO), - DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3), - DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3), + DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S3D1), + DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S3D1), DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3), + DEF_MOD("sceg-pub", 229, R8A7796_CLK_CR), DEF_MOD("cmt3", 300, R8A7796_CLK_R), DEF_MOD("cmt2", 301, R8A7796_CLK_R), DEF_MOD("cmt1", 302, R8A7796_CLK_R), DEF_MOD("cmt0", 303, R8A7796_CLK_R), + DEF_MOD("tpu0", 304, R8A7796_CLK_S3D4), DEF_MOD("scif2", 310, R8A7796_CLK_S3D4), DEF_MOD("sdif3", 311, R8A7796_CLK_SD3), DEF_MOD("sdif2", 312, R8A7796_CLK_SD2), @@ -155,16 +166,16 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = { DEF_MOD("rwdt", 402, R8A7796_CLK_R), DEF_MOD("intc-ex", 407, R8A7796_CLK_CP), DEF_MOD("intc-ap", 408, R8A7796_CLK_S0D3), - DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3), - DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3), - DEF_MOD("drif7", 508, R8A7796_CLK_S3D2), - DEF_MOD("drif6", 509, R8A7796_CLK_S3D2), - DEF_MOD("drif5", 510, R8A7796_CLK_S3D2), - DEF_MOD("drif4", 511, R8A7796_CLK_S3D2), - DEF_MOD("drif3", 512, R8A7796_CLK_S3D2), - DEF_MOD("drif2", 513, R8A7796_CLK_S3D2), - DEF_MOD("drif1", 514, R8A7796_CLK_S3D2), - DEF_MOD("drif0", 515, R8A7796_CLK_S3D2), + DEF_MOD("audmac1", 501, R8A7796_CLK_S1D2), + DEF_MOD("audmac0", 502, R8A7796_CLK_S1D2), + DEF_MOD("drif31", 508, R8A7796_CLK_S3D2), + DEF_MOD("drif30", 509, R8A7796_CLK_S3D2), + DEF_MOD("drif21", 510, R8A7796_CLK_S3D2), + DEF_MOD("drif20", 511, R8A7796_CLK_S3D2), + DEF_MOD("drif11", 512, R8A7796_CLK_S3D2), + DEF_MOD("drif10", 513, R8A7796_CLK_S3D2), + DEF_MOD("drif01", 514, R8A7796_CLK_S3D2), + DEF_MOD("drif00", 515, R8A7796_CLK_S3D2), DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1), DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1), DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1), @@ -185,9 +196,12 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = { DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2), DEF_MOD("vspb", 626, R8A7796_CLK_S0D1), DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1), - DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4), - DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4), - DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4), + DEF_MOD("ehci1", 702, R8A7796_CLK_S3D2), + DEF_MOD("ehci0", 703, R8A7796_CLK_S3D2), + DEF_MOD("hsusb", 704, R8A7796_CLK_S3D2), + DEF_MOD("cmm2", 709, R8A7796_CLK_S2D1), + DEF_MOD("cmm1", 710, R8A7796_CLK_S2D1), + DEF_MOD("cmm0", 711, R8A7796_CLK_S2D1), DEF_MOD("csi20", 714, R8A7796_CLK_CSI0), DEF_MOD("csi40", 716, R8A7796_CLK_CSI0), DEF_MOD("du2", 722, R8A7796_CLK_S2D1), @@ -217,7 +231,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = { DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2), DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4), DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4), - DEF_MOD("rpc", 917, R8A7796_CLK_RPC), + DEF_MOD("rpc-if", 917, R8A7796_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6), DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6), DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP), diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index 8d792bceee..a839ffa41f 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -41,8 +41,8 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC, - CLK_RPCSRC, CLK_SSPSRC, + CLK_RPCSRC, CLK_RINT,
/* Module Clocks */ @@ -68,12 +68,17 @@ static const struct cpg_core_clk r8a77965_core_clks[] = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), - DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), + + DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC, + CLK_RPCSRC), + DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, + R8A77965_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */ - DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), + DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1), @@ -100,9 +105,8 @@ static const struct cpg_core_clk r8a77965_core_clks[] = { DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268), DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c),
- DEF_GEN3_RPC("rpc", R8A77965_CLK_RPC, CLK_RPCSRC, 0x238), - - DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1), + DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1), + DEF_FIXED("cr", R8A77965_CLK_CR, CLK_PLL1_DIV4, 2, 1), DEF_FIXED("cp", R8A77965_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cpex", R8A77965_CLK_CPEX, CLK_EXTAL, 2, 1),
@@ -118,6 +122,11 @@ static const struct cpg_core_clk r8a77965_core_clks[] = {
static const struct mssr_mod_clk r8a77965_mod_clks[] = { DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1), + DEF_MOD("tmu4", 121, R8A77965_CLK_S0D6), + DEF_MOD("tmu3", 122, R8A77965_CLK_S3D2), + DEF_MOD("tmu2", 123, R8A77965_CLK_S3D2), + DEF_MOD("tmu1", 124, R8A77965_CLK_S3D2), + DEF_MOD("tmu0", 125, R8A77965_CLK_CP), DEF_MOD("scif5", 202, R8A77965_CLK_S3D4), DEF_MOD("scif4", 203, R8A77965_CLK_S3D4), DEF_MOD("scif3", 204, R8A77965_CLK_S3D4), @@ -127,14 +136,16 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = { DEF_MOD("msiof2", 209, R8A77965_CLK_MSO), DEF_MOD("msiof1", 210, R8A77965_CLK_MSO), DEF_MOD("msiof0", 211, R8A77965_CLK_MSO), - DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S0D3), - DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3), + DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S3D1), + DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S3D1), DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3), + DEF_MOD("sceg-pub", 229, R8A77965_CLK_CR),
DEF_MOD("cmt3", 300, R8A77965_CLK_R), DEF_MOD("cmt2", 301, R8A77965_CLK_R), DEF_MOD("cmt1", 302, R8A77965_CLK_R), DEF_MOD("cmt0", 303, R8A77965_CLK_R), + DEF_MOD("tpu0", 304, R8A77965_CLK_S3D4), DEF_MOD("scif2", 310, R8A77965_CLK_S3D4), DEF_MOD("sdif3", 311, R8A77965_CLK_SD3), DEF_MOD("sdif2", 312, R8A77965_CLK_SD2), @@ -150,16 +161,16 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = { DEF_MOD("intc-ex", 407, R8A77965_CLK_CP), DEF_MOD("intc-ap", 408, R8A77965_CLK_S0D3),
- DEF_MOD("audmac1", 501, R8A77965_CLK_S0D3), - DEF_MOD("audmac0", 502, R8A77965_CLK_S0D3), - DEF_MOD("drif7", 508, R8A77965_CLK_S3D2), - DEF_MOD("drif6", 509, R8A77965_CLK_S3D2), - DEF_MOD("drif5", 510, R8A77965_CLK_S3D2), - DEF_MOD("drif4", 511, R8A77965_CLK_S3D2), - DEF_MOD("drif3", 512, R8A77965_CLK_S3D2), - DEF_MOD("drif2", 513, R8A77965_CLK_S3D2), - DEF_MOD("drif1", 514, R8A77965_CLK_S3D2), - DEF_MOD("drif0", 515, R8A77965_CLK_S3D2), + DEF_MOD("audmac1", 501, R8A77965_CLK_S1D2), + DEF_MOD("audmac0", 502, R8A77965_CLK_S1D2), + DEF_MOD("drif31", 508, R8A77965_CLK_S3D2), + DEF_MOD("drif30", 509, R8A77965_CLK_S3D2), + DEF_MOD("drif21", 510, R8A77965_CLK_S3D2), + DEF_MOD("drif20", 511, R8A77965_CLK_S3D2), + DEF_MOD("drif11", 512, R8A77965_CLK_S3D2), + DEF_MOD("drif10", 513, R8A77965_CLK_S3D2), + DEF_MOD("drif01", 514, R8A77965_CLK_S3D2), + DEF_MOD("drif00", 515, R8A77965_CLK_S3D2), DEF_MOD("hscif4", 516, R8A77965_CLK_S3D1), DEF_MOD("hscif3", 517, R8A77965_CLK_S3D1), DEF_MOD("hscif2", 518, R8A77965_CLK_S3D1), @@ -179,9 +190,12 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = { DEF_MOD("vspb", 626, R8A77965_CLK_S0D1), DEF_MOD("vspi0", 631, R8A77965_CLK_S0D1),
- DEF_MOD("ehci1", 702, R8A77965_CLK_S3D4), - DEF_MOD("ehci0", 703, R8A77965_CLK_S3D4), - DEF_MOD("hsusb", 704, R8A77965_CLK_S3D4), + DEF_MOD("ehci1", 702, R8A77965_CLK_S3D2), + DEF_MOD("ehci0", 703, R8A77965_CLK_S3D2), + DEF_MOD("hsusb", 704, R8A77965_CLK_S3D2), + DEF_MOD("cmm3", 708, R8A77965_CLK_S2D1), + DEF_MOD("cmm1", 710, R8A77965_CLK_S2D1), + DEF_MOD("cmm0", 711, R8A77965_CLK_S2D1), DEF_MOD("csi20", 714, R8A77965_CLK_CSI0), DEF_MOD("csi40", 716, R8A77965_CLK_CSI0), DEF_MOD("du3", 721, R8A77965_CLK_S2D1), @@ -214,7 +228,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = { DEF_MOD("can-fd", 914, R8A77965_CLK_S3D2), DEF_MOD("can-if1", 915, R8A77965_CLK_S3D4), DEF_MOD("can-if0", 916, R8A77965_CLK_S3D4), - DEF_MOD("rpc", 917, R8A77965_CLK_RPC), + DEF_MOD("rpc-if", 917, R8A77965_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A77965_CLK_S0D6), DEF_MOD("i2c5", 919, R8A77965_CLK_S0D6), DEF_MOD("i2c-dvfs", 926, R8A77965_CLK_CP), diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c index b2b32be946..3b84c658f7 100644 --- a/drivers/clk/renesas/r8a77970-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c @@ -20,6 +20,13 @@ #include "renesas-cpg-mssr.h" #include "rcar-gen3-cpg.h"
+#define CPG_SD0CKCR 0x0074 + +enum r8a77970_clk_types { + CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE, + CLK_TYPE_R8A77970_SD0, +}; + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A77970_CLK_OSC, @@ -32,24 +39,9 @@ enum clk_ids { CLK_MAIN, CLK_PLL0, CLK_PLL1, - CLK_PLL2, CLK_PLL3, - CLK_PLL4, CLK_PLL1_DIV2, CLK_PLL1_DIV4, - CLK_PLL0D2, - CLK_PLL0D3, - CLK_PLL0D5, - CLK_PLL1D2, - CLK_PE, - CLK_S0, - CLK_S1, - CLK_S2, - CLK_S3, - CLK_SDSRC, - CLK_RPCSRC, - CLK_SSPSRC, - CLK_RINT,
/* Module Clocks */ MOD_CLK_BASE @@ -57,67 +49,80 @@ enum clk_ids {
static const struct cpg_core_clk r8a77970_core_clks[] = { /* External Clock Inputs */ - DEF_INPUT("extal", CLK_EXTAL), - DEF_INPUT("extalr", CLK_EXTALR), + DEF_INPUT("extal", CLK_EXTAL), + DEF_INPUT("extalr", CLK_EXTALR),
/* Internal Core Clocks */ - DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), - DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), - DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), - DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), + DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
- DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), - DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), - DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 4, 1), - DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 6, 1), - DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), + DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
/* Core Clock Outputs */ - DEF_BASE("z2", R8A77970_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL1_DIV4), - DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), - DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), - DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1), - DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1), - DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_S1, 1, 1), - DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_S1, 2, 1), - DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_S1, 4, 1), - DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_S2, 1, 1), - DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_S2, 2, 1), - DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_S2, 4, 1), - - DEF_GEN3_SD("sd0", R8A77970_CLK_SD0, CLK_PLL1_DIV4, 0x0074), - - DEF_GEN3_RPC("rpc", R8A77970_CLK_RPC, CLK_RPCSRC, 0x238), - - DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1), - DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1), - - /* NOTE: HDMI, CSI, CAN etc. clock are missing */ - - DEF_BASE("r", R8A77970_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), + DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), + DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), + DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1), + DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_PLL1_DIV2, 8, 1), + DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_PLL1_DIV2, 16, 1), + DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_PLL1_DIV2, 6, 1), + DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_PLL1_DIV2, 12, 1), + DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_PLL1_DIV2, 24, 1), + + DEF_BASE("sd0h", R8A77970_CLK_SD0H, CLK_TYPE_R8A77970_SD0H, + CLK_PLL1_DIV2), + DEF_BASE("sd0", R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2), + + DEF_FIXED("rpc", R8A77970_CLK_RPC, CLK_PLL1_DIV2, 5, 1), + DEF_FIXED("rpcd2", R8A77970_CLK_RPCD2, CLK_PLL1_DIV2, 10, 1), + + DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1), + DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1), + DEF_FIXED("cpex", R8A77970_CLK_CPEX, CLK_EXTAL, 2, 1), + + DEF_DIV6P1("canfd", R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244), + DEF_DIV6P1("mso", R8A77970_CLK_MSO, CLK_PLL1_DIV4, 0x014), + DEF_DIV6P1("csi0", R8A77970_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), + + DEF_FIXED("osc", R8A77970_CLK_OSC, CLK_PLL1_DIV2, 12*1024, 1), + DEF_FIXED("r", R8A77970_CLK_R, CLK_EXTALR, 1, 1), };
static const struct mssr_mod_clk r8a77970_mod_clks[] = { + DEF_MOD("tmu4", 121, R8A77970_CLK_S2D2), + DEF_MOD("tmu3", 122, R8A77970_CLK_S2D2), + DEF_MOD("tmu2", 123, R8A77970_CLK_S2D2), + DEF_MOD("tmu1", 124, R8A77970_CLK_S2D2), + DEF_MOD("tmu0", 125, R8A77970_CLK_CP), DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1), - DEF_MOD("scif4", 203, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */ - DEF_MOD("scif3", 204, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */ - DEF_MOD("scif1", 206, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */ - DEF_MOD("scif0", 207, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */ + DEF_MOD("scif4", 203, R8A77970_CLK_S2D4), + DEF_MOD("scif3", 204, R8A77970_CLK_S2D4), + DEF_MOD("scif1", 206, R8A77970_CLK_S2D4), + DEF_MOD("scif0", 207, R8A77970_CLK_S2D4), DEF_MOD("msiof3", 208, R8A77970_CLK_MSO), DEF_MOD("msiof2", 209, R8A77970_CLK_MSO), DEF_MOD("msiof1", 210, R8A77970_CLK_MSO), DEF_MOD("msiof0", 211, R8A77970_CLK_MSO), - DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), /* @@ H3=S3D2 */ - DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ - DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ - DEF_MOD("sdif", 314, R8A77970_CLK_SD0), - DEF_MOD("rwdt0", 402, R8A77970_CLK_R), + DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), + DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), + DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), + DEF_MOD("cmt3", 300, R8A77970_CLK_R), + DEF_MOD("cmt2", 301, R8A77970_CLK_R), + DEF_MOD("cmt1", 302, R8A77970_CLK_R), + DEF_MOD("cmt0", 303, R8A77970_CLK_R), + DEF_MOD("tpu0", 304, R8A77970_CLK_S2D4), + DEF_MOD("sd-if", 314, R8A77970_CLK_SD0), + DEF_MOD("rwdt", 402, R8A77970_CLK_R), DEF_MOD("intc-ex", 407, R8A77970_CLK_CP), - DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ - DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ - DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ - DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ - DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ + DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), + DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1), + DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1), + DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1), + DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1), DEF_MOD("thermal", 522, R8A77970_CLK_CP), DEF_MOD("pwm", 523, R8A77970_CLK_S2D4), DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1), @@ -130,7 +135,6 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] = { DEF_MOD("vin1", 810, R8A77970_CLK_S2D1), DEF_MOD("vin0", 811, R8A77970_CLK_S2D1), DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2), - DEF_MOD("isp", 817, R8A77970_CLK_S2D1), DEF_MOD("gpio5", 907, R8A77970_CLK_CP), DEF_MOD("gpio4", 908, R8A77970_CLK_CP), DEF_MOD("gpio3", 909, R8A77970_CLK_CP), @@ -138,7 +142,7 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] = { DEF_MOD("gpio1", 911, R8A77970_CLK_CP), DEF_MOD("gpio0", 912, R8A77970_CLK_CP), DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2), - DEF_MOD("rpc", 917, R8A77970_CLK_RPC), + DEF_MOD("rpc-if", 917, R8A77970_CLK_RPC), DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2), DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2), DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2), diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index e983296b3a..504dc871d1 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -44,7 +44,6 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC, - CLK_RPCSRC, CLK_RINT, CLK_OCO,
@@ -74,7 +73,6 @@ static const struct cpg_core_clk r8a77990_core_clks[] = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), - DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
@@ -83,6 +81,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] = { /* Core Clock Outputs */ DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1), DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1), + DEF_GEN3_Z("z2", R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8), DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1), DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1), DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1), @@ -105,9 +104,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] = { DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, CLK_SDSRC, 0x0078), DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c),
- DEF_GEN3_RPC("rpc", R8A77990_CLK_RPC, CLK_RPCSRC, 0x238), - DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1), + DEF_FIXED("cr", R8A77990_CLK_CR, CLK_PLL1D2, 2, 1), DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1),
@@ -126,6 +124,11 @@ static const struct cpg_core_clk r8a77990_core_clks[] = { };
static const struct mssr_mod_clk r8a77990_mod_clks[] = { + DEF_MOD("tmu4", 121, R8A77990_CLK_S0D6C), + DEF_MOD("tmu3", 122, R8A77990_CLK_S3D2C), + DEF_MOD("tmu2", 123, R8A77990_CLK_S3D2C), + DEF_MOD("tmu1", 124, R8A77990_CLK_S3D2C), + DEF_MOD("tmu0", 125, R8A77990_CLK_CP), DEF_MOD("scif5", 202, R8A77990_CLK_S3D4C), DEF_MOD("scif4", 203, R8A77990_CLK_S3D4C), DEF_MOD("scif3", 204, R8A77990_CLK_S3D4C), @@ -138,6 +141,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = { DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1), DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1), DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1), + DEF_MOD("sceg-pub", 229, R8A77990_CLK_CR),
DEF_MOD("cmt3", 300, R8A77990_CLK_R), DEF_MOD("cmt2", 301, R8A77990_CLK_R), @@ -156,15 +160,15 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = { DEF_MOD("intc-ex", 407, R8A77990_CLK_CP), DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3),
- DEF_MOD("audmac0", 502, R8A77990_CLK_S3D4), - DEF_MOD("drif7", 508, R8A77990_CLK_S3D2), - DEF_MOD("drif6", 509, R8A77990_CLK_S3D2), - DEF_MOD("drif5", 510, R8A77990_CLK_S3D2), - DEF_MOD("drif4", 511, R8A77990_CLK_S3D2), - DEF_MOD("drif3", 512, R8A77990_CLK_S3D2), - DEF_MOD("drif2", 513, R8A77990_CLK_S3D2), - DEF_MOD("drif1", 514, R8A77990_CLK_S3D2), - DEF_MOD("drif0", 515, R8A77990_CLK_S3D2), + DEF_MOD("audmac0", 502, R8A77990_CLK_S1D2), + DEF_MOD("drif31", 508, R8A77990_CLK_S3D2), + DEF_MOD("drif30", 509, R8A77990_CLK_S3D2), + DEF_MOD("drif21", 510, R8A77990_CLK_S3D2), + DEF_MOD("drif20", 511, R8A77990_CLK_S3D2), + DEF_MOD("drif11", 512, R8A77990_CLK_S3D2), + DEF_MOD("drif10", 513, R8A77990_CLK_S3D2), + DEF_MOD("drif01", 514, R8A77990_CLK_S3D2), + DEF_MOD("drif00", 515, R8A77990_CLK_S3D2), DEF_MOD("hscif4", 516, R8A77990_CLK_S3D1C), DEF_MOD("hscif3", 517, R8A77990_CLK_S3D1C), DEF_MOD("hscif2", 518, R8A77990_CLK_S3D1C), @@ -184,8 +188,10 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = { DEF_MOD("vspb", 626, R8A77990_CLK_S0D1), DEF_MOD("vspi0", 631, R8A77990_CLK_S0D1),
- DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4), - DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4), + DEF_MOD("ehci0", 703, R8A77990_CLK_S3D2), + DEF_MOD("hsusb", 704, R8A77990_CLK_S3D2), + DEF_MOD("cmm1", 710, R8A77990_CLK_S1D1), + DEF_MOD("cmm0", 711, R8A77990_CLK_S1D1), DEF_MOD("csi40", 716, R8A77990_CLK_CSI0), DEF_MOD("du1", 723, R8A77990_CLK_S1D1), DEF_MOD("du0", 724, R8A77990_CLK_S1D1), @@ -205,7 +211,6 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = { DEF_MOD("can-fd", 914, R8A77990_CLK_S3D2), DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4), DEF_MOD("can-if0", 916, R8A77990_CLK_S3D4), - DEF_MOD("rpc", 917, R8A77990_CLK_RPC), DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2), DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2), DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP), diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index fb1df6d10e..58dc295d6a 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -42,7 +42,6 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC, - CLK_RPCSRC, CLK_RINT, CLK_OCO,
@@ -70,7 +69,6 @@ static const struct cpg_core_clk r8a77995_core_clks[] = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), - DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
@@ -93,13 +91,12 @@ static const struct cpg_core_clk r8a77995_core_clks[] = { DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1),
DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1), + DEF_FIXED("cr", R8A77995_CLK_CR, CLK_PLL1D2, 2, 1), DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cpex", R8A77995_CLK_CPEX, CLK_EXTAL, 4, 1),
DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
- DEF_GEN3_RPC("rpc", R8A77995_CLK_RPC, CLK_RPCSRC, 0x238), - DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2), DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1), DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2), @@ -114,6 +111,11 @@ static const struct cpg_core_clk r8a77995_core_clks[] = { };
static const struct mssr_mod_clk r8a77995_mod_clks[] = { + DEF_MOD("tmu4", 121, R8A77995_CLK_S1D4C), + DEF_MOD("tmu3", 122, R8A77995_CLK_S3D2C), + DEF_MOD("tmu2", 123, R8A77995_CLK_S3D2C), + DEF_MOD("tmu1", 124, R8A77995_CLK_S3D2C), + DEF_MOD("tmu0", 125, R8A77995_CLK_CP), DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C), DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C), DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C), @@ -126,6 +128,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = { DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1), DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1), DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1), + DEF_MOD("sceg-pub", 229, R8A77995_CLK_CR), DEF_MOD("cmt3", 300, R8A77995_CLK_R), DEF_MOD("cmt2", 301, R8A77995_CLK_R), DEF_MOD("cmt1", 302, R8A77995_CLK_R), @@ -137,7 +140,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = { DEF_MOD("rwdt", 402, R8A77995_CLK_R), DEF_MOD("intc-ex", 407, R8A77995_CLK_CP), DEF_MOD("intc-ap", 408, R8A77995_CLK_S1D2), - DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1), + DEF_MOD("audmac0", 502, R8A77995_CLK_S1D2), DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C), DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C), DEF_MOD("thermal", 522, R8A77995_CLK_CP), @@ -150,6 +153,8 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = { DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1), DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2), DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2), + DEF_MOD("cmm1", 710, R8A77995_CLK_S1D1), + DEF_MOD("cmm0", 711, R8A77995_CLK_S1D1), DEF_MOD("du1", 723, R8A77995_CLK_S1D1), DEF_MOD("du0", 724, R8A77995_CLK_S1D1), DEF_MOD("lvds", 727, R8A77995_CLK_S2D1), @@ -166,7 +171,6 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = { DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2), DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4), DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4), - DEF_MOD("rpc", 917, R8A77995_CLK_RPC), DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2), DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2), DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2), diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 3beae7d825..8265c96cf6 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -1,11 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * R-Car Gen3 Clock Pulse Generator * - * Copyright (C) 2015-2016 Glider bvba + * Copyright (C) 2015-2018 Glider bvba + * Copyright (C) 2018 Renesas Electronics Corp. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. */
#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__ @@ -22,10 +21,10 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_R, CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */ CLK_TYPE_GEN3_Z, - CLK_TYPE_GEN3_Z2, CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ CLK_TYPE_GEN3_RPCSRC, + CLK_TYPE_GEN3_E3_RPCSRC, CLK_TYPE_GEN3_RPC, CLK_TYPE_GEN3_RPCD2,
@@ -36,9 +35,6 @@ enum rcar_gen3_clk_types { #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
-#define DEF_GEN3_RPC(_name, _id, _parent, _offset) \ - DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset) - #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \ (_parent0) << 16 | (_parent1), \ @@ -59,6 +55,10 @@ enum rcar_gen3_clk_types { #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
+#define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \ + (_parent0) << 16 | (_parent1), .div = 8) + struct rcar_gen3_cpg_pll_config { u8 extal_div; u8 pll1_mult;
Reinstate RPC clock on D3/E3 after Linux 5.12 synchronization. The D3 and E3 clock drivers do not contain RPC clock entries mainline Linux yet.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- drivers/clk/renesas/r8a77990-cpg-mssr.c | 9 +++++++++ drivers/clk/renesas/r8a77995-cpg-mssr.c | 9 +++++++++ 2 files changed, 18 insertions(+)
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index 504dc871d1..d953c0b421 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -44,6 +44,7 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC, + CLK_RPCSRC, CLK_RINT, CLK_OCO,
@@ -74,6 +75,13 @@ static const struct cpg_core_clk r8a77990_core_clks[] = { DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
+ DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1), + + DEF_BASE("rpc", R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC, + CLK_RPCSRC), + DEF_BASE("rpcd2", R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, + R8A77990_CLK_RPC), + DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000), @@ -211,6 +219,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = { DEF_MOD("can-fd", 914, R8A77990_CLK_S3D2), DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4), DEF_MOD("can-if0", 916, R8A77990_CLK_S3D4), + DEF_MOD("rpc", 917, R8A77990_CLK_RPC), DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2), DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2), DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP), diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index 58dc295d6a..0771c48964 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -42,6 +42,7 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC, + CLK_RPCSRC, CLK_RINT, CLK_OCO,
@@ -70,6 +71,13 @@ static const struct cpg_core_clk r8a77995_core_clks[] = { DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
+ DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1), + + DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC, + CLK_RPCSRC), + DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, + R8A77995_CLK_RPC), + DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000), @@ -171,6 +179,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = { DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2), DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4), DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4), + DEF_MOD("rpc", 917, R8A77995_CLK_RPC), DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2), DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2), DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
From: Hai Pham hai.pham.ud@renesas.com
RPC clk_get_rate will return error code instead of expected clock rate. Fix this.
Signed-off-by: Hai Pham hai.pham.ud@renesas.com Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- drivers/clk/renesas/clk-rcar-gen3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 3223becd75..09d84c44e1 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -310,7 +310,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk) __func__, __LINE__, core->parent, prediv, postdiv, rate);
- return -EINVAL; + return rate;
}
Hi Marek,
Thank you for the patch.
On Wed, Apr 28, 2021 at 8:31 PM Marek Vasut marek.vasut@gmail.com wrote:
From: Hai Pham hai.pham.ud@renesas.com
RPC clk_get_rate will return error code instead of expected clock rate. Fix this.
Signed-off-by: Hai Pham hai.pham.ud@renesas.com Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com
drivers/clk/renesas/clk-rcar-gen3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Tested on RZ/G2E board
Tested-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
Cheers, Prabhakar
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 3223becd75..09d84c44e1 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -310,7 +310,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk) __func__, __LINE__, core->parent, prediv, postdiv, rate);
return -EINVAL;
return rate; }-- 2.30.2
From: Hai Pham hai.pham.ud@renesas.com
This patch fixes Realtime Module Stop Control Register (RMSTPCR) offsets based on R-Car Gen3, H2/M2/M2N/E2/E2X hardware user's manual. The r8a73a4 only has RMSTPCR0 - RMSTPCR5 so this calculation change doesn't affect it.
Signed-off-by: Hai Pham hai.pham.ud@renesas.com Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- drivers/clk/renesas/renesas-cpg-mssr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index 7c1222f6c8..bed2a16448 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -55,7 +55,7 @@ static const u16 smstpcr[] = {
/* Realtime Module Stop Control Register offsets */ -#define RMSTPCR(i) (smstpcr[i] - 0x20) +#define RMSTPCR(i) ((i) < 8 ? smstpcr[i] - 0x20 : smstpcr[i] - 0x10)
/* Modem Module Stop Control Register offsets (r8a73a4) */ #define MMSTPCR(i) (smstpcr[i] + 0x20)
From: Hai Pham hai.pham.ud@renesas.com
This supports RPCD2 clock handling. While at it, add the check point for RPC-IF clock RPCD2 Frequency Division Ratio, since it must be odd number
Signed-off-by: Hai Pham hai.pham.ud@renesas.com Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- drivers/clk/renesas/clk-rcar-gen3.c | 19 ++++++++++++++----- drivers/clk/renesas/rcar-gen3-cpg.h | 3 +++ 2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 09d84c44e1..763e268937 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -289,6 +289,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk) return -EINVAL;
case CLK_TYPE_GEN3_RPC: + case CLK_TYPE_GEN3_RPCD2: rate = gen3_clk_get_rate64(&parent);
value = readl(priv->base + core->offset); @@ -304,13 +305,21 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) & CPG_RPC_POSTDIV_MASK; - rate /= postdiv + 1;
- debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%llu\n", - __func__, __LINE__, - core->parent, prediv, postdiv, rate); + if (postdiv % 2 != 0) { + rate /= postdiv + 1;
- return rate; + if (core->type == CLK_TYPE_GEN3_RPCD2) + rate /= 2; + + debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%llu\n", + __func__, __LINE__, + core->parent, prediv, postdiv, rate); + + return rate; + } + + return -EINVAL;
}
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 8265c96cf6..52526a0cab 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -35,6 +35,9 @@ enum rcar_gen3_clk_types { #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
+#define DEF_GEN3_RPCD2(_name, _id, _parent, _offset) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPCD2, _parent, .offset = _offset) + #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \ (_parent0) << 16 | (_parent1), \
Hi Marek,
Thank you for the patch.
On Wed, Apr 28, 2021 at 8:30 PM Marek Vasut marek.vasut@gmail.com wrote:
From: Hai Pham hai.pham.ud@renesas.com
This supports RPCD2 clock handling. While at it, add the check point for RPC-IF clock RPCD2 Frequency Division Ratio, since it must be odd number
Signed-off-by: Hai Pham hai.pham.ud@renesas.com Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com
drivers/clk/renesas/clk-rcar-gen3.c | 19 ++++++++++++++----- drivers/clk/renesas/rcar-gen3-cpg.h | 3 +++ 2 files changed, 17 insertions(+), 5 deletions(-)
Tested on RZ/G2E board
Tested-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
Cheers, Prabhakar
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 09d84c44e1..763e268937 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -289,6 +289,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk) return -EINVAL;
case CLK_TYPE_GEN3_RPC:
case CLK_TYPE_GEN3_RPCD2: rate = gen3_clk_get_rate64(&parent); value = readl(priv->base + core->offset);@@ -304,13 +305,21 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) & CPG_RPC_POSTDIV_MASK;
rate /= postdiv + 1;debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%llu\n",__func__, __LINE__,core->parent, prediv, postdiv, rate);
if (postdiv % 2 != 0) {rate /= postdiv + 1;
return rate;
if (core->type == CLK_TYPE_GEN3_RPCD2)rate /= 2;debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%llu\n",__func__, __LINE__,core->parent, prediv, postdiv, rate);return rate;}return -EINVAL; }diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 8265c96cf6..52526a0cab 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -35,6 +35,9 @@ enum rcar_gen3_clk_types { #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
+#define DEF_GEN3_RPCD2(_name, _id, _parent, _offset) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPCD2, _parent, .offset = _offset)#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \ (_parent0) << 16 | (_parent1), \ -- 2.30.2
The MODEMR register offset changed on R8A779A0, make the MODEMR offset configurable. Fill the offset in on all clock drivers. No functional change.
Based off "clk: renesas: Make CPG Reset MODEMR offset accessible from struct cpg_mssr_info" by Hai Pham hai.pham.ud@renesas.com
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- drivers/clk/renesas/clk-rcar-gen2.c | 2 -- drivers/clk/renesas/clk-rcar-gen3.c | 4 +--- drivers/clk/renesas/r8a774a1-cpg-mssr.c | 1 + drivers/clk/renesas/r8a774b1-cpg-mssr.c | 1 + drivers/clk/renesas/r8a774c0-cpg-mssr.c | 1 + drivers/clk/renesas/r8a774e1-cpg-mssr.c | 1 + drivers/clk/renesas/r8a7790-cpg-mssr.c | 1 + drivers/clk/renesas/r8a7791-cpg-mssr.c | 1 + drivers/clk/renesas/r8a7792-cpg-mssr.c | 1 + drivers/clk/renesas/r8a7794-cpg-mssr.c | 1 + drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 + drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 + drivers/clk/renesas/r8a77965-cpg-mssr.c | 1 + drivers/clk/renesas/r8a77970-cpg-mssr.c | 1 + drivers/clk/renesas/r8a77980-cpg-mssr.c | 1 + drivers/clk/renesas/r8a77990-cpg-mssr.c | 1 + drivers/clk/renesas/r8a77995-cpg-mssr.c | 1 + drivers/clk/renesas/rcar-gen2-cpg.h | 2 ++ drivers/clk/renesas/rcar-gen3-cpg.h | 2 ++ drivers/clk/renesas/renesas-cpg-mssr.h | 1 + 20 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c index b423c9414b..b0164a6486 100644 --- a/drivers/clk/renesas/clk-rcar-gen2.c +++ b/drivers/clk/renesas/clk-rcar-gen2.c @@ -23,8 +23,6 @@ #include "renesas-cpg-mssr.h" #include "rcar-gen2-cpg.h"
-#define CPG_RST_MODEMR 0x0060 - #define CPG_PLL0CR 0x00d8 #define CPG_SDCKCR 0x0074
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 763e268937..938d98546b 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -25,8 +25,6 @@ #include "renesas-cpg-mssr.h" #include "rcar-gen3-cpg.h"
-#define CPG_RST_MODEMR 0x0060 - #define CPG_PLL0CR 0x00d8 #define CPG_PLL2CR 0x002c #define CPG_PLL4CR 0x01f4 @@ -382,7 +380,7 @@ int gen3_clk_probe(struct udevice *dev) if (rst_base == FDT_ADDR_T_NONE) return -EINVAL;
- cpg_mode = readl(rst_base + CPG_RST_MODEMR); + cpg_mode = readl(rst_base + info->reset_modemr_offset);
priv->cpg_pll_config = (struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode); diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index ef2bb6d777..48da65cd3d 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -321,6 +321,7 @@ static const struct cpg_mssr_info r8a774a1_cpg_mssr_info = { .mstp_table = r8a774a1_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a774a1_mstp_table), .reset_node = "renesas,r8a774a1-rst", + .reset_modemr_offset = CPG_RST_MODEMR, .extalr_node = "extalr", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c index a8b242dc47..418c393a20 100644 --- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c @@ -318,6 +318,7 @@ static const struct cpg_mssr_info r8a774b1_cpg_mssr_info = { .mstp_table = r8a774b1_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a774b1_mstp_table), .reset_node = "renesas,r8a774b1-rst", + .reset_modemr_offset = CPG_RST_MODEMR, .extalr_node = "extalr", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c index 6e9558a107..c1283d2614 100644 --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c @@ -292,6 +292,7 @@ const struct cpg_mssr_info r8a774c0_cpg_mssr_info = { .mstp_table = r8a774c0_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a774c0_mstp_table), .reset_node = "renesas,r8a774c0-rst", + .reset_modemr_offset = CPG_RST_MODEMR, .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, .clk_extalr_id = ~0, diff --git a/drivers/clk/renesas/r8a774e1-cpg-mssr.c b/drivers/clk/renesas/r8a774e1-cpg-mssr.c index c969ec6888..0cacd8d0c8 100644 --- a/drivers/clk/renesas/r8a774e1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774e1-cpg-mssr.c @@ -332,6 +332,7 @@ static const struct cpg_mssr_info r8a774e1_cpg_mssr_info = { .mstp_table = r8a774e1_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a774e1_mstp_table), .reset_node = "renesas,r8a774e1-rst", + .reset_modemr_offset = CPG_RST_MODEMR, .extalr_node = "extalr", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c b/drivers/clk/renesas/r8a7790-cpg-mssr.c index 8d616476c7..1f3477fa6e 100644 --- a/drivers/clk/renesas/r8a7790-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c @@ -263,6 +263,7 @@ static const struct cpg_mssr_info r8a7790_cpg_mssr_info = { .mstp_table = r8a7790_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a7790_mstp_table), .reset_node = "renesas,r8a7790-rst", + .reset_modemr_offset = CPG_RST_MODEMR, .extal_usb_node = "usb_extal", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c b/drivers/clk/renesas/r8a7791-cpg-mssr.c index 7a89613b32..fcca7be886 100644 --- a/drivers/clk/renesas/r8a7791-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c @@ -265,6 +265,7 @@ static const struct cpg_mssr_info r8a7791_cpg_mssr_info = { .mstp_table = r8a7791_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a7791_mstp_table), .reset_node = "renesas,r8a7791-rst", + .reset_modemr_offset = CPG_RST_MODEMR, .extal_usb_node = "usb_extal", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c index e18774dae4..5b333638ac 100644 --- a/drivers/clk/renesas/r8a7792-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c @@ -213,6 +213,7 @@ static const struct cpg_mssr_info r8a7792_cpg_mssr_info = { .mstp_table = r8a7792_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a7792_mstp_table), .reset_node = "renesas,r8a7792-rst", + .reset_modemr_offset = CPG_RST_MODEMR, .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, .pll0_div = 2, diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c index 790bc1bbd9..b9dd88de98 100644 --- a/drivers/clk/renesas/r8a7794-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c @@ -240,6 +240,7 @@ static const struct cpg_mssr_info r8a7794_cpg_mssr_info = { .mstp_table = r8a7794_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a7794_mstp_table), .reset_node = "renesas,r8a7794-rst", + .reset_modemr_offset = CPG_RST_MODEMR, .extal_usb_node = "usb_extal", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index ca74250276..6ba796b98c 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -362,6 +362,7 @@ static const struct cpg_mssr_info r8a7795_cpg_mssr_info = { .mstp_table = r8a7795_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a7795_mstp_table), .reset_node = "renesas,r8a7795-rst", + .reset_modemr_offset = CPG_RST_MODEMR, .extalr_node = "extalr", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 2e9a8b6448..e318719033 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -346,6 +346,7 @@ static const struct cpg_mssr_info r8a7796_cpg_mssr_info = { .mstp_table = r8a7796_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a7796_mstp_table), .reset_node = "renesas,r8a7796-rst", + .reset_modemr_offset = CPG_RST_MODEMR, .extalr_node = "extalr", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index a839ffa41f..0a15617da8 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -344,6 +344,7 @@ static const struct cpg_mssr_info r8a77965_cpg_mssr_info = { .mstp_table = r8a77965_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a77965_mstp_table), .reset_node = "renesas,r8a77965-rst", + .reset_modemr_offset = CPG_RST_MODEMR, .extalr_node = "extalr", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c index 3b84c658f7..a85bed6192 100644 --- a/drivers/clk/renesas/r8a77970-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c @@ -211,6 +211,7 @@ static const struct cpg_mssr_info r8a77970_cpg_mssr_info = { .mstp_table = r8a77970_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a77970_mstp_table), .reset_node = "renesas,r8a77970-rst", + .reset_modemr_offset = CPG_RST_MODEMR, .extalr_node = "extalr", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c index cf96309d12..bd9d7c9be5 100644 --- a/drivers/clk/renesas/r8a77980-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c @@ -230,6 +230,7 @@ static const struct cpg_mssr_info r8a77980_cpg_mssr_info = { .mstp_table = r8a77980_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a77980_mstp_table), .reset_node = "renesas,r8a77980-rst", + .reset_modemr_offset = CPG_RST_MODEMR, .extalr_node = "extalr", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index d953c0b421..67a1f586e2 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -304,6 +304,7 @@ static const struct cpg_mssr_info r8a77990_cpg_mssr_info = { .mstp_table = r8a77990_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a77990_mstp_table), .reset_node = "renesas,r8a77990-rst", + .reset_modemr_offset = CPG_RST_MODEMR, .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, .clk_extalr_id = ~0, diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index 0771c48964..83e8e9bfaa 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -242,6 +242,7 @@ static const struct cpg_mssr_info r8a77995_cpg_mssr_info = { .mstp_table = r8a77995_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a77995_mstp_table), .reset_node = "renesas,r8a77995-rst", + .reset_modemr_offset = CPG_RST_MODEMR, .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, .clk_extalr_id = ~0, diff --git a/drivers/clk/renesas/rcar-gen2-cpg.h b/drivers/clk/renesas/rcar-gen2-cpg.h index 2739480dad..ca7c3ed6b5 100644 --- a/drivers/clk/renesas/rcar-gen2-cpg.h +++ b/drivers/clk/renesas/rcar-gen2-cpg.h @@ -30,6 +30,8 @@ struct rcar_gen2_cpg_pll_config { unsigned int pll0_mult; /* leave as zero if PLL0CR exists */ };
+#define CPG_RST_MODEMR 0x060 + struct gen2_clk_priv { void __iomem *base; struct cpg_mssr_info *info; diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 52526a0cab..4fce0a9946 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -71,6 +71,8 @@ struct rcar_gen3_cpg_pll_config { u8 osc_prediv; };
+#define CPG_RST_MODEMR 0x060 + #define CPG_RPCCKCR 0x238 #define CPG_RCKCR 0x240
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index b669dec594..ad5d269fc4 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -22,6 +22,7 @@ struct cpg_mssr_info { const struct mstp_stop_table *mstp_table; unsigned int mstp_table_size; const char *reset_node; + unsigned int reset_modemr_offset; const char *extalr_node; const char *extal_usb_node; unsigned int mod_clk_base;
Hi Marek,
Thank you for the patch.
On Wed, Apr 28, 2021 at 8:32 PM Marek Vasut marek.vasut@gmail.com wrote:
The MODEMR register offset changed on R8A779A0, make the MODEMR offset configurable. Fill the offset in on all clock drivers. No functional change.
Based off "clk: renesas: Make CPG Reset MODEMR offset accessible from struct cpg_mssr_info" by Hai Pham hai.pham.ud@renesas.com
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com
drivers/clk/renesas/clk-rcar-gen2.c | 2 -- drivers/clk/renesas/clk-rcar-gen3.c | 4 +--- drivers/clk/renesas/r8a774a1-cpg-mssr.c | 1 + drivers/clk/renesas/r8a774b1-cpg-mssr.c | 1 + drivers/clk/renesas/r8a774c0-cpg-mssr.c | 1 + drivers/clk/renesas/r8a774e1-cpg-mssr.c | 1 + drivers/clk/renesas/r8a7790-cpg-mssr.c | 1 + drivers/clk/renesas/r8a7791-cpg-mssr.c | 1 + drivers/clk/renesas/r8a7792-cpg-mssr.c | 1 + drivers/clk/renesas/r8a7794-cpg-mssr.c | 1 + drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 + drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 + drivers/clk/renesas/r8a77965-cpg-mssr.c | 1 + drivers/clk/renesas/r8a77970-cpg-mssr.c | 1 + drivers/clk/renesas/r8a77980-cpg-mssr.c | 1 + drivers/clk/renesas/r8a77990-cpg-mssr.c | 1 + drivers/clk/renesas/r8a77995-cpg-mssr.c | 1 + drivers/clk/renesas/rcar-gen2-cpg.h | 2 ++ drivers/clk/renesas/rcar-gen3-cpg.h | 2 ++ drivers/clk/renesas/renesas-cpg-mssr.h | 1 + 20 files changed, 21 insertions(+), 5 deletions(-)
For RZ/G2{EHMN}
Tested-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
Cheers, Prabhakar
diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c index b423c9414b..b0164a6486 100644 --- a/drivers/clk/renesas/clk-rcar-gen2.c +++ b/drivers/clk/renesas/clk-rcar-gen2.c @@ -23,8 +23,6 @@ #include "renesas-cpg-mssr.h" #include "rcar-gen2-cpg.h"
-#define CPG_RST_MODEMR 0x0060
#define CPG_PLL0CR 0x00d8 #define CPG_SDCKCR 0x0074
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 763e268937..938d98546b 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -25,8 +25,6 @@ #include "renesas-cpg-mssr.h" #include "rcar-gen3-cpg.h"
-#define CPG_RST_MODEMR 0x0060
#define CPG_PLL0CR 0x00d8 #define CPG_PLL2CR 0x002c #define CPG_PLL4CR 0x01f4 @@ -382,7 +380,7 @@ int gen3_clk_probe(struct udevice *dev) if (rst_base == FDT_ADDR_T_NONE) return -EINVAL;
cpg_mode = readl(rst_base + CPG_RST_MODEMR);
cpg_mode = readl(rst_base + info->reset_modemr_offset); priv->cpg_pll_config = (struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode);diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index ef2bb6d777..48da65cd3d 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -321,6 +321,7 @@ static const struct cpg_mssr_info r8a774a1_cpg_mssr_info = { .mstp_table = r8a774a1_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a774a1_mstp_table), .reset_node = "renesas,r8a774a1-rst",
.reset_modemr_offset = CPG_RST_MODEMR, .extalr_node = "extalr", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL,diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c index a8b242dc47..418c393a20 100644 --- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c @@ -318,6 +318,7 @@ static const struct cpg_mssr_info r8a774b1_cpg_mssr_info = { .mstp_table = r8a774b1_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a774b1_mstp_table), .reset_node = "renesas,r8a774b1-rst",
.reset_modemr_offset = CPG_RST_MODEMR, .extalr_node = "extalr", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL,diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c index 6e9558a107..c1283d2614 100644 --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c @@ -292,6 +292,7 @@ const struct cpg_mssr_info r8a774c0_cpg_mssr_info = { .mstp_table = r8a774c0_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a774c0_mstp_table), .reset_node = "renesas,r8a774c0-rst",
.reset_modemr_offset = CPG_RST_MODEMR, .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, .clk_extalr_id = ~0,diff --git a/drivers/clk/renesas/r8a774e1-cpg-mssr.c b/drivers/clk/renesas/r8a774e1-cpg-mssr.c index c969ec6888..0cacd8d0c8 100644 --- a/drivers/clk/renesas/r8a774e1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774e1-cpg-mssr.c @@ -332,6 +332,7 @@ static const struct cpg_mssr_info r8a774e1_cpg_mssr_info = { .mstp_table = r8a774e1_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a774e1_mstp_table), .reset_node = "renesas,r8a774e1-rst",
.reset_modemr_offset = CPG_RST_MODEMR, .extalr_node = "extalr", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL,diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c b/drivers/clk/renesas/r8a7790-cpg-mssr.c index 8d616476c7..1f3477fa6e 100644 --- a/drivers/clk/renesas/r8a7790-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c @@ -263,6 +263,7 @@ static const struct cpg_mssr_info r8a7790_cpg_mssr_info = { .mstp_table = r8a7790_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a7790_mstp_table), .reset_node = "renesas,r8a7790-rst",
.reset_modemr_offset = CPG_RST_MODEMR, .extal_usb_node = "usb_extal", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL,diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c b/drivers/clk/renesas/r8a7791-cpg-mssr.c index 7a89613b32..fcca7be886 100644 --- a/drivers/clk/renesas/r8a7791-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c @@ -265,6 +265,7 @@ static const struct cpg_mssr_info r8a7791_cpg_mssr_info = { .mstp_table = r8a7791_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a7791_mstp_table), .reset_node = "renesas,r8a7791-rst",
.reset_modemr_offset = CPG_RST_MODEMR, .extal_usb_node = "usb_extal", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL,diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c index e18774dae4..5b333638ac 100644 --- a/drivers/clk/renesas/r8a7792-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c @@ -213,6 +213,7 @@ static const struct cpg_mssr_info r8a7792_cpg_mssr_info = { .mstp_table = r8a7792_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a7792_mstp_table), .reset_node = "renesas,r8a7792-rst",
.reset_modemr_offset = CPG_RST_MODEMR, .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, .pll0_div = 2,diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c index 790bc1bbd9..b9dd88de98 100644 --- a/drivers/clk/renesas/r8a7794-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c @@ -240,6 +240,7 @@ static const struct cpg_mssr_info r8a7794_cpg_mssr_info = { .mstp_table = r8a7794_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a7794_mstp_table), .reset_node = "renesas,r8a7794-rst",
.reset_modemr_offset = CPG_RST_MODEMR, .extal_usb_node = "usb_extal", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL,diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index ca74250276..6ba796b98c 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -362,6 +362,7 @@ static const struct cpg_mssr_info r8a7795_cpg_mssr_info = { .mstp_table = r8a7795_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a7795_mstp_table), .reset_node = "renesas,r8a7795-rst",
.reset_modemr_offset = CPG_RST_MODEMR, .extalr_node = "extalr", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL,diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 2e9a8b6448..e318719033 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -346,6 +346,7 @@ static const struct cpg_mssr_info r8a7796_cpg_mssr_info = { .mstp_table = r8a7796_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a7796_mstp_table), .reset_node = "renesas,r8a7796-rst",
.reset_modemr_offset = CPG_RST_MODEMR, .extalr_node = "extalr", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL,diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index a839ffa41f..0a15617da8 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -344,6 +344,7 @@ static const struct cpg_mssr_info r8a77965_cpg_mssr_info = { .mstp_table = r8a77965_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a77965_mstp_table), .reset_node = "renesas,r8a77965-rst",
.reset_modemr_offset = CPG_RST_MODEMR, .extalr_node = "extalr", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL,diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c index 3b84c658f7..a85bed6192 100644 --- a/drivers/clk/renesas/r8a77970-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c @@ -211,6 +211,7 @@ static const struct cpg_mssr_info r8a77970_cpg_mssr_info = { .mstp_table = r8a77970_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a77970_mstp_table), .reset_node = "renesas,r8a77970-rst",
.reset_modemr_offset = CPG_RST_MODEMR, .extalr_node = "extalr", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL,diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c index cf96309d12..bd9d7c9be5 100644 --- a/drivers/clk/renesas/r8a77980-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c @@ -230,6 +230,7 @@ static const struct cpg_mssr_info r8a77980_cpg_mssr_info = { .mstp_table = r8a77980_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a77980_mstp_table), .reset_node = "renesas,r8a77980-rst",
.reset_modemr_offset = CPG_RST_MODEMR, .extalr_node = "extalr", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL,diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index d953c0b421..67a1f586e2 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -304,6 +304,7 @@ static const struct cpg_mssr_info r8a77990_cpg_mssr_info = { .mstp_table = r8a77990_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a77990_mstp_table), .reset_node = "renesas,r8a77990-rst",
.reset_modemr_offset = CPG_RST_MODEMR, .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, .clk_extalr_id = ~0,diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index 0771c48964..83e8e9bfaa 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -242,6 +242,7 @@ static const struct cpg_mssr_info r8a77995_cpg_mssr_info = { .mstp_table = r8a77995_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a77995_mstp_table), .reset_node = "renesas,r8a77995-rst",
.reset_modemr_offset = CPG_RST_MODEMR, .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, .clk_extalr_id = ~0,diff --git a/drivers/clk/renesas/rcar-gen2-cpg.h b/drivers/clk/renesas/rcar-gen2-cpg.h index 2739480dad..ca7c3ed6b5 100644 --- a/drivers/clk/renesas/rcar-gen2-cpg.h +++ b/drivers/clk/renesas/rcar-gen2-cpg.h @@ -30,6 +30,8 @@ struct rcar_gen2_cpg_pll_config { unsigned int pll0_mult; /* leave as zero if PLL0CR exists */ };
+#define CPG_RST_MODEMR 0x060
struct gen2_clk_priv { void __iomem *base; struct cpg_mssr_info *info; diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 52526a0cab..4fce0a9946 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -71,6 +71,8 @@ struct rcar_gen3_cpg_pll_config { u8 osc_prediv; };
+#define CPG_RST_MODEMR 0x060
#define CPG_RPCCKCR 0x238 #define CPG_RCKCR 0x240
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index b669dec594..ad5d269fc4 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -22,6 +22,7 @@ struct cpg_mssr_info { const struct mstp_stop_table *mstp_table; unsigned int mstp_table_size; const char *reset_node;
unsigned int reset_modemr_offset; const char *extalr_node; const char *extal_usb_node; unsigned int mod_clk_base;-- 2.30.2
From: Hai Pham hai.pham.ud@renesas.com
CPG IP in some specific Renesas SoCs (i.e. new R8A779A0 V3U SoC) requires a different setting procedure. Make struct cpg_mssr_info accessible to handle the clock setting in that case.
Signed-off-by: Hai Pham hai.pham.ud@renesas.com Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- drivers/clk/renesas/clk-rcar-gen2.c | 4 ++-- drivers/clk/renesas/clk-rcar-gen3.c | 4 ++-- drivers/clk/renesas/renesas-cpg-mssr.c | 3 ++- drivers/clk/renesas/renesas-cpg-mssr.h | 3 ++- 4 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c index b0164a6486..d2d0169dd8 100644 --- a/drivers/clk/renesas/clk-rcar-gen2.c +++ b/drivers/clk/renesas/clk-rcar-gen2.c @@ -61,14 +61,14 @@ static int gen2_clk_enable(struct clk *clk) { struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
- return renesas_clk_endisable(clk, priv->base, true); + return renesas_clk_endisable(clk, priv->base, priv->info, true); }
static int gen2_clk_disable(struct clk *clk) { struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
- return renesas_clk_endisable(clk, priv->base, false); + return renesas_clk_endisable(clk, priv->base, priv->info, false); }
static ulong gen2_clk_get_rate(struct clk *clk) diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 938d98546b..27939d6318 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -143,14 +143,14 @@ static int gen3_clk_enable(struct clk *clk) { struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
- return renesas_clk_endisable(clk, priv->base, true); + return renesas_clk_endisable(clk, priv->base, priv->info, true); }
static int gen3_clk_disable(struct clk *clk) { struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
- return renesas_clk_endisable(clk, priv->base, false); + return renesas_clk_endisable(clk, priv->base, priv->info, false); }
static u64 gen3_clk_get_rate64(struct clk *clk) diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index bed2a16448..0cf80a9866 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -132,7 +132,8 @@ int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info, return 0; }
-int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable) +int renesas_clk_endisable(struct clk *clk, void __iomem *base, + struct cpg_mssr_info *info, bool enable) { const unsigned long clkid = clk->id & 0xffff; const unsigned int reg = clkid / 100; diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index ad5d269fc4..8c8a09b904 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -115,7 +115,8 @@ int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info, const struct cpg_core_clk **core); int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info, struct clk *parent); -int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable); +int renesas_clk_endisable(struct clk *clk, void __iomem *base, + struct cpg_mssr_info *info, bool enable); int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
#endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */
From: Hai Pham hai.pham.ud@renesas.com
From Linux v5.10-rc2, commit ffbf9cf3f946 by Yoshihiro Shimoda
Introduce enum clk_reg_layout to support multiple register layout variants
Signed-off-by: Hai Pham hai.pham.ud@renesas.com Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- drivers/clk/renesas/renesas-cpg-mssr.h | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 8c8a09b904..3c3b128c4c 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -14,9 +14,15 @@ #define __DRIVERS_CLK_RENESAS_CPG_MSSR__
#include <linux/bitops.h> + +enum clk_reg_layout { + CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0, +}; + struct cpg_mssr_info { const struct cpg_core_clk *core_clk; unsigned int core_clk_size; + enum clk_reg_layout reg_layout; const struct mssr_mod_clk *mod_clk; unsigned int mod_clk_size; const struct mstp_stop_table *mstp_table;
From: Hai Pham hai.pham.ud@renesas.com
Base on Linux v5.10-rc2, commit 8b652aa8a1fb by Yoshihiro Shimoda To support other register layouts in the future, add register pointers of {control,status,reset,reset_clear}_regs into struct cpg_mssr_info
Signed-off-by: Hai Pham hai.pham.ud@renesas.com Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- drivers/clk/renesas/clk-rcar-gen3.c | 9 +++++ drivers/clk/renesas/renesas-cpg-mssr.c | 49 ++---------------------- drivers/clk/renesas/renesas-cpg-mssr.h | 52 ++++++++++++++++++++++++++ 3 files changed, 65 insertions(+), 45 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 27939d6318..49ab9134af 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -389,6 +389,15 @@ int gen3_clk_probe(struct udevice *dev)
priv->sscg = !(cpg_mode & BIT(12));
+ if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) { + priv->info->status_regs = mstpsr; + priv->info->control_regs = smstpcr; + priv->info->reset_regs = srcr; + priv->info->reset_clear_regs = srstclr; + } else { + return -EINVAL; + } + ret = clk_get_by_name(dev, "extal", &priv->clk_extal); if (ret < 0) return ret; diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index 0cf80a9866..b1cf7f599c 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -22,47 +22,6 @@
#include "renesas-cpg-mssr.h"
-/* - * Module Standby and Software Reset register offets. - * - * If the registers exist, these are valid for SH-Mobile, R-Mobile, - * R-Car Gen2, R-Car Gen3, and RZ/G1. - * These are NOT valid for R-Car Gen1 and RZ/A1! - */ - -/* - * Module Stop Status Register offsets - */ - -static const u16 mstpsr[] = { - 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4, - 0x9A0, 0x9A4, 0x9A8, 0x9AC, -}; - -#define MSTPSR(i) mstpsr[i] - - -/* - * System Module Stop Control Register offsets - */ - -static const u16 smstpcr[] = { - 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C, - 0x990, 0x994, 0x998, 0x99C, -}; - -#define SMSTPCR(i) smstpcr[i] - - -/* Realtime Module Stop Control Register offsets */ -#define RMSTPCR(i) ((i) < 8 ? smstpcr[i] - 0x20 : smstpcr[i] - 0x10) - -/* Modem Module Stop Control Register offsets (r8a73a4) */ -#define MMSTPCR(i) (smstpcr[i] + 0x20) - -/* Software Reset Clearing Register offsets */ -#define SRSTCLR(i) (0x940 + (i) * 4) - bool renesas_clk_is_mod(struct clk *clk) { return (clk->id >> 16) == CPG_MOD; @@ -147,11 +106,11 @@ int renesas_clk_endisable(struct clk *clk, void __iomem *base, clkid, reg, bit, enable ? "ON" : "OFF");
if (enable) { - clrbits_le32(base + SMSTPCR(reg), bitmask); - return wait_for_bit_le32(base + MSTPSR(reg), + clrbits_le32(base + info->control_regs[reg], bitmask); + return wait_for_bit_le32(base + info->status_regs[reg], bitmask, 0, 100, 0); } else { - setbits_le32(base + SMSTPCR(reg), bitmask); + setbits_le32(base + info->control_regs[reg], bitmask); return 0; } } @@ -165,7 +124,7 @@ int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info)
/* Stop module clock */ for (i = 0; i < info->mstp_table_size; i++) { - clrsetbits_le32(base + SMSTPCR(i), + clrsetbits_le32(base + info->control_regs[i], info->mstp_table[i].sdis, info->mstp_table[i].sen); clrsetbits_le32(base + RMSTPCR(i), diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 3c3b128c4c..92421b15ee 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -37,6 +37,10 @@ struct cpg_mssr_info { unsigned int clk_extal_usb_id; unsigned int pll0_div; const void *(*get_pll_config)(const u32 cpg_mode); + const u16 *status_regs; + const u16 *control_regs; + const u16 *reset_regs; + const u16 *reset_clear_regs; };
/* @@ -125,4 +129,52 @@ int renesas_clk_endisable(struct clk *clk, void __iomem *base, struct cpg_mssr_info *info, bool enable); int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
+/* + * Module Standby and Software Reset register offets. + * + * If the registers exist, these are valid for SH-Mobile, R-Mobile, + * R-Car Gen2, R-Car Gen3, and RZ/G1. + * These are NOT valid for R-Car Gen1 and RZ/A1! + */ + +/* + * Module Stop Status Register offsets + */ + +static const u16 mstpsr[] = { + 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4, + 0x9A0, 0x9A4, 0x9A8, 0x9AC, +}; + +/* + * System Module Stop Control Register offsets + */ + +static const u16 smstpcr[] = { + 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C, + 0x990, 0x994, 0x998, 0x99C, +}; + +/* + * Software Reset Register offsets + */ + +static const u16 srcr[] = { + 0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC, + 0x920, 0x924, 0x928, 0x92C, +}; + +/* Realtime Module Stop Control Register offsets */ +#define RMSTPCR(i) ((i) < 8 ? smstpcr[i] - 0x20 : smstpcr[i] - 0x10) + +/* Modem Module Stop Control Register offsets (r8a73a4) */ +#define MMSTPCR(i) (smstpcr[i] + 0x20) + +/* Software Reset Clearing Register offsets */ + +static const u16 srstclr[] = { + 0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C, + 0x960, 0x964, 0x968, 0x96C, +}; + #endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */
Hi Marek,
Thank you for the patch.
On Wed, Apr 28, 2021 at 8:32 PM Marek Vasut marek.vasut@gmail.com wrote:
From: Hai Pham hai.pham.ud@renesas.com
Base on Linux v5.10-rc2, commit 8b652aa8a1fb by Yoshihiro Shimoda To support other register layouts in the future, add register pointers of {control,status,reset,reset_clear}_regs into struct cpg_mssr_info
Signed-off-by: Hai Pham hai.pham.ud@renesas.com Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com
drivers/clk/renesas/clk-rcar-gen3.c | 9 +++++ drivers/clk/renesas/renesas-cpg-mssr.c | 49 ++---------------------- drivers/clk/renesas/renesas-cpg-mssr.h | 52 ++++++++++++++++++++++++++ 3 files changed, 65 insertions(+), 45 deletions(-)
Tested on RZ/G2{EHMN} board
Tested-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
Cheers, Prabhaka
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 27939d6318..49ab9134af 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -389,6 +389,15 @@ int gen3_clk_probe(struct udevice *dev)
priv->sscg = !(cpg_mode & BIT(12));
if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {priv->info->status_regs = mstpsr;priv->info->control_regs = smstpcr;priv->info->reset_regs = srcr;priv->info->reset_clear_regs = srstclr;} else {return -EINVAL;}ret = clk_get_by_name(dev, "extal", &priv->clk_extal); if (ret < 0) return ret;diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index 0cf80a9866..b1cf7f599c 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -22,47 +22,6 @@
#include "renesas-cpg-mssr.h"
-/*
- Module Standby and Software Reset register offets.
- If the registers exist, these are valid for SH-Mobile, R-Mobile,
- R-Car Gen2, R-Car Gen3, and RZ/G1.
- These are NOT valid for R-Car Gen1 and RZ/A1!
- */
-/*
- Module Stop Status Register offsets
- */
-static const u16 mstpsr[] = {
0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,0x9A0, 0x9A4, 0x9A8, 0x9AC,-};
-#define MSTPSR(i) mstpsr[i]
-/*
- System Module Stop Control Register offsets
- */
-static const u16 smstpcr[] = {
0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,0x990, 0x994, 0x998, 0x99C,-};
-#define SMSTPCR(i) smstpcr[i]
-/* Realtime Module Stop Control Register offsets */ -#define RMSTPCR(i) ((i) < 8 ? smstpcr[i] - 0x20 : smstpcr[i] - 0x10)
-/* Modem Module Stop Control Register offsets (r8a73a4) */ -#define MMSTPCR(i) (smstpcr[i] + 0x20)
-/* Software Reset Clearing Register offsets */ -#define SRSTCLR(i) (0x940 + (i) * 4)
bool renesas_clk_is_mod(struct clk *clk) { return (clk->id >> 16) == CPG_MOD; @@ -147,11 +106,11 @@ int renesas_clk_endisable(struct clk *clk, void __iomem *base, clkid, reg, bit, enable ? "ON" : "OFF");
if (enable) {
clrbits_le32(base + SMSTPCR(reg), bitmask);return wait_for_bit_le32(base + MSTPSR(reg),
clrbits_le32(base + info->control_regs[reg], bitmask);return wait_for_bit_le32(base + info->status_regs[reg], bitmask, 0, 100, 0); } else {
setbits_le32(base + SMSTPCR(reg), bitmask);
setbits_le32(base + info->control_regs[reg], bitmask); return 0; }} @@ -165,7 +124,7 @@ int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info)
/* Stop module clock */ for (i = 0; i < info->mstp_table_size; i++) {
clrsetbits_le32(base + SMSTPCR(i),
clrsetbits_le32(base + info->control_regs[i], info->mstp_table[i].sdis, info->mstp_table[i].sen); clrsetbits_le32(base + RMSTPCR(i),diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 3c3b128c4c..92421b15ee 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -37,6 +37,10 @@ struct cpg_mssr_info { unsigned int clk_extal_usb_id; unsigned int pll0_div; const void *(*get_pll_config)(const u32 cpg_mode);
const u16 *status_regs;const u16 *control_regs;const u16 *reset_regs;const u16 *reset_clear_regs;};
/* @@ -125,4 +129,52 @@ int renesas_clk_endisable(struct clk *clk, void __iomem *base, struct cpg_mssr_info *info, bool enable); int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
+/*
- Module Standby and Software Reset register offets.
- If the registers exist, these are valid for SH-Mobile, R-Mobile,
- R-Car Gen2, R-Car Gen3, and RZ/G1.
- These are NOT valid for R-Car Gen1 and RZ/A1!
- */
+/*
- Module Stop Status Register offsets
- */
+static const u16 mstpsr[] = {
0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,0x9A0, 0x9A4, 0x9A8, 0x9AC,+};
+/*
- System Module Stop Control Register offsets
- */
+static const u16 smstpcr[] = {
0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,0x990, 0x994, 0x998, 0x99C,+};
+/*
- Software Reset Register offsets
- */
+static const u16 srcr[] = {
0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,0x920, 0x924, 0x928, 0x92C,+};
+/* Realtime Module Stop Control Register offsets */ +#define RMSTPCR(i) ((i) < 8 ? smstpcr[i] - 0x20 : smstpcr[i] - 0x10)
+/* Modem Module Stop Control Register offsets (r8a73a4) */ +#define MMSTPCR(i) (smstpcr[i] + 0x20)
+/* Software Reset Clearing Register offsets */
+static const u16 srstclr[] = {
0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C,0x960, 0x964, 0x968, 0x96C,+};
#endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */
2.30.2
Most of the PLLx, MAIN, FIXED clock handlers are calling very similar code, which determines parent rate and then applies multiplication and division. The only difference is whether multiplication is fixed factor or coming from CRx register. Deduplicate the code into a single function.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- drivers/clk/renesas/clk-rcar-gen3.c | 86 ++++++++++++++--------------- 1 file changed, 43 insertions(+), 43 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 49ab9134af..7b42e28e83 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -153,6 +153,30 @@ static int gen3_clk_disable(struct clk *clk) return renesas_clk_endisable(clk, priv->base, priv->info, false); }
+static u64 gen3_clk_get_rate64(struct clk *clk); + +static u64 gen3_clk_get_rate64_pll_mul_reg(struct gen3_clk_priv *priv, + struct clk *parent, + const struct cpg_core_clk *core, + u32 mul_reg, u32 mult, u32 div, + char *name) +{ + u32 value; + u64 rate; + + if (mul_reg) { + value = readl(priv->base + mul_reg); + mult = (((value >> 24) & 0x7f) + 1) * 2; + div = 1; + } + + rate = (gen3_clk_get_rate64(parent) * mult) / div; + + debug("%s[%i] %s clk: parent=%i mult=%u div=%u => rate=%llu\n", + __func__, __LINE__, name, core->parent, mult, div, rate); + return rate; +} + static u64 gen3_clk_get_rate64(struct clk *clk) { struct gen3_clk_priv *priv = dev_get_priv(clk->dev); @@ -161,7 +185,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk) const struct cpg_core_clk *core; const struct rcar_gen3_cpg_pll_config *pll_config = priv->cpg_pll_config; - u32 value, mult, div, prediv, postdiv; + u32 value, div, prediv, postdiv; u64 rate = 0; int i, ret;
@@ -203,60 +227,36 @@ static u64 gen3_clk_get_rate64(struct clk *clk) return -EINVAL;
case CLK_TYPE_GEN3_MAIN: - rate = gen3_clk_get_rate64(&parent) / pll_config->extal_div; - debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%llu\n", - __func__, __LINE__, - core->parent, pll_config->extal_div, rate); - return rate; + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + 0, 1, pll_config->extal_div, + "MAIN");
case CLK_TYPE_GEN3_PLL0: - value = readl(priv->base + CPG_PLL0CR); - mult = (((value >> 24) & 0x7f) + 1) * 2; - rate = gen3_clk_get_rate64(&parent) * mult; - debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%llu\n", - __func__, __LINE__, core->parent, mult, rate); - return rate; + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + CPG_PLL0CR, 0, 0, "PLL0");
case CLK_TYPE_GEN3_PLL1: - rate = gen3_clk_get_rate64(&parent) * pll_config->pll1_mult; - rate /= pll_config->pll1_div; - debug("%s[%i] PLL1 clk: parent=%i mul=%i div=%i => rate=%llu\n", - __func__, __LINE__, - core->parent, pll_config->pll1_mult, - pll_config->pll1_div, rate); - return rate; + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + 0, pll_config->pll1_mult, + pll_config->pll1_div, "PLL1");
case CLK_TYPE_GEN3_PLL2: - value = readl(priv->base + CPG_PLL2CR); - mult = (((value >> 24) & 0x7f) + 1) * 2; - rate = gen3_clk_get_rate64(&parent) * mult; - debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%llu\n", - __func__, __LINE__, core->parent, mult, rate); - return rate; + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + CPG_PLL2CR, 0, 0, "PLL2");
case CLK_TYPE_GEN3_PLL3: - rate = gen3_clk_get_rate64(&parent) * pll_config->pll3_mult; - rate /= pll_config->pll3_div; - debug("%s[%i] PLL3 clk: parent=%i mul=%i div=%i => rate=%llu\n", - __func__, __LINE__, - core->parent, pll_config->pll3_mult, - pll_config->pll3_div, rate); - return rate; + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + 0, pll_config->pll3_mult, + pll_config->pll3_div, "PLL3");
case CLK_TYPE_GEN3_PLL4: - value = readl(priv->base + CPG_PLL4CR); - mult = (((value >> 24) & 0x7f) + 1) * 2; - rate = gen3_clk_get_rate64(&parent) * mult; - debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%llu\n", - __func__, __LINE__, core->parent, mult, rate); - return rate; + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + CPG_PLL4CR, 0, 0, "PLL4");
case CLK_TYPE_FF: - rate = (gen3_clk_get_rate64(&parent) * core->mult) / core->div; - debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%llu\n", - __func__, __LINE__, - core->parent, core->mult, core->div, rate); - return rate; + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + 0, core->mult, core->div, + "FIXED");
case CLK_TYPE_GEN3_MDSEL: div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff;
Hi Marek,
Thank you for the patch.
On Wed, Apr 28, 2021 at 8:33 PM Marek Vasut marek.vasut@gmail.com wrote:
Most of the PLLx, MAIN, FIXED clock handlers are calling very similar code, which determines parent rate and then applies multiplication and division. The only difference is whether multiplication is fixed factor or coming from CRx register. Deduplicate the code into a single function.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com
drivers/clk/renesas/clk-rcar-gen3.c | 86 ++++++++++++++--------------- 1 file changed, 43 insertions(+), 43 deletions(-)
Tested on RZ/G2{EHMN} boards
Tested-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
Cheers, Prabhakar
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 49ab9134af..7b42e28e83 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -153,6 +153,30 @@ static int gen3_clk_disable(struct clk *clk) return renesas_clk_endisable(clk, priv->base, priv->info, false); }
+static u64 gen3_clk_get_rate64(struct clk *clk);
+static u64 gen3_clk_get_rate64_pll_mul_reg(struct gen3_clk_priv *priv,
struct clk *parent,const struct cpg_core_clk *core,u32 mul_reg, u32 mult, u32 div,char *name)+{
u32 value;u64 rate;if (mul_reg) {value = readl(priv->base + mul_reg);mult = (((value >> 24) & 0x7f) + 1) * 2;div = 1;}rate = (gen3_clk_get_rate64(parent) * mult) / div;debug("%s[%i] %s clk: parent=%i mult=%u div=%u => rate=%llu\n",__func__, __LINE__, name, core->parent, mult, div, rate);return rate;+}
static u64 gen3_clk_get_rate64(struct clk *clk) { struct gen3_clk_priv *priv = dev_get_priv(clk->dev); @@ -161,7 +185,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk) const struct cpg_core_clk *core; const struct rcar_gen3_cpg_pll_config *pll_config = priv->cpg_pll_config;
u32 value, mult, div, prediv, postdiv;
u32 value, div, prediv, postdiv; u64 rate = 0; int i, ret;@@ -203,60 +227,36 @@ static u64 gen3_clk_get_rate64(struct clk *clk) return -EINVAL;
case CLK_TYPE_GEN3_MAIN:
rate = gen3_clk_get_rate64(&parent) / pll_config->extal_div;debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%llu\n",__func__, __LINE__,core->parent, pll_config->extal_div, rate);return rate;
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,0, 1, pll_config->extal_div,"MAIN"); case CLK_TYPE_GEN3_PLL0:
value = readl(priv->base + CPG_PLL0CR);mult = (((value >> 24) & 0x7f) + 1) * 2;rate = gen3_clk_get_rate64(&parent) * mult;debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%llu\n",__func__, __LINE__, core->parent, mult, rate);return rate;
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,CPG_PLL0CR, 0, 0, "PLL0"); case CLK_TYPE_GEN3_PLL1:
rate = gen3_clk_get_rate64(&parent) * pll_config->pll1_mult;rate /= pll_config->pll1_div;debug("%s[%i] PLL1 clk: parent=%i mul=%i div=%i => rate=%llu\n",__func__, __LINE__,core->parent, pll_config->pll1_mult,pll_config->pll1_div, rate);return rate;
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,0, pll_config->pll1_mult,pll_config->pll1_div, "PLL1"); case CLK_TYPE_GEN3_PLL2:
value = readl(priv->base + CPG_PLL2CR);mult = (((value >> 24) & 0x7f) + 1) * 2;rate = gen3_clk_get_rate64(&parent) * mult;debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%llu\n",__func__, __LINE__, core->parent, mult, rate);return rate;
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,CPG_PLL2CR, 0, 0, "PLL2"); case CLK_TYPE_GEN3_PLL3:
rate = gen3_clk_get_rate64(&parent) * pll_config->pll3_mult;rate /= pll_config->pll3_div;debug("%s[%i] PLL3 clk: parent=%i mul=%i div=%i => rate=%llu\n",__func__, __LINE__,core->parent, pll_config->pll3_mult,pll_config->pll3_div, rate);return rate;
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,0, pll_config->pll3_mult,pll_config->pll3_div, "PLL3"); case CLK_TYPE_GEN3_PLL4:
value = readl(priv->base + CPG_PLL4CR);mult = (((value >> 24) & 0x7f) + 1) * 2;rate = gen3_clk_get_rate64(&parent) * mult;debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%llu\n",__func__, __LINE__, core->parent, mult, rate);return rate;
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,CPG_PLL4CR, 0, 0, "PLL4"); case CLK_TYPE_FF:
rate = (gen3_clk_get_rate64(&parent) * core->mult) / core->div;debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%llu\n",__func__, __LINE__,core->parent, core->mult, core->div, rate);return rate;
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,0, core->mult, core->div,"FIXED"); case CLK_TYPE_GEN3_MDSEL: div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff;-- 2.30.2
On R8A779A0 V3U SoC, PLL1 and PLL5 use a divider value from cpg_pll_configs table while PLL{20,21,30,31,4} use different control offset. Introduce new types to handle this and handle those types in the Gen3 clock code.
Based on "clk: renesas: Add support for R8A779A0 V3U PLLn" by Hai Pham hai.pham.ud@renesas.com
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- drivers/clk/renesas/clk-rcar-gen3.c | 24 ++++++++++++++++++++++++ drivers/clk/renesas/rcar-gen3-cpg.h | 9 +++++++++ 2 files changed, 33 insertions(+)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 7b42e28e83..c7dba341c1 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -253,6 +253,28 @@ static u64 gen3_clk_get_rate64(struct clk *clk) return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, CPG_PLL4CR, 0, 0, "PLL4");
+ case CLK_TYPE_R8A779A0_MAIN: + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + 0, 1, pll_config->extal_div, + "V3U_MAIN"); + + case CLK_TYPE_R8A779A0_PLL1: + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + 0, pll_config->pll1_mult, + pll_config->pll1_div, + "V3U_PLL1"); + + case CLK_TYPE_R8A779A0_PLL2X_3X: + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + core->offset, 0, 0, + "V3U_PLL2X_3X"); + + case CLK_TYPE_R8A779A0_PLL5: + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + 0, pll_config->pll5_mult, + pll_config->pll5_div, + "V3U_PLL5"); + case CLK_TYPE_FF: return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, 0, core->mult, core->div, @@ -268,6 +290,8 @@ static u64 gen3_clk_get_rate64(struct clk *clk) return rate;
case CLK_TYPE_GEN3_SD: /* FIXME */ + fallthrough; + case CLK_TYPE_R8A779A0_SD: value = readl(priv->base + core->offset); value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 4fce0a9946..aa940a1ca2 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -27,6 +27,13 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_E3_RPCSRC, CLK_TYPE_GEN3_RPC, CLK_TYPE_GEN3_RPCD2, + CLK_TYPE_R8A779A0_MAIN, + CLK_TYPE_R8A779A0_PLL1, + CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */ + CLK_TYPE_R8A779A0_PLL5, + CLK_TYPE_R8A779A0_SD, + CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */ + CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */
/* SoC specific definitions start here */ CLK_TYPE_GEN3_SOC_BASE, @@ -69,6 +76,8 @@ struct rcar_gen3_cpg_pll_config { u8 pll3_mult; u8 pll3_div; u8 osc_prediv; + u8 pll5_mult; + u8 pll5_div; };
#define CPG_RST_MODEMR 0x060
From: Hai Pham hai.pham.ud@renesas.com
Add clock tables for R8A779A0 V3U SoC from Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12")
Signed-off-by: Hai Pham hai.pham.ud@renesas.com Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com -- Marek: - Add .reset_modemr_offset - Sync tables from Linux 5.12 - Rebase on latest u-boot --- drivers/clk/renesas/Kconfig | 6 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/clk-rcar-gen3.c | 5 + drivers/clk/renesas/r8a779a0-cpg-mssr.c | 300 ++++++++++++++++++++++++ drivers/clk/renesas/rcar-gen3-cpg.h | 1 + drivers/clk/renesas/renesas-cpg-mssr.c | 4 + drivers/clk/renesas/renesas-cpg-mssr.h | 21 ++ 7 files changed, 338 insertions(+) create mode 100644 drivers/clk/renesas/r8a779a0-cpg-mssr.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 0c8b9eb47d..f4d6ef9f93 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -114,3 +114,9 @@ config CLK_R8A77995 depends on CLK_RCAR_GEN3 help Enable this to support the clocks on Renesas R8A77995 SoC. + +config CLK_R8A779A0 + bool "Renesas R8A779A0 clock driver" + depends on CLK_RCAR_GEN3 + help + Enable this to support the clocks on Renesas R8A779A0 SoC. diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index ed1a1252c4..36a5ca65f4 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -17,3 +17,4 @@ obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o +obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index c7dba341c1..6cf07fb418 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -418,6 +418,11 @@ int gen3_clk_probe(struct udevice *dev) priv->info->control_regs = smstpcr; priv->info->reset_regs = srcr; priv->info->reset_clear_regs = srstclr; + } else if (info->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) { + priv->info->status_regs = mstpsr_for_v3u; + priv->info->control_regs = mstpcr_for_v3u; + priv->info->reset_regs = srcr_for_v3u; + priv->info->reset_clear_regs = srstclr_for_v3u; } else { return -EINVAL; } diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c new file mode 100644 index 0000000000..bda6995236 --- /dev/null +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset + * + * Copyright (C) 2020 Renesas Electronics Corp. + * + * Based on r8a7795-cpg-mssr.c + * + * Copyright (C) 2015 Glider bvba + * Copyright (C) 2015 Renesas Electronics Corp. + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> + +#include <dt-bindings/clock/r8a779a0-cpg-mssr.h> + +#include "renesas-cpg-mssr.h" +#include "rcar-gen3-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R8A779A0_CLK_OSC, + + /* External Input Clocks */ + CLK_EXTAL, + CLK_EXTALR, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_PLL1, + CLK_PLL20, + CLK_PLL21, + CLK_PLL30, + CLK_PLL31, + CLK_PLL5, + CLK_PLL1_DIV2, + CLK_PLL20_DIV2, + CLK_PLL21_DIV2, + CLK_PLL30_DIV2, + CLK_PLL31_DIV2, + CLK_PLL5_DIV2, + CLK_PLL5_DIV4, + CLK_S1, + CLK_S3, + CLK_SDSRC, + CLK_RPCSRC, + CLK_OCO, + + /* Module Clocks */ + MOD_CLK_BASE +}; + +#define DEF_PLL(_name, _id, _offset) \ + DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \ + .offset = _offset) + +#define DEF_SD(_name, _id, _parent, _offset) \ + DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SD, _parent, .offset = _offset) + +#define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ + DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL, \ + (_parent0) << 16 | (_parent1), \ + .div = (_div0) << 16 | (_div1), .offset = _md) + +#define DEF_OSC(_name, _id, _parent, _div) \ + DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div) + +static const struct cpg_core_clk r8a779a0_core_clks[] = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + DEF_INPUT("extalr", CLK_EXTALR), + + /* Internal Core Clocks */ + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN), + DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN), + DEF_PLL(".pll20", CLK_PLL20, 0x0834), + DEF_PLL(".pll21", CLK_PLL21, 0x0838), + DEF_PLL(".pll30", CLK_PLL30, 0x083c), + DEF_PLL(".pll31", CLK_PLL31, 0x0840), + + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), + DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2, CLK_PLL20, 2, 1), + DEF_FIXED(".pll21_div2", CLK_PLL21_DIV2, CLK_PLL21, 2, 1), + DEF_FIXED(".pll30_div2", CLK_PLL30_DIV2, CLK_PLL30, 2, 1), + DEF_FIXED(".pll31_div2", CLK_PLL31_DIV2, CLK_PLL31, 2, 1), + DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1), + DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), + DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV4, 1, 1), + DEF_RATE(".oco", CLK_OCO, 32768), + + /* Core Clock Outputs */ + DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1), + DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1), + DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1), + DEF_FIXED("s1d4", R8A779A0_CLK_S1D4, CLK_S1, 4, 1), + DEF_FIXED("s1d8", R8A779A0_CLK_S1D8, CLK_S1, 8, 1), + DEF_FIXED("s1d12", R8A779A0_CLK_S1D12, CLK_S1, 12, 1), + DEF_FIXED("s3d1", R8A779A0_CLK_S3D1, CLK_S3, 1, 1), + DEF_FIXED("s3d2", R8A779A0_CLK_S3D2, CLK_S3, 2, 1), + DEF_FIXED("s3d4", R8A779A0_CLK_S3D4, CLK_S3, 4, 1), + DEF_FIXED("zs", R8A779A0_CLK_ZS, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED("zt", R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED("ztr", R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED("zr", R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1, 1), + DEF_FIXED("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 1, 1), + DEF_FIXED("cnndsp", R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1, 1), + DEF_FIXED("vip", R8A779A0_CLK_VIP, CLK_PLL5, 5, 1), + DEF_FIXED("adgh", R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1, 1), + DEF_FIXED("icu", R8A779A0_CLK_ICU, CLK_PLL5_DIV4, 2, 1), + DEF_FIXED("icud2", R8A779A0_CLK_ICUD2, CLK_PLL5_DIV4, 4, 1), + DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1), + DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_EXTAL, 2, 1), + DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1), + + DEF_SD("sd0", R8A779A0_CLK_SD0, CLK_SDSRC, 0x870), + + DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), + DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), + DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880), + + DEF_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8), + DEF_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), +}; + +static const struct mssr_mod_clk r8a779a0_mod_clks[] = { + DEF_MOD("avb0", 211, R8A779A0_CLK_S3D2), + DEF_MOD("avb1", 212, R8A779A0_CLK_S3D2), + DEF_MOD("avb2", 213, R8A779A0_CLK_S3D2), + DEF_MOD("avb3", 214, R8A779A0_CLK_S3D2), + DEF_MOD("avb4", 215, R8A779A0_CLK_S3D2), + DEF_MOD("avb5", 216, R8A779A0_CLK_S3D2), + DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0), + DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0), + DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0), + DEF_MOD("csi43", 402, R8A779A0_CLK_CSI0), + DEF_MOD("fcpvd0", 508, R8A779A0_CLK_S3D1), + DEF_MOD("fcpvd1", 509, R8A779A0_CLK_S3D1), + DEF_MOD("hscif0", 514, R8A779A0_CLK_S1D2), + DEF_MOD("hscif1", 515, R8A779A0_CLK_S1D2), + DEF_MOD("hscif2", 516, R8A779A0_CLK_S1D2), + DEF_MOD("hscif3", 517, R8A779A0_CLK_S1D2), + DEF_MOD("i2c0", 518, R8A779A0_CLK_S1D4), + DEF_MOD("i2c1", 519, R8A779A0_CLK_S1D4), + DEF_MOD("i2c2", 520, R8A779A0_CLK_S1D4), + DEF_MOD("i2c3", 521, R8A779A0_CLK_S1D4), + DEF_MOD("i2c4", 522, R8A779A0_CLK_S1D4), + DEF_MOD("i2c5", 523, R8A779A0_CLK_S1D4), + DEF_MOD("i2c6", 524, R8A779A0_CLK_S1D4), + DEF_MOD("msi0", 618, R8A779A0_CLK_MSO), + DEF_MOD("msi1", 619, R8A779A0_CLK_MSO), + DEF_MOD("msi2", 620, R8A779A0_CLK_MSO), + DEF_MOD("msi3", 621, R8A779A0_CLK_MSO), + DEF_MOD("msi4", 622, R8A779A0_CLK_MSO), + DEF_MOD("msi5", 623, R8A779A0_CLK_MSO), + DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8), + DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8), + DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8), + DEF_MOD("scif4", 705, R8A779A0_CLK_S1D8), + DEF_MOD("sdhi0", 706, R8A779A0_CLK_SD0), + DEF_MOD("sydm1", 709, R8A779A0_CLK_S1D2), + DEF_MOD("sydm2", 710, R8A779A0_CLK_S1D2), + DEF_MOD("vin00", 730, R8A779A0_CLK_S1D1), + DEF_MOD("vin01", 731, R8A779A0_CLK_S1D1), + DEF_MOD("vin02", 800, R8A779A0_CLK_S1D1), + DEF_MOD("vin03", 801, R8A779A0_CLK_S1D1), + DEF_MOD("vin04", 802, R8A779A0_CLK_S1D1), + DEF_MOD("vin05", 803, R8A779A0_CLK_S1D1), + DEF_MOD("vin06", 804, R8A779A0_CLK_S1D1), + DEF_MOD("vin07", 805, R8A779A0_CLK_S1D1), + DEF_MOD("vin10", 806, R8A779A0_CLK_S1D1), + DEF_MOD("vin11", 807, R8A779A0_CLK_S1D1), + DEF_MOD("vin12", 808, R8A779A0_CLK_S1D1), + DEF_MOD("vin13", 809, R8A779A0_CLK_S1D1), + DEF_MOD("vin14", 810, R8A779A0_CLK_S1D1), + DEF_MOD("vin15", 811, R8A779A0_CLK_S1D1), + DEF_MOD("vin16", 812, R8A779A0_CLK_S1D1), + DEF_MOD("vin17", 813, R8A779A0_CLK_S1D1), + DEF_MOD("vin20", 814, R8A779A0_CLK_S1D1), + DEF_MOD("vin21", 815, R8A779A0_CLK_S1D1), + DEF_MOD("vin22", 816, R8A779A0_CLK_S1D1), + DEF_MOD("vin23", 817, R8A779A0_CLK_S1D1), + DEF_MOD("vin24", 818, R8A779A0_CLK_S1D1), + DEF_MOD("vin25", 819, R8A779A0_CLK_S1D1), + DEF_MOD("vin26", 820, R8A779A0_CLK_S1D1), + DEF_MOD("vin27", 821, R8A779A0_CLK_S1D1), + DEF_MOD("vin30", 822, R8A779A0_CLK_S1D1), + DEF_MOD("vin31", 823, R8A779A0_CLK_S1D1), + DEF_MOD("vin32", 824, R8A779A0_CLK_S1D1), + DEF_MOD("vin33", 825, R8A779A0_CLK_S1D1), + DEF_MOD("vin34", 826, R8A779A0_CLK_S1D1), + DEF_MOD("vin35", 827, R8A779A0_CLK_S1D1), + DEF_MOD("vin36", 828, R8A779A0_CLK_S1D1), + DEF_MOD("vin37", 829, R8A779A0_CLK_S1D1), + DEF_MOD("vspd0", 830, R8A779A0_CLK_S3D1), + DEF_MOD("vspd1", 831, R8A779A0_CLK_S3D1), + DEF_MOD("rwdt", 907, R8A779A0_CLK_R), + DEF_MOD("pfc0", 915, R8A779A0_CLK_CP), + DEF_MOD("pfc1", 916, R8A779A0_CLK_CP), + DEF_MOD("pfc2", 917, R8A779A0_CLK_CP), + DEF_MOD("pfc3", 918, R8A779A0_CLK_CP), + DEF_MOD("vspx0", 1028, R8A779A0_CLK_S1D1), + DEF_MOD("vspx1", 1029, R8A779A0_CLK_S1D1), + DEF_MOD("vspx2", 1030, R8A779A0_CLK_S1D1), + DEF_MOD("vspx3", 1031, R8A779A0_CLK_S1D1), +}; + +/* + * CPG Clock Data + */ + +/* + * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC + * 14 13 (MHz) 21 31 + * -------------------------------------------------------- + * 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16 + * 0 1 20 x 1 x106 x180 x106 x120 x160 /19 + * 1 0 Prohibited setting + * 1 1 33.33 / 2 x128 x216 x128 x144 x192 /32 + */ +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ + (((md) & BIT(13)) >> 13)) + +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] = { + /* EXTAL div PLL1 mult/div Not used OSC prediv PLL5 mult/div */ + { 1, 128, 1, 128, 1, 16, 192, 1, }, + { 1, 106, 1, 106, 1, 19, 160, 1, }, + { 0, 0, 0, 0, 0, 0, 0, 0, }, + { 2, 128, 1, 128, 1, 32, 192, 1, }, +}; + +/* + * Note that the only clock left running before booting Linux are now + * MFIS, INTC-AP, INTC-EX and SCIF0 on V3U + */ +#define MSTPCR7_SCIF0 BIT(2) +#define MSTPCR6_MFIS BIT(17) +#define MSTPCR6_INTC BIT(11) /* No information: INTC-AP, INTC-EX */ + +static const struct mstp_stop_table r8a779a0_mstp_table[] = { + { 0x003f7ffe, 0x0, 0x0, 0x0 }, + { 0x00cb0000, 0x0, 0x0, 0x0 }, + { 0x0001f800, 0x0, 0x0, 0x0 }, + { 0x90000000, 0x0, 0x0, 0x0 }, + { 0x0001c807, 0x0, 0x0, 0x0 }, + { 0x7e03c380, 0x0, 0x0, 0x0 }, + { 0x1f01f001, MSTPCR6_MFIS, 0x0, 0x0 }, + { 0xffffe040, MSTPCR7_SCIF0, 0x0, 0x0 }, + { 0xffffffff, 0x0, 0x0, 0x0 }, + { 0x00003c78, 0x0, 0x0, 0x0 }, + { 0xf0000000, 0x0, 0x0, 0x0 }, + { 0x0000000f, 0x0, 0x0, 0x0 }, + { 0xbe800000, 0x0, 0x0, 0x0 }, + { 0x00000037, 0x0, 0x0, 0x0 }, + { 0x00000000, 0x0, 0x0, 0x0 }, +}; + +static const void *r8a779a0_get_pll_config(const u32 cpg_mode) +{ + return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; +} + +static const struct cpg_mssr_info r8a779a0_cpg_mssr_info = { + .core_clk = r8a779a0_core_clks, + .core_clk_size = ARRAY_SIZE(r8a779a0_core_clks), + .mod_clk = r8a779a0_mod_clks, + .mod_clk_size = ARRAY_SIZE(r8a779a0_mod_clks), + .mstp_table = r8a779a0_mstp_table, + .mstp_table_size = ARRAY_SIZE(r8a779a0_mstp_table), + .reset_node = "renesas,r8a779a0-rst", + .reset_modemr_offset = 0x00, + .extalr_node = "extalr", + .mod_clk_base = MOD_CLK_BASE, + .clk_extal_id = CLK_EXTAL, + .clk_extalr_id = CLK_EXTALR, + .get_pll_config = r8a779a0_get_pll_config, + .reg_layout = CLK_REG_LAYOUT_RCAR_V3U, +}; + +static const struct udevice_id r8a779a0_clk_ids[] = { + { + .compatible = "renesas,r8a779a0-cpg-mssr", + .data = (ulong)&r8a779a0_cpg_mssr_info + }, + { } +}; + +U_BOOT_DRIVER(clk_r8a779a0) = { + .name = "clk_r8a779a0", + .id = UCLASS_CLK, + .of_match = r8a779a0_clk_ids, + .priv_auto = sizeof(struct gen3_clk_priv), + .ops = &gen3_clk_ops, + .probe = gen3_clk_probe, + .remove = gen3_clk_remove, +}; diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index aa940a1ca2..7bf5701361 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -27,6 +27,7 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_E3_RPCSRC, CLK_TYPE_GEN3_RPC, CLK_TYPE_GEN3_RPCD2, + CLK_TYPE_R8A779A0_MAIN, CLK_TYPE_R8A779A0_PLL1, CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */ diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index b1cf7f599c..e0895d2c2f 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -127,6 +127,10 @@ int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info) clrsetbits_le32(base + info->control_regs[i], info->mstp_table[i].sdis, info->mstp_table[i].sen); + + if (info->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) + continue; + clrsetbits_le32(base + RMSTPCR(i), info->mstp_table[i].rdis, info->mstp_table[i].ren); diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 92421b15ee..519f88548f 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -17,6 +17,7 @@
enum clk_reg_layout { CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0, + CLK_REG_LAYOUT_RCAR_V3U, };
struct cpg_mssr_info { @@ -146,6 +147,11 @@ static const u16 mstpsr[] = { 0x9A0, 0x9A4, 0x9A8, 0x9AC, };
+static const u16 mstpsr_for_v3u[] = { + 0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C, + 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, +}; + /* * System Module Stop Control Register offsets */ @@ -155,6 +161,11 @@ static const u16 smstpcr[] = { 0x990, 0x994, 0x998, 0x99C, };
+static const u16 mstpcr_for_v3u[] = { + 0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C, + 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, +}; + /* * Software Reset Register offsets */ @@ -164,6 +175,11 @@ static const u16 srcr[] = { 0x920, 0x924, 0x928, 0x92C, };
+static const u16 srcr_for_v3u[] = { + 0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C, + 0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, +}; + /* Realtime Module Stop Control Register offsets */ #define RMSTPCR(i) ((i) < 8 ? smstpcr[i] - 0x20 : smstpcr[i] - 0x10)
@@ -177,4 +193,9 @@ static const u16 srstclr[] = { 0x960, 0x964, 0x968, 0x96C, };
+static const u16 srstclr_for_v3u[] = { + 0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C, + 0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, +}; + #endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */
Pass struct udevice to rcar_gpio_set_direction() in preparation of quirk handling in rcar_gpio_set_direction(). No functional change.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- drivers/gpio/gpio-rcar.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index daaac5e784..5f1ec39a9b 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -66,9 +66,12 @@ static int rcar_gpio_set_value(struct udevice *dev, unsigned offset, return 0; }
-static void rcar_gpio_set_direction(void __iomem *regs, unsigned offset, +static void rcar_gpio_set_direction(struct udevice *dev, unsigned offset, bool output) { + struct rcar_gpio_priv *priv = dev_get_priv(dev); + void __iomem *regs = priv->regs; + /* * follow steps in the GPIO documentation for * "Setting General Output Mode" and @@ -90,9 +93,7 @@ static void rcar_gpio_set_direction(void __iomem *regs, unsigned offset,
static int rcar_gpio_direction_input(struct udevice *dev, unsigned offset) { - struct rcar_gpio_priv *priv = dev_get_priv(dev); - - rcar_gpio_set_direction(priv->regs, offset, false); + rcar_gpio_set_direction(dev, offset, false);
return 0; } @@ -100,11 +101,9 @@ static int rcar_gpio_direction_input(struct udevice *dev, unsigned offset) static int rcar_gpio_direction_output(struct udevice *dev, unsigned offset, int value) { - struct rcar_gpio_priv *priv = dev_get_priv(dev); - /* write GPIO value to output before selecting output mode of pin */ rcar_gpio_set_value(dev, offset, value); - rcar_gpio_set_direction(priv->regs, offset, true); + rcar_gpio_set_direction(dev, offset, true);
return 0; }
Hi Marek,
Thank you for the patch.
On Wed, Apr 28, 2021 at 8:33 PM Marek Vasut marek.vasut@gmail.com wrote:
Pass struct udevice to rcar_gpio_set_direction() in preparation of quirk handling in rcar_gpio_set_direction(). No functional change.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com
drivers/gpio/gpio-rcar.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-)
Tested on RZ/G2{EHMN} boards
Tested-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
Cheers, Prabhakar
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index daaac5e784..5f1ec39a9b 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -66,9 +66,12 @@ static int rcar_gpio_set_value(struct udevice *dev, unsigned offset, return 0; }
-static void rcar_gpio_set_direction(void __iomem *regs, unsigned offset, +static void rcar_gpio_set_direction(struct udevice *dev, unsigned offset, bool output) {
struct rcar_gpio_priv *priv = dev_get_priv(dev);void __iomem *regs = priv->regs;/* * follow steps in the GPIO documentation for * "Setting General Output Mode" and@@ -90,9 +93,7 @@ static void rcar_gpio_set_direction(void __iomem *regs, unsigned offset,
static int rcar_gpio_direction_input(struct udevice *dev, unsigned offset) {
struct rcar_gpio_priv *priv = dev_get_priv(dev);rcar_gpio_set_direction(priv->regs, offset, false);
rcar_gpio_set_direction(dev, offset, false); return 0;} @@ -100,11 +101,9 @@ static int rcar_gpio_direction_input(struct udevice *dev, unsigned offset) static int rcar_gpio_direction_output(struct udevice *dev, unsigned offset, int value) {
struct rcar_gpio_priv *priv = dev_get_priv(dev);/* write GPIO value to output before selecting output mode of pin */ rcar_gpio_set_value(dev, offset, value);rcar_gpio_set_direction(priv->regs, offset, true);
rcar_gpio_set_direction(dev, offset, true); return 0;}
2.30.2
The R8A779A0 V3U GPIO block has additional "General Input Enable" INEN register. Add new R8A779A0 compatible string with a new quirk and also a handler for this quirk which toggles the INEN register in the right place. INEN register handling is based on "gpio: renesas: Add R8A779A0 V3U support" by Hai Pham hai.pham.ud@renesas.com
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- drivers/gpio/gpio-rcar.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index 5f1ec39a9b..76f47027a3 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -28,13 +28,17 @@ #define GPIO_EDGLEVEL 0x24 /* Edge/level Select Register */ #define GPIO_FILONOFF 0x28 /* Chattering Prevention On/Off Register */ #define GPIO_BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */ +#define GPIO_INEN 0x50 /* General Input Enable Register */
#define RCAR_MAX_GPIO_PER_BANK 32
+#define RCAR_GPIO_HAS_INEN BIT(0) + DECLARE_GLOBAL_DATA_PTR;
struct rcar_gpio_priv { void __iomem *regs; + u32 quirks; int pfc_offset; };
@@ -81,6 +85,14 @@ static void rcar_gpio_set_direction(struct udevice *dev, unsigned offset, /* Configure postive logic in POSNEG */ clrbits_le32(regs + GPIO_POSNEG, BIT(offset));
+ /* Select "Input Enable/Disable" in INEN */ + if (priv->quirks & RCAR_GPIO_HAS_INEN) { + if (output) + clrbits_le32(regs + GPIO_INEN, BIT(offset)); + else + setbits_le32(regs + GPIO_INEN, BIT(offset)); + } + /* Select "General Input/Output Mode" in IOINTSEL */ clrbits_le32(regs + GPIO_IOINTSEL, BIT(offset));
@@ -149,6 +161,7 @@ static int rcar_gpio_probe(struct udevice *dev) int ret;
priv->regs = dev_read_addr_ptr(dev); + priv->quirks = dev_get_driver_data(dev); uc_priv->bank_name = dev->name;
ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges", @@ -179,6 +192,7 @@ static const struct udevice_id rcar_gpio_ids[] = { { .compatible = "renesas,gpio-r8a77970" }, { .compatible = "renesas,gpio-r8a77990" }, { .compatible = "renesas,gpio-r8a77995" }, + { .compatible = "renesas,gpio-r8a779a0", .data = RCAR_GPIO_HAS_INEN }, { .compatible = "renesas,rcar-gen2-gpio" }, { .compatible = "renesas,rcar-gen3-gpio" }, { /* sentinel */ }
Synchronize R-Car Gen2/Gen3 pinctrl tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . This is a rather large commit, since the macros in sh-pfc.h also got updated, so all the PFC tables must be updated in lockstep.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- drivers/pinctrl/renesas/pfc-r8a7790.c | 1019 +++++++++++++++--------- drivers/pinctrl/renesas/pfc-r8a7791.c | 20 +- drivers/pinctrl/renesas/pfc-r8a7792.c | 2 +- drivers/pinctrl/renesas/pfc-r8a7794.c | 2 +- drivers/pinctrl/renesas/pfc-r8a7795.c | 467 ++++++----- drivers/pinctrl/renesas/pfc-r8a7796.c | 492 +++++++----- drivers/pinctrl/renesas/pfc-r8a77965.c | 446 ++++++----- drivers/pinctrl/renesas/pfc-r8a77970.c | 104 ++- drivers/pinctrl/renesas/pfc-r8a77980.c | 80 +- drivers/pinctrl/renesas/pfc-r8a77990.c | 183 ++--- drivers/pinctrl/renesas/pfc-r8a77995.c | 4 +- drivers/pinctrl/renesas/sh_pfc.h | 130 ++- 12 files changed, 1834 insertions(+), 1115 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c index 5e1502ed96..1793000ab5 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7790.c +++ b/drivers/pinctrl/renesas/pfc-r8a7790.c @@ -20,7 +20,7 @@ * All pins assigned to GPIO bank 3 can be used for SD interfaces in * which case they support both 3.3V and 1.8V signalling. */ -#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ PORT_GP_30(1, fn, sfx), \ PORT_GP_30(2, fn, sfx), \ @@ -28,6 +28,12 @@ PORT_GP_32(4, fn, sfx), \ PORT_GP_32(5, fn, sfx)
+#define CPU_ALL_NOGP(fn) \ + PIN_NOGP(IIC0_SDA, "AF15", fn), \ + PIN_NOGP(IIC0_SCL, "AG15", fn), \ + PIN_NOGP(IIC3_SDA, "AH15", fn), \ + PIN_NOGP(IIC3_SCL, "AJ15", fn) + enum { PINMUX_RESERVED = 0,
@@ -1727,19 +1733,17 @@ static const u16 pinmux_data[] = { PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1), };
-/* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */ -#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) -#define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200) -#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) +/* + * Pins not associated with a GPIO port. + */ +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +};
static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), - - /* Pins not associated with a GPIO port */ - SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15), - SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15), - SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15), - SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15), + PINMUX_NOGP_ALL(), };
/* - AUDIO CLOCK ------------------------------------------------------------ */ @@ -1867,6 +1871,86 @@ static const unsigned int avb_gmii_mux[] = { AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, AVB_COL_MARK, }; +/* - CAN0 ----------------------------------------------------------------- */ +static const unsigned int can0_data_pins[] = { + /* CAN0 RX */ + RCAR_GP_PIN(1, 17), + /* CAN0 TX */ + RCAR_GP_PIN(1, 19), +}; +static const unsigned int can0_data_mux[] = { + CAN0_RX_MARK, + CAN0_TX_MARK, +}; +static const unsigned int can0_data_b_pins[] = { + /* CAN0 RXB */ + RCAR_GP_PIN(4, 5), + /* CAN0 TXB */ + RCAR_GP_PIN(4, 4), +}; +static const unsigned int can0_data_b_mux[] = { + CAN0_RX_B_MARK, + CAN0_TX_B_MARK, +}; +static const unsigned int can0_data_c_pins[] = { + /* CAN0 RXC */ + RCAR_GP_PIN(4, 26), + /* CAN0 TXC */ + RCAR_GP_PIN(4, 23), +}; +static const unsigned int can0_data_c_mux[] = { + CAN0_RX_C_MARK, + CAN0_TX_C_MARK, +}; +static const unsigned int can0_data_d_pins[] = { + /* CAN0 RXD */ + RCAR_GP_PIN(4, 26), + /* CAN0 TXD */ + RCAR_GP_PIN(4, 18), +}; +static const unsigned int can0_data_d_mux[] = { + CAN0_RX_D_MARK, + CAN0_TX_D_MARK, +}; +/* - CAN1 ----------------------------------------------------------------- */ +static const unsigned int can1_data_pins[] = { + /* CAN1 RX */ + RCAR_GP_PIN(1, 22), + /* CAN1 TX */ + RCAR_GP_PIN(1, 18), +}; +static const unsigned int can1_data_mux[] = { + CAN1_RX_MARK, + CAN1_TX_MARK, +}; +static const unsigned int can1_data_b_pins[] = { + /* CAN1 RXB */ + RCAR_GP_PIN(4, 7), + /* CAN1 TXB */ + RCAR_GP_PIN(4, 6), +}; +static const unsigned int can1_data_b_mux[] = { + CAN1_RX_B_MARK, + CAN1_TX_B_MARK, +}; +/* - CAN Clock -------------------------------------------------------------- */ +static const unsigned int can_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(1, 21), +}; + +static const unsigned int can_clk_mux[] = { + CAN_CLK_MARK, +}; + +static const unsigned int can_clk_b_pins[] = { + /* CLK */ + RCAR_GP_PIN(4, 3), +}; + +static const unsigned int can_clk_b_mux[] = { + CAN_CLK_B_MARK, +}; /* - DU RGB ----------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -2135,7 +2219,7 @@ static const unsigned int hscif1_ctrl_b_mux[] = { /* - I2C0 ------------------------------------------------------------------- */ static const unsigned int i2c0_pins[] = { /* SCL, SDA */ - PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15), + PIN_IIC0_SCL, PIN_IIC0_SDA, }; static const unsigned int i2c0_mux[] = { I2C0_SCL_MARK, I2C0_SDA_MARK, @@ -2201,7 +2285,7 @@ static const unsigned int i2c2_e_mux[] = { /* - I2C3 ------------------------------------------------------------------- */ static const unsigned int i2c3_pins[] = { /* SCL, SDA */ - PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15), + PIN_IIC3_SCL, PIN_IIC3_SDA, }; static const unsigned int i2c3_mux[] = { I2C3_SCL_MARK, I2C3_SDA_MARK, @@ -2209,7 +2293,7 @@ static const unsigned int i2c3_mux[] = { /* - IIC0 (I2C4) ------------------------------------------------------------ */ static const unsigned int iic0_pins[] = { /* SCL, SDA */ - PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15), + PIN_IIC0_SCL, PIN_IIC0_SDA, }; static const unsigned int iic0_mux[] = { IIC0_SCL_MARK, IIC0_SDA_MARK, @@ -2274,8 +2358,8 @@ static const unsigned int iic2_e_mux[] = { }; /* - IIC3 (I2C7) ------------------------------------------------------------ */ static const unsigned int iic3_pins[] = { -/* SCL, SDA */ - PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15), + /* SCL, SDA */ + PIN_IIC3_SCL, PIN_IIC3_SDA, }; static const unsigned int iic3_mux[] = { IIC3_SCL_MARK, IIC3_SDA_MARK, @@ -2309,6 +2393,8 @@ static const unsigned int intc_irq3_pins[] = { static const unsigned int intc_irq3_mux[] = { IRQ3_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_R8A7790 /* - MLB+ ------------------------------------------------------------------- */ static const unsigned int mlb_3pin_pins[] = { RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), @@ -2316,6 +2402,8 @@ static const unsigned int mlb_3pin_pins[] = { static const unsigned int mlb_3pin_mux[] = { MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, }; +#endif /* CONFIG_PINCTRL_PFC_R8A7790 */ + /* - MMCIF0 ----------------------------------------------------------------- */ static const unsigned int mmc0_data1_pins[] = { /* D[0] */ @@ -3607,6 +3695,13 @@ static const unsigned int usb1_pins[] = { static const unsigned int usb1_mux[] = { USB1_PWEN_MARK, USB1_OVC_MARK, }; +static const unsigned int usb1_pwen_pins[] = { + /* PWEN */ + RCAR_GP_PIN(5, 20), +}; +static const unsigned int usb1_pwen_mux[] = { + USB1_PWEN_MARK, +}; /* - USB2 ------------------------------------------------------------------- */ static const unsigned int usb2_pins[] = { /* PWEN, OVC */ @@ -3775,6 +3870,72 @@ static const unsigned int vin1_data18_mux[] = { VI1_R4_MARK, VI1_R5_MARK, VI1_R6_MARK, VI1_R7_MARK, }; +static const union vin_data vin1_data_b_pins = { + .data24 = { + /* B */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), + /* G */ + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), + /* R */ + RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), + }, +}; +static const union vin_data vin1_data_b_mux = { + .data24 = { + /* B */ + VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK, + VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK, + VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK, + VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK, + /* G */ + VI1_G0_B_MARK, VI1_G1_B_MARK, + VI1_G2_B_MARK, VI1_G3_B_MARK, + VI1_G4_B_MARK, VI1_G5_B_MARK, + VI1_G6_B_MARK, VI1_G7_B_MARK, + /* R */ + VI1_R0_B_MARK, VI1_R1_B_MARK, + VI1_R2_B_MARK, VI1_R3_B_MARK, + VI1_R4_B_MARK, VI1_R5_B_MARK, + VI1_R6_B_MARK, VI1_R7_B_MARK, + }, +}; +static const unsigned int vin1_data18_b_pins[] = { + /* B */ + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), + /* G */ + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), + /* R */ + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), +}; +static const unsigned int vin1_data18_b_mux[] = { + /* B */ + VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK, + VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK, + VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK, + /* G */ + VI1_G2_B_MARK, VI1_G3_B_MARK, + VI1_G4_B_MARK, VI1_G5_B_MARK, + VI1_G6_B_MARK, VI1_G7_B_MARK, + /* R */ + VI1_R2_B_MARK, VI1_R3_B_MARK, + VI1_R4_B_MARK, VI1_R5_B_MARK, + VI1_R6_B_MARK, VI1_R7_B_MARK, +}; static const unsigned int vin1_sync_pins[] = { RCAR_GP_PIN(1, 24), /* HSYNC */ RCAR_GP_PIN(1, 25), /* VSYNC */ @@ -3783,24 +3944,50 @@ static const unsigned int vin1_sync_mux[] = { VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK, }; +static const unsigned int vin1_sync_b_pins[] = { + RCAR_GP_PIN(1, 24), /* HSYNC */ + RCAR_GP_PIN(1, 25), /* VSYNC */ +}; +static const unsigned int vin1_sync_b_mux[] = { + VI1_HSYNC_N_B_MARK, + VI1_VSYNC_N_B_MARK, +}; static const unsigned int vin1_field_pins[] = { RCAR_GP_PIN(1, 13), }; static const unsigned int vin1_field_mux[] = { VI1_FIELD_MARK, }; +static const unsigned int vin1_field_b_pins[] = { + RCAR_GP_PIN(1, 13), +}; +static const unsigned int vin1_field_b_mux[] = { + VI1_FIELD_B_MARK, +}; static const unsigned int vin1_clkenb_pins[] = { RCAR_GP_PIN(1, 26), }; static const unsigned int vin1_clkenb_mux[] = { VI1_CLKENB_MARK, }; +static const unsigned int vin1_clkenb_b_pins[] = { + RCAR_GP_PIN(1, 26), +}; +static const unsigned int vin1_clkenb_b_mux[] = { + VI1_CLKENB_B_MARK, +}; static const unsigned int vin1_clk_pins[] = { RCAR_GP_PIN(2, 9), }; static const unsigned int vin1_clk_mux[] = { VI1_CLK_MARK, }; +static const unsigned int vin1_clk_b_pins[] = { + RCAR_GP_PIN(3, 15), +}; +static const unsigned int vin1_clk_b_mux[] = { + VI1_CLK_B_MARK, +}; /* - VIN2 ----------------------------------------------------------------- */ static const union vin_data vin2_data_pins = { .data24 = { @@ -3868,6 +4055,18 @@ static const unsigned int vin2_data18_mux[] = { VI2_R4_MARK, VI2_R5_MARK, VI2_R6_MARK, VI2_R7_MARK, }; +static const unsigned int vin2_g8_pins[] = { + RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +}; +static const unsigned int vin2_g8_mux[] = { + VI2_G0_MARK, VI2_G1_MARK, + VI2_G2_MARK, VI2_G3_MARK, + VI2_G4_MARK, VI2_G5_MARK, + VI2_G6_MARK, VI2_G7_MARK, +}; static const unsigned int vin2_sync_pins[] = { RCAR_GP_PIN(1, 16), /* HSYNC */ RCAR_GP_PIN(1, 21), /* VSYNC */ @@ -3934,297 +4133,330 @@ static const unsigned int vin3_clk_mux[] = { VI3_CLK_MARK, };
-static const struct sh_pfc_pin_group pinmux_groups[] = { - SH_PFC_PIN_GROUP(audio_clk_a), - SH_PFC_PIN_GROUP(audio_clk_b), - SH_PFC_PIN_GROUP(audio_clk_c), - SH_PFC_PIN_GROUP(audio_clkout), - SH_PFC_PIN_GROUP(audio_clkout_b), - SH_PFC_PIN_GROUP(audio_clkout_c), - SH_PFC_PIN_GROUP(audio_clkout_d), - SH_PFC_PIN_GROUP(avb_link), - SH_PFC_PIN_GROUP(avb_magic), - SH_PFC_PIN_GROUP(avb_phy_int), - SH_PFC_PIN_GROUP(avb_mdio), - SH_PFC_PIN_GROUP(avb_mii), - SH_PFC_PIN_GROUP(avb_gmii), - SH_PFC_PIN_GROUP(du_rgb666), - SH_PFC_PIN_GROUP(du_rgb888), - SH_PFC_PIN_GROUP(du_clk_out_0), - SH_PFC_PIN_GROUP(du_clk_out_1), - SH_PFC_PIN_GROUP(du_sync_0), - SH_PFC_PIN_GROUP(du_sync_1), - SH_PFC_PIN_GROUP(du_cde), - SH_PFC_PIN_GROUP(du0_clk_in), - SH_PFC_PIN_GROUP(du1_clk_in), - SH_PFC_PIN_GROUP(du2_clk_in), - SH_PFC_PIN_GROUP(eth_link), - SH_PFC_PIN_GROUP(eth_magic), - SH_PFC_PIN_GROUP(eth_mdio), - SH_PFC_PIN_GROUP(eth_rmii), - SH_PFC_PIN_GROUP(hscif0_data), - SH_PFC_PIN_GROUP(hscif0_clk), - SH_PFC_PIN_GROUP(hscif0_ctrl), - SH_PFC_PIN_GROUP(hscif0_data_b), - SH_PFC_PIN_GROUP(hscif0_ctrl_b), - SH_PFC_PIN_GROUP(hscif0_data_c), - SH_PFC_PIN_GROUP(hscif0_ctrl_c), - SH_PFC_PIN_GROUP(hscif0_data_d), - SH_PFC_PIN_GROUP(hscif0_ctrl_d), - SH_PFC_PIN_GROUP(hscif0_data_e), - SH_PFC_PIN_GROUP(hscif0_ctrl_e), - SH_PFC_PIN_GROUP(hscif0_data_f), - SH_PFC_PIN_GROUP(hscif0_ctrl_f), - SH_PFC_PIN_GROUP(hscif1_data), - SH_PFC_PIN_GROUP(hscif1_clk), - SH_PFC_PIN_GROUP(hscif1_ctrl), - SH_PFC_PIN_GROUP(hscif1_data_b), - SH_PFC_PIN_GROUP(hscif1_clk_b), - SH_PFC_PIN_GROUP(hscif1_ctrl_b), - SH_PFC_PIN_GROUP(i2c0), - SH_PFC_PIN_GROUP(i2c1), - SH_PFC_PIN_GROUP(i2c1_b), - SH_PFC_PIN_GROUP(i2c1_c), - SH_PFC_PIN_GROUP(i2c2), - SH_PFC_PIN_GROUP(i2c2_b), - SH_PFC_PIN_GROUP(i2c2_c), - SH_PFC_PIN_GROUP(i2c2_d), - SH_PFC_PIN_GROUP(i2c2_e), - SH_PFC_PIN_GROUP(i2c3), - SH_PFC_PIN_GROUP(iic0), - SH_PFC_PIN_GROUP(iic1), - SH_PFC_PIN_GROUP(iic1_b), - SH_PFC_PIN_GROUP(iic1_c), - SH_PFC_PIN_GROUP(iic2), - SH_PFC_PIN_GROUP(iic2_b), - SH_PFC_PIN_GROUP(iic2_c), - SH_PFC_PIN_GROUP(iic2_d), - SH_PFC_PIN_GROUP(iic2_e), - SH_PFC_PIN_GROUP(iic3), - SH_PFC_PIN_GROUP(intc_irq0), - SH_PFC_PIN_GROUP(intc_irq1), - SH_PFC_PIN_GROUP(intc_irq2), - SH_PFC_PIN_GROUP(intc_irq3), - SH_PFC_PIN_GROUP(mlb_3pin), - SH_PFC_PIN_GROUP(mmc0_data1), - SH_PFC_PIN_GROUP(mmc0_data4), - SH_PFC_PIN_GROUP(mmc0_data8), - SH_PFC_PIN_GROUP(mmc0_ctrl), - SH_PFC_PIN_GROUP(mmc1_data1), - SH_PFC_PIN_GROUP(mmc1_data4), - SH_PFC_PIN_GROUP(mmc1_data8), - SH_PFC_PIN_GROUP(mmc1_ctrl), - SH_PFC_PIN_GROUP(msiof0_clk), - SH_PFC_PIN_GROUP(msiof0_sync), - SH_PFC_PIN_GROUP(msiof0_ss1), - SH_PFC_PIN_GROUP(msiof0_ss2), - SH_PFC_PIN_GROUP(msiof0_rx), - SH_PFC_PIN_GROUP(msiof0_tx), - SH_PFC_PIN_GROUP(msiof0_clk_b), - SH_PFC_PIN_GROUP(msiof0_ss1_b), - SH_PFC_PIN_GROUP(msiof0_ss2_b), - SH_PFC_PIN_GROUP(msiof0_rx_b), - SH_PFC_PIN_GROUP(msiof0_tx_b), - SH_PFC_PIN_GROUP(msiof1_clk), - SH_PFC_PIN_GROUP(msiof1_sync), - SH_PFC_PIN_GROUP(msiof1_ss1), - SH_PFC_PIN_GROUP(msiof1_ss2), - SH_PFC_PIN_GROUP(msiof1_rx), - SH_PFC_PIN_GROUP(msiof1_tx), - SH_PFC_PIN_GROUP(msiof1_clk_b), - SH_PFC_PIN_GROUP(msiof1_ss1_b), - SH_PFC_PIN_GROUP(msiof1_ss2_b), - SH_PFC_PIN_GROUP(msiof1_rx_b), - SH_PFC_PIN_GROUP(msiof1_tx_b), - SH_PFC_PIN_GROUP(msiof2_clk), - SH_PFC_PIN_GROUP(msiof2_sync), - SH_PFC_PIN_GROUP(msiof2_ss1), - SH_PFC_PIN_GROUP(msiof2_ss2), - SH_PFC_PIN_GROUP(msiof2_rx), - SH_PFC_PIN_GROUP(msiof2_tx), - SH_PFC_PIN_GROUP(msiof3_clk), - SH_PFC_PIN_GROUP(msiof3_sync), - SH_PFC_PIN_GROUP(msiof3_ss1), - SH_PFC_PIN_GROUP(msiof3_ss2), - SH_PFC_PIN_GROUP(msiof3_rx), - SH_PFC_PIN_GROUP(msiof3_tx), - SH_PFC_PIN_GROUP(msiof3_clk_b), - SH_PFC_PIN_GROUP(msiof3_sync_b), - SH_PFC_PIN_GROUP(msiof3_rx_b), - SH_PFC_PIN_GROUP(msiof3_tx_b), - SH_PFC_PIN_GROUP(pwm0), - SH_PFC_PIN_GROUP(pwm0_b), - SH_PFC_PIN_GROUP(pwm1), - SH_PFC_PIN_GROUP(pwm1_b), - SH_PFC_PIN_GROUP(pwm2), - SH_PFC_PIN_GROUP(pwm3), - SH_PFC_PIN_GROUP(pwm4), - SH_PFC_PIN_GROUP(pwm5), - SH_PFC_PIN_GROUP(pwm6), - SH_PFC_PIN_GROUP(qspi_ctrl), - SH_PFC_PIN_GROUP(qspi_data2), - SH_PFC_PIN_GROUP(qspi_data4), - SH_PFC_PIN_GROUP(scif0_data), - SH_PFC_PIN_GROUP(scif0_clk), - SH_PFC_PIN_GROUP(scif0_ctrl), - SH_PFC_PIN_GROUP(scif0_data_b), - SH_PFC_PIN_GROUP(scif1_data), - SH_PFC_PIN_GROUP(scif1_clk), - SH_PFC_PIN_GROUP(scif1_ctrl), - SH_PFC_PIN_GROUP(scif1_data_b), - SH_PFC_PIN_GROUP(scif1_data_c), - SH_PFC_PIN_GROUP(scif1_data_d), - SH_PFC_PIN_GROUP(scif1_clk_d), - SH_PFC_PIN_GROUP(scif1_data_e), - SH_PFC_PIN_GROUP(scif1_clk_e), - SH_PFC_PIN_GROUP(scif2_data), - SH_PFC_PIN_GROUP(scif2_clk), - SH_PFC_PIN_GROUP(scif2_data_b), - SH_PFC_PIN_GROUP(scifa0_data), - SH_PFC_PIN_GROUP(scifa0_clk), - SH_PFC_PIN_GROUP(scifa0_ctrl), - SH_PFC_PIN_GROUP(scifa0_data_b), - SH_PFC_PIN_GROUP(scifa0_clk_b), - SH_PFC_PIN_GROUP(scifa0_ctrl_b), - SH_PFC_PIN_GROUP(scifa1_data), - SH_PFC_PIN_GROUP(scifa1_clk), - SH_PFC_PIN_GROUP(scifa1_ctrl), - SH_PFC_PIN_GROUP(scifa1_data_b), - SH_PFC_PIN_GROUP(scifa1_clk_b), - SH_PFC_PIN_GROUP(scifa1_ctrl_b), - SH_PFC_PIN_GROUP(scifa1_data_c), - SH_PFC_PIN_GROUP(scifa1_clk_c), - SH_PFC_PIN_GROUP(scifa1_ctrl_c), - SH_PFC_PIN_GROUP(scifa1_data_d), - SH_PFC_PIN_GROUP(scifa1_clk_d), - SH_PFC_PIN_GROUP(scifa1_ctrl_d), - SH_PFC_PIN_GROUP(scifa2_data), - SH_PFC_PIN_GROUP(scifa2_clk), - SH_PFC_PIN_GROUP(scifa2_ctrl), - SH_PFC_PIN_GROUP(scifa2_data_b), - SH_PFC_PIN_GROUP(scifa2_data_c), - SH_PFC_PIN_GROUP(scifa2_clk_c), - SH_PFC_PIN_GROUP(scifb0_data), - SH_PFC_PIN_GROUP(scifb0_clk), - SH_PFC_PIN_GROUP(scifb0_ctrl), - SH_PFC_PIN_GROUP(scifb0_data_b), - SH_PFC_PIN_GROUP(scifb0_clk_b), - SH_PFC_PIN_GROUP(scifb0_ctrl_b), - SH_PFC_PIN_GROUP(scifb0_data_c), - SH_PFC_PIN_GROUP(scifb1_data), - SH_PFC_PIN_GROUP(scifb1_clk), - SH_PFC_PIN_GROUP(scifb1_ctrl), - SH_PFC_PIN_GROUP(scifb1_data_b), - SH_PFC_PIN_GROUP(scifb1_clk_b), - SH_PFC_PIN_GROUP(scifb1_ctrl_b), - SH_PFC_PIN_GROUP(scifb1_data_c), - SH_PFC_PIN_GROUP(scifb1_data_d), - SH_PFC_PIN_GROUP(scifb1_data_e), - SH_PFC_PIN_GROUP(scifb1_clk_e), - SH_PFC_PIN_GROUP(scifb1_data_f), - SH_PFC_PIN_GROUP(scifb1_data_g), - SH_PFC_PIN_GROUP(scifb1_clk_g), - SH_PFC_PIN_GROUP(scifb2_data), - SH_PFC_PIN_GROUP(scifb2_clk), - SH_PFC_PIN_GROUP(scifb2_ctrl), - SH_PFC_PIN_GROUP(scifb2_data_b), - SH_PFC_PIN_GROUP(scifb2_clk_b), - SH_PFC_PIN_GROUP(scifb2_ctrl_b), - SH_PFC_PIN_GROUP(scifb2_data_c), - SH_PFC_PIN_GROUP(scif_clk), - SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), - SH_PFC_PIN_GROUP(sdhi0_ctrl), - SH_PFC_PIN_GROUP(sdhi0_cd), - SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), - SH_PFC_PIN_GROUP(sdhi1_ctrl), - SH_PFC_PIN_GROUP(sdhi1_cd), - SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_ctrl), - SH_PFC_PIN_GROUP(sdhi2_cd), - SH_PFC_PIN_GROUP(sdhi2_wp), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_ctrl), - SH_PFC_PIN_GROUP(sdhi3_cd), - SH_PFC_PIN_GROUP(sdhi3_wp), - SH_PFC_PIN_GROUP(ssi0_data), - SH_PFC_PIN_GROUP(ssi0129_ctrl), - SH_PFC_PIN_GROUP(ssi1_data), - SH_PFC_PIN_GROUP(ssi1_ctrl), - SH_PFC_PIN_GROUP(ssi2_data), - SH_PFC_PIN_GROUP(ssi2_ctrl), - SH_PFC_PIN_GROUP(ssi3_data), - SH_PFC_PIN_GROUP(ssi34_ctrl), - SH_PFC_PIN_GROUP(ssi4_data), - SH_PFC_PIN_GROUP(ssi4_ctrl), - SH_PFC_PIN_GROUP(ssi5), - SH_PFC_PIN_GROUP(ssi5_b), - SH_PFC_PIN_GROUP(ssi5_c), - SH_PFC_PIN_GROUP(ssi6), - SH_PFC_PIN_GROUP(ssi6_b), - SH_PFC_PIN_GROUP(ssi7_data), - SH_PFC_PIN_GROUP(ssi7_b_data), - SH_PFC_PIN_GROUP(ssi7_c_data), - SH_PFC_PIN_GROUP(ssi78_ctrl), - SH_PFC_PIN_GROUP(ssi78_b_ctrl), - SH_PFC_PIN_GROUP(ssi78_c_ctrl), - SH_PFC_PIN_GROUP(ssi8_data), - SH_PFC_PIN_GROUP(ssi8_b_data), - SH_PFC_PIN_GROUP(ssi8_c_data), - SH_PFC_PIN_GROUP(ssi9_data), - SH_PFC_PIN_GROUP(ssi9_ctrl), - SH_PFC_PIN_GROUP(tpu0_to0), - SH_PFC_PIN_GROUP(tpu0_to1), - SH_PFC_PIN_GROUP(tpu0_to2), - SH_PFC_PIN_GROUP(tpu0_to3), - SH_PFC_PIN_GROUP(usb0), - SH_PFC_PIN_GROUP(usb0_ovc_vbus), - SH_PFC_PIN_GROUP(usb1), - SH_PFC_PIN_GROUP(usb2), - VIN_DATA_PIN_GROUP(vin0_data, 24), - VIN_DATA_PIN_GROUP(vin0_data, 20), - SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 16), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 8), - VIN_DATA_PIN_GROUP(vin0_data, 4), - SH_PFC_PIN_GROUP(vin0_sync), - SH_PFC_PIN_GROUP(vin0_field), - SH_PFC_PIN_GROUP(vin0_clkenb), - SH_PFC_PIN_GROUP(vin0_clk), - VIN_DATA_PIN_GROUP(vin1_data, 24), - VIN_DATA_PIN_GROUP(vin1_data, 20), - SH_PFC_PIN_GROUP(vin1_data18), - VIN_DATA_PIN_GROUP(vin1_data, 16), - VIN_DATA_PIN_GROUP(vin1_data, 12), - VIN_DATA_PIN_GROUP(vin1_data, 10), - VIN_DATA_PIN_GROUP(vin1_data, 8), - VIN_DATA_PIN_GROUP(vin1_data, 4), - SH_PFC_PIN_GROUP(vin1_sync), - SH_PFC_PIN_GROUP(vin1_field), - SH_PFC_PIN_GROUP(vin1_clkenb), - SH_PFC_PIN_GROUP(vin1_clk), - VIN_DATA_PIN_GROUP(vin2_data, 24), - SH_PFC_PIN_GROUP(vin2_data18), - VIN_DATA_PIN_GROUP(vin2_data, 16), - VIN_DATA_PIN_GROUP(vin2_data, 8), - VIN_DATA_PIN_GROUP(vin2_data, 4), - SH_PFC_PIN_GROUP(vin2_sync), - SH_PFC_PIN_GROUP(vin2_field), - SH_PFC_PIN_GROUP(vin2_clkenb), - SH_PFC_PIN_GROUP(vin2_clk), - SH_PFC_PIN_GROUP(vin3_data8), - SH_PFC_PIN_GROUP(vin3_sync), - SH_PFC_PIN_GROUP(vin3_field), - SH_PFC_PIN_GROUP(vin3_clkenb), - SH_PFC_PIN_GROUP(vin3_clk), +static const struct { + struct sh_pfc_pin_group common[311]; +#ifdef CONFIG_PINCTRL_PFC_R8A7790 + struct sh_pfc_pin_group automotive[1]; +#endif +} pinmux_groups = { + .common = { + SH_PFC_PIN_GROUP(audio_clk_a), + SH_PFC_PIN_GROUP(audio_clk_b), + SH_PFC_PIN_GROUP(audio_clk_c), + SH_PFC_PIN_GROUP(audio_clkout), + SH_PFC_PIN_GROUP(audio_clkout_b), + SH_PFC_PIN_GROUP(audio_clkout_c), + SH_PFC_PIN_GROUP(audio_clkout_d), + SH_PFC_PIN_GROUP(avb_link), + SH_PFC_PIN_GROUP(avb_magic), + SH_PFC_PIN_GROUP(avb_phy_int), + SH_PFC_PIN_GROUP(avb_mdio), + SH_PFC_PIN_GROUP(avb_mii), + SH_PFC_PIN_GROUP(avb_gmii), + SH_PFC_PIN_GROUP(can0_data), + SH_PFC_PIN_GROUP(can0_data_b), + SH_PFC_PIN_GROUP(can0_data_c), + SH_PFC_PIN_GROUP(can0_data_d), + SH_PFC_PIN_GROUP(can1_data), + SH_PFC_PIN_GROUP(can1_data_b), + SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(can_clk_b), + SH_PFC_PIN_GROUP(du_rgb666), + SH_PFC_PIN_GROUP(du_rgb888), + SH_PFC_PIN_GROUP(du_clk_out_0), + SH_PFC_PIN_GROUP(du_clk_out_1), + SH_PFC_PIN_GROUP(du_sync_0), + SH_PFC_PIN_GROUP(du_sync_1), + SH_PFC_PIN_GROUP(du_cde), + SH_PFC_PIN_GROUP(du0_clk_in), + SH_PFC_PIN_GROUP(du1_clk_in), + SH_PFC_PIN_GROUP(du2_clk_in), + SH_PFC_PIN_GROUP(eth_link), + SH_PFC_PIN_GROUP(eth_magic), + SH_PFC_PIN_GROUP(eth_mdio), + SH_PFC_PIN_GROUP(eth_rmii), + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif0_data_b), + SH_PFC_PIN_GROUP(hscif0_ctrl_b), + SH_PFC_PIN_GROUP(hscif0_data_c), + SH_PFC_PIN_GROUP(hscif0_ctrl_c), + SH_PFC_PIN_GROUP(hscif0_data_d), + SH_PFC_PIN_GROUP(hscif0_ctrl_d), + SH_PFC_PIN_GROUP(hscif0_data_e), + SH_PFC_PIN_GROUP(hscif0_ctrl_e), + SH_PFC_PIN_GROUP(hscif0_data_f), + SH_PFC_PIN_GROUP(hscif0_ctrl_f), + SH_PFC_PIN_GROUP(hscif1_data), + SH_PFC_PIN_GROUP(hscif1_clk), + SH_PFC_PIN_GROUP(hscif1_ctrl), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_clk_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(i2c0), + SH_PFC_PIN_GROUP(i2c1), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c1_c), + SH_PFC_PIN_GROUP(i2c2), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c2_c), + SH_PFC_PIN_GROUP(i2c2_d), + SH_PFC_PIN_GROUP(i2c2_e), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(iic0), + SH_PFC_PIN_GROUP(iic1), + SH_PFC_PIN_GROUP(iic1_b), + SH_PFC_PIN_GROUP(iic1_c), + SH_PFC_PIN_GROUP(iic2), + SH_PFC_PIN_GROUP(iic2_b), + SH_PFC_PIN_GROUP(iic2_c), + SH_PFC_PIN_GROUP(iic2_d), + SH_PFC_PIN_GROUP(iic2_e), + SH_PFC_PIN_GROUP(iic3), + SH_PFC_PIN_GROUP(intc_irq0), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq2), + SH_PFC_PIN_GROUP(intc_irq3), + SH_PFC_PIN_GROUP(mmc0_data1), + SH_PFC_PIN_GROUP(mmc0_data4), + SH_PFC_PIN_GROUP(mmc0_data8), + SH_PFC_PIN_GROUP(mmc0_ctrl), + SH_PFC_PIN_GROUP(mmc1_data1), + SH_PFC_PIN_GROUP(mmc1_data4), + SH_PFC_PIN_GROUP(mmc1_data8), + SH_PFC_PIN_GROUP(mmc1_ctrl), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_rx), + SH_PFC_PIN_GROUP(msiof0_tx), + SH_PFC_PIN_GROUP(msiof0_clk_b), + SH_PFC_PIN_GROUP(msiof0_ss1_b), + SH_PFC_PIN_GROUP(msiof0_ss2_b), + SH_PFC_PIN_GROUP(msiof0_rx_b), + SH_PFC_PIN_GROUP(msiof0_tx_b), + SH_PFC_PIN_GROUP(msiof1_clk), + SH_PFC_PIN_GROUP(msiof1_sync), + SH_PFC_PIN_GROUP(msiof1_ss1), + SH_PFC_PIN_GROUP(msiof1_ss2), + SH_PFC_PIN_GROUP(msiof1_rx), + SH_PFC_PIN_GROUP(msiof1_tx), + SH_PFC_PIN_GROUP(msiof1_clk_b), + SH_PFC_PIN_GROUP(msiof1_ss1_b), + SH_PFC_PIN_GROUP(msiof1_ss2_b), + SH_PFC_PIN_GROUP(msiof1_rx_b), + SH_PFC_PIN_GROUP(msiof1_tx_b), + SH_PFC_PIN_GROUP(msiof2_clk), + SH_PFC_PIN_GROUP(msiof2_sync), + SH_PFC_PIN_GROUP(msiof2_ss1), + SH_PFC_PIN_GROUP(msiof2_ss2), + SH_PFC_PIN_GROUP(msiof2_rx), + SH_PFC_PIN_GROUP(msiof2_tx), + SH_PFC_PIN_GROUP(msiof3_clk), + SH_PFC_PIN_GROUP(msiof3_sync), + SH_PFC_PIN_GROUP(msiof3_ss1), + SH_PFC_PIN_GROUP(msiof3_ss2), + SH_PFC_PIN_GROUP(msiof3_rx), + SH_PFC_PIN_GROUP(msiof3_tx), + SH_PFC_PIN_GROUP(msiof3_clk_b), + SH_PFC_PIN_GROUP(msiof3_sync_b), + SH_PFC_PIN_GROUP(msiof3_rx_b), + SH_PFC_PIN_GROUP(msiof3_tx_b), + SH_PFC_PIN_GROUP(pwm0), + SH_PFC_PIN_GROUP(pwm0_b), + SH_PFC_PIN_GROUP(pwm1), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm2), + SH_PFC_PIN_GROUP(pwm3), + SH_PFC_PIN_GROUP(pwm4), + SH_PFC_PIN_GROUP(pwm5), + SH_PFC_PIN_GROUP(pwm6), + SH_PFC_PIN_GROUP(qspi_ctrl), + SH_PFC_PIN_GROUP(qspi_data2), + SH_PFC_PIN_GROUP(qspi_data4), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif0_data_b), + SH_PFC_PIN_GROUP(scif1_data), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_data_c), + SH_PFC_PIN_GROUP(scif1_data_d), + SH_PFC_PIN_GROUP(scif1_clk_d), + SH_PFC_PIN_GROUP(scif1_data_e), + SH_PFC_PIN_GROUP(scif1_clk_e), + SH_PFC_PIN_GROUP(scif2_data), + SH_PFC_PIN_GROUP(scif2_clk), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_clk), + SH_PFC_PIN_GROUP(scifa0_ctrl), + SH_PFC_PIN_GROUP(scifa0_data_b), + SH_PFC_PIN_GROUP(scifa0_clk_b), + SH_PFC_PIN_GROUP(scifa0_ctrl_b), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_ctrl), + SH_PFC_PIN_GROUP(scifa1_data_b), + SH_PFC_PIN_GROUP(scifa1_clk_b), + SH_PFC_PIN_GROUP(scifa1_ctrl_b), + SH_PFC_PIN_GROUP(scifa1_data_c), + SH_PFC_PIN_GROUP(scifa1_clk_c), + SH_PFC_PIN_GROUP(scifa1_ctrl_c), + SH_PFC_PIN_GROUP(scifa1_data_d), + SH_PFC_PIN_GROUP(scifa1_clk_d), + SH_PFC_PIN_GROUP(scifa1_ctrl_d), + SH_PFC_PIN_GROUP(scifa2_data), + SH_PFC_PIN_GROUP(scifa2_clk), + SH_PFC_PIN_GROUP(scifa2_ctrl), + SH_PFC_PIN_GROUP(scifa2_data_b), + SH_PFC_PIN_GROUP(scifa2_data_c), + SH_PFC_PIN_GROUP(scifa2_clk_c), + SH_PFC_PIN_GROUP(scifb0_data), + SH_PFC_PIN_GROUP(scifb0_clk), + SH_PFC_PIN_GROUP(scifb0_ctrl), + SH_PFC_PIN_GROUP(scifb0_data_b), + SH_PFC_PIN_GROUP(scifb0_clk_b), + SH_PFC_PIN_GROUP(scifb0_ctrl_b), + SH_PFC_PIN_GROUP(scifb0_data_c), + SH_PFC_PIN_GROUP(scifb1_data), + SH_PFC_PIN_GROUP(scifb1_clk), + SH_PFC_PIN_GROUP(scifb1_ctrl), + SH_PFC_PIN_GROUP(scifb1_data_b), + SH_PFC_PIN_GROUP(scifb1_clk_b), + SH_PFC_PIN_GROUP(scifb1_ctrl_b), + SH_PFC_PIN_GROUP(scifb1_data_c), + SH_PFC_PIN_GROUP(scifb1_data_d), + SH_PFC_PIN_GROUP(scifb1_data_e), + SH_PFC_PIN_GROUP(scifb1_clk_e), + SH_PFC_PIN_GROUP(scifb1_data_f), + SH_PFC_PIN_GROUP(scifb1_data_g), + SH_PFC_PIN_GROUP(scifb1_clk_g), + SH_PFC_PIN_GROUP(scifb2_data), + SH_PFC_PIN_GROUP(scifb2_clk), + SH_PFC_PIN_GROUP(scifb2_ctrl), + SH_PFC_PIN_GROUP(scifb2_data_b), + SH_PFC_PIN_GROUP(scifb2_clk_b), + SH_PFC_PIN_GROUP(scifb2_ctrl_b), + SH_PFC_PIN_GROUP(scifb2_data_c), + SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd), + SH_PFC_PIN_GROUP(sdhi2_wp), + SH_PFC_PIN_GROUP(sdhi3_data1), + SH_PFC_PIN_GROUP(sdhi3_data4), + SH_PFC_PIN_GROUP(sdhi3_ctrl), + SH_PFC_PIN_GROUP(sdhi3_cd), + SH_PFC_PIN_GROUP(sdhi3_wp), + SH_PFC_PIN_GROUP(ssi0_data), + SH_PFC_PIN_GROUP(ssi0129_ctrl), + SH_PFC_PIN_GROUP(ssi1_data), + SH_PFC_PIN_GROUP(ssi1_ctrl), + SH_PFC_PIN_GROUP(ssi2_data), + SH_PFC_PIN_GROUP(ssi2_ctrl), + SH_PFC_PIN_GROUP(ssi3_data), + SH_PFC_PIN_GROUP(ssi34_ctrl), + SH_PFC_PIN_GROUP(ssi4_data), + SH_PFC_PIN_GROUP(ssi4_ctrl), + SH_PFC_PIN_GROUP(ssi5), + SH_PFC_PIN_GROUP(ssi5_b), + SH_PFC_PIN_GROUP(ssi5_c), + SH_PFC_PIN_GROUP(ssi6), + SH_PFC_PIN_GROUP(ssi6_b), + SH_PFC_PIN_GROUP(ssi7_data), + SH_PFC_PIN_GROUP(ssi7_b_data), + SH_PFC_PIN_GROUP(ssi7_c_data), + SH_PFC_PIN_GROUP(ssi78_ctrl), + SH_PFC_PIN_GROUP(ssi78_b_ctrl), + SH_PFC_PIN_GROUP(ssi78_c_ctrl), + SH_PFC_PIN_GROUP(ssi8_data), + SH_PFC_PIN_GROUP(ssi8_b_data), + SH_PFC_PIN_GROUP(ssi8_c_data), + SH_PFC_PIN_GROUP(ssi9_data), + SH_PFC_PIN_GROUP(ssi9_ctrl), + SH_PFC_PIN_GROUP(tpu0_to0), + SH_PFC_PIN_GROUP(tpu0_to1), + SH_PFC_PIN_GROUP(tpu0_to2), + SH_PFC_PIN_GROUP(tpu0_to3), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb0_ovc_vbus), + SH_PFC_PIN_GROUP(usb1), + SH_PFC_PIN_GROUP(usb1_pwen), + SH_PFC_PIN_GROUP(usb2), + VIN_DATA_PIN_GROUP(vin0_data, 24), + VIN_DATA_PIN_GROUP(vin0_data, 20), + SH_PFC_PIN_GROUP(vin0_data18), + VIN_DATA_PIN_GROUP(vin0_data, 16), + VIN_DATA_PIN_GROUP(vin0_data, 12), + VIN_DATA_PIN_GROUP(vin0_data, 10), + VIN_DATA_PIN_GROUP(vin0_data, 8), + VIN_DATA_PIN_GROUP(vin0_data, 4), + SH_PFC_PIN_GROUP(vin0_sync), + SH_PFC_PIN_GROUP(vin0_field), + SH_PFC_PIN_GROUP(vin0_clkenb), + SH_PFC_PIN_GROUP(vin0_clk), + VIN_DATA_PIN_GROUP(vin1_data, 24), + VIN_DATA_PIN_GROUP(vin1_data, 20), + SH_PFC_PIN_GROUP(vin1_data18), + VIN_DATA_PIN_GROUP(vin1_data, 16), + VIN_DATA_PIN_GROUP(vin1_data, 12), + VIN_DATA_PIN_GROUP(vin1_data, 10), + VIN_DATA_PIN_GROUP(vin1_data, 8), + VIN_DATA_PIN_GROUP(vin1_data, 4), + VIN_DATA_PIN_GROUP(vin1_data, 24, _b), + VIN_DATA_PIN_GROUP(vin1_data, 20, _b), + SH_PFC_PIN_GROUP(vin1_data18_b), + VIN_DATA_PIN_GROUP(vin1_data, 16, _b), + VIN_DATA_PIN_GROUP(vin1_data, 12, _b), + VIN_DATA_PIN_GROUP(vin1_data, 10, _b), + VIN_DATA_PIN_GROUP(vin1_data, 8, _b), + VIN_DATA_PIN_GROUP(vin1_data, 4, _b), + SH_PFC_PIN_GROUP(vin1_sync), + SH_PFC_PIN_GROUP(vin1_sync_b), + SH_PFC_PIN_GROUP(vin1_field), + SH_PFC_PIN_GROUP(vin1_field_b), + SH_PFC_PIN_GROUP(vin1_clkenb), + SH_PFC_PIN_GROUP(vin1_clkenb_b), + SH_PFC_PIN_GROUP(vin1_clk), + SH_PFC_PIN_GROUP(vin1_clk_b), + VIN_DATA_PIN_GROUP(vin2_data, 24), + SH_PFC_PIN_GROUP(vin2_data18), + VIN_DATA_PIN_GROUP(vin2_data, 16), + VIN_DATA_PIN_GROUP(vin2_data, 8), + VIN_DATA_PIN_GROUP(vin2_data, 4), + SH_PFC_PIN_GROUP(vin2_g8), + SH_PFC_PIN_GROUP(vin2_sync), + SH_PFC_PIN_GROUP(vin2_field), + SH_PFC_PIN_GROUP(vin2_clkenb), + SH_PFC_PIN_GROUP(vin2_clk), + SH_PFC_PIN_GROUP(vin3_data8), + SH_PFC_PIN_GROUP(vin3_sync), + SH_PFC_PIN_GROUP(vin3_field), + SH_PFC_PIN_GROUP(vin3_clkenb), + SH_PFC_PIN_GROUP(vin3_clk), + }, +#ifdef CONFIG_PINCTRL_PFC_R8A7790 + .automotive = { + SH_PFC_PIN_GROUP(mlb_3pin), + } +#endif /* CONFIG_PINCTRL_PFC_R8A7790 */ };
static const char * const audio_clk_groups[] = { @@ -4246,6 +4478,23 @@ static const char * const avb_groups[] = { "avb_gmii", };
+static const char * const can0_groups[] = { + "can0_data", + "can0_data_b", + "can0_data_c", + "can0_data_d", +}; + +static const char * const can1_groups[] = { + "can1_data", + "can1_data_b", +}; + +static const char * const can_clk_groups[] = { + "can_clk", + "can_clk_b", +}; + static const char * const du_groups[] = { "du_rgb666", "du_rgb888", @@ -4351,9 +4600,11 @@ static const char * const intc_groups[] = { "intc_irq3", };
+#ifdef CONFIG_PINCTRL_PFC_R8A7790 static const char * const mlb_groups[] = { "mlb_3pin", }; +#endif /* CONFIG_PINCTRL_PFC_R8A7790 */
static const char * const mmc0_groups[] = { "mmc0_data1", @@ -4629,6 +4880,7 @@ static const char * const usb0_groups[] = {
static const char * const usb1_groups[] = { "usb1", + "usb1_pwen", };
static const char * const usb2_groups[] = { @@ -4659,10 +4911,22 @@ static const char * const vin1_groups[] = { "vin1_data10", "vin1_data8", "vin1_data4", + "vin1_data24_b", + "vin1_data20_b", + "vin1_data18_b", + "vin1_data16_b", + "vin1_data12_b", + "vin1_data10_b", + "vin1_data8_b", + "vin1_data4_b", "vin1_sync", + "vin1_sync_b", "vin1_field", + "vin1_field_b", "vin1_clkenb", + "vin1_clkenb_b", "vin1_clk", + "vin1_clk_b", };
static const char * const vin2_groups[] = { @@ -4671,6 +4935,7 @@ static const char * const vin2_groups[] = { "vin2_data16", "vin2_data8", "vin2_data4", + "vin2_g8", "vin2_sync", "vin2_field", "vin2_clkenb", @@ -4685,63 +4950,77 @@ static const char * const vin3_groups[] = { "vin3_clk", };
-static const struct sh_pfc_function pinmux_functions[] = { - SH_PFC_FUNCTION(audio_clk), - SH_PFC_FUNCTION(avb), - SH_PFC_FUNCTION(du), - SH_PFC_FUNCTION(du0), - SH_PFC_FUNCTION(du1), - SH_PFC_FUNCTION(du2), - SH_PFC_FUNCTION(eth), - SH_PFC_FUNCTION(hscif0), - SH_PFC_FUNCTION(hscif1), - SH_PFC_FUNCTION(i2c0), - SH_PFC_FUNCTION(i2c1), - SH_PFC_FUNCTION(i2c2), - SH_PFC_FUNCTION(i2c3), - SH_PFC_FUNCTION(iic0), - SH_PFC_FUNCTION(iic1), - SH_PFC_FUNCTION(iic2), - SH_PFC_FUNCTION(iic3), - SH_PFC_FUNCTION(intc), - SH_PFC_FUNCTION(mlb), - SH_PFC_FUNCTION(mmc0), - SH_PFC_FUNCTION(mmc1), - SH_PFC_FUNCTION(msiof0), - SH_PFC_FUNCTION(msiof1), - SH_PFC_FUNCTION(msiof2), - SH_PFC_FUNCTION(msiof3), - SH_PFC_FUNCTION(pwm0), - SH_PFC_FUNCTION(pwm1), - SH_PFC_FUNCTION(pwm2), - SH_PFC_FUNCTION(pwm3), - SH_PFC_FUNCTION(pwm4), - SH_PFC_FUNCTION(pwm5), - SH_PFC_FUNCTION(pwm6), - SH_PFC_FUNCTION(qspi), - SH_PFC_FUNCTION(scif0), - SH_PFC_FUNCTION(scif1), - SH_PFC_FUNCTION(scif2), - SH_PFC_FUNCTION(scifa0), - SH_PFC_FUNCTION(scifa1), - SH_PFC_FUNCTION(scifa2), - SH_PFC_FUNCTION(scifb0), - SH_PFC_FUNCTION(scifb1), - SH_PFC_FUNCTION(scifb2), - SH_PFC_FUNCTION(scif_clk), - SH_PFC_FUNCTION(sdhi0), - SH_PFC_FUNCTION(sdhi1), - SH_PFC_FUNCTION(sdhi2), - SH_PFC_FUNCTION(sdhi3), - SH_PFC_FUNCTION(ssi), - SH_PFC_FUNCTION(tpu0), - SH_PFC_FUNCTION(usb0), - SH_PFC_FUNCTION(usb1), - SH_PFC_FUNCTION(usb2), - SH_PFC_FUNCTION(vin0), - SH_PFC_FUNCTION(vin1), - SH_PFC_FUNCTION(vin2), - SH_PFC_FUNCTION(vin3), +static const struct { + struct sh_pfc_function common[58]; +#ifdef CONFIG_PINCTRL_PFC_R8A7790 + struct sh_pfc_function automotive[1]; +#endif +} pinmux_functions = { + .common = { + SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(can0), + SH_PFC_FUNCTION(can1), + SH_PFC_FUNCTION(can_clk), + SH_PFC_FUNCTION(du0), + SH_PFC_FUNCTION(du1), + SH_PFC_FUNCTION(du2), + SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(iic0), + SH_PFC_FUNCTION(iic1), + SH_PFC_FUNCTION(iic2), + SH_PFC_FUNCTION(iic3), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(mmc1), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(pwm5), + SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(qspi), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifa2), + SH_PFC_FUNCTION(scifb0), + SH_PFC_FUNCTION(scifb1), + SH_PFC_FUNCTION(scifb2), + SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(sdhi3), + SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(tpu0), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(usb2), + SH_PFC_FUNCTION(vin0), + SH_PFC_FUNCTION(vin1), + SH_PFC_FUNCTION(vin2), + SH_PFC_FUNCTION(vin3), + }, +#ifdef CONFIG_PINCTRL_PFC_R8A7790 + .automotive = { + SH_PFC_FUNCTION(mlb), + } +#endif /* CONFIG_PINCTRL_PFC_R8A7790 */ };
static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -5728,6 +6007,7 @@ static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = { .pin_to_pocctrl = r8a7790_pin_to_pocctrl, };
+#ifdef CONFIG_PINCTRL_PFC_R8A7790 const struct sh_pfc_soc_info r8a7790_pinmux_info = { .name = "r8a77900_pfc", .ops = &r8a7790_pinmux_ops, @@ -5737,13 +6017,16 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = {
.pins = pinmux_pins, .nr_pins = ARRAY_SIZE(pinmux_pins), - .groups = pinmux_groups, - .nr_groups = ARRAY_SIZE(pinmux_groups), - .functions = pinmux_functions, - .nr_functions = ARRAY_SIZE(pinmux_functions), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common) + + ARRAY_SIZE(pinmux_groups.automotive), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common) + + ARRAY_SIZE(pinmux_functions.automotive),
.cfg_regs = pinmux_config_regs,
.pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; +#endif diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c index d6095d6f67..7c8db5dc2c 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7791.c +++ b/drivers/pinctrl/renesas/pfc-r8a7791.c @@ -18,7 +18,7 @@ * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in * which case they support both 3.3V and 1.8V signalling. */ -#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ PORT_GP_26(1, fn, sfx), \ PORT_GP_32(2, fn, sfx), \ @@ -1703,6 +1703,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), };
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) /* - ADI -------------------------------------------------------------------- */ static const unsigned int adi_common_pins[] = { /* ADIDATA, ADICS/SAMP, ADICLK */ @@ -1768,6 +1769,7 @@ static const unsigned int adi_chsel2_b_mux[] = { /* ADICHS B 2 */ ADICHS2_B_MARK, }; +#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
/* - Audio Clock ------------------------------------------------------------ */ static const unsigned int audio_clk_a_pins[] = { @@ -2556,6 +2558,8 @@ static const unsigned int intc_irq3_pins[] = { static const unsigned int intc_irq3_mux[] = { IRQ3_MARK, }; + +#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) /* - MLB+ ------------------------------------------------------------------- */ static const unsigned int mlb_3pin_pins[] = { RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), @@ -2563,6 +2567,8 @@ static const unsigned int mlb_3pin_pins[] = { static const unsigned int mlb_3pin_mux[] = { MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, }; +#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ + /* - MMCIF ------------------------------------------------------------------ */ static const unsigned int mmc_data1_pins[] = { /* D[0] */ @@ -4455,7 +4461,9 @@ static const unsigned int vin2_clk_mux[] = {
static const struct { struct sh_pfc_pin_group common[346]; +#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) struct sh_pfc_pin_group automotive[9]; +#endif } pinmux_groups = { .common = { SH_PFC_PIN_GROUP(audio_clk_a), @@ -4805,6 +4813,7 @@ static const struct { SH_PFC_PIN_GROUP(vin2_clkenb), SH_PFC_PIN_GROUP(vin2_clk), }, +#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) .automotive = { SH_PFC_PIN_GROUP(adi_common), SH_PFC_PIN_GROUP(adi_chsel0), @@ -4816,8 +4825,10 @@ static const struct { SH_PFC_PIN_GROUP(adi_chsel2_b), SH_PFC_PIN_GROUP(mlb_3pin), } +#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ };
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) static const char * const adi_groups[] = { "adi_common", "adi_chsel0", @@ -4828,6 +4839,7 @@ static const char * const adi_groups[] = { "adi_chsel1_b", "adi_chsel2_b", }; +#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
static const char * const audio_clk_groups[] = { "audio_clk_a", @@ -5005,9 +5017,11 @@ static const char * const intc_groups[] = { "intc_irq3", };
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) static const char * const mlb_groups[] = { "mlb_3pin", }; +#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
static const char * const mmc_groups[] = { "mmc_data1", @@ -5362,7 +5376,9 @@ static const char * const vin2_groups[] = {
static const struct { struct sh_pfc_function common[58]; +#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) struct sh_pfc_function automotive[2]; +#endif } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk), @@ -5424,10 +5440,12 @@ static const struct { SH_PFC_FUNCTION(vin1), SH_PFC_FUNCTION(vin2), }, +#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) .automotive = { SH_PFC_FUNCTION(adi), SH_PFC_FUNCTION(mlb), } +#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ };
static const struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c b/drivers/pinctrl/renesas/pfc-r8a7792.c index 1c90412093..054c02a4ae 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7792.c +++ b/drivers/pinctrl/renesas/pfc-r8a7792.c @@ -14,7 +14,7 @@
#include "sh_pfc.h"
-#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_29(0, fn, sfx), \ PORT_GP_23(1, fn, sfx), \ PORT_GP_32(2, fn, sfx), \ diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c index 91ac815f3d..9495603f7c 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7794.c +++ b/drivers/pinctrl/renesas/pfc-r8a7794.c @@ -15,7 +15,7 @@
#include "sh_pfc.h"
-#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ PORT_GP_26(1, fn, sfx), \ PORT_GP_32(2, fn, sfx), \ diff --git a/drivers/pinctrl/renesas/pfc-r8a7795.c b/drivers/pinctrl/renesas/pfc-r8a7795.c index 898f837950..015a50f1de 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7795.c +++ b/drivers/pinctrl/renesas/pfc-r8a7795.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * R8A7795 ES2.0+ processor support - PFC hardware block. + * R8A77951 processor support - PFC hardware block. * * Copyright (C) 2015-2019 Renesas Electronics Corporation */ @@ -13,11 +13,9 @@
#include "sh_pfc.h"
-#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \ - SH_PFC_PIN_CFG_PULL_UP | \ - SH_PFC_PIN_CFG_PULL_DOWN) +#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
-#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ @@ -30,6 +28,52 @@ PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ + PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ + PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) + /* * F_() : just information * FM() : macro for FN_xxx / xxx_MARK @@ -1509,68 +1553,16 @@ static const u16 pinmux_data[] = { };
/* - * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs. - * Physical layout rows: A - AW, cols: 1 - 39. + * Pins not associated with a GPIO port. */ -#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) -#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) -#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) -#define PIN_NONE U16_MAX +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +};
static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), - - /* - * Pins not associated with a GPIO port. - * - * The pin positions are different between different r8a7795 - * packages, all that is needed for the pfc driver is a unique - * number for each pin. To this end use the pin layout from - * R-Car H3SiP to calculate a unique number for each pin. - */ - SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), + PINMUX_NOGP_ALL(), };
/* - AUDIO CLOCK ------------------------------------------------------------ */ @@ -1718,7 +1710,7 @@ static const unsigned int avb_phy_int_mux[] = { }; static const unsigned int avb_mdio_pins[] = { /* AVB_MDC, AVB_MDIO */ - RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9), + RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, }; static const unsigned int avb_mdio_mux[] = { AVB_MDC_MARK, AVB_MDIO_MARK, @@ -1731,12 +1723,11 @@ static const unsigned int avb_mii_pins[] = { * AVB_RD1, AVB_RD2, AVB_RD3, * AVB_TXCREFCLK */ - PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18), - PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17), - PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13), - PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14), - PIN_NUMBER('A', 12), - + PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, + PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, + PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, + PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, + PIN_AVB_TXCREFCLK, }; static const unsigned int avb_mii_mux[] = { AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, @@ -3261,6 +3252,57 @@ static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, };
+/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* QSPI0_SPCLK, QSPI0_SSL */ + PIN_QSPI0_SPCLK, PIN_QSPI0_SSL, +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data2_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ + PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, +}; +static const unsigned int qspi0_data2_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, +}; +static const unsigned int qspi0_data4_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ + PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, + /* QSPI0_IO2, QSPI0_IO3 */ + PIN_QSPI0_IO2, PIN_QSPI0_IO3, +}; +static const unsigned int qspi0_data4_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK, +}; +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* QSPI1_SPCLK, QSPI1_SSL */ + PIN_QSPI1_SPCLK, PIN_QSPI1_SSL, +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data2_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, +}; +static const unsigned int qspi1_data2_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +}; +static const unsigned int qspi1_data4_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, + /* QSPI1_IO2, QSPI1_IO3 */ + PIN_QSPI1_IO2, PIN_QSPI1_IO3, +}; +static const unsigned int qspi1_data4_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK, +}; + /* - SATA --------------------------------------------------------------------*/ static const unsigned int sata0_devslp_a_pins[] = { /* DEVSLP */ @@ -4169,7 +4211,7 @@ static const unsigned int vin5_clk_mux[] = { };
static const struct { - struct sh_pfc_pin_group common[320]; + struct sh_pfc_pin_group common[326]; #ifdef CONFIG_PINCTRL_PFC_R8A7795 struct sh_pfc_pin_group automotive[30]; #endif @@ -4374,6 +4416,12 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), + SH_PFC_PIN_GROUP(qspi0_ctrl), + SH_PFC_PIN_GROUP(qspi0_data2), + SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + SH_PFC_PIN_GROUP(qspi1_data2), + SH_PFC_PIN_GROUP(qspi1_data4), SH_PFC_PIN_GROUP(sata0_devslp_a), SH_PFC_PIN_GROUP(sata0_devslp_b), SH_PFC_PIN_GROUP(scif0_data), @@ -4868,6 +4916,18 @@ static const char * const pwm6_groups[] = { "pwm6_b", };
+static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + static const char * const sata0_groups[] = { "sata0_devslp_a", "sata0_devslp_b", @@ -5056,7 +5116,7 @@ static const char * const vin5_groups[] = { };
static const struct { - struct sh_pfc_function common[53]; + struct sh_pfc_function common[55]; #ifdef CONFIG_PINCTRL_PFC_R8A7795 struct sh_pfc_function automotive[4]; #endif @@ -5093,6 +5153,8 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(sata0), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), @@ -5692,44 +5754,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
static const struct pinmux_drive_reg pinmux_drive_regs[] = { { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { - { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */ - { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */ - { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */ - { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */ - { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */ - { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */ - { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */ - { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */ + { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ + { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ + { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ + { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ + { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ + { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ + { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ + { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { - { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */ - { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */ - { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */ - { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */ - { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */ - { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */ - { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */ - { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */ + { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ + { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ + { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ + { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ + { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ + { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ + { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ + { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ } }, { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { - { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */ - { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */ - { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */ - { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */ - { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */ - { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */ - { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */ - { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */ + { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ + { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ + { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ + { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ + { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ + { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ + { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ + { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { - { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */ - { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */ - { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */ - { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */ - { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */ - { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ - { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ - { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ + { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ + { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ + { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ + { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ + { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ + { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ + { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ + { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ } }, { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ @@ -5783,7 +5845,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { } }, { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ - { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */ + { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ @@ -5802,30 +5864,32 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ } }, { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { - { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ - { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ - { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ - { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ - { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ - { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ - { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ + { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ + { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ + { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ + { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ + { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ + { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ + { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ } }, { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { - { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */ - { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */ - { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */ - { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */ +#ifdef CONFIG_PINCTRL_PFC_R8A7795 + { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */ +#endif + { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ + { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */ + { PIN_TMS, 4, 2 }, /* TMS */ } }, { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { - { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */ - { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */ - { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ - { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ - { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ - { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ - { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ - { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ + { PIN_TDO, 28, 2 }, /* TDO */ + { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ + { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ + { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ + { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ + { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ + { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ + { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ } }, { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ @@ -5894,7 +5958,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ - { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */ + { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ } }, { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { @@ -5933,8 +5997,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ - { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */ - { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */ + { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */ + { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */ } }, { }, }; @@ -5950,7 +6014,8 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, };
-static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +static int r8a77951_pin_to_pocctrl(struct sh_pfc *pfc, + unsigned int pin, u32 *pocctrl) { int bit = -EINVAL;
@@ -5967,35 +6032,35 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
static const struct pinmux_bias_reg pinmux_bias_regs[] = { { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { - [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */ - [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */ - [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */ - [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */ - [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */ - [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */ - [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */ - [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */ - [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */ - [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */ - [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */ - [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */ - [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */ - [13] = PIN_NUMBER('V', 6), /* RPC_WP# */ - [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */ - [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */ - [16] = PIN_NUMBER('B', 19), /* AVB_RXC */ - [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */ - [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */ - [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */ - [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */ - [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */ - [22] = PIN_NUMBER('A', 19), /* AVB_TXC */ - [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */ - [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */ - [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */ - [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */ - [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */ - [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */ + [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ + [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ + [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ + [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ + [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ + [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ + [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ + [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ + [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ + [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ + [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ + [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ + [12] = PIN_RPC_INT_N, /* RPC_INT# */ + [13] = PIN_RPC_WP_N, /* RPC_WP# */ + [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ + [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ + [16] = PIN_AVB_RXC, /* AVB_RXC */ + [17] = PIN_AVB_RD0, /* AVB_RD0 */ + [18] = PIN_AVB_RD1, /* AVB_RD1 */ + [19] = PIN_AVB_RD2, /* AVB_RD2 */ + [20] = PIN_AVB_RD3, /* AVB_RD3 */ + [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ + [22] = PIN_AVB_TXC, /* AVB_TXC */ + [23] = PIN_AVB_TD0, /* AVB_TD0 */ + [24] = PIN_AVB_TD1, /* AVB_TD1 */ + [25] = PIN_AVB_TD2, /* AVB_TD2 */ + [26] = PIN_AVB_TD3, /* AVB_TD3 */ + [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ + [28] = PIN_AVB_MDIO, /* AVB_MDIO */ [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ @@ -6044,7 +6109,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ - [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */ + [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ [10] = RCAR_GP_PIN(0, 0), /* D0 */ [11] = RCAR_GP_PIN(0, 1), /* D1 */ [12] = RCAR_GP_PIN(0, 2), /* D2 */ @@ -6065,20 +6130,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ - [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ - [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ + [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ + [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ } }, { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { - [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */ - [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */ - [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */ - [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/ - [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */ - [ 5] = PIN_A_NUMBER('T', 27), /* TCK */ - [ 6] = PIN_A_NUMBER('R', 30), /* TMS */ - [ 7] = PIN_A_NUMBER('R', 29), /* TDI */ - [ 8] = PIN_NONE, - [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */ + [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */ + [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ + [ 2] = PIN_FSCLKST_N, /* FSCLKST# */ + [ 3] = PIN_EXTALR, /* EXTALR*/ + [ 4] = PIN_TRST_N, /* TRST# */ + [ 5] = PIN_TCK, /* TCK */ + [ 6] = PIN_TMS, /* TMS */ + [ 7] = PIN_TDI, /* TDI */ + [ 8] = SH_PFC_PIN_NONE, + [ 9] = PIN_ASEBRK, /* ASEBRK */ [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ @@ -6143,7 +6208,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ - [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */ + [ 6] = PIN_MLB_REF, /* MLB_REF */ [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ @@ -6178,31 +6243,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */ [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */ - [ 7] = PIN_NONE, - [ 8] = PIN_NONE, - [ 9] = PIN_NONE, - [10] = PIN_NONE, - [11] = PIN_NONE, - [12] = PIN_NONE, - [13] = PIN_NONE, - [14] = PIN_NONE, - [15] = PIN_NONE, - [16] = PIN_NONE, - [17] = PIN_NONE, - [18] = PIN_NONE, - [19] = PIN_NONE, - [20] = PIN_NONE, - [21] = PIN_NONE, - [22] = PIN_NONE, - [23] = PIN_NONE, - [24] = PIN_NONE, - [25] = PIN_NONE, - [26] = PIN_NONE, - [27] = PIN_NONE, - [28] = PIN_NONE, - [29] = PIN_NONE, - [30] = PIN_NONE, - [31] = PIN_NONE, + [ 7] = SH_PFC_PIN_NONE, + [ 8] = SH_PFC_PIN_NONE, + [ 9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, } }, { /* sentinel */ }, }; @@ -6248,8 +6313,8 @@ static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, sh_pfc_write(pfc, reg->puen, enable); }
-static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = { - .pin_to_pocctrl = r8a7795_pin_to_pocctrl, +static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = { + .pin_to_pocctrl = r8a77951_pin_to_pocctrl, .get_bias = r8a7795_pinmux_get_bias, .set_bias = r8a7795_pinmux_set_bias, }; @@ -6257,7 +6322,7 @@ static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = { #ifdef CONFIG_PINCTRL_PFC_R8A774E1 const struct sh_pfc_soc_info r8a774e1_pinmux_info = { .name = "r8a774e1_pfc", - .ops = &r8a7795_pinmux_ops, + .ops = &r8a77951_pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -6282,7 +6347,7 @@ const struct sh_pfc_soc_info r8a774e1_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A7795 const struct sh_pfc_soc_info r8a7795_pinmux_info = { .name = "r8a77951_pfc", - .ops = &r8a7795_pinmux_ops, + .ops = &r8a77951_pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index da7901ea6e..06cae74fb5 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -1,10 +1,10 @@ // SPDX-License-Identifier: GPL-2.0 /* - * R8A7796 processor support - PFC hardware block. + * R8A7796 (R-Car M3-W/W+) support - PFC hardware block. * * Copyright (C) 2016-2019 Renesas Electronics Corp. * - * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c + * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c * * R-Car Gen3 processor support - PFC hardware block. * @@ -19,11 +19,9 @@
#include "sh_pfc.h"
-#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \ - SH_PFC_PIN_CFG_PULL_UP | \ - SH_PFC_PIN_CFG_PULL_DOWN) +#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
-#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ @@ -36,6 +34,51 @@ PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ + PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ + PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) + /* * F_() : just information * FM() : macro for FN_xxx / xxx_MARK @@ -688,7 +731,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), - PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1), + PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), @@ -1514,67 +1557,16 @@ static const u16 pinmux_data[] = { };
/* - * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs. - * Physical layout rows: A - AW, cols: 1 - 39. + * Pins not associated with a GPIO port. */ -#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) -#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) -#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) -#define PIN_NONE U16_MAX +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +};
static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), - - /* - * Pins not associated with a GPIO port. - * - * The pin positions are different between different r8a7796 - * packages, all that is needed for the pfc driver is a unique - * number for each pin. To this end use the pin layout from - * R-Car M3SiP to calculate a unique number for each pin. - */ - SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), + PINMUX_NOGP_ALL(), };
/* - AUDIO CLOCK ------------------------------------------------------------ */ @@ -1723,7 +1715,7 @@ static const unsigned int avb_phy_int_mux[] = { }; static const unsigned int avb_mdio_pins[] = { /* AVB_MDC, AVB_MDIO */ - RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9), + RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, }; static const unsigned int avb_mdio_mux[] = { AVB_MDC_MARK, AVB_MDIO_MARK, @@ -1736,12 +1728,11 @@ static const unsigned int avb_mii_pins[] = { * AVB_RD1, AVB_RD2, AVB_RD3, * AVB_TXCREFCLK */ - PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18), - PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17), - PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13), - PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14), - PIN_NUMBER('A', 12), - + PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, + PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, + PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, + PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, + PIN_AVB_TXCREFCLK, }; static const unsigned int avb_mii_mux[] = { AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, @@ -3267,6 +3258,57 @@ static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, };
+/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* QSPI0_SPCLK, QSPI0_SSL */ + PIN_QSPI0_SPCLK, PIN_QSPI0_SSL, +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data2_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ + PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, +}; +static const unsigned int qspi0_data2_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, +}; +static const unsigned int qspi0_data4_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ + PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, + /* QSPI0_IO2, QSPI0_IO3 */ + PIN_QSPI0_IO2, PIN_QSPI0_IO3, +}; +static const unsigned int qspi0_data4_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK, +}; +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* QSPI1_SPCLK, QSPI1_SSL */ + PIN_QSPI1_SPCLK, PIN_QSPI1_SSL, +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data2_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, +}; +static const unsigned int qspi1_data2_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +}; +static const unsigned int qspi1_data4_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, + /* QSPI1_IO2, QSPI1_IO3 */ + PIN_QSPI1_IO2, PIN_QSPI1_IO3, +}; +static const unsigned int qspi1_data4_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK, +}; + /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -3895,6 +3937,36 @@ static const unsigned int tmu_tclk2_b_mux[] = { TCLK2_B_MARK, };
+/* - TPU ------------------------------------------------------------------- */ +static const unsigned int tpu_to0_pins[] = { + /* TPU0TO0 */ + RCAR_GP_PIN(6, 28), +}; +static const unsigned int tpu_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu_to1_pins[] = { + /* TPU0TO1 */ + RCAR_GP_PIN(6, 29), +}; +static const unsigned int tpu_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu_to2_pins[] = { + /* TPU0TO2 */ + RCAR_GP_PIN(6, 30), +}; +static const unsigned int tpu_to2_mux[] = { + TPU0TO2_MARK, +}; +static const unsigned int tpu_to3_pins[] = { + /* TPU0TO3 */ + RCAR_GP_PIN(6, 31), +}; +static const unsigned int tpu_to3_mux[] = { + TPU0TO3_MARK, +}; + /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { /* PWEN, OVC */ @@ -4114,7 +4186,7 @@ static const unsigned int vin5_clk_mux[] = { };
static const struct { - struct sh_pfc_pin_group common[312]; + struct sh_pfc_pin_group common[322]; #if defined(CONFIG_PINCTRL_PFC_R8A7796) struct sh_pfc_pin_group automotive[30]; #endif @@ -4319,6 +4391,12 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), + SH_PFC_PIN_GROUP(qspi0_ctrl), + SH_PFC_PIN_GROUP(qspi0_data2), + SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + SH_PFC_PIN_GROUP(qspi1_data2), + SH_PFC_PIN_GROUP(qspi1_data4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -4403,6 +4481,10 @@ static const struct { SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), SH_PFC_PIN_GROUP(tmu_tclk2_b), + SH_PFC_PIN_GROUP(tpu_to0), + SH_PFC_PIN_GROUP(tpu_to1), + SH_PFC_PIN_GROUP(tpu_to2), + SH_PFC_PIN_GROUP(tpu_to3), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb30), @@ -4805,6 +4887,18 @@ static const char * const pwm6_groups[] = { "pwm6_b", };
+static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + static const char * const scif0_groups[] = { "scif0_data", "scif0_clk", @@ -4928,6 +5022,13 @@ static const char * const tmu_groups[] = { "tmu_tclk2_b", };
+static const char * const tpu_groups[] = { + "tpu_to0", + "tpu_to1", + "tpu_to2", + "tpu_to3", +}; + static const char * const usb0_groups[] = { "usb0", }; @@ -4973,7 +5074,7 @@ static const char * const vin5_groups[] = { };
static const struct { - struct sh_pfc_function common[49]; + struct sh_pfc_function common[52]; #if defined(CONFIG_PINCTRL_PFC_R8A7796) struct sh_pfc_function automotive[4]; #endif @@ -5010,6 +5111,8 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), @@ -5023,6 +5126,7 @@ static const struct { SH_PFC_FUNCTION(sdhi3), SH_PFC_FUNCTION(ssi), SH_PFC_FUNCTION(tmu), + SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb30), @@ -5604,44 +5708,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
static const struct pinmux_drive_reg pinmux_drive_regs[] = { { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { - { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */ - { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */ - { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */ - { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */ - { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */ - { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */ - { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */ - { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */ + { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ + { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ + { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ + { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ + { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ + { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ + { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ + { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { - { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */ - { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */ - { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */ - { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */ - { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */ - { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */ - { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */ - { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */ + { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ + { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ + { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ + { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ + { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ + { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ + { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ + { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ } }, { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { - { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */ - { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */ - { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */ - { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */ - { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */ - { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */ - { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */ - { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */ + { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ + { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ + { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ + { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ + { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ + { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ + { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ + { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { - { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */ - { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */ - { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */ - { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */ - { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */ - { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ - { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ - { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ + { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ + { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ + { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ + { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ + { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ + { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ + { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ + { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ } }, { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ @@ -5695,7 +5799,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { } }, { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ - { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */ + { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ @@ -5714,29 +5818,29 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ } }, { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { - { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ - { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ - { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ - { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ - { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ - { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ - { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ + { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ + { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ + { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ + { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ + { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ + { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ + { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ } }, { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { - { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN2 */ - { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */ - { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */ + { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */ + { PIN_FSCLKST, 20, 2 }, /* FSCLKST */ + { PIN_TMS, 4, 2 }, /* TMS */ } }, { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { - { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */ - { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */ - { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ - { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ - { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ - { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ - { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ - { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ + { PIN_TDO, 28, 2 }, /* TDO */ + { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ + { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ + { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ + { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ + { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ + { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ + { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ } }, { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ @@ -5805,7 +5909,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ - { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */ + { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ } }, { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { @@ -5878,35 +5982,35 @@ static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
static const struct pinmux_bias_reg pinmux_bias_regs[] = { { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { - [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */ - [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */ - [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */ - [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */ - [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */ - [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */ - [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */ - [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */ - [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */ - [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */ - [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */ - [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */ - [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */ - [13] = PIN_NUMBER('V', 6), /* RPC_WP# */ - [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */ - [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */ - [16] = PIN_NUMBER('B', 19), /* AVB_RXC */ - [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */ - [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */ - [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */ - [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */ - [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */ - [22] = PIN_NUMBER('A', 19), /* AVB_TXC */ - [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */ - [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */ - [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */ - [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */ - [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */ - [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */ + [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ + [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ + [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ + [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ + [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ + [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ + [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ + [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ + [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ + [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ + [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ + [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ + [12] = PIN_RPC_INT_N, /* RPC_INT# */ + [13] = PIN_RPC_WP_N, /* RPC_WP# */ + [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ + [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ + [16] = PIN_AVB_RXC, /* AVB_RXC */ + [17] = PIN_AVB_RD0, /* AVB_RD0 */ + [18] = PIN_AVB_RD1, /* AVB_RD1 */ + [19] = PIN_AVB_RD2, /* AVB_RD2 */ + [20] = PIN_AVB_RD3, /* AVB_RD3 */ + [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ + [22] = PIN_AVB_TXC, /* AVB_TXC */ + [23] = PIN_AVB_TD0, /* AVB_TD0 */ + [24] = PIN_AVB_TD1, /* AVB_TD1 */ + [25] = PIN_AVB_TD2, /* AVB_TD2 */ + [26] = PIN_AVB_TD3, /* AVB_TD3 */ + [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ + [28] = PIN_AVB_MDIO, /* AVB_MDIO */ [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ @@ -5955,7 +6059,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ - [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */ + [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ [10] = RCAR_GP_PIN(0, 0), /* D0 */ [11] = RCAR_GP_PIN(0, 1), /* D1 */ [12] = RCAR_GP_PIN(0, 2), /* D2 */ @@ -5976,20 +6080,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ - [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ - [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ + [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ + [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ } }, { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { - [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */ - [ 1] = PIN_NONE, - [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */ - [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/ - [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */ - [ 5] = PIN_A_NUMBER('T', 27), /* TCK */ - [ 6] = PIN_A_NUMBER('R', 30), /* TMS */ - [ 7] = PIN_A_NUMBER('R', 29), /* TDI */ - [ 8] = PIN_NONE, - [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */ + [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */ + [ 1] = SH_PFC_PIN_NONE, + [ 2] = PIN_FSCLKST, /* FSCLKST */ + [ 3] = PIN_EXTALR, /* EXTALR*/ + [ 4] = PIN_TRST_N, /* TRST# */ + [ 5] = PIN_TCK, /* TCK */ + [ 6] = PIN_TMS, /* TMS */ + [ 7] = PIN_TDI, /* TDI */ + [ 8] = SH_PFC_PIN_NONE, + [ 9] = PIN_ASEBRK, /* ASEBRK */ [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ @@ -6054,7 +6158,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ - [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */ + [ 6] = PIN_MLB_REF, /* MLB_REF */ [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ @@ -6089,31 +6193,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */ [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */ - [ 7] = PIN_NONE, - [ 8] = PIN_NONE, - [ 9] = PIN_NONE, - [10] = PIN_NONE, - [11] = PIN_NONE, - [12] = PIN_NONE, - [13] = PIN_NONE, - [14] = PIN_NONE, - [15] = PIN_NONE, - [16] = PIN_NONE, - [17] = PIN_NONE, - [18] = PIN_NONE, - [19] = PIN_NONE, - [20] = PIN_NONE, - [21] = PIN_NONE, - [22] = PIN_NONE, - [23] = PIN_NONE, - [24] = PIN_NONE, - [25] = PIN_NONE, - [26] = PIN_NONE, - [27] = PIN_NONE, - [28] = PIN_NONE, - [29] = PIN_NONE, - [30] = PIN_NONE, - [31] = PIN_NONE, + [ 7] = SH_PFC_PIN_NONE, + [ 8] = SH_PFC_PIN_NONE, + [ 9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, } }, { /* sentinel */ }, }; diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c index d143750c2d..fae29d535c 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -5,7 +5,7 @@ * Copyright (C) 2018 Jacopo Mondi jacopo+renesas@jmondi.org * Copyright (C) 2016-2019 Renesas Electronics Corp. * - * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c + * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c * * R-Car Gen3 processor support - PFC hardware block. * @@ -20,11 +20,9 @@
#include "sh_pfc.h"
-#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \ - SH_PFC_PIN_CFG_PULL_UP | \ - SH_PFC_PIN_CFG_PULL_DOWN) +#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
-#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ @@ -37,6 +35,51 @@ PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ + PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ + PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) + /* * F_() : just information * FM() : macro for FN_xxx / xxx_MARK @@ -1519,67 +1562,16 @@ static const u16 pinmux_data[] = { };
/* - * R8A77965 has 8 banks with 32 GPIOs in each => 256 GPIOs. - * Physical layout rows: A - AW, cols: 1 - 39. + * Pins not associated with a GPIO port. */ -#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) -#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) -#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) -#define PIN_NONE U16_MAX +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +};
static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), - - /* - * Pins not associated with a GPIO port. - * - * The pin positions are different between different r8a77965 - * packages, all that is needed for the pfc driver is a unique - * number for each pin. To this end use the pin layout from - * R-Car M3SiP to calculate a unique number for each pin. - */ - SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), + PINMUX_NOGP_ALL(), };
/* - AUDIO CLOCK ------------------------------------------------------------ */ @@ -1728,7 +1720,7 @@ static const unsigned int avb_phy_int_mux[] = { }; static const unsigned int avb_mdio_pins[] = { /* AVB_MDC, AVB_MDIO */ - RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9), + RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, }; static const unsigned int avb_mdio_mux[] = { AVB_MDC_MARK, AVB_MDIO_MARK, @@ -1741,12 +1733,11 @@ static const unsigned int avb_mii_pins[] = { * AVB_RD1, AVB_RD2, AVB_RD3, * AVB_TXCREFCLK */ - PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18), - PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17), - PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13), - PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14), - PIN_NUMBER('A', 12), - + PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, + PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, + PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, + PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, + PIN_AVB_TXCREFCLK, }; static const unsigned int avb_mii_mux[] = { AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, @@ -3418,6 +3409,57 @@ static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, };
+/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* QSPI0_SPCLK, QSPI0_SSL */ + PIN_QSPI0_SPCLK, PIN_QSPI0_SSL, +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data2_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ + PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, +}; +static const unsigned int qspi0_data2_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, +}; +static const unsigned int qspi0_data4_pins[] = { + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ + PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, + /* QSPI0_IO2, QSPI0_IO3 */ + PIN_QSPI0_IO2, PIN_QSPI0_IO3, +}; +static const unsigned int qspi0_data4_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK, +}; +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* QSPI1_SPCLK, QSPI1_SSL */ + PIN_QSPI1_SPCLK, PIN_QSPI1_SSL, +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data2_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, +}; +static const unsigned int qspi1_data2_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +}; +static const unsigned int qspi1_data4_pins[] = { + /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, + /* QSPI1_IO2, QSPI1_IO3 */ + PIN_QSPI1_IO2, PIN_QSPI1_IO3, +}; +static const unsigned int qspi1_data4_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK, +}; + /* - SATA --------------------------------------------------------------------*/ static const unsigned int sata0_devslp_a_pins[] = { /* DEVSLP */ @@ -4391,7 +4433,7 @@ static const unsigned int vin5_clk_mux[] = { };
static const struct { - struct sh_pfc_pin_group common[318]; + struct sh_pfc_pin_group common[324]; #ifdef CONFIG_PINCTRL_PFC_R8A77965 struct sh_pfc_pin_group automotive[30]; #endif @@ -4596,6 +4638,12 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), + SH_PFC_PIN_GROUP(qspi0_ctrl), + SH_PFC_PIN_GROUP(qspi0_data2), + SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + SH_PFC_PIN_GROUP(qspi1_data2), + SH_PFC_PIN_GROUP(qspi1_data4), SH_PFC_PIN_GROUP(sata0_devslp_a), SH_PFC_PIN_GROUP(sata0_devslp_b), SH_PFC_PIN_GROUP(scif0_data), @@ -5088,6 +5136,18 @@ static const char * const pwm6_groups[] = { "pwm6_b", };
+static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + static const char * const sata0_groups[] = { "sata0_devslp_a", "sata0_devslp_b", @@ -5267,7 +5327,7 @@ static const char * const vin5_groups[] = { };
static const struct { - struct sh_pfc_function common[51]; + struct sh_pfc_function common[53]; #ifdef CONFIG_PINCTRL_PFC_R8A77965 struct sh_pfc_function automotive[4]; #endif @@ -5304,6 +5364,8 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(sata0), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), @@ -5900,44 +5962,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
static const struct pinmux_drive_reg pinmux_drive_regs[] = { { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { - { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */ - { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */ - { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */ - { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */ - { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */ - { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */ - { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */ - { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */ + { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ + { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ + { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ + { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ + { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ + { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ + { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ + { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { - { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */ - { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */ - { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */ - { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */ - { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */ - { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */ - { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */ - { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */ + { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ + { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ + { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ + { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ + { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ + { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ + { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ + { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ } }, { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { - { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */ - { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */ - { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */ - { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */ - { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */ - { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */ - { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */ - { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */ + { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ + { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ + { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ + { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ + { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ + { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ + { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ + { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { - { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */ - { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */ - { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */ - { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */ - { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */ - { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ - { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ - { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ + { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ + { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ + { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ + { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ + { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ + { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ + { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ + { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ } }, { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ @@ -5991,7 +6053,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { } }, { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ - { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */ + { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ @@ -6010,29 +6072,29 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ } }, { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { - { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ - { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ - { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ - { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ - { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ - { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ - { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ + { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ + { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ + { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ + { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ + { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ + { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ + { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ } }, { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { - { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN3 */ - { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */ - { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */ + { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ + { PIN_FSCLKST, 20, 2 }, /* FSCLKST */ + { PIN_TMS, 4, 2 }, /* TMS */ } }, { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { - { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */ - { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */ - { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ - { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ - { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ - { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ - { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ - { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ + { PIN_TDO, 28, 2 }, /* TDO */ + { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ + { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ + { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ + { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ + { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ + { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ + { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ } }, { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ @@ -6101,7 +6163,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ - { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */ + { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ } }, { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { @@ -6174,35 +6236,35 @@ static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po
static const struct pinmux_bias_reg pinmux_bias_regs[] = { { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { - [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */ - [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */ - [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */ - [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */ - [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */ - [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */ - [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */ - [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */ - [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */ - [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */ - [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */ - [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */ - [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */ - [13] = PIN_NUMBER('V', 6), /* RPC_WP# */ - [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */ - [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */ - [16] = PIN_NUMBER('B', 19), /* AVB_RXC */ - [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */ - [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */ - [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */ - [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */ - [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */ - [22] = PIN_NUMBER('A', 19), /* AVB_TXC */ - [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */ - [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */ - [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */ - [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */ - [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */ - [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */ + [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ + [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ + [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ + [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ + [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ + [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ + [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ + [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ + [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ + [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ + [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ + [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ + [12] = PIN_RPC_INT_N, /* RPC_INT# */ + [13] = PIN_RPC_WP_N, /* RPC_WP# */ + [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ + [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ + [16] = PIN_AVB_RXC, /* AVB_RXC */ + [17] = PIN_AVB_RD0, /* AVB_RD0 */ + [18] = PIN_AVB_RD1, /* AVB_RD1 */ + [19] = PIN_AVB_RD2, /* AVB_RD2 */ + [20] = PIN_AVB_RD3, /* AVB_RD3 */ + [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ + [22] = PIN_AVB_TXC, /* AVB_TXC */ + [23] = PIN_AVB_TD0, /* AVB_TD0 */ + [24] = PIN_AVB_TD1, /* AVB_TD1 */ + [25] = PIN_AVB_TD2, /* AVB_TD2 */ + [26] = PIN_AVB_TD3, /* AVB_TD3 */ + [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ + [28] = PIN_AVB_MDIO, /* AVB_MDIO */ [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ @@ -6251,7 +6313,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ - [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */ + [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ [10] = RCAR_GP_PIN(0, 0), /* D0 */ [11] = RCAR_GP_PIN(0, 1), /* D1 */ [12] = RCAR_GP_PIN(0, 2), /* D2 */ @@ -6272,20 +6334,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ - [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ - [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ + [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ + [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ } }, { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { - [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */ - [ 1] = PIN_NONE, - [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */ - [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/ - [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */ - [ 5] = PIN_A_NUMBER('T', 27), /* TCK */ - [ 6] = PIN_A_NUMBER('R', 30), /* TMS */ - [ 7] = PIN_A_NUMBER('R', 29), /* TDI */ - [ 8] = PIN_NONE, - [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */ + [ 0] = SH_PFC_PIN_NONE, + [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ + [ 2] = PIN_FSCLKST, /* FSCLKST */ + [ 3] = PIN_EXTALR, /* EXTALR*/ + [ 4] = PIN_TRST_N, /* TRST# */ + [ 5] = PIN_TCK, /* TCK */ + [ 6] = PIN_TMS, /* TMS */ + [ 7] = PIN_TDI, /* TDI */ + [ 8] = SH_PFC_PIN_NONE, + [ 9] = PIN_ASEBRK, /* ASEBRK */ [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ @@ -6350,7 +6412,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ - [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */ + [ 6] = PIN_MLB_REF, /* MLB_REF */ [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ @@ -6385,31 +6447,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */ [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */ - [ 7] = PIN_NONE, - [ 8] = PIN_NONE, - [ 9] = PIN_NONE, - [10] = PIN_NONE, - [11] = PIN_NONE, - [12] = PIN_NONE, - [13] = PIN_NONE, - [14] = PIN_NONE, - [15] = PIN_NONE, - [16] = PIN_NONE, - [17] = PIN_NONE, - [18] = PIN_NONE, - [19] = PIN_NONE, - [20] = PIN_NONE, - [21] = PIN_NONE, - [22] = PIN_NONE, - [23] = PIN_NONE, - [24] = PIN_NONE, - [25] = PIN_NONE, - [26] = PIN_NONE, - [27] = PIN_NONE, - [28] = PIN_NONE, - [29] = PIN_NONE, - [30] = PIN_NONE, - [31] = PIN_NONE, + [ 7] = SH_PFC_PIN_NONE, + [ 8] = SH_PFC_PIN_NONE, + [ 9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, } }, { /* sentinel */ }, }; diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c index 33ecd93398..4e6f406214 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77970.c +++ b/drivers/pinctrl/renesas/pfc-r8a77970.c @@ -5,7 +5,7 @@ * Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2017 Cogent Embedded, Inc. source@cogentembedded.com * - * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c + * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c * * R-Car Gen3 processor support - PFC hardware block. * @@ -20,7 +20,7 @@
#include "sh_pfc.h"
-#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ PORT_GP_28(1, fn, sfx), \ PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ @@ -206,8 +206,8 @@ #define IP6_19_16 FM(VI1_DATA8) F_(0, 0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_23_20 FM(VI1_DATA9) F_(0, 0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_27_24 FM(VI1_DATA10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -632,14 +632,12 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP6_31_28, SCL4), PINMUX_IPSR_GPSR(IP6_31_28, IRQ4), PINMUX_IPSR_GPSR(IP6_31_28, D14), - PINMUX_IPSR_GPSR(IP6_31_28, MMC_WP),
/* IPSR7 */ PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD), PINMUX_IPSR_GPSR(IP7_3_0, SDA4), PINMUX_IPSR_GPSR(IP7_3_0, IRQ5), PINMUX_IPSR_GPSR(IP7_3_0, D15), - PINMUX_IPSR_GPSR(IP7_3_0, MMC_CD),
PINMUX_IPSR_GPSR(IP7_7_4, SCL0), PINMUX_IPSR_GPSR(IP7_7_4, DU_DR0), @@ -1122,20 +1120,6 @@ static const unsigned int mmc_ctrl_pins[] = { static const unsigned int mmc_ctrl_mux[] = { MMC_CLK_MARK, MMC_CMD_MARK, }; -static const unsigned int mmc_cd_pins[] = { - /* CD */ - RCAR_GP_PIN(3, 16), -}; -static const unsigned int mmc_cd_mux[] = { - MMC_CD_MARK, -}; -static const unsigned int mmc_wp_pins[] = { - /* WP */ - RCAR_GP_PIN(3, 15), -}; -static const unsigned int mmc_wp_mux[] = { - MMC_WP_MARK, -};
/* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { @@ -1433,6 +1417,64 @@ static const unsigned int qspi1_data4_mux[] = { QSPI1_IO2_MARK, QSPI1_IO3_MARK };
+/* - RPC -------------------------------------------------------------------- */ +static const unsigned int rpc_clk1_pins[] = { + /* Octal-SPI flash: C/SCLK */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int rpc_clk1_mux[] = { + QSPI0_SPCLK_MARK, +}; +static const unsigned int rpc_clk2_pins[] = { + /* HyperFlash: CK, CK# */ + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6), +}; +static const unsigned int rpc_clk2_mux[] = { + QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, +}; +static const unsigned int rpc_ctrl_pins[] = { + /* Octal-SPI flash: S#/CS, DQS */ + /* HyperFlash: CS#, RDS */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), +}; +static const unsigned int rpc_ctrl_mux[] = { + QSPI0_SSL_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int rpc_data_pins[] = { + /* DQ[0:7] */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), + RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), + RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), + RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), +}; +static const unsigned int rpc_data_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK, + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK, +}; +static const unsigned int rpc_reset_pins[] = { + /* RPC_RESET# */ + RCAR_GP_PIN(5, 12), +}; +static const unsigned int rpc_reset_mux[] = { + RPC_RESET_N_MARK, +}; +static const unsigned int rpc_int_pins[] = { + /* RPC_INT# */ + RCAR_GP_PIN(5, 14), +}; +static const unsigned int rpc_int_mux[] = { + RPC_INT_N_MARK, +}; +static const unsigned int rpc_wp_pins[] = { + /* RPC_WP# */ + RCAR_GP_PIN(5, 13), +}; +static const unsigned int rpc_wp_mux[] = { + RPC_WP_N_MARK, +}; + /* - SCIF Clock ------------------------------------------------------------- */ static const unsigned int scif_clk_a_pins[] = { /* SCIF_CLK */ @@ -1727,8 +1769,6 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc_data4), SH_PFC_PIN_GROUP(mmc_data8), SH_PFC_PIN_GROUP(mmc_ctrl), - SH_PFC_PIN_GROUP(mmc_cd), - SH_PFC_PIN_GROUP(mmc_wp), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -1769,6 +1809,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(qspi1_ctrl), SH_PFC_PIN_GROUP(qspi1_data2), SH_PFC_PIN_GROUP(qspi1_data4), + SH_PFC_PIN_GROUP(rpc_clk1), + SH_PFC_PIN_GROUP(rpc_clk2), + SH_PFC_PIN_GROUP(rpc_ctrl), + SH_PFC_PIN_GROUP(rpc_data), + SH_PFC_PIN_GROUP(rpc_reset), + SH_PFC_PIN_GROUP(rpc_int), + SH_PFC_PIN_GROUP(rpc_wp), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), SH_PFC_PIN_GROUP(scif0_data), @@ -1898,8 +1945,6 @@ static const char * const mmc_groups[] = { "mmc_data4", "mmc_data8", "mmc_ctrl", - "mmc_cd", - "mmc_wp", };
static const char * const msiof0_groups[] = { @@ -1975,6 +2020,16 @@ static const char * const qspi1_groups[] = { "qspi1_data4", };
+static const char * const rpc_groups[] = { + "rpc_clk1", + "rpc_clk2", + "rpc_ctrl", + "rpc_data", + "rpc_reset", + "rpc_int", + "rpc_wp", +}; + static const char * const scif_clk_groups[] = { "scif_clk_a", "scif_clk_b", @@ -2060,6 +2115,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), + SH_PFC_FUNCTION(rpc), SH_PFC_FUNCTION(scif_clk), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c index 32efb4409c..2d15500f0f 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77980.c +++ b/drivers/pinctrl/renesas/pfc-r8a77980.c @@ -5,7 +5,7 @@ * Copyright (C) 2018 Renesas Electronics Corp. * Copyright (C) 2018 Cogent Embedded, Inc. * - * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c + * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c * * R-Car Gen3 processor support - PFC hardware block. * @@ -20,7 +20,7 @@
#include "sh_pfc.h"
-#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ PORT_GP_28(1, fn, sfx), \ PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ @@ -1711,6 +1711,64 @@ static const unsigned int qspi1_data4_mux[] = { QSPI1_IO2_MARK, QSPI1_IO3_MARK };
+/* - RPC -------------------------------------------------------------------- */ +static const unsigned int rpc_clk1_pins[] = { + /* Octal-SPI flash: C/SCLK */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int rpc_clk1_mux[] = { + QSPI0_SPCLK_MARK, +}; +static const unsigned int rpc_clk2_pins[] = { + /* HyperFlash: CK, CK# */ + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6), +}; +static const unsigned int rpc_clk2_mux[] = { + QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, +}; +static const unsigned int rpc_ctrl_pins[] = { + /* Octal-SPI flash: S#/CS, DQS */ + /* HyperFlash: CS#, RDS */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), +}; +static const unsigned int rpc_ctrl_mux[] = { + QSPI0_SSL_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int rpc_data_pins[] = { + /* DQ[0:7] */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), + RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), + RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), + RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), +}; +static const unsigned int rpc_data_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK, + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK, +}; +static const unsigned int rpc_reset_pins[] = { + /* RPC_RESET# */ + RCAR_GP_PIN(5, 12), +}; +static const unsigned int rpc_reset_mux[] = { + RPC_RESET_N_MARK, +}; +static const unsigned int rpc_int_pins[] = { + /* RPC_INT# */ + RCAR_GP_PIN(5, 14), +}; +static const unsigned int rpc_int_mux[] = { + RPC_INT_N_MARK, +}; +static const unsigned int rpc_wp_pins[] = { + /* RPC_WP# */ + RCAR_GP_PIN(5, 13), +}; +static const unsigned int rpc_wp_mux[] = { + RPC_WP_N_MARK, +}; + /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX0, TX0 */ @@ -2127,6 +2185,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(qspi1_ctrl), SH_PFC_PIN_GROUP(qspi1_data2), SH_PFC_PIN_GROUP(qspi1_data4), + SH_PFC_PIN_GROUP(rpc_clk1), + SH_PFC_PIN_GROUP(rpc_clk2), + SH_PFC_PIN_GROUP(rpc_ctrl), + SH_PFC_PIN_GROUP(rpc_data), + SH_PFC_PIN_GROUP(rpc_reset), + SH_PFC_PIN_GROUP(rpc_int), + SH_PFC_PIN_GROUP(rpc_wp), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -2363,6 +2428,16 @@ static const char * const qspi1_groups[] = { "qspi1_data4", };
+static const char * const rpc_groups[] = { + "rpc_clk1", + "rpc_clk2", + "rpc_ctrl", + "rpc_data", + "rpc_reset", + "rpc_int", + "rpc_wp", +}; + static const char * const scif0_groups[] = { "scif0_data", "scif0_clk", @@ -2461,6 +2536,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), + SH_PFC_FUNCTION(rpc), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif3), diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index 572b041b83..78b46de041 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -4,7 +4,7 @@ * * Copyright (C) 2018-2019 Renesas Electronics Corp. * - * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c + * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c * * R8A7796 processor support - PFC hardware block. * @@ -20,10 +20,9 @@
#include "sh_pfc.h"
-#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP | \ - SH_PFC_PIN_CFG_PULL_DOWN) +#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP_DOWN)
-#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \ @@ -44,6 +43,25 @@ PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_MDC, "AVB_MDC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TCK, "TCK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TDI, "TDI", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TRST_N, "TRST_N", fn, CFG_FLAGS) + /* * F_() : just information * FM() : macro for FN_xxx / xxx_MARK @@ -1283,41 +1301,16 @@ static const u16 pinmux_data[] = { };
/* - * R8A77990 has 7 banks with 32 GPIOs in each => 224 GPIOs. - * Physical layout rows: A - AE, cols: 1 - 25. + * Pins not associated with a GPIO port. */ -#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) -#define PIN_NUMBER(r, c) (((r) - 'A') * 25 + (c) + 300) -#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) -#define PIN_NONE U16_MAX +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +};
static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), - - /* - * Pins not associated with a GPIO port. - * - * The pin positions are different between different R8A77990 - * packages, all that is needed for the pfc driver is a unique - * number for each pin. To this end use the pin layout from - * R8A77990 to calculate a unique number for each pin. - */ - SH_PFC_PIN_NAMED_CFG('F', 1, TRST_N, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('F', 3, TMS, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('F', 4, TCK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('G', 2, TDI, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('G', 3, FSCLKST_N, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('H', 1, ASEBRK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('N', 1, AVB_TXC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('N', 2, AVB_TD0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('N', 3, AVB_TD1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('N', 5, AVB_TD2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('N', 6, AVB_TD3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('P', 3, AVB_TX_CTL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('P', 4, AVB_MDIO, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('P', 5, AVB_MDC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('T', 21, MLB_REF, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS), + PINMUX_NOGP_ALL(), };
/* - AUDIO CLOCK ------------------------------------------------------------ */ @@ -5115,15 +5108,15 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [0] = RCAR_GP_PIN(2, 23), /* RD# */ [1] = RCAR_GP_PIN(2, 22), /* BS# */ [2] = RCAR_GP_PIN(2, 21), /* AVB_PHY_INT */ - [3] = PIN_NUMBER('P', 5), /* AVB_MDC */ - [4] = PIN_NUMBER('P', 4), /* AVB_MDIO */ + [3] = PIN_AVB_MDC, /* AVB_MDC */ + [4] = PIN_AVB_MDIO, /* AVB_MDIO */ [5] = RCAR_GP_PIN(2, 20), /* AVB_TXCREFCLK */ - [6] = PIN_NUMBER('N', 6), /* AVB_TD3 */ - [7] = PIN_NUMBER('N', 5), /* AVB_TD2 */ - [8] = PIN_NUMBER('N', 3), /* AVB_TD1 */ - [9] = PIN_NUMBER('N', 2), /* AVB_TD0 */ - [10] = PIN_NUMBER('N', 1), /* AVB_TXC */ - [11] = PIN_NUMBER('P', 3), /* AVB_TX_CTL */ + [6] = PIN_AVB_TD3, /* AVB_TD3 */ + [7] = PIN_AVB_TD2, /* AVB_TD2 */ + [8] = PIN_AVB_TD1, /* AVB_TD1 */ + [9] = PIN_AVB_TD0, /* AVB_TD0 */ + [10] = PIN_AVB_TXC, /* AVB_TXC */ + [11] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ [12] = RCAR_GP_PIN(2, 19), /* AVB_RD3 */ [13] = RCAR_GP_PIN(2, 18), /* AVB_RD2 */ [14] = RCAR_GP_PIN(2, 17), /* AVB_RD1 */ @@ -5174,33 +5167,33 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [25] = RCAR_GP_PIN(1, 2), /* A2 */ [26] = RCAR_GP_PIN(1, 1), /* A1 */ [27] = RCAR_GP_PIN(1, 0), /* A0 */ - [28] = PIN_NONE, - [29] = PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, [30] = RCAR_GP_PIN(2, 25), /* PUEN_EX_WAIT0 */ [31] = RCAR_GP_PIN(2, 24), /* PUEN_RD/WR# */ } }, { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { [0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ [1] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ - [2] = PIN_NUMBER('H', 1), /* ASEBRK */ - [3] = PIN_NONE, - [4] = PIN_NUMBER('G', 2), /* TDI */ - [5] = PIN_NUMBER('F', 3), /* TMS */ - [6] = PIN_NUMBER('F', 4), /* TCK */ - [7] = PIN_NUMBER('F', 1), /* TRST# */ - [8] = PIN_NONE, - [9] = PIN_NONE, - [10] = PIN_NONE, - [11] = PIN_NONE, - [12] = PIN_NONE, - [13] = PIN_NONE, - [14] = PIN_NONE, - [15] = PIN_NUMBER('G', 3), /* FSCLKST# */ + [2] = PIN_ASEBRK, /* ASEBRK */ + [3] = SH_PFC_PIN_NONE, + [4] = PIN_TDI, /* TDI */ + [5] = PIN_TMS, /* TMS */ + [6] = PIN_TCK, /* TCK */ + [7] = PIN_TRST_N, /* TRST# */ + [8] = SH_PFC_PIN_NONE, + [9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = PIN_FSCLKST_N, /* FSCLKST# */ [16] = RCAR_GP_PIN(0, 17), /* SDA4 */ [17] = RCAR_GP_PIN(0, 16), /* SCL4 */ - [18] = PIN_NONE, - [19] = PIN_NONE, - [20] = PIN_A_NUMBER('D', 3), /* PRESETOUT# */ + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = PIN_PRESETOUT_N, /* PRESETOUT# */ [21] = RCAR_GP_PIN(0, 15), /* D15 */ [22] = RCAR_GP_PIN(0, 14), /* D14 */ [23] = RCAR_GP_PIN(0, 13), /* D13 */ @@ -5219,8 +5212,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */ [3] = RCAR_GP_PIN(5, 2), /* TX0_A */ [4] = RCAR_GP_PIN(5, 1), /* RX0_A */ - [5] = PIN_NONE, - [6] = PIN_NONE, + [5] = SH_PFC_PIN_NONE, + [6] = SH_PFC_PIN_NONE, [7] = RCAR_GP_PIN(3, 15), /* SD1_WP */ [8] = RCAR_GP_PIN(3, 14), /* SD1_CD */ [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ @@ -5264,7 +5257,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [13] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ [14] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ [15] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ - [16] = PIN_NUMBER('T', 21), /* MLB_REF */ + [16] = PIN_MLB_REF, /* MLB_REF */ [17] = RCAR_GP_PIN(5, 19), /* MLB_DAT */ [18] = RCAR_GP_PIN(5, 18), /* MLB_SIG */ [19] = RCAR_GP_PIN(5, 17), /* MLB_CLK */ @@ -5282,36 +5275,36 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [31] = RCAR_GP_PIN(5, 5), /* RX1 */ } }, { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { - [0] = PIN_NONE, - [1] = PIN_NONE, - [2] = PIN_NONE, - [3] = PIN_NONE, - [4] = PIN_NONE, - [5] = PIN_NONE, - [6] = PIN_NONE, - [7] = PIN_NONE, - [8] = PIN_NONE, - [9] = PIN_NONE, - [10] = PIN_NONE, - [11] = PIN_NONE, - [12] = PIN_NONE, - [13] = PIN_NONE, - [14] = PIN_NONE, - [15] = PIN_NONE, - [16] = PIN_NONE, - [17] = PIN_NONE, - [18] = PIN_NONE, - [19] = PIN_NONE, - [20] = PIN_NONE, - [21] = PIN_NONE, - [22] = PIN_NONE, - [23] = PIN_NONE, - [24] = PIN_NONE, - [25] = PIN_NONE, - [26] = PIN_NONE, - [27] = PIN_NONE, - [28] = PIN_NONE, - [29] = PIN_NONE, + [0] = SH_PFC_PIN_NONE, + [1] = SH_PFC_PIN_NONE, + [2] = SH_PFC_PIN_NONE, + [3] = SH_PFC_PIN_NONE, + [4] = SH_PFC_PIN_NONE, + [5] = SH_PFC_PIN_NONE, + [6] = SH_PFC_PIN_NONE, + [7] = SH_PFC_PIN_NONE, + [8] = SH_PFC_PIN_NONE, + [9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, [30] = RCAR_GP_PIN(6, 9), /* PUEN_USB30_OVC */ [31] = RCAR_GP_PIN(6, 17), /* PUEN_USB30_PWEN */ } }, diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c index 724cf4ae3c..4ff1b76588 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77995.c +++ b/drivers/pinctrl/renesas/pfc-r8a77995.c @@ -4,7 +4,7 @@ * * Copyright (C) 2017 Renesas Electronics Corp. * - * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c + * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c * * R-Car Gen3 processor support - PFC hardware block. * @@ -19,7 +19,7 @@
#include "sh_pfc.h"
-#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_9(0, fn, sfx), \ PORT_GP_32(1, fn, sfx), \ PORT_GP_32(2, fn, sfx), \ diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index f563916f10..9d74f5fb4e 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -1,11 +1,8 @@ -/* +/* SPDX-License-Identifier: GPL-2.0 + * * SuperH Pin Function Controller Support * * Copyright (c) 2008 Magnus Damm - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. */
#ifndef __SH_PFC_H @@ -21,19 +18,32 @@ enum { PINMUX_TYPE_INPUT, };
+#define SH_PFC_PIN_NONE U16_MAX + #define SH_PFC_PIN_CFG_INPUT (1 << 0) #define SH_PFC_PIN_CFG_OUTPUT (1 << 1) #define SH_PFC_PIN_CFG_PULL_UP (1 << 2) #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) +#define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \ + SH_PFC_PIN_CFG_PULL_DOWN) #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4) #define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5) + +#define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6) +#define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6) + +#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \ + SH_PFC_PIN_VOLTAGE_18_33) +#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \ + SH_PFC_PIN_VOLTAGE_25_33) + #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
struct sh_pfc_pin { - u16 pin; - u16 enum_id; const char *name; unsigned int configs; + u16 pin; + u16 enum_id; };
#define SH_PFC_PIN_GROUP_ALIAS(alias, n) \ @@ -393,12 +403,12 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; /* * Describe a pinmux configuration in which a pin is physically multiplexed * with other pins. - * - ipsr: IPSR field (unused, for documentation purposes only) + * - ipsr: IPSR field * - fn: Function name * - psel: Physical multiplexing selector */ #define PINMUX_IPSR_PHYS(ipsr, fn, psel) \ - PINMUX_DATA(fn##_MARK, FN_##psel) + PINMUX_DATA(fn##_MARK, FN_##psel, FN_##ipsr)
/* * Describe a pinmux configuration for a single-function pin with GPIO @@ -416,9 +426,13 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; fn(bank, pin, GP_##bank##_##pin, sfx, cfg) #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
-#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_2(bank, fn, sfx, cfg) \ PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 1, fn, sfx, cfg) +#define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0) + +#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ + PORT_GP_CFG_2(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 3, fn, sfx, cfg) #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0) @@ -517,9 +531,13 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; PORT_GP_CFG_1(bank, 25, fn, sfx, cfg) #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
-#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_27(bank, fn, sfx, cfg) \ PORT_GP_CFG_26(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 26, fn, sfx, cfg) +#define PORT_GP_27(bank, fn, sfx) PORT_GP_CFG_27(bank, fn, sfx, 0) + +#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \ + PORT_GP_CFG_27(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 27, fn, sfx, cfg) #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
@@ -533,9 +551,13 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; PORT_GP_CFG_1(bank, 29, fn, sfx, cfg) #define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
-#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_31(bank, fn, sfx, cfg) \ PORT_GP_CFG_30(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 30, fn, sfx, cfg) +#define PORT_GP_31(bank, fn, sfx) PORT_GP_CFG_31(bank, fn, sfx, 0) + +#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \ + PORT_GP_CFG_31(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 31, fn, sfx, cfg) #define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
@@ -559,7 +581,7 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */ #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx -#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str) +#define GP_ALL(str) CPU_ALL_GP(_GP_ALL, str)
/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ #define _GP_GPIO(bank, _pin, _name, sfx, cfg) \ @@ -569,11 +591,29 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; .enum_id = _name##_DATA, \ .configs = cfg, \ } -#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */ #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN) -#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_GP(_GP_DATA, unused) + +/* + * GP_ASSIGN_LAST() - Expand to an enum definition for the last GP pin + * + * The largest GP pin index is obtained by taking the size of a union, + * containing one array per GP pin, sized by the corresponding pin index. + * As the fields in the CPU_ALL_GP() macro definition are separated by commas, + * while the members of a union must be terminated by semicolons, the commas + * are absorbed by wrapping them inside dummy attributes. + */ +#define _GP_ENTRY(bank, pin, name, sfx, cfg) \ + deprecated)); char name[(bank * 32) + pin] __attribute__((deprecated +#define GP_ASSIGN_LAST() \ + GP_LAST = sizeof(union { \ + char dummy[0] __attribute__((deprecated, \ + CPU_ALL_GP(_GP_ENTRY, unused), \ + deprecated)); \ + })
/* * PORT style (linear pin space) @@ -616,22 +656,6 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; .configs = cfgs, \ }
-/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */ -#define SH_PFC_PIN_NAMED(row, col, _name) \ - { \ - .pin = PIN_NUMBER(row, col), \ - .name = __stringify(PIN_##_name), \ - .configs = SH_PFC_PIN_CFG_NO_GPIO, \ - } - -/* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */ -#define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \ - { \ - .pin = PIN_NUMBER(row, col), \ - .name = __stringify(PIN_##_name), \ - .configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \ - } - /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0, * PORT_name_OUT, PORT_name_IN marks */ @@ -640,6 +664,24 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; PORT##pfx##_OUT, PORT##pfx##_IN) #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
+/* + * PORT_ASSIGN_LAST() - Expand to an enum definition for the last PORT pin + * + * The largest PORT pin index is obtained by taking the size of a union, + * containing one array per PORT pin, sized by the corresponding pin index. + * As the fields in the CPU_ALL_PORT() macro definition are separated by + * commas, while the members of a union must be terminated by semicolons, the + * commas are absorbed by wrapping them inside dummy attributes. + */ +#define _PORT_ENTRY(pn, pfx, sfx) \ + deprecated)); char pfx[pn] __attribute__((deprecated +#define PORT_ASSIGN_LAST() \ + PORT_LAST = sizeof(union { \ + char dummy[0] __attribute__((deprecated, \ + CPU_ALL_PORT(_PORT_ENTRY, PORT, unused), \ + deprecated)); \ + }) + /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */ #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ [gpio - (base)] = { \ @@ -649,6 +691,26 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; #define GPIO_FN(str) \ PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
+/* + * Pins not associated with a GPIO port + */ + +#define PIN_NOGP_CFG(pin, name, fn, cfg) fn(pin, name, cfg) +#define PIN_NOGP(pin, name, fn) fn(pin, name, 0) + +/* NOGP_ALL - Expand to a list of PIN_id */ +#define _NOGP_ALL(pin, name, cfg) PIN_##pin +#define NOGP_ALL() CPU_ALL_NOGP(_NOGP_ALL) + +/* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */ +#define _NOGP_PINMUX(_pin, _name, cfg) \ + { \ + .pin = PIN_##_pin, \ + .name = "PIN_" _name, \ + .configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \ + } +#define PINMUX_NOGP_ALL() CPU_ALL_NOGP(_NOGP_PINMUX) + /* * PORTnCR helper macro for SH-Mobile/R-Mobile */
Hi Marek,
Thank you for the patch.
On Wed, Apr 28, 2021 at 8:38 PM Marek Vasut marek.vasut@gmail.com wrote:
Synchronize R-Car Gen2/Gen3 pinctrl tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . This is a rather large commit, since the macros in sh-pfc.h also got updated, so all the PFC tables must be updated in lockstep.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com
drivers/pinctrl/renesas/pfc-r8a7790.c | 1019 +++++++++++++++--------- drivers/pinctrl/renesas/pfc-r8a7791.c | 20 +- drivers/pinctrl/renesas/pfc-r8a7792.c | 2 +- drivers/pinctrl/renesas/pfc-r8a7794.c | 2 +- drivers/pinctrl/renesas/pfc-r8a7795.c | 467 ++++++----- drivers/pinctrl/renesas/pfc-r8a7796.c | 492 +++++++----- drivers/pinctrl/renesas/pfc-r8a77965.c | 446 ++++++----- drivers/pinctrl/renesas/pfc-r8a77970.c | 104 ++- drivers/pinctrl/renesas/pfc-r8a77980.c | 80 +- drivers/pinctrl/renesas/pfc-r8a77990.c | 183 ++--- drivers/pinctrl/renesas/pfc-r8a77995.c | 4 +- drivers/pinctrl/renesas/sh_pfc.h | 130 ++- 12 files changed, 1834 insertions(+), 1115 deletions(-)
Tested on RZ/G2{EHMN} boards
Tested-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
Cheers, Prabhakar
diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c index 5e1502ed96..1793000ab5 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7790.c +++ b/drivers/pinctrl/renesas/pfc-r8a7790.c @@ -20,7 +20,7 @@
- All pins assigned to GPIO bank 3 can be used for SD interfaces in
- which case they support both 3.3V and 1.8V signalling.
*/ -#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ PORT_GP_30(1, fn, sfx), \ PORT_GP_30(2, fn, sfx), \ @@ -28,6 +28,12 @@ PORT_GP_32(4, fn, sfx), \ PORT_GP_32(5, fn, sfx)
+#define CPU_ALL_NOGP(fn) \
PIN_NOGP(IIC0_SDA, "AF15", fn), \PIN_NOGP(IIC0_SCL, "AG15", fn), \PIN_NOGP(IIC3_SDA, "AH15", fn), \PIN_NOGP(IIC3_SCL, "AJ15", fn)enum { PINMUX_RESERVED = 0,
@@ -1727,19 +1733,17 @@ static const u16 pinmux_data[] = { PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1), };
-/* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */ -#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) -#define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200) -#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) +/*
- Pins not associated with a GPIO port.
- */
+enum {
GP_ASSIGN_LAST(),NOGP_ALL(),+};
static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(),
/* Pins not associated with a GPIO port */SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15),SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15),SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15),SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15),
PINMUX_NOGP_ALL(),};
/* - AUDIO CLOCK ------------------------------------------------------------ */ @@ -1867,6 +1871,86 @@ static const unsigned int avb_gmii_mux[] = { AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, AVB_COL_MARK, }; +/* - CAN0 ----------------------------------------------------------------- */ +static const unsigned int can0_data_pins[] = {
/* CAN0 RX */RCAR_GP_PIN(1, 17),/* CAN0 TX */RCAR_GP_PIN(1, 19),+}; +static const unsigned int can0_data_mux[] = {
CAN0_RX_MARK,CAN0_TX_MARK,+}; +static const unsigned int can0_data_b_pins[] = {
/* CAN0 RXB */RCAR_GP_PIN(4, 5),/* CAN0 TXB */RCAR_GP_PIN(4, 4),+}; +static const unsigned int can0_data_b_mux[] = {
CAN0_RX_B_MARK,CAN0_TX_B_MARK,+}; +static const unsigned int can0_data_c_pins[] = {
/* CAN0 RXC */RCAR_GP_PIN(4, 26),/* CAN0 TXC */RCAR_GP_PIN(4, 23),+}; +static const unsigned int can0_data_c_mux[] = {
CAN0_RX_C_MARK,CAN0_TX_C_MARK,+}; +static const unsigned int can0_data_d_pins[] = {
/* CAN0 RXD */RCAR_GP_PIN(4, 26),/* CAN0 TXD */RCAR_GP_PIN(4, 18),+}; +static const unsigned int can0_data_d_mux[] = {
CAN0_RX_D_MARK,CAN0_TX_D_MARK,+}; +/* - CAN1 ----------------------------------------------------------------- */ +static const unsigned int can1_data_pins[] = {
/* CAN1 RX */RCAR_GP_PIN(1, 22),/* CAN1 TX */RCAR_GP_PIN(1, 18),+}; +static const unsigned int can1_data_mux[] = {
CAN1_RX_MARK,CAN1_TX_MARK,+}; +static const unsigned int can1_data_b_pins[] = {
/* CAN1 RXB */RCAR_GP_PIN(4, 7),/* CAN1 TXB */RCAR_GP_PIN(4, 6),+}; +static const unsigned int can1_data_b_mux[] = {
CAN1_RX_B_MARK,CAN1_TX_B_MARK,+}; +/* - CAN Clock -------------------------------------------------------------- */ +static const unsigned int can_clk_pins[] = {
/* CLK */RCAR_GP_PIN(1, 21),+};
+static const unsigned int can_clk_mux[] = {
CAN_CLK_MARK,+};
+static const unsigned int can_clk_b_pins[] = {
/* CLK */RCAR_GP_PIN(4, 3),+};
+static const unsigned int can_clk_b_mux[] = {
CAN_CLK_B_MARK,+}; /* - DU RGB ----------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -2135,7 +2219,7 @@ static const unsigned int hscif1_ctrl_b_mux[] = { /* - I2C0 ------------------------------------------------------------------- */ static const unsigned int i2c0_pins[] = { /* SCL, SDA */
PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
PIN_IIC0_SCL, PIN_IIC0_SDA,}; static const unsigned int i2c0_mux[] = { I2C0_SCL_MARK, I2C0_SDA_MARK, @@ -2201,7 +2285,7 @@ static const unsigned int i2c2_e_mux[] = { /* - I2C3 ------------------------------------------------------------------- */ static const unsigned int i2c3_pins[] = { /* SCL, SDA */
PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
PIN_IIC3_SCL, PIN_IIC3_SDA,}; static const unsigned int i2c3_mux[] = { I2C3_SCL_MARK, I2C3_SDA_MARK, @@ -2209,7 +2293,7 @@ static const unsigned int i2c3_mux[] = { /* - IIC0 (I2C4) ------------------------------------------------------------ */ static const unsigned int iic0_pins[] = { /* SCL, SDA */
PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
PIN_IIC0_SCL, PIN_IIC0_SDA,}; static const unsigned int iic0_mux[] = { IIC0_SCL_MARK, IIC0_SDA_MARK, @@ -2274,8 +2358,8 @@ static const unsigned int iic2_e_mux[] = { }; /* - IIC3 (I2C7) ------------------------------------------------------------ */ static const unsigned int iic3_pins[] = { -/* SCL, SDA */
PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
/* SCL, SDA */PIN_IIC3_SCL, PIN_IIC3_SDA,}; static const unsigned int iic3_mux[] = { IIC3_SCL_MARK, IIC3_SDA_MARK, @@ -2309,6 +2393,8 @@ static const unsigned int intc_irq3_pins[] = { static const unsigned int intc_irq3_mux[] = { IRQ3_MARK, };
+#ifdef CONFIG_PINCTRL_PFC_R8A7790 /* - MLB+ ------------------------------------------------------------------- */ static const unsigned int mlb_3pin_pins[] = { RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), @@ -2316,6 +2402,8 @@ static const unsigned int mlb_3pin_pins[] = { static const unsigned int mlb_3pin_mux[] = { MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, }; +#endif /* CONFIG_PINCTRL_PFC_R8A7790 */
/* - MMCIF0 ----------------------------------------------------------------- */ static const unsigned int mmc0_data1_pins[] = { /* D[0] */ @@ -3607,6 +3695,13 @@ static const unsigned int usb1_pins[] = { static const unsigned int usb1_mux[] = { USB1_PWEN_MARK, USB1_OVC_MARK, }; +static const unsigned int usb1_pwen_pins[] = {
/* PWEN */RCAR_GP_PIN(5, 20),+}; +static const unsigned int usb1_pwen_mux[] = {
USB1_PWEN_MARK,+}; /* - USB2 ------------------------------------------------------------------- */ static const unsigned int usb2_pins[] = { /* PWEN, OVC */ @@ -3775,6 +3870,72 @@ static const unsigned int vin1_data18_mux[] = { VI1_R4_MARK, VI1_R5_MARK, VI1_R6_MARK, VI1_R7_MARK, }; +static const union vin_data vin1_data_b_pins = {
.data24 = {/* B */RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),/* G */RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),/* R */RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),},+}; +static const union vin_data vin1_data_b_mux = {
.data24 = {/* B */VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK,VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,/* G */VI1_G0_B_MARK, VI1_G1_B_MARK,VI1_G2_B_MARK, VI1_G3_B_MARK,VI1_G4_B_MARK, VI1_G5_B_MARK,VI1_G6_B_MARK, VI1_G7_B_MARK,/* R */VI1_R0_B_MARK, VI1_R1_B_MARK,VI1_R2_B_MARK, VI1_R3_B_MARK,VI1_R4_B_MARK, VI1_R5_B_MARK,VI1_R6_B_MARK, VI1_R7_B_MARK,},+}; +static const unsigned int vin1_data18_b_pins[] = {
/* B */RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),/* G */RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),/* R */RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),+}; +static const unsigned int vin1_data18_b_mux[] = {
/* B */VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,/* G */VI1_G2_B_MARK, VI1_G3_B_MARK,VI1_G4_B_MARK, VI1_G5_B_MARK,VI1_G6_B_MARK, VI1_G7_B_MARK,/* R */VI1_R2_B_MARK, VI1_R3_B_MARK,VI1_R4_B_MARK, VI1_R5_B_MARK,VI1_R6_B_MARK, VI1_R7_B_MARK,+}; static const unsigned int vin1_sync_pins[] = { RCAR_GP_PIN(1, 24), /* HSYNC */ RCAR_GP_PIN(1, 25), /* VSYNC */ @@ -3783,24 +3944,50 @@ static const unsigned int vin1_sync_mux[] = { VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK, }; +static const unsigned int vin1_sync_b_pins[] = {
RCAR_GP_PIN(1, 24), /* HSYNC */RCAR_GP_PIN(1, 25), /* VSYNC */+}; +static const unsigned int vin1_sync_b_mux[] = {
VI1_HSYNC_N_B_MARK,VI1_VSYNC_N_B_MARK,+}; static const unsigned int vin1_field_pins[] = { RCAR_GP_PIN(1, 13), }; static const unsigned int vin1_field_mux[] = { VI1_FIELD_MARK, }; +static const unsigned int vin1_field_b_pins[] = {
RCAR_GP_PIN(1, 13),+}; +static const unsigned int vin1_field_b_mux[] = {
VI1_FIELD_B_MARK,+}; static const unsigned int vin1_clkenb_pins[] = { RCAR_GP_PIN(1, 26), }; static const unsigned int vin1_clkenb_mux[] = { VI1_CLKENB_MARK, }; +static const unsigned int vin1_clkenb_b_pins[] = {
RCAR_GP_PIN(1, 26),+}; +static const unsigned int vin1_clkenb_b_mux[] = {
VI1_CLKENB_B_MARK,+}; static const unsigned int vin1_clk_pins[] = { RCAR_GP_PIN(2, 9), }; static const unsigned int vin1_clk_mux[] = { VI1_CLK_MARK, }; +static const unsigned int vin1_clk_b_pins[] = {
RCAR_GP_PIN(3, 15),+}; +static const unsigned int vin1_clk_b_mux[] = {
VI1_CLK_B_MARK,+}; /* - VIN2 ----------------------------------------------------------------- */ static const union vin_data vin2_data_pins = { .data24 = { @@ -3868,6 +4055,18 @@ static const unsigned int vin2_data18_mux[] = { VI2_R4_MARK, VI2_R5_MARK, VI2_R6_MARK, VI2_R7_MARK, }; +static const unsigned int vin2_g8_pins[] = {
RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),+}; +static const unsigned int vin2_g8_mux[] = {
VI2_G0_MARK, VI2_G1_MARK,VI2_G2_MARK, VI2_G3_MARK,VI2_G4_MARK, VI2_G5_MARK,VI2_G6_MARK, VI2_G7_MARK,+}; static const unsigned int vin2_sync_pins[] = { RCAR_GP_PIN(1, 16), /* HSYNC */ RCAR_GP_PIN(1, 21), /* VSYNC */ @@ -3934,297 +4133,330 @@ static const unsigned int vin3_clk_mux[] = { VI3_CLK_MARK, };
-static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(audio_clk_a),SH_PFC_PIN_GROUP(audio_clk_b),SH_PFC_PIN_GROUP(audio_clk_c),SH_PFC_PIN_GROUP(audio_clkout),SH_PFC_PIN_GROUP(audio_clkout_b),SH_PFC_PIN_GROUP(audio_clkout_c),SH_PFC_PIN_GROUP(audio_clkout_d),SH_PFC_PIN_GROUP(avb_link),SH_PFC_PIN_GROUP(avb_magic),SH_PFC_PIN_GROUP(avb_phy_int),SH_PFC_PIN_GROUP(avb_mdio),SH_PFC_PIN_GROUP(avb_mii),SH_PFC_PIN_GROUP(avb_gmii),SH_PFC_PIN_GROUP(du_rgb666),SH_PFC_PIN_GROUP(du_rgb888),SH_PFC_PIN_GROUP(du_clk_out_0),SH_PFC_PIN_GROUP(du_clk_out_1),SH_PFC_PIN_GROUP(du_sync_0),SH_PFC_PIN_GROUP(du_sync_1),SH_PFC_PIN_GROUP(du_cde),SH_PFC_PIN_GROUP(du0_clk_in),SH_PFC_PIN_GROUP(du1_clk_in),SH_PFC_PIN_GROUP(du2_clk_in),SH_PFC_PIN_GROUP(eth_link),SH_PFC_PIN_GROUP(eth_magic),SH_PFC_PIN_GROUP(eth_mdio),SH_PFC_PIN_GROUP(eth_rmii),SH_PFC_PIN_GROUP(hscif0_data),SH_PFC_PIN_GROUP(hscif0_clk),SH_PFC_PIN_GROUP(hscif0_ctrl),SH_PFC_PIN_GROUP(hscif0_data_b),SH_PFC_PIN_GROUP(hscif0_ctrl_b),SH_PFC_PIN_GROUP(hscif0_data_c),SH_PFC_PIN_GROUP(hscif0_ctrl_c),SH_PFC_PIN_GROUP(hscif0_data_d),SH_PFC_PIN_GROUP(hscif0_ctrl_d),SH_PFC_PIN_GROUP(hscif0_data_e),SH_PFC_PIN_GROUP(hscif0_ctrl_e),SH_PFC_PIN_GROUP(hscif0_data_f),SH_PFC_PIN_GROUP(hscif0_ctrl_f),SH_PFC_PIN_GROUP(hscif1_data),SH_PFC_PIN_GROUP(hscif1_clk),SH_PFC_PIN_GROUP(hscif1_ctrl),SH_PFC_PIN_GROUP(hscif1_data_b),SH_PFC_PIN_GROUP(hscif1_clk_b),SH_PFC_PIN_GROUP(hscif1_ctrl_b),SH_PFC_PIN_GROUP(i2c0),SH_PFC_PIN_GROUP(i2c1),SH_PFC_PIN_GROUP(i2c1_b),SH_PFC_PIN_GROUP(i2c1_c),SH_PFC_PIN_GROUP(i2c2),SH_PFC_PIN_GROUP(i2c2_b),SH_PFC_PIN_GROUP(i2c2_c),SH_PFC_PIN_GROUP(i2c2_d),SH_PFC_PIN_GROUP(i2c2_e),SH_PFC_PIN_GROUP(i2c3),SH_PFC_PIN_GROUP(iic0),SH_PFC_PIN_GROUP(iic1),SH_PFC_PIN_GROUP(iic1_b),SH_PFC_PIN_GROUP(iic1_c),SH_PFC_PIN_GROUP(iic2),SH_PFC_PIN_GROUP(iic2_b),SH_PFC_PIN_GROUP(iic2_c),SH_PFC_PIN_GROUP(iic2_d),SH_PFC_PIN_GROUP(iic2_e),SH_PFC_PIN_GROUP(iic3),SH_PFC_PIN_GROUP(intc_irq0),SH_PFC_PIN_GROUP(intc_irq1),SH_PFC_PIN_GROUP(intc_irq2),SH_PFC_PIN_GROUP(intc_irq3),SH_PFC_PIN_GROUP(mlb_3pin),SH_PFC_PIN_GROUP(mmc0_data1),SH_PFC_PIN_GROUP(mmc0_data4),SH_PFC_PIN_GROUP(mmc0_data8),SH_PFC_PIN_GROUP(mmc0_ctrl),SH_PFC_PIN_GROUP(mmc1_data1),SH_PFC_PIN_GROUP(mmc1_data4),SH_PFC_PIN_GROUP(mmc1_data8),SH_PFC_PIN_GROUP(mmc1_ctrl),SH_PFC_PIN_GROUP(msiof0_clk),SH_PFC_PIN_GROUP(msiof0_sync),SH_PFC_PIN_GROUP(msiof0_ss1),SH_PFC_PIN_GROUP(msiof0_ss2),SH_PFC_PIN_GROUP(msiof0_rx),SH_PFC_PIN_GROUP(msiof0_tx),SH_PFC_PIN_GROUP(msiof0_clk_b),SH_PFC_PIN_GROUP(msiof0_ss1_b),SH_PFC_PIN_GROUP(msiof0_ss2_b),SH_PFC_PIN_GROUP(msiof0_rx_b),SH_PFC_PIN_GROUP(msiof0_tx_b),SH_PFC_PIN_GROUP(msiof1_clk),SH_PFC_PIN_GROUP(msiof1_sync),SH_PFC_PIN_GROUP(msiof1_ss1),SH_PFC_PIN_GROUP(msiof1_ss2),SH_PFC_PIN_GROUP(msiof1_rx),SH_PFC_PIN_GROUP(msiof1_tx),SH_PFC_PIN_GROUP(msiof1_clk_b),SH_PFC_PIN_GROUP(msiof1_ss1_b),SH_PFC_PIN_GROUP(msiof1_ss2_b),SH_PFC_PIN_GROUP(msiof1_rx_b),SH_PFC_PIN_GROUP(msiof1_tx_b),SH_PFC_PIN_GROUP(msiof2_clk),SH_PFC_PIN_GROUP(msiof2_sync),SH_PFC_PIN_GROUP(msiof2_ss1),SH_PFC_PIN_GROUP(msiof2_ss2),SH_PFC_PIN_GROUP(msiof2_rx),SH_PFC_PIN_GROUP(msiof2_tx),SH_PFC_PIN_GROUP(msiof3_clk),SH_PFC_PIN_GROUP(msiof3_sync),SH_PFC_PIN_GROUP(msiof3_ss1),SH_PFC_PIN_GROUP(msiof3_ss2),SH_PFC_PIN_GROUP(msiof3_rx),SH_PFC_PIN_GROUP(msiof3_tx),SH_PFC_PIN_GROUP(msiof3_clk_b),SH_PFC_PIN_GROUP(msiof3_sync_b),SH_PFC_PIN_GROUP(msiof3_rx_b),SH_PFC_PIN_GROUP(msiof3_tx_b),SH_PFC_PIN_GROUP(pwm0),SH_PFC_PIN_GROUP(pwm0_b),SH_PFC_PIN_GROUP(pwm1),SH_PFC_PIN_GROUP(pwm1_b),SH_PFC_PIN_GROUP(pwm2),SH_PFC_PIN_GROUP(pwm3),SH_PFC_PIN_GROUP(pwm4),SH_PFC_PIN_GROUP(pwm5),SH_PFC_PIN_GROUP(pwm6),SH_PFC_PIN_GROUP(qspi_ctrl),SH_PFC_PIN_GROUP(qspi_data2),SH_PFC_PIN_GROUP(qspi_data4),SH_PFC_PIN_GROUP(scif0_data),SH_PFC_PIN_GROUP(scif0_clk),SH_PFC_PIN_GROUP(scif0_ctrl),SH_PFC_PIN_GROUP(scif0_data_b),SH_PFC_PIN_GROUP(scif1_data),SH_PFC_PIN_GROUP(scif1_clk),SH_PFC_PIN_GROUP(scif1_ctrl),SH_PFC_PIN_GROUP(scif1_data_b),SH_PFC_PIN_GROUP(scif1_data_c),SH_PFC_PIN_GROUP(scif1_data_d),SH_PFC_PIN_GROUP(scif1_clk_d),SH_PFC_PIN_GROUP(scif1_data_e),SH_PFC_PIN_GROUP(scif1_clk_e),SH_PFC_PIN_GROUP(scif2_data),SH_PFC_PIN_GROUP(scif2_clk),SH_PFC_PIN_GROUP(scif2_data_b),SH_PFC_PIN_GROUP(scifa0_data),SH_PFC_PIN_GROUP(scifa0_clk),SH_PFC_PIN_GROUP(scifa0_ctrl),SH_PFC_PIN_GROUP(scifa0_data_b),SH_PFC_PIN_GROUP(scifa0_clk_b),SH_PFC_PIN_GROUP(scifa0_ctrl_b),SH_PFC_PIN_GROUP(scifa1_data),SH_PFC_PIN_GROUP(scifa1_clk),SH_PFC_PIN_GROUP(scifa1_ctrl),SH_PFC_PIN_GROUP(scifa1_data_b),SH_PFC_PIN_GROUP(scifa1_clk_b),SH_PFC_PIN_GROUP(scifa1_ctrl_b),SH_PFC_PIN_GROUP(scifa1_data_c),SH_PFC_PIN_GROUP(scifa1_clk_c),SH_PFC_PIN_GROUP(scifa1_ctrl_c),SH_PFC_PIN_GROUP(scifa1_data_d),SH_PFC_PIN_GROUP(scifa1_clk_d),SH_PFC_PIN_GROUP(scifa1_ctrl_d),SH_PFC_PIN_GROUP(scifa2_data),SH_PFC_PIN_GROUP(scifa2_clk),SH_PFC_PIN_GROUP(scifa2_ctrl),SH_PFC_PIN_GROUP(scifa2_data_b),SH_PFC_PIN_GROUP(scifa2_data_c),SH_PFC_PIN_GROUP(scifa2_clk_c),SH_PFC_PIN_GROUP(scifb0_data),SH_PFC_PIN_GROUP(scifb0_clk),SH_PFC_PIN_GROUP(scifb0_ctrl),SH_PFC_PIN_GROUP(scifb0_data_b),SH_PFC_PIN_GROUP(scifb0_clk_b),SH_PFC_PIN_GROUP(scifb0_ctrl_b),SH_PFC_PIN_GROUP(scifb0_data_c),SH_PFC_PIN_GROUP(scifb1_data),SH_PFC_PIN_GROUP(scifb1_clk),SH_PFC_PIN_GROUP(scifb1_ctrl),SH_PFC_PIN_GROUP(scifb1_data_b),SH_PFC_PIN_GROUP(scifb1_clk_b),SH_PFC_PIN_GROUP(scifb1_ctrl_b),SH_PFC_PIN_GROUP(scifb1_data_c),SH_PFC_PIN_GROUP(scifb1_data_d),SH_PFC_PIN_GROUP(scifb1_data_e),SH_PFC_PIN_GROUP(scifb1_clk_e),SH_PFC_PIN_GROUP(scifb1_data_f),SH_PFC_PIN_GROUP(scifb1_data_g),SH_PFC_PIN_GROUP(scifb1_clk_g),SH_PFC_PIN_GROUP(scifb2_data),SH_PFC_PIN_GROUP(scifb2_clk),SH_PFC_PIN_GROUP(scifb2_ctrl),SH_PFC_PIN_GROUP(scifb2_data_b),SH_PFC_PIN_GROUP(scifb2_clk_b),SH_PFC_PIN_GROUP(scifb2_ctrl_b),SH_PFC_PIN_GROUP(scifb2_data_c),SH_PFC_PIN_GROUP(scif_clk),SH_PFC_PIN_GROUP(scif_clk_b),SH_PFC_PIN_GROUP(sdhi0_data1),SH_PFC_PIN_GROUP(sdhi0_data4),SH_PFC_PIN_GROUP(sdhi0_ctrl),SH_PFC_PIN_GROUP(sdhi0_cd),SH_PFC_PIN_GROUP(sdhi0_wp),SH_PFC_PIN_GROUP(sdhi1_data1),SH_PFC_PIN_GROUP(sdhi1_data4),SH_PFC_PIN_GROUP(sdhi1_ctrl),SH_PFC_PIN_GROUP(sdhi1_cd),SH_PFC_PIN_GROUP(sdhi1_wp),SH_PFC_PIN_GROUP(sdhi2_data1),SH_PFC_PIN_GROUP(sdhi2_data4),SH_PFC_PIN_GROUP(sdhi2_ctrl),SH_PFC_PIN_GROUP(sdhi2_cd),SH_PFC_PIN_GROUP(sdhi2_wp),SH_PFC_PIN_GROUP(sdhi3_data1),SH_PFC_PIN_GROUP(sdhi3_data4),SH_PFC_PIN_GROUP(sdhi3_ctrl),SH_PFC_PIN_GROUP(sdhi3_cd),SH_PFC_PIN_GROUP(sdhi3_wp),SH_PFC_PIN_GROUP(ssi0_data),SH_PFC_PIN_GROUP(ssi0129_ctrl),SH_PFC_PIN_GROUP(ssi1_data),SH_PFC_PIN_GROUP(ssi1_ctrl),SH_PFC_PIN_GROUP(ssi2_data),SH_PFC_PIN_GROUP(ssi2_ctrl),SH_PFC_PIN_GROUP(ssi3_data),SH_PFC_PIN_GROUP(ssi34_ctrl),SH_PFC_PIN_GROUP(ssi4_data),SH_PFC_PIN_GROUP(ssi4_ctrl),SH_PFC_PIN_GROUP(ssi5),SH_PFC_PIN_GROUP(ssi5_b),SH_PFC_PIN_GROUP(ssi5_c),SH_PFC_PIN_GROUP(ssi6),SH_PFC_PIN_GROUP(ssi6_b),SH_PFC_PIN_GROUP(ssi7_data),SH_PFC_PIN_GROUP(ssi7_b_data),SH_PFC_PIN_GROUP(ssi7_c_data),SH_PFC_PIN_GROUP(ssi78_ctrl),SH_PFC_PIN_GROUP(ssi78_b_ctrl),SH_PFC_PIN_GROUP(ssi78_c_ctrl),SH_PFC_PIN_GROUP(ssi8_data),SH_PFC_PIN_GROUP(ssi8_b_data),SH_PFC_PIN_GROUP(ssi8_c_data),SH_PFC_PIN_GROUP(ssi9_data),SH_PFC_PIN_GROUP(ssi9_ctrl),SH_PFC_PIN_GROUP(tpu0_to0),SH_PFC_PIN_GROUP(tpu0_to1),SH_PFC_PIN_GROUP(tpu0_to2),SH_PFC_PIN_GROUP(tpu0_to3),SH_PFC_PIN_GROUP(usb0),SH_PFC_PIN_GROUP(usb0_ovc_vbus),SH_PFC_PIN_GROUP(usb1),SH_PFC_PIN_GROUP(usb2),VIN_DATA_PIN_GROUP(vin0_data, 24),VIN_DATA_PIN_GROUP(vin0_data, 20),SH_PFC_PIN_GROUP(vin0_data18),VIN_DATA_PIN_GROUP(vin0_data, 16),VIN_DATA_PIN_GROUP(vin0_data, 12),VIN_DATA_PIN_GROUP(vin0_data, 10),VIN_DATA_PIN_GROUP(vin0_data, 8),VIN_DATA_PIN_GROUP(vin0_data, 4),SH_PFC_PIN_GROUP(vin0_sync),SH_PFC_PIN_GROUP(vin0_field),SH_PFC_PIN_GROUP(vin0_clkenb),SH_PFC_PIN_GROUP(vin0_clk),VIN_DATA_PIN_GROUP(vin1_data, 24),VIN_DATA_PIN_GROUP(vin1_data, 20),SH_PFC_PIN_GROUP(vin1_data18),VIN_DATA_PIN_GROUP(vin1_data, 16),VIN_DATA_PIN_GROUP(vin1_data, 12),VIN_DATA_PIN_GROUP(vin1_data, 10),VIN_DATA_PIN_GROUP(vin1_data, 8),VIN_DATA_PIN_GROUP(vin1_data, 4),SH_PFC_PIN_GROUP(vin1_sync),SH_PFC_PIN_GROUP(vin1_field),SH_PFC_PIN_GROUP(vin1_clkenb),SH_PFC_PIN_GROUP(vin1_clk),VIN_DATA_PIN_GROUP(vin2_data, 24),SH_PFC_PIN_GROUP(vin2_data18),VIN_DATA_PIN_GROUP(vin2_data, 16),VIN_DATA_PIN_GROUP(vin2_data, 8),VIN_DATA_PIN_GROUP(vin2_data, 4),SH_PFC_PIN_GROUP(vin2_sync),SH_PFC_PIN_GROUP(vin2_field),SH_PFC_PIN_GROUP(vin2_clkenb),SH_PFC_PIN_GROUP(vin2_clk),SH_PFC_PIN_GROUP(vin3_data8),SH_PFC_PIN_GROUP(vin3_sync),SH_PFC_PIN_GROUP(vin3_field),SH_PFC_PIN_GROUP(vin3_clkenb),SH_PFC_PIN_GROUP(vin3_clk),+static const struct {
struct sh_pfc_pin_group common[311];+#ifdef CONFIG_PINCTRL_PFC_R8A7790
struct sh_pfc_pin_group automotive[1];+#endif +} pinmux_groups = {
.common = {SH_PFC_PIN_GROUP(audio_clk_a),SH_PFC_PIN_GROUP(audio_clk_b),SH_PFC_PIN_GROUP(audio_clk_c),SH_PFC_PIN_GROUP(audio_clkout),SH_PFC_PIN_GROUP(audio_clkout_b),SH_PFC_PIN_GROUP(audio_clkout_c),SH_PFC_PIN_GROUP(audio_clkout_d),SH_PFC_PIN_GROUP(avb_link),SH_PFC_PIN_GROUP(avb_magic),SH_PFC_PIN_GROUP(avb_phy_int),SH_PFC_PIN_GROUP(avb_mdio),SH_PFC_PIN_GROUP(avb_mii),SH_PFC_PIN_GROUP(avb_gmii),SH_PFC_PIN_GROUP(can0_data),SH_PFC_PIN_GROUP(can0_data_b),SH_PFC_PIN_GROUP(can0_data_c),SH_PFC_PIN_GROUP(can0_data_d),SH_PFC_PIN_GROUP(can1_data),SH_PFC_PIN_GROUP(can1_data_b),SH_PFC_PIN_GROUP(can_clk),SH_PFC_PIN_GROUP(can_clk_b),SH_PFC_PIN_GROUP(du_rgb666),SH_PFC_PIN_GROUP(du_rgb888),SH_PFC_PIN_GROUP(du_clk_out_0),SH_PFC_PIN_GROUP(du_clk_out_1),SH_PFC_PIN_GROUP(du_sync_0),SH_PFC_PIN_GROUP(du_sync_1),SH_PFC_PIN_GROUP(du_cde),SH_PFC_PIN_GROUP(du0_clk_in),SH_PFC_PIN_GROUP(du1_clk_in),SH_PFC_PIN_GROUP(du2_clk_in),SH_PFC_PIN_GROUP(eth_link),SH_PFC_PIN_GROUP(eth_magic),SH_PFC_PIN_GROUP(eth_mdio),SH_PFC_PIN_GROUP(eth_rmii),SH_PFC_PIN_GROUP(hscif0_data),SH_PFC_PIN_GROUP(hscif0_clk),SH_PFC_PIN_GROUP(hscif0_ctrl),SH_PFC_PIN_GROUP(hscif0_data_b),SH_PFC_PIN_GROUP(hscif0_ctrl_b),SH_PFC_PIN_GROUP(hscif0_data_c),SH_PFC_PIN_GROUP(hscif0_ctrl_c),SH_PFC_PIN_GROUP(hscif0_data_d),SH_PFC_PIN_GROUP(hscif0_ctrl_d),SH_PFC_PIN_GROUP(hscif0_data_e),SH_PFC_PIN_GROUP(hscif0_ctrl_e),SH_PFC_PIN_GROUP(hscif0_data_f),SH_PFC_PIN_GROUP(hscif0_ctrl_f),SH_PFC_PIN_GROUP(hscif1_data),SH_PFC_PIN_GROUP(hscif1_clk),SH_PFC_PIN_GROUP(hscif1_ctrl),SH_PFC_PIN_GROUP(hscif1_data_b),SH_PFC_PIN_GROUP(hscif1_clk_b),SH_PFC_PIN_GROUP(hscif1_ctrl_b),SH_PFC_PIN_GROUP(i2c0),SH_PFC_PIN_GROUP(i2c1),SH_PFC_PIN_GROUP(i2c1_b),SH_PFC_PIN_GROUP(i2c1_c),SH_PFC_PIN_GROUP(i2c2),SH_PFC_PIN_GROUP(i2c2_b),SH_PFC_PIN_GROUP(i2c2_c),SH_PFC_PIN_GROUP(i2c2_d),SH_PFC_PIN_GROUP(i2c2_e),SH_PFC_PIN_GROUP(i2c3),SH_PFC_PIN_GROUP(iic0),SH_PFC_PIN_GROUP(iic1),SH_PFC_PIN_GROUP(iic1_b),SH_PFC_PIN_GROUP(iic1_c),SH_PFC_PIN_GROUP(iic2),SH_PFC_PIN_GROUP(iic2_b),SH_PFC_PIN_GROUP(iic2_c),SH_PFC_PIN_GROUP(iic2_d),SH_PFC_PIN_GROUP(iic2_e),SH_PFC_PIN_GROUP(iic3),SH_PFC_PIN_GROUP(intc_irq0),SH_PFC_PIN_GROUP(intc_irq1),SH_PFC_PIN_GROUP(intc_irq2),SH_PFC_PIN_GROUP(intc_irq3),SH_PFC_PIN_GROUP(mmc0_data1),SH_PFC_PIN_GROUP(mmc0_data4),SH_PFC_PIN_GROUP(mmc0_data8),SH_PFC_PIN_GROUP(mmc0_ctrl),SH_PFC_PIN_GROUP(mmc1_data1),SH_PFC_PIN_GROUP(mmc1_data4),SH_PFC_PIN_GROUP(mmc1_data8),SH_PFC_PIN_GROUP(mmc1_ctrl),SH_PFC_PIN_GROUP(msiof0_clk),SH_PFC_PIN_GROUP(msiof0_sync),SH_PFC_PIN_GROUP(msiof0_ss1),SH_PFC_PIN_GROUP(msiof0_ss2),SH_PFC_PIN_GROUP(msiof0_rx),SH_PFC_PIN_GROUP(msiof0_tx),SH_PFC_PIN_GROUP(msiof0_clk_b),SH_PFC_PIN_GROUP(msiof0_ss1_b),SH_PFC_PIN_GROUP(msiof0_ss2_b),SH_PFC_PIN_GROUP(msiof0_rx_b),SH_PFC_PIN_GROUP(msiof0_tx_b),SH_PFC_PIN_GROUP(msiof1_clk),SH_PFC_PIN_GROUP(msiof1_sync),SH_PFC_PIN_GROUP(msiof1_ss1),SH_PFC_PIN_GROUP(msiof1_ss2),SH_PFC_PIN_GROUP(msiof1_rx),SH_PFC_PIN_GROUP(msiof1_tx),SH_PFC_PIN_GROUP(msiof1_clk_b),SH_PFC_PIN_GROUP(msiof1_ss1_b),SH_PFC_PIN_GROUP(msiof1_ss2_b),SH_PFC_PIN_GROUP(msiof1_rx_b),SH_PFC_PIN_GROUP(msiof1_tx_b),SH_PFC_PIN_GROUP(msiof2_clk),SH_PFC_PIN_GROUP(msiof2_sync),SH_PFC_PIN_GROUP(msiof2_ss1),SH_PFC_PIN_GROUP(msiof2_ss2),SH_PFC_PIN_GROUP(msiof2_rx),SH_PFC_PIN_GROUP(msiof2_tx),SH_PFC_PIN_GROUP(msiof3_clk),SH_PFC_PIN_GROUP(msiof3_sync),SH_PFC_PIN_GROUP(msiof3_ss1),SH_PFC_PIN_GROUP(msiof3_ss2),SH_PFC_PIN_GROUP(msiof3_rx),SH_PFC_PIN_GROUP(msiof3_tx),SH_PFC_PIN_GROUP(msiof3_clk_b),SH_PFC_PIN_GROUP(msiof3_sync_b),SH_PFC_PIN_GROUP(msiof3_rx_b),SH_PFC_PIN_GROUP(msiof3_tx_b),SH_PFC_PIN_GROUP(pwm0),SH_PFC_PIN_GROUP(pwm0_b),SH_PFC_PIN_GROUP(pwm1),SH_PFC_PIN_GROUP(pwm1_b),SH_PFC_PIN_GROUP(pwm2),SH_PFC_PIN_GROUP(pwm3),SH_PFC_PIN_GROUP(pwm4),SH_PFC_PIN_GROUP(pwm5),SH_PFC_PIN_GROUP(pwm6),SH_PFC_PIN_GROUP(qspi_ctrl),SH_PFC_PIN_GROUP(qspi_data2),SH_PFC_PIN_GROUP(qspi_data4),SH_PFC_PIN_GROUP(scif0_data),SH_PFC_PIN_GROUP(scif0_clk),SH_PFC_PIN_GROUP(scif0_ctrl),SH_PFC_PIN_GROUP(scif0_data_b),SH_PFC_PIN_GROUP(scif1_data),SH_PFC_PIN_GROUP(scif1_clk),SH_PFC_PIN_GROUP(scif1_ctrl),SH_PFC_PIN_GROUP(scif1_data_b),SH_PFC_PIN_GROUP(scif1_data_c),SH_PFC_PIN_GROUP(scif1_data_d),SH_PFC_PIN_GROUP(scif1_clk_d),SH_PFC_PIN_GROUP(scif1_data_e),SH_PFC_PIN_GROUP(scif1_clk_e),SH_PFC_PIN_GROUP(scif2_data),SH_PFC_PIN_GROUP(scif2_clk),SH_PFC_PIN_GROUP(scif2_data_b),SH_PFC_PIN_GROUP(scifa0_data),SH_PFC_PIN_GROUP(scifa0_clk),SH_PFC_PIN_GROUP(scifa0_ctrl),SH_PFC_PIN_GROUP(scifa0_data_b),SH_PFC_PIN_GROUP(scifa0_clk_b),SH_PFC_PIN_GROUP(scifa0_ctrl_b),SH_PFC_PIN_GROUP(scifa1_data),SH_PFC_PIN_GROUP(scifa1_clk),SH_PFC_PIN_GROUP(scifa1_ctrl),SH_PFC_PIN_GROUP(scifa1_data_b),SH_PFC_PIN_GROUP(scifa1_clk_b),SH_PFC_PIN_GROUP(scifa1_ctrl_b),SH_PFC_PIN_GROUP(scifa1_data_c),SH_PFC_PIN_GROUP(scifa1_clk_c),SH_PFC_PIN_GROUP(scifa1_ctrl_c),SH_PFC_PIN_GROUP(scifa1_data_d),SH_PFC_PIN_GROUP(scifa1_clk_d),SH_PFC_PIN_GROUP(scifa1_ctrl_d),SH_PFC_PIN_GROUP(scifa2_data),SH_PFC_PIN_GROUP(scifa2_clk),SH_PFC_PIN_GROUP(scifa2_ctrl),SH_PFC_PIN_GROUP(scifa2_data_b),SH_PFC_PIN_GROUP(scifa2_data_c),SH_PFC_PIN_GROUP(scifa2_clk_c),SH_PFC_PIN_GROUP(scifb0_data),SH_PFC_PIN_GROUP(scifb0_clk),SH_PFC_PIN_GROUP(scifb0_ctrl),SH_PFC_PIN_GROUP(scifb0_data_b),SH_PFC_PIN_GROUP(scifb0_clk_b),SH_PFC_PIN_GROUP(scifb0_ctrl_b),SH_PFC_PIN_GROUP(scifb0_data_c),SH_PFC_PIN_GROUP(scifb1_data),SH_PFC_PIN_GROUP(scifb1_clk),SH_PFC_PIN_GROUP(scifb1_ctrl),SH_PFC_PIN_GROUP(scifb1_data_b),SH_PFC_PIN_GROUP(scifb1_clk_b),SH_PFC_PIN_GROUP(scifb1_ctrl_b),SH_PFC_PIN_GROUP(scifb1_data_c),SH_PFC_PIN_GROUP(scifb1_data_d),SH_PFC_PIN_GROUP(scifb1_data_e),SH_PFC_PIN_GROUP(scifb1_clk_e),SH_PFC_PIN_GROUP(scifb1_data_f),SH_PFC_PIN_GROUP(scifb1_data_g),SH_PFC_PIN_GROUP(scifb1_clk_g),SH_PFC_PIN_GROUP(scifb2_data),SH_PFC_PIN_GROUP(scifb2_clk),SH_PFC_PIN_GROUP(scifb2_ctrl),SH_PFC_PIN_GROUP(scifb2_data_b),SH_PFC_PIN_GROUP(scifb2_clk_b),SH_PFC_PIN_GROUP(scifb2_ctrl_b),SH_PFC_PIN_GROUP(scifb2_data_c),SH_PFC_PIN_GROUP(scif_clk),SH_PFC_PIN_GROUP(scif_clk_b),SH_PFC_PIN_GROUP(sdhi0_data1),SH_PFC_PIN_GROUP(sdhi0_data4),SH_PFC_PIN_GROUP(sdhi0_ctrl),SH_PFC_PIN_GROUP(sdhi0_cd),SH_PFC_PIN_GROUP(sdhi0_wp),SH_PFC_PIN_GROUP(sdhi1_data1),SH_PFC_PIN_GROUP(sdhi1_data4),SH_PFC_PIN_GROUP(sdhi1_ctrl),SH_PFC_PIN_GROUP(sdhi1_cd),SH_PFC_PIN_GROUP(sdhi1_wp),SH_PFC_PIN_GROUP(sdhi2_data1),SH_PFC_PIN_GROUP(sdhi2_data4),SH_PFC_PIN_GROUP(sdhi2_ctrl),SH_PFC_PIN_GROUP(sdhi2_cd),SH_PFC_PIN_GROUP(sdhi2_wp),SH_PFC_PIN_GROUP(sdhi3_data1),SH_PFC_PIN_GROUP(sdhi3_data4),SH_PFC_PIN_GROUP(sdhi3_ctrl),SH_PFC_PIN_GROUP(sdhi3_cd),SH_PFC_PIN_GROUP(sdhi3_wp),SH_PFC_PIN_GROUP(ssi0_data),SH_PFC_PIN_GROUP(ssi0129_ctrl),SH_PFC_PIN_GROUP(ssi1_data),SH_PFC_PIN_GROUP(ssi1_ctrl),SH_PFC_PIN_GROUP(ssi2_data),SH_PFC_PIN_GROUP(ssi2_ctrl),SH_PFC_PIN_GROUP(ssi3_data),SH_PFC_PIN_GROUP(ssi34_ctrl),SH_PFC_PIN_GROUP(ssi4_data),SH_PFC_PIN_GROUP(ssi4_ctrl),SH_PFC_PIN_GROUP(ssi5),SH_PFC_PIN_GROUP(ssi5_b),SH_PFC_PIN_GROUP(ssi5_c),SH_PFC_PIN_GROUP(ssi6),SH_PFC_PIN_GROUP(ssi6_b),SH_PFC_PIN_GROUP(ssi7_data),SH_PFC_PIN_GROUP(ssi7_b_data),SH_PFC_PIN_GROUP(ssi7_c_data),SH_PFC_PIN_GROUP(ssi78_ctrl),SH_PFC_PIN_GROUP(ssi78_b_ctrl),SH_PFC_PIN_GROUP(ssi78_c_ctrl),SH_PFC_PIN_GROUP(ssi8_data),SH_PFC_PIN_GROUP(ssi8_b_data),SH_PFC_PIN_GROUP(ssi8_c_data),SH_PFC_PIN_GROUP(ssi9_data),SH_PFC_PIN_GROUP(ssi9_ctrl),SH_PFC_PIN_GROUP(tpu0_to0),SH_PFC_PIN_GROUP(tpu0_to1),SH_PFC_PIN_GROUP(tpu0_to2),SH_PFC_PIN_GROUP(tpu0_to3),SH_PFC_PIN_GROUP(usb0),SH_PFC_PIN_GROUP(usb0_ovc_vbus),SH_PFC_PIN_GROUP(usb1),SH_PFC_PIN_GROUP(usb1_pwen),SH_PFC_PIN_GROUP(usb2),VIN_DATA_PIN_GROUP(vin0_data, 24),VIN_DATA_PIN_GROUP(vin0_data, 20),SH_PFC_PIN_GROUP(vin0_data18),VIN_DATA_PIN_GROUP(vin0_data, 16),VIN_DATA_PIN_GROUP(vin0_data, 12),VIN_DATA_PIN_GROUP(vin0_data, 10),VIN_DATA_PIN_GROUP(vin0_data, 8),VIN_DATA_PIN_GROUP(vin0_data, 4),SH_PFC_PIN_GROUP(vin0_sync),SH_PFC_PIN_GROUP(vin0_field),SH_PFC_PIN_GROUP(vin0_clkenb),SH_PFC_PIN_GROUP(vin0_clk),VIN_DATA_PIN_GROUP(vin1_data, 24),VIN_DATA_PIN_GROUP(vin1_data, 20),SH_PFC_PIN_GROUP(vin1_data18),VIN_DATA_PIN_GROUP(vin1_data, 16),VIN_DATA_PIN_GROUP(vin1_data, 12),VIN_DATA_PIN_GROUP(vin1_data, 10),VIN_DATA_PIN_GROUP(vin1_data, 8),VIN_DATA_PIN_GROUP(vin1_data, 4),VIN_DATA_PIN_GROUP(vin1_data, 24, _b),VIN_DATA_PIN_GROUP(vin1_data, 20, _b),SH_PFC_PIN_GROUP(vin1_data18_b),VIN_DATA_PIN_GROUP(vin1_data, 16, _b),VIN_DATA_PIN_GROUP(vin1_data, 12, _b),VIN_DATA_PIN_GROUP(vin1_data, 10, _b),VIN_DATA_PIN_GROUP(vin1_data, 8, _b),VIN_DATA_PIN_GROUP(vin1_data, 4, _b),SH_PFC_PIN_GROUP(vin1_sync),SH_PFC_PIN_GROUP(vin1_sync_b),SH_PFC_PIN_GROUP(vin1_field),SH_PFC_PIN_GROUP(vin1_field_b),SH_PFC_PIN_GROUP(vin1_clkenb),SH_PFC_PIN_GROUP(vin1_clkenb_b),SH_PFC_PIN_GROUP(vin1_clk),SH_PFC_PIN_GROUP(vin1_clk_b),VIN_DATA_PIN_GROUP(vin2_data, 24),SH_PFC_PIN_GROUP(vin2_data18),VIN_DATA_PIN_GROUP(vin2_data, 16),VIN_DATA_PIN_GROUP(vin2_data, 8),VIN_DATA_PIN_GROUP(vin2_data, 4),SH_PFC_PIN_GROUP(vin2_g8),SH_PFC_PIN_GROUP(vin2_sync),SH_PFC_PIN_GROUP(vin2_field),SH_PFC_PIN_GROUP(vin2_clkenb),SH_PFC_PIN_GROUP(vin2_clk),SH_PFC_PIN_GROUP(vin3_data8),SH_PFC_PIN_GROUP(vin3_sync),SH_PFC_PIN_GROUP(vin3_field),SH_PFC_PIN_GROUP(vin3_clkenb),SH_PFC_PIN_GROUP(vin3_clk),},+#ifdef CONFIG_PINCTRL_PFC_R8A7790
.automotive = {SH_PFC_PIN_GROUP(mlb_3pin),}+#endif /* CONFIG_PINCTRL_PFC_R8A7790 */ };
static const char * const audio_clk_groups[] = { @@ -4246,6 +4478,23 @@ static const char * const avb_groups[] = { "avb_gmii", };
+static const char * const can0_groups[] = {
"can0_data","can0_data_b","can0_data_c","can0_data_d",+};
+static const char * const can1_groups[] = {
"can1_data","can1_data_b",+};
+static const char * const can_clk_groups[] = {
"can_clk","can_clk_b",+};
static const char * const du_groups[] = { "du_rgb666", "du_rgb888", @@ -4351,9 +4600,11 @@ static const char * const intc_groups[] = { "intc_irq3", };
+#ifdef CONFIG_PINCTRL_PFC_R8A7790 static const char * const mlb_groups[] = { "mlb_3pin", }; +#endif /* CONFIG_PINCTRL_PFC_R8A7790 */
static const char * const mmc0_groups[] = { "mmc0_data1", @@ -4629,6 +4880,7 @@ static const char * const usb0_groups[] = {
static const char * const usb1_groups[] = { "usb1",
"usb1_pwen",};
static const char * const usb2_groups[] = { @@ -4659,10 +4911,22 @@ static const char * const vin1_groups[] = { "vin1_data10", "vin1_data8", "vin1_data4",
"vin1_data24_b","vin1_data20_b","vin1_data18_b","vin1_data16_b","vin1_data12_b","vin1_data10_b","vin1_data8_b","vin1_data4_b", "vin1_sync","vin1_sync_b", "vin1_field","vin1_field_b", "vin1_clkenb","vin1_clkenb_b", "vin1_clk","vin1_clk_b",};
static const char * const vin2_groups[] = { @@ -4671,6 +4935,7 @@ static const char * const vin2_groups[] = { "vin2_data16", "vin2_data8", "vin2_data4",
"vin2_g8", "vin2_sync", "vin2_field", "vin2_clkenb",@@ -4685,63 +4950,77 @@ static const char * const vin3_groups[] = { "vin3_clk", };
-static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(audio_clk),SH_PFC_FUNCTION(avb),SH_PFC_FUNCTION(du),SH_PFC_FUNCTION(du0),SH_PFC_FUNCTION(du1),SH_PFC_FUNCTION(du2),SH_PFC_FUNCTION(eth),SH_PFC_FUNCTION(hscif0),SH_PFC_FUNCTION(hscif1),SH_PFC_FUNCTION(i2c0),SH_PFC_FUNCTION(i2c1),SH_PFC_FUNCTION(i2c2),SH_PFC_FUNCTION(i2c3),SH_PFC_FUNCTION(iic0),SH_PFC_FUNCTION(iic1),SH_PFC_FUNCTION(iic2),SH_PFC_FUNCTION(iic3),SH_PFC_FUNCTION(intc),SH_PFC_FUNCTION(mlb),SH_PFC_FUNCTION(mmc0),SH_PFC_FUNCTION(mmc1),SH_PFC_FUNCTION(msiof0),SH_PFC_FUNCTION(msiof1),SH_PFC_FUNCTION(msiof2),SH_PFC_FUNCTION(msiof3),SH_PFC_FUNCTION(pwm0),SH_PFC_FUNCTION(pwm1),SH_PFC_FUNCTION(pwm2),SH_PFC_FUNCTION(pwm3),SH_PFC_FUNCTION(pwm4),SH_PFC_FUNCTION(pwm5),SH_PFC_FUNCTION(pwm6),SH_PFC_FUNCTION(qspi),SH_PFC_FUNCTION(scif0),SH_PFC_FUNCTION(scif1),SH_PFC_FUNCTION(scif2),SH_PFC_FUNCTION(scifa0),SH_PFC_FUNCTION(scifa1),SH_PFC_FUNCTION(scifa2),SH_PFC_FUNCTION(scifb0),SH_PFC_FUNCTION(scifb1),SH_PFC_FUNCTION(scifb2),SH_PFC_FUNCTION(scif_clk),SH_PFC_FUNCTION(sdhi0),SH_PFC_FUNCTION(sdhi1),SH_PFC_FUNCTION(sdhi2),SH_PFC_FUNCTION(sdhi3),SH_PFC_FUNCTION(ssi),SH_PFC_FUNCTION(tpu0),SH_PFC_FUNCTION(usb0),SH_PFC_FUNCTION(usb1),SH_PFC_FUNCTION(usb2),SH_PFC_FUNCTION(vin0),SH_PFC_FUNCTION(vin1),SH_PFC_FUNCTION(vin2),SH_PFC_FUNCTION(vin3),+static const struct {
struct sh_pfc_function common[58];+#ifdef CONFIG_PINCTRL_PFC_R8A7790
struct sh_pfc_function automotive[1];+#endif +} pinmux_functions = {
.common = {SH_PFC_FUNCTION(audio_clk),SH_PFC_FUNCTION(avb),SH_PFC_FUNCTION(du),SH_PFC_FUNCTION(can0),SH_PFC_FUNCTION(can1),SH_PFC_FUNCTION(can_clk),SH_PFC_FUNCTION(du0),SH_PFC_FUNCTION(du1),SH_PFC_FUNCTION(du2),SH_PFC_FUNCTION(eth),SH_PFC_FUNCTION(hscif0),SH_PFC_FUNCTION(hscif1),SH_PFC_FUNCTION(i2c0),SH_PFC_FUNCTION(i2c1),SH_PFC_FUNCTION(i2c2),SH_PFC_FUNCTION(i2c3),SH_PFC_FUNCTION(iic0),SH_PFC_FUNCTION(iic1),SH_PFC_FUNCTION(iic2),SH_PFC_FUNCTION(iic3),SH_PFC_FUNCTION(intc),SH_PFC_FUNCTION(mmc0),SH_PFC_FUNCTION(mmc1),SH_PFC_FUNCTION(msiof0),SH_PFC_FUNCTION(msiof1),SH_PFC_FUNCTION(msiof2),SH_PFC_FUNCTION(msiof3),SH_PFC_FUNCTION(pwm0),SH_PFC_FUNCTION(pwm1),SH_PFC_FUNCTION(pwm2),SH_PFC_FUNCTION(pwm3),SH_PFC_FUNCTION(pwm4),SH_PFC_FUNCTION(pwm5),SH_PFC_FUNCTION(pwm6),SH_PFC_FUNCTION(qspi),SH_PFC_FUNCTION(scif0),SH_PFC_FUNCTION(scif1),SH_PFC_FUNCTION(scif2),SH_PFC_FUNCTION(scifa0),SH_PFC_FUNCTION(scifa1),SH_PFC_FUNCTION(scifa2),SH_PFC_FUNCTION(scifb0),SH_PFC_FUNCTION(scifb1),SH_PFC_FUNCTION(scifb2),SH_PFC_FUNCTION(scif_clk),SH_PFC_FUNCTION(sdhi0),SH_PFC_FUNCTION(sdhi1),SH_PFC_FUNCTION(sdhi2),SH_PFC_FUNCTION(sdhi3),SH_PFC_FUNCTION(ssi),SH_PFC_FUNCTION(tpu0),SH_PFC_FUNCTION(usb0),SH_PFC_FUNCTION(usb1),SH_PFC_FUNCTION(usb2),SH_PFC_FUNCTION(vin0),SH_PFC_FUNCTION(vin1),SH_PFC_FUNCTION(vin2),SH_PFC_FUNCTION(vin3),},+#ifdef CONFIG_PINCTRL_PFC_R8A7790
.automotive = {SH_PFC_FUNCTION(mlb),}+#endif /* CONFIG_PINCTRL_PFC_R8A7790 */ };
static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -5728,6 +6007,7 @@ static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = { .pin_to_pocctrl = r8a7790_pin_to_pocctrl, };
+#ifdef CONFIG_PINCTRL_PFC_R8A7790 const struct sh_pfc_soc_info r8a7790_pinmux_info = { .name = "r8a77900_pfc", .ops = &r8a7790_pinmux_ops, @@ -5737,13 +6017,16 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = {
.pins = pinmux_pins, .nr_pins = ARRAY_SIZE(pinmux_pins),
.groups = pinmux_groups,.nr_groups = ARRAY_SIZE(pinmux_groups),.functions = pinmux_functions,.nr_functions = ARRAY_SIZE(pinmux_functions),
.groups = pinmux_groups.common,.nr_groups = ARRAY_SIZE(pinmux_groups.common) +ARRAY_SIZE(pinmux_groups.automotive),.functions = pinmux_functions.common,.nr_functions = ARRAY_SIZE(pinmux_functions.common) +ARRAY_SIZE(pinmux_functions.automotive), .cfg_regs = pinmux_config_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data),}; +#endif diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c index d6095d6f67..7c8db5dc2c 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7791.c +++ b/drivers/pinctrl/renesas/pfc-r8a7791.c @@ -18,7 +18,7 @@
- Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
- which case they support both 3.3V and 1.8V signalling.
*/ -#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ PORT_GP_26(1, fn, sfx), \ PORT_GP_32(2, fn, sfx), \ @@ -1703,6 +1703,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), };
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) /* - ADI -------------------------------------------------------------------- */ static const unsigned int adi_common_pins[] = { /* ADIDATA, ADICS/SAMP, ADICLK */ @@ -1768,6 +1769,7 @@ static const unsigned int adi_chsel2_b_mux[] = { /* ADICHS B 2 */ ADICHS2_B_MARK, }; +#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
/* - Audio Clock ------------------------------------------------------------ */ static const unsigned int audio_clk_a_pins[] = { @@ -2556,6 +2558,8 @@ static const unsigned int intc_irq3_pins[] = { static const unsigned int intc_irq3_mux[] = { IRQ3_MARK, };
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) /* - MLB+ ------------------------------------------------------------------- */ static const unsigned int mlb_3pin_pins[] = { RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), @@ -2563,6 +2567,8 @@ static const unsigned int mlb_3pin_pins[] = { static const unsigned int mlb_3pin_mux[] = { MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, }; +#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
/* - MMCIF ------------------------------------------------------------------ */ static const unsigned int mmc_data1_pins[] = { /* D[0] */ @@ -4455,7 +4461,9 @@ static const unsigned int vin2_clk_mux[] = {
static const struct { struct sh_pfc_pin_group common[346]; +#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) struct sh_pfc_pin_group automotive[9]; +#endif } pinmux_groups = { .common = { SH_PFC_PIN_GROUP(audio_clk_a), @@ -4805,6 +4813,7 @@ static const struct { SH_PFC_PIN_GROUP(vin2_clkenb), SH_PFC_PIN_GROUP(vin2_clk), }, +#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) .automotive = { SH_PFC_PIN_GROUP(adi_common), SH_PFC_PIN_GROUP(adi_chsel0), @@ -4816,8 +4825,10 @@ static const struct { SH_PFC_PIN_GROUP(adi_chsel2_b), SH_PFC_PIN_GROUP(mlb_3pin), } +#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ };
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) static const char * const adi_groups[] = { "adi_common", "adi_chsel0", @@ -4828,6 +4839,7 @@ static const char * const adi_groups[] = { "adi_chsel1_b", "adi_chsel2_b", }; +#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
static const char * const audio_clk_groups[] = { "audio_clk_a", @@ -5005,9 +5017,11 @@ static const char * const intc_groups[] = { "intc_irq3", };
+#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) static const char * const mlb_groups[] = { "mlb_3pin", }; +#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
static const char * const mmc_groups[] = { "mmc_data1", @@ -5362,7 +5376,9 @@ static const char * const vin2_groups[] = {
static const struct { struct sh_pfc_function common[58]; +#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) struct sh_pfc_function automotive[2]; +#endif } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk), @@ -5424,10 +5440,12 @@ static const struct { SH_PFC_FUNCTION(vin1), SH_PFC_FUNCTION(vin2), }, +#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) .automotive = { SH_PFC_FUNCTION(adi), SH_PFC_FUNCTION(mlb), } +#endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ };
static const struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c b/drivers/pinctrl/renesas/pfc-r8a7792.c index 1c90412093..054c02a4ae 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7792.c +++ b/drivers/pinctrl/renesas/pfc-r8a7792.c @@ -14,7 +14,7 @@
#include "sh_pfc.h"
-#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_29(0, fn, sfx), \ PORT_GP_23(1, fn, sfx), \ PORT_GP_32(2, fn, sfx), \ diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c index 91ac815f3d..9495603f7c 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7794.c +++ b/drivers/pinctrl/renesas/pfc-r8a7794.c @@ -15,7 +15,7 @@
#include "sh_pfc.h"
-#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ PORT_GP_26(1, fn, sfx), \ PORT_GP_32(2, fn, sfx), \ diff --git a/drivers/pinctrl/renesas/pfc-r8a7795.c b/drivers/pinctrl/renesas/pfc-r8a7795.c index 898f837950..015a50f1de 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7795.c +++ b/drivers/pinctrl/renesas/pfc-r8a7795.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /*
- R8A7795 ES2.0+ processor support - PFC hardware block.
*/
- R8A77951 processor support - PFC hardware block.
- Copyright (C) 2015-2019 Renesas Electronics Corporation
@@ -13,11 +13,9 @@
#include "sh_pfc.h"
-#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
SH_PFC_PIN_CFG_PULL_UP | \SH_PFC_PIN_CFG_PULL_DOWN)+#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
-#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ @@ -30,6 +28,52 @@ PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
+#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)/*
- F_() : just information
- FM() : macro for FN_xxx / xxx_MARK
@@ -1509,68 +1553,16 @@ static const u16 pinmux_data[] = { };
/*
- R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
- Physical layout rows: A - AW, cols: 1 - 39.
*/
- Pins not associated with a GPIO port.
-#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) -#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) -#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) -#define PIN_NONE U16_MAX +enum {
GP_ASSIGN_LAST(),NOGP_ALL(),+};
static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(),
/** Pins not associated with a GPIO port.** The pin positions are different between different r8a7795* packages, all that is needed for the pfc driver is a unique* number for each pin. To this end use the pin layout from* R-Car H3SiP to calculate a unique number for each pin.*/SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
PINMUX_NOGP_ALL(),};
/* - AUDIO CLOCK ------------------------------------------------------------ */ @@ -1718,7 +1710,7 @@ static const unsigned int avb_phy_int_mux[] = { }; static const unsigned int avb_mdio_pins[] = { /* AVB_MDC, AVB_MDIO */
RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,}; static const unsigned int avb_mdio_mux[] = { AVB_MDC_MARK, AVB_MDIO_MARK, @@ -1731,12 +1723,11 @@ static const unsigned int avb_mii_pins[] = { * AVB_RD1, AVB_RD2, AVB_RD3, * AVB_TXCREFCLK */
PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),PIN_NUMBER('A', 12),
PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,PIN_AVB_TXCREFCLK,}; static const unsigned int avb_mii_mux[] = { AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, @@ -3261,6 +3252,57 @@ static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, };
+/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = {
/* QSPI0_SPCLK, QSPI0_SSL */PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,+}; +static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,+}; +static const unsigned int qspi0_data2_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,+}; +static const unsigned int qspi0_data2_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,+}; +static const unsigned int qspi0_data4_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,/* QSPI0_IO2, QSPI0_IO3 */PIN_QSPI0_IO2, PIN_QSPI0_IO3,+}; +static const unsigned int qspi0_data4_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,QSPI0_IO2_MARK, QSPI0_IO3_MARK,+}; +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = {
/* QSPI1_SPCLK, QSPI1_SSL */PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,+}; +static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,+}; +static const unsigned int qspi1_data2_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,+}; +static const unsigned int qspi1_data2_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,+}; +static const unsigned int qspi1_data4_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,/* QSPI1_IO2, QSPI1_IO3 */PIN_QSPI1_IO2, PIN_QSPI1_IO3,+}; +static const unsigned int qspi1_data4_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,QSPI1_IO2_MARK, QSPI1_IO3_MARK,+};
/* - SATA --------------------------------------------------------------------*/ static const unsigned int sata0_devslp_a_pins[] = { /* DEVSLP */ @@ -4169,7 +4211,7 @@ static const unsigned int vin5_clk_mux[] = { };
static const struct {
struct sh_pfc_pin_group common[320];
struct sh_pfc_pin_group common[326];#ifdef CONFIG_PINCTRL_PFC_R8A7795 struct sh_pfc_pin_group automotive[30]; #endif @@ -4374,6 +4416,12 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b),
SH_PFC_PIN_GROUP(qspi0_ctrl),SH_PFC_PIN_GROUP(qspi0_data2),SH_PFC_PIN_GROUP(qspi0_data4),SH_PFC_PIN_GROUP(qspi1_ctrl),SH_PFC_PIN_GROUP(qspi1_data2),SH_PFC_PIN_GROUP(qspi1_data4), SH_PFC_PIN_GROUP(sata0_devslp_a), SH_PFC_PIN_GROUP(sata0_devslp_b), SH_PFC_PIN_GROUP(scif0_data),@@ -4868,6 +4916,18 @@ static const char * const pwm6_groups[] = { "pwm6_b", };
+static const char * const qspi0_groups[] = {
"qspi0_ctrl","qspi0_data2","qspi0_data4",+};
+static const char * const qspi1_groups[] = {
"qspi1_ctrl","qspi1_data2","qspi1_data4",+};
static const char * const sata0_groups[] = { "sata0_devslp_a", "sata0_devslp_b", @@ -5056,7 +5116,7 @@ static const char * const vin5_groups[] = { };
static const struct {
struct sh_pfc_function common[53];
struct sh_pfc_function common[55];#ifdef CONFIG_PINCTRL_PFC_R8A7795 struct sh_pfc_function automotive[4]; #endif @@ -5093,6 +5153,8 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6),
SH_PFC_FUNCTION(qspi0),SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(sata0), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1),@@ -5692,44 +5754,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
static const struct pinmux_drive_reg pinmux_drive_regs[] = { { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
{ PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */{ PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */{ PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */{ PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */{ PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */{ PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */{ PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */{ PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
{ PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */{ PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */{ PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */{ PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */{ PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */{ PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */{ PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */{ PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
{ PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */{ PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */{ PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */{ PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */{ PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */{ PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */{ PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */{ PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
{ PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */{ PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */{ PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */{ PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */{ PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */{ PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */{ PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */{ PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ } }, { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
{ PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */{ PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */{ PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */{ PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */{ PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */{ PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */{ PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */{ PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
{ PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */{ PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */{ PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */{ PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */{ PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */{ PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */{ PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */{ PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
{ PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */{ PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */{ PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */{ PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */{ PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
{ PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */{ PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */{ PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */{ PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */{ PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ } }, { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */@@ -5783,7 +5845,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { } }, { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
{ PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
{ PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */@@ -5802,30 +5864,32 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ } }, { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */{ PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */{ PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ } }, { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
{ PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */{ PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */{ PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */{ PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */+#ifdef CONFIG_PINCTRL_PFC_R8A7795
{ PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */+#endif
{ PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */{ PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */{ PIN_TMS, 4, 2 }, /* TMS */ } }, { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
{ PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */{ PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
{ PIN_TDO, 28, 2 }, /* TDO */{ PIN_ASEBRK, 24, 2 }, /* ASEBRK */{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ } }, { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */@@ -5894,7 +5958,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
{ PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
{ PIN_MLB_REF, 4, 3 }, /* MLB_REF */ { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ } }, { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {@@ -5933,8 +5997,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
{ RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */{ RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */
{ RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */{ RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */ } }, { },}; @@ -5950,7 +6014,8 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, };
-static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +static int r8a77951_pin_to_pocctrl(struct sh_pfc *pfc,
unsigned int pin, u32 *pocctrl){ int bit = -EINVAL;
@@ -5967,35 +6032,35 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
static const struct pinmux_bias_reg pinmux_bias_regs[] = { { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
[ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */[ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */[ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */[ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */[ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */[ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */[ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */[ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */[ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */[ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */[10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */[11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */[12] = PIN_NUMBER('Y', 7), /* RPC_INT# */[13] = PIN_NUMBER('V', 6), /* RPC_WP# */[14] = PIN_NUMBER('V', 7), /* RPC_RESET# */[15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */[16] = PIN_NUMBER('B', 19), /* AVB_RXC */[17] = PIN_NUMBER('A', 13), /* AVB_RD0 */[18] = PIN_NUMBER('B', 13), /* AVB_RD1 */[19] = PIN_NUMBER('A', 14), /* AVB_RD2 */[20] = PIN_NUMBER('B', 14), /* AVB_RD3 */[21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */[22] = PIN_NUMBER('A', 19), /* AVB_TXC */[23] = PIN_NUMBER('A', 18), /* AVB_TD0 */[24] = PIN_NUMBER('B', 18), /* AVB_TD1 */[25] = PIN_NUMBER('A', 17), /* AVB_TD2 */[26] = PIN_NUMBER('B', 17), /* AVB_TD3 */[27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */[28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
[ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */[ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */[ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */[ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */[ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */[ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */[ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */[ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */[ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */[ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */[10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */[11] = PIN_QSPI1_SSL, /* QSPI1_SSL */[12] = PIN_RPC_INT_N, /* RPC_INT# */[13] = PIN_RPC_WP_N, /* RPC_WP# */[14] = PIN_RPC_RESET_N, /* RPC_RESET# */[15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */[16] = PIN_AVB_RXC, /* AVB_RXC */[17] = PIN_AVB_RD0, /* AVB_RD0 */[18] = PIN_AVB_RD1, /* AVB_RD1 */[19] = PIN_AVB_RD2, /* AVB_RD2 */[20] = PIN_AVB_RD3, /* AVB_RD3 */[21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */[22] = PIN_AVB_TXC, /* AVB_TXC */[23] = PIN_AVB_TD0, /* AVB_TD0 */[24] = PIN_AVB_TD1, /* AVB_TD1 */[25] = PIN_AVB_TD2, /* AVB_TD2 */[26] = PIN_AVB_TD3, /* AVB_TD3 */[27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */[28] = PIN_AVB_MDIO, /* AVB_MDIO */ [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */@@ -6044,7 +6109,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
[ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
[ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ [10] = RCAR_GP_PIN(0, 0), /* D0 */ [11] = RCAR_GP_PIN(0, 1), /* D1 */ [12] = RCAR_GP_PIN(0, 2), /* D2 */@@ -6065,20 +6130,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
[30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */[31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ } }, { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
[ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */[ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */[ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */[ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/[ 4] = PIN_A_NUMBER('R', 26), /* TRST# */[ 5] = PIN_A_NUMBER('T', 27), /* TCK */[ 6] = PIN_A_NUMBER('R', 30), /* TMS */[ 7] = PIN_A_NUMBER('R', 29), /* TDI */[ 8] = PIN_NONE,[ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
[ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */[ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */[ 2] = PIN_FSCLKST_N, /* FSCLKST# */[ 3] = PIN_EXTALR, /* EXTALR*/[ 4] = PIN_TRST_N, /* TRST# */[ 5] = PIN_TCK, /* TCK */[ 6] = PIN_TMS, /* TMS */[ 7] = PIN_TDI, /* TDI */[ 8] = SH_PFC_PIN_NONE,[ 9] = PIN_ASEBRK, /* ASEBRK */ [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */@@ -6143,7 +6208,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
[ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
[ 6] = PIN_MLB_REF, /* MLB_REF */ [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */@@ -6178,31 +6243,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */ [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
[ 7] = PIN_NONE,[ 8] = PIN_NONE,[ 9] = PIN_NONE,[10] = PIN_NONE,[11] = PIN_NONE,[12] = PIN_NONE,[13] = PIN_NONE,[14] = PIN_NONE,[15] = PIN_NONE,[16] = PIN_NONE,[17] = PIN_NONE,[18] = PIN_NONE,[19] = PIN_NONE,[20] = PIN_NONE,[21] = PIN_NONE,[22] = PIN_NONE,[23] = PIN_NONE,[24] = PIN_NONE,[25] = PIN_NONE,[26] = PIN_NONE,[27] = PIN_NONE,[28] = PIN_NONE,[29] = PIN_NONE,[30] = PIN_NONE,[31] = PIN_NONE,
[ 7] = SH_PFC_PIN_NONE,[ 8] = SH_PFC_PIN_NONE,[ 9] = SH_PFC_PIN_NONE,[10] = SH_PFC_PIN_NONE,[11] = SH_PFC_PIN_NONE,[12] = SH_PFC_PIN_NONE,[13] = SH_PFC_PIN_NONE,[14] = SH_PFC_PIN_NONE,[15] = SH_PFC_PIN_NONE,[16] = SH_PFC_PIN_NONE,[17] = SH_PFC_PIN_NONE,[18] = SH_PFC_PIN_NONE,[19] = SH_PFC_PIN_NONE,[20] = SH_PFC_PIN_NONE,[21] = SH_PFC_PIN_NONE,[22] = SH_PFC_PIN_NONE,[23] = SH_PFC_PIN_NONE,[24] = SH_PFC_PIN_NONE,[25] = SH_PFC_PIN_NONE,[26] = SH_PFC_PIN_NONE,[27] = SH_PFC_PIN_NONE,[28] = SH_PFC_PIN_NONE,[29] = SH_PFC_PIN_NONE,[30] = SH_PFC_PIN_NONE,[31] = SH_PFC_PIN_NONE, } }, { /* sentinel */ },}; @@ -6248,8 +6313,8 @@ static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, sh_pfc_write(pfc, reg->puen, enable); }
-static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
.pin_to_pocctrl = r8a7795_pin_to_pocctrl,+static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = {
.pin_to_pocctrl = r8a77951_pin_to_pocctrl, .get_bias = r8a7795_pinmux_get_bias, .set_bias = r8a7795_pinmux_set_bias,}; @@ -6257,7 +6322,7 @@ static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = { #ifdef CONFIG_PINCTRL_PFC_R8A774E1 const struct sh_pfc_soc_info r8a774e1_pinmux_info = { .name = "r8a774e1_pfc",
.ops = &r8a7795_pinmux_ops,
.ops = &r8a77951_pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },@@ -6282,7 +6347,7 @@ const struct sh_pfc_soc_info r8a774e1_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A7795 const struct sh_pfc_soc_info r8a7795_pinmux_info = { .name = "r8a77951_pfc",
.ops = &r8a7795_pinmux_ops,
.ops = &r8a77951_pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index da7901ea6e..06cae74fb5 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -1,10 +1,10 @@ // SPDX-License-Identifier: GPL-2.0 /*
- R8A7796 processor support - PFC hardware block.
- R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
- Copyright (C) 2016-2019 Renesas Electronics Corp.
- This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
- This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
- R-Car Gen3 processor support - PFC hardware block.
@@ -19,11 +19,9 @@
#include "sh_pfc.h"
-#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
SH_PFC_PIN_CFG_PULL_UP | \SH_PFC_PIN_CFG_PULL_DOWN)+#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
-#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ @@ -36,6 +34,51 @@ PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
+#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)/*
- F_() : just information
- FM() : macro for FN_xxx / xxx_MARK
@@ -688,7 +731,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),@@ -1514,67 +1557,16 @@ static const u16 pinmux_data[] = { };
/*
- R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
- Physical layout rows: A - AW, cols: 1 - 39.
*/
- Pins not associated with a GPIO port.
-#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) -#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) -#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) -#define PIN_NONE U16_MAX +enum {
GP_ASSIGN_LAST(),NOGP_ALL(),+};
static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(),
/** Pins not associated with a GPIO port.** The pin positions are different between different r8a7796* packages, all that is needed for the pfc driver is a unique* number for each pin. To this end use the pin layout from* R-Car M3SiP to calculate a unique number for each pin.*/SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
PINMUX_NOGP_ALL(),};
/* - AUDIO CLOCK ------------------------------------------------------------ */ @@ -1723,7 +1715,7 @@ static const unsigned int avb_phy_int_mux[] = { }; static const unsigned int avb_mdio_pins[] = { /* AVB_MDC, AVB_MDIO */
RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,}; static const unsigned int avb_mdio_mux[] = { AVB_MDC_MARK, AVB_MDIO_MARK, @@ -1736,12 +1728,11 @@ static const unsigned int avb_mii_pins[] = { * AVB_RD1, AVB_RD2, AVB_RD3, * AVB_TXCREFCLK */
PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),PIN_NUMBER('A', 12),
PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,PIN_AVB_TXCREFCLK,}; static const unsigned int avb_mii_mux[] = { AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, @@ -3267,6 +3258,57 @@ static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, };
+/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = {
/* QSPI0_SPCLK, QSPI0_SSL */PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,+}; +static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,+}; +static const unsigned int qspi0_data2_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,+}; +static const unsigned int qspi0_data2_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,+}; +static const unsigned int qspi0_data4_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,/* QSPI0_IO2, QSPI0_IO3 */PIN_QSPI0_IO2, PIN_QSPI0_IO3,+}; +static const unsigned int qspi0_data4_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,QSPI0_IO2_MARK, QSPI0_IO3_MARK,+}; +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = {
/* QSPI1_SPCLK, QSPI1_SSL */PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,+}; +static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,+}; +static const unsigned int qspi1_data2_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,+}; +static const unsigned int qspi1_data2_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,+}; +static const unsigned int qspi1_data4_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,/* QSPI1_IO2, QSPI1_IO3 */PIN_QSPI1_IO2, PIN_QSPI1_IO3,+}; +static const unsigned int qspi1_data4_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,QSPI1_IO2_MARK, QSPI1_IO3_MARK,+};
/* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -3895,6 +3937,36 @@ static const unsigned int tmu_tclk2_b_mux[] = { TCLK2_B_MARK, };
+/* - TPU ------------------------------------------------------------------- */ +static const unsigned int tpu_to0_pins[] = {
/* TPU0TO0 */RCAR_GP_PIN(6, 28),+}; +static const unsigned int tpu_to0_mux[] = {
TPU0TO0_MARK,+}; +static const unsigned int tpu_to1_pins[] = {
/* TPU0TO1 */RCAR_GP_PIN(6, 29),+}; +static const unsigned int tpu_to1_mux[] = {
TPU0TO1_MARK,+}; +static const unsigned int tpu_to2_pins[] = {
/* TPU0TO2 */RCAR_GP_PIN(6, 30),+}; +static const unsigned int tpu_to2_mux[] = {
TPU0TO2_MARK,+}; +static const unsigned int tpu_to3_pins[] = {
/* TPU0TO3 */RCAR_GP_PIN(6, 31),+}; +static const unsigned int tpu_to3_mux[] = {
TPU0TO3_MARK,+};
/* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { /* PWEN, OVC */ @@ -4114,7 +4186,7 @@ static const unsigned int vin5_clk_mux[] = { };
static const struct {
struct sh_pfc_pin_group common[312];
struct sh_pfc_pin_group common[322];#if defined(CONFIG_PINCTRL_PFC_R8A7796) struct sh_pfc_pin_group automotive[30]; #endif @@ -4319,6 +4391,12 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b),
SH_PFC_PIN_GROUP(qspi0_ctrl),SH_PFC_PIN_GROUP(qspi0_data2),SH_PFC_PIN_GROUP(qspi0_data4),SH_PFC_PIN_GROUP(qspi1_ctrl),SH_PFC_PIN_GROUP(qspi1_data2),SH_PFC_PIN_GROUP(qspi1_data4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl),@@ -4403,6 +4481,10 @@ static const struct { SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), SH_PFC_PIN_GROUP(tmu_tclk2_b),
SH_PFC_PIN_GROUP(tpu_to0),SH_PFC_PIN_GROUP(tpu_to1),SH_PFC_PIN_GROUP(tpu_to2),SH_PFC_PIN_GROUP(tpu_to3), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb30),@@ -4805,6 +4887,18 @@ static const char * const pwm6_groups[] = { "pwm6_b", };
+static const char * const qspi0_groups[] = {
"qspi0_ctrl","qspi0_data2","qspi0_data4",+};
+static const char * const qspi1_groups[] = {
"qspi1_ctrl","qspi1_data2","qspi1_data4",+};
static const char * const scif0_groups[] = { "scif0_data", "scif0_clk", @@ -4928,6 +5022,13 @@ static const char * const tmu_groups[] = { "tmu_tclk2_b", };
+static const char * const tpu_groups[] = {
"tpu_to0","tpu_to1","tpu_to2","tpu_to3",+};
static const char * const usb0_groups[] = { "usb0", }; @@ -4973,7 +5074,7 @@ static const char * const vin5_groups[] = { };
static const struct {
struct sh_pfc_function common[49];
struct sh_pfc_function common[52];#if defined(CONFIG_PINCTRL_PFC_R8A7796) struct sh_pfc_function automotive[4]; #endif @@ -5010,6 +5111,8 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6),
SH_PFC_FUNCTION(qspi0),SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2),@@ -5023,6 +5126,7 @@ static const struct { SH_PFC_FUNCTION(sdhi3), SH_PFC_FUNCTION(ssi), SH_PFC_FUNCTION(tmu),
SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb30),@@ -5604,44 +5708,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
static const struct pinmux_drive_reg pinmux_drive_regs[] = { { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
{ PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */{ PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */{ PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */{ PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */{ PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */{ PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */{ PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */{ PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
{ PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */{ PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */{ PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */{ PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */{ PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */{ PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */{ PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */{ PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
{ PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */{ PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */{ PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */{ PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */{ PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */{ PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */{ PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */{ PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
{ PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */{ PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */{ PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */{ PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */{ PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */{ PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */{ PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */{ PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ } }, { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
{ PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */{ PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */{ PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */{ PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */{ PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */{ PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */{ PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */{ PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
{ PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */{ PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */{ PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */{ PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */{ PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */{ PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */{ PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */{ PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
{ PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */{ PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */{ PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */{ PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */{ PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
{ PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */{ PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */{ PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */{ PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */{ PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ } }, { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */@@ -5695,7 +5799,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { } }, { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
{ PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
{ PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */@@ -5714,29 +5818,29 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ } }, { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */{ PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */{ PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ } }, { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
{ PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN2 */{ PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */{ PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
{ PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */{ PIN_FSCLKST, 20, 2 }, /* FSCLKST */{ PIN_TMS, 4, 2 }, /* TMS */ } }, { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
{ PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */{ PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
{ PIN_TDO, 28, 2 }, /* TDO */{ PIN_ASEBRK, 24, 2 }, /* ASEBRK */{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ } }, { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */@@ -5805,7 +5909,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
{ PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
{ PIN_MLB_REF, 4, 3 }, /* MLB_REF */ { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ } }, { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {@@ -5878,35 +5982,35 @@ static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
static const struct pinmux_bias_reg pinmux_bias_regs[] = { { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
[ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */[ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */[ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */[ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */[ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */[ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */[ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */[ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */[ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */[ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */[10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */[11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */[12] = PIN_NUMBER('Y', 7), /* RPC_INT# */[13] = PIN_NUMBER('V', 6), /* RPC_WP# */[14] = PIN_NUMBER('V', 7), /* RPC_RESET# */[15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */[16] = PIN_NUMBER('B', 19), /* AVB_RXC */[17] = PIN_NUMBER('A', 13), /* AVB_RD0 */[18] = PIN_NUMBER('B', 13), /* AVB_RD1 */[19] = PIN_NUMBER('A', 14), /* AVB_RD2 */[20] = PIN_NUMBER('B', 14), /* AVB_RD3 */[21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */[22] = PIN_NUMBER('A', 19), /* AVB_TXC */[23] = PIN_NUMBER('A', 18), /* AVB_TD0 */[24] = PIN_NUMBER('B', 18), /* AVB_TD1 */[25] = PIN_NUMBER('A', 17), /* AVB_TD2 */[26] = PIN_NUMBER('B', 17), /* AVB_TD3 */[27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */[28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
[ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */[ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */[ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */[ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */[ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */[ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */[ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */[ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */[ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */[ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */[10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */[11] = PIN_QSPI1_SSL, /* QSPI1_SSL */[12] = PIN_RPC_INT_N, /* RPC_INT# */[13] = PIN_RPC_WP_N, /* RPC_WP# */[14] = PIN_RPC_RESET_N, /* RPC_RESET# */[15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */[16] = PIN_AVB_RXC, /* AVB_RXC */[17] = PIN_AVB_RD0, /* AVB_RD0 */[18] = PIN_AVB_RD1, /* AVB_RD1 */[19] = PIN_AVB_RD2, /* AVB_RD2 */[20] = PIN_AVB_RD3, /* AVB_RD3 */[21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */[22] = PIN_AVB_TXC, /* AVB_TXC */[23] = PIN_AVB_TD0, /* AVB_TD0 */[24] = PIN_AVB_TD1, /* AVB_TD1 */[25] = PIN_AVB_TD2, /* AVB_TD2 */[26] = PIN_AVB_TD3, /* AVB_TD3 */[27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */[28] = PIN_AVB_MDIO, /* AVB_MDIO */ [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */@@ -5955,7 +6059,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
[ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
[ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ [10] = RCAR_GP_PIN(0, 0), /* D0 */ [11] = RCAR_GP_PIN(0, 1), /* D1 */ [12] = RCAR_GP_PIN(0, 2), /* D2 */@@ -5976,20 +6080,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
[30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */[31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ } }, { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
[ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */[ 1] = PIN_NONE,[ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */[ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/[ 4] = PIN_A_NUMBER('R', 26), /* TRST# */[ 5] = PIN_A_NUMBER('T', 27), /* TCK */[ 6] = PIN_A_NUMBER('R', 30), /* TMS */[ 7] = PIN_A_NUMBER('R', 29), /* TDI */[ 8] = PIN_NONE,[ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
[ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */[ 1] = SH_PFC_PIN_NONE,[ 2] = PIN_FSCLKST, /* FSCLKST */[ 3] = PIN_EXTALR, /* EXTALR*/[ 4] = PIN_TRST_N, /* TRST# */[ 5] = PIN_TCK, /* TCK */[ 6] = PIN_TMS, /* TMS */[ 7] = PIN_TDI, /* TDI */[ 8] = SH_PFC_PIN_NONE,[ 9] = PIN_ASEBRK, /* ASEBRK */ [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */@@ -6054,7 +6158,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
[ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
[ 6] = PIN_MLB_REF, /* MLB_REF */ [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */@@ -6089,31 +6193,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */ [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
[ 7] = PIN_NONE,[ 8] = PIN_NONE,[ 9] = PIN_NONE,[10] = PIN_NONE,[11] = PIN_NONE,[12] = PIN_NONE,[13] = PIN_NONE,[14] = PIN_NONE,[15] = PIN_NONE,[16] = PIN_NONE,[17] = PIN_NONE,[18] = PIN_NONE,[19] = PIN_NONE,[20] = PIN_NONE,[21] = PIN_NONE,[22] = PIN_NONE,[23] = PIN_NONE,[24] = PIN_NONE,[25] = PIN_NONE,[26] = PIN_NONE,[27] = PIN_NONE,[28] = PIN_NONE,[29] = PIN_NONE,[30] = PIN_NONE,[31] = PIN_NONE,
[ 7] = SH_PFC_PIN_NONE,[ 8] = SH_PFC_PIN_NONE,[ 9] = SH_PFC_PIN_NONE,[10] = SH_PFC_PIN_NONE,[11] = SH_PFC_PIN_NONE,[12] = SH_PFC_PIN_NONE,[13] = SH_PFC_PIN_NONE,[14] = SH_PFC_PIN_NONE,[15] = SH_PFC_PIN_NONE,[16] = SH_PFC_PIN_NONE,[17] = SH_PFC_PIN_NONE,[18] = SH_PFC_PIN_NONE,[19] = SH_PFC_PIN_NONE,[20] = SH_PFC_PIN_NONE,[21] = SH_PFC_PIN_NONE,[22] = SH_PFC_PIN_NONE,[23] = SH_PFC_PIN_NONE,[24] = SH_PFC_PIN_NONE,[25] = SH_PFC_PIN_NONE,[26] = SH_PFC_PIN_NONE,[27] = SH_PFC_PIN_NONE,[28] = SH_PFC_PIN_NONE,[29] = SH_PFC_PIN_NONE,[30] = SH_PFC_PIN_NONE,[31] = SH_PFC_PIN_NONE, } }, { /* sentinel */ },}; diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c index d143750c2d..fae29d535c 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -5,7 +5,7 @@
- Copyright (C) 2018 Jacopo Mondi jacopo+renesas@jmondi.org
- Copyright (C) 2016-2019 Renesas Electronics Corp.
- This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
- This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
- R-Car Gen3 processor support - PFC hardware block.
@@ -20,11 +20,9 @@
#include "sh_pfc.h"
-#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
SH_PFC_PIN_CFG_PULL_UP | \SH_PFC_PIN_CFG_PULL_DOWN)+#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
-#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ @@ -37,6 +35,51 @@ PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
+#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)/*
- F_() : just information
- FM() : macro for FN_xxx / xxx_MARK
@@ -1519,67 +1562,16 @@ static const u16 pinmux_data[] = { };
/*
- R8A77965 has 8 banks with 32 GPIOs in each => 256 GPIOs.
- Physical layout rows: A - AW, cols: 1 - 39.
*/
- Pins not associated with a GPIO port.
-#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) -#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) -#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) -#define PIN_NONE U16_MAX +enum {
GP_ASSIGN_LAST(),NOGP_ALL(),+};
static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(),
/** Pins not associated with a GPIO port.** The pin positions are different between different r8a77965* packages, all that is needed for the pfc driver is a unique* number for each pin. To this end use the pin layout from* R-Car M3SiP to calculate a unique number for each pin.*/SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
PINMUX_NOGP_ALL(),};
/* - AUDIO CLOCK ------------------------------------------------------------ */ @@ -1728,7 +1720,7 @@ static const unsigned int avb_phy_int_mux[] = { }; static const unsigned int avb_mdio_pins[] = { /* AVB_MDC, AVB_MDIO */
RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,}; static const unsigned int avb_mdio_mux[] = { AVB_MDC_MARK, AVB_MDIO_MARK, @@ -1741,12 +1733,11 @@ static const unsigned int avb_mii_pins[] = { * AVB_RD1, AVB_RD2, AVB_RD3, * AVB_TXCREFCLK */
PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),PIN_NUMBER('A', 12),
PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,PIN_AVB_TXCREFCLK,}; static const unsigned int avb_mii_mux[] = { AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, @@ -3418,6 +3409,57 @@ static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, };
+/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = {
/* QSPI0_SPCLK, QSPI0_SSL */PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,+}; +static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,+}; +static const unsigned int qspi0_data2_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,+}; +static const unsigned int qspi0_data2_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,+}; +static const unsigned int qspi0_data4_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,/* QSPI0_IO2, QSPI0_IO3 */PIN_QSPI0_IO2, PIN_QSPI0_IO3,+}; +static const unsigned int qspi0_data4_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,QSPI0_IO2_MARK, QSPI0_IO3_MARK,+}; +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = {
/* QSPI1_SPCLK, QSPI1_SSL */PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,+}; +static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,+}; +static const unsigned int qspi1_data2_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,+}; +static const unsigned int qspi1_data2_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,+}; +static const unsigned int qspi1_data4_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,/* QSPI1_IO2, QSPI1_IO3 */PIN_QSPI1_IO2, PIN_QSPI1_IO3,+}; +static const unsigned int qspi1_data4_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,QSPI1_IO2_MARK, QSPI1_IO3_MARK,+};
/* - SATA --------------------------------------------------------------------*/ static const unsigned int sata0_devslp_a_pins[] = { /* DEVSLP */ @@ -4391,7 +4433,7 @@ static const unsigned int vin5_clk_mux[] = { };
static const struct {
struct sh_pfc_pin_group common[318];
struct sh_pfc_pin_group common[324];#ifdef CONFIG_PINCTRL_PFC_R8A77965 struct sh_pfc_pin_group automotive[30]; #endif @@ -4596,6 +4638,12 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b),
SH_PFC_PIN_GROUP(qspi0_ctrl),SH_PFC_PIN_GROUP(qspi0_data2),SH_PFC_PIN_GROUP(qspi0_data4),SH_PFC_PIN_GROUP(qspi1_ctrl),SH_PFC_PIN_GROUP(qspi1_data2),SH_PFC_PIN_GROUP(qspi1_data4), SH_PFC_PIN_GROUP(sata0_devslp_a), SH_PFC_PIN_GROUP(sata0_devslp_b), SH_PFC_PIN_GROUP(scif0_data),@@ -5088,6 +5136,18 @@ static const char * const pwm6_groups[] = { "pwm6_b", };
+static const char * const qspi0_groups[] = {
"qspi0_ctrl","qspi0_data2","qspi0_data4",+};
+static const char * const qspi1_groups[] = {
"qspi1_ctrl","qspi1_data2","qspi1_data4",+};
static const char * const sata0_groups[] = { "sata0_devslp_a", "sata0_devslp_b", @@ -5267,7 +5327,7 @@ static const char * const vin5_groups[] = { };
static const struct {
struct sh_pfc_function common[51];
struct sh_pfc_function common[53];#ifdef CONFIG_PINCTRL_PFC_R8A77965 struct sh_pfc_function automotive[4]; #endif @@ -5304,6 +5364,8 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6),
SH_PFC_FUNCTION(qspi0),SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(sata0), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1),@@ -5900,44 +5962,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
static const struct pinmux_drive_reg pinmux_drive_regs[] = { { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
{ PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */{ PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */{ PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */{ PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */{ PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */{ PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */{ PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */{ PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
{ PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */{ PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */{ PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */{ PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */{ PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */{ PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */{ PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */{ PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
{ PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */{ PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */{ PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */{ PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */{ PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */{ PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */{ PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */{ PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
{ PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */{ PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */{ PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */{ PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */{ PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */{ PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */{ PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */{ PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ } }, { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
{ PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */{ PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */{ PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */{ PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */{ PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */{ PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */{ PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */{ PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
{ PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */{ PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */{ PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */{ PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */{ PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */{ PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */{ PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */{ PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
{ PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */{ PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */{ PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */{ PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */{ PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
{ PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */{ PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */{ PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */{ PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */{ PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ } }, { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */@@ -5991,7 +6053,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { } }, { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
{ PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
{ PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */@@ -6010,29 +6072,29 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ } }, { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */{ PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */{ PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ } }, { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
{ PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN3 */{ PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */{ PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
{ PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */{ PIN_FSCLKST, 20, 2 }, /* FSCLKST */{ PIN_TMS, 4, 2 }, /* TMS */ } }, { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
{ PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */{ PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
{ PIN_TDO, 28, 2 }, /* TDO */{ PIN_ASEBRK, 24, 2 }, /* ASEBRK */{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ } }, { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */@@ -6101,7 +6163,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
{ PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
{ PIN_MLB_REF, 4, 3 }, /* MLB_REF */ { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ } }, { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {@@ -6174,35 +6236,35 @@ static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po
static const struct pinmux_bias_reg pinmux_bias_regs[] = { { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
[ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */[ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */[ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */[ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */[ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */[ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */[ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */[ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */[ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */[ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */[10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */[11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */[12] = PIN_NUMBER('Y', 7), /* RPC_INT# */[13] = PIN_NUMBER('V', 6), /* RPC_WP# */[14] = PIN_NUMBER('V', 7), /* RPC_RESET# */[15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */[16] = PIN_NUMBER('B', 19), /* AVB_RXC */[17] = PIN_NUMBER('A', 13), /* AVB_RD0 */[18] = PIN_NUMBER('B', 13), /* AVB_RD1 */[19] = PIN_NUMBER('A', 14), /* AVB_RD2 */[20] = PIN_NUMBER('B', 14), /* AVB_RD3 */[21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */[22] = PIN_NUMBER('A', 19), /* AVB_TXC */[23] = PIN_NUMBER('A', 18), /* AVB_TD0 */[24] = PIN_NUMBER('B', 18), /* AVB_TD1 */[25] = PIN_NUMBER('A', 17), /* AVB_TD2 */[26] = PIN_NUMBER('B', 17), /* AVB_TD3 */[27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */[28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
[ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */[ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */[ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */[ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */[ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */[ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */[ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */[ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */[ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */[ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */[10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */[11] = PIN_QSPI1_SSL, /* QSPI1_SSL */[12] = PIN_RPC_INT_N, /* RPC_INT# */[13] = PIN_RPC_WP_N, /* RPC_WP# */[14] = PIN_RPC_RESET_N, /* RPC_RESET# */[15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */[16] = PIN_AVB_RXC, /* AVB_RXC */[17] = PIN_AVB_RD0, /* AVB_RD0 */[18] = PIN_AVB_RD1, /* AVB_RD1 */[19] = PIN_AVB_RD2, /* AVB_RD2 */[20] = PIN_AVB_RD3, /* AVB_RD3 */[21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */[22] = PIN_AVB_TXC, /* AVB_TXC */[23] = PIN_AVB_TD0, /* AVB_TD0 */[24] = PIN_AVB_TD1, /* AVB_TD1 */[25] = PIN_AVB_TD2, /* AVB_TD2 */[26] = PIN_AVB_TD3, /* AVB_TD3 */[27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */[28] = PIN_AVB_MDIO, /* AVB_MDIO */ [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */@@ -6251,7 +6313,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
[ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
[ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ [10] = RCAR_GP_PIN(0, 0), /* D0 */ [11] = RCAR_GP_PIN(0, 1), /* D1 */ [12] = RCAR_GP_PIN(0, 2), /* D2 */@@ -6272,20 +6334,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
[30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */[31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ } }, { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
[ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */[ 1] = PIN_NONE,[ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */[ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/[ 4] = PIN_A_NUMBER('R', 26), /* TRST# */[ 5] = PIN_A_NUMBER('T', 27), /* TCK */[ 6] = PIN_A_NUMBER('R', 30), /* TMS */[ 7] = PIN_A_NUMBER('R', 29), /* TDI */[ 8] = PIN_NONE,[ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
[ 0] = SH_PFC_PIN_NONE,[ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */[ 2] = PIN_FSCLKST, /* FSCLKST */[ 3] = PIN_EXTALR, /* EXTALR*/[ 4] = PIN_TRST_N, /* TRST# */[ 5] = PIN_TCK, /* TCK */[ 6] = PIN_TMS, /* TMS */[ 7] = PIN_TDI, /* TDI */[ 8] = SH_PFC_PIN_NONE,[ 9] = PIN_ASEBRK, /* ASEBRK */ [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */@@ -6350,7 +6412,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
[ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
[ 6] = PIN_MLB_REF, /* MLB_REF */ [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */@@ -6385,31 +6447,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */ [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
[ 7] = PIN_NONE,[ 8] = PIN_NONE,[ 9] = PIN_NONE,[10] = PIN_NONE,[11] = PIN_NONE,[12] = PIN_NONE,[13] = PIN_NONE,[14] = PIN_NONE,[15] = PIN_NONE,[16] = PIN_NONE,[17] = PIN_NONE,[18] = PIN_NONE,[19] = PIN_NONE,[20] = PIN_NONE,[21] = PIN_NONE,[22] = PIN_NONE,[23] = PIN_NONE,[24] = PIN_NONE,[25] = PIN_NONE,[26] = PIN_NONE,[27] = PIN_NONE,[28] = PIN_NONE,[29] = PIN_NONE,[30] = PIN_NONE,[31] = PIN_NONE,
[ 7] = SH_PFC_PIN_NONE,[ 8] = SH_PFC_PIN_NONE,[ 9] = SH_PFC_PIN_NONE,[10] = SH_PFC_PIN_NONE,[11] = SH_PFC_PIN_NONE,[12] = SH_PFC_PIN_NONE,[13] = SH_PFC_PIN_NONE,[14] = SH_PFC_PIN_NONE,[15] = SH_PFC_PIN_NONE,[16] = SH_PFC_PIN_NONE,[17] = SH_PFC_PIN_NONE,[18] = SH_PFC_PIN_NONE,[19] = SH_PFC_PIN_NONE,[20] = SH_PFC_PIN_NONE,[21] = SH_PFC_PIN_NONE,[22] = SH_PFC_PIN_NONE,[23] = SH_PFC_PIN_NONE,[24] = SH_PFC_PIN_NONE,[25] = SH_PFC_PIN_NONE,[26] = SH_PFC_PIN_NONE,[27] = SH_PFC_PIN_NONE,[28] = SH_PFC_PIN_NONE,[29] = SH_PFC_PIN_NONE,[30] = SH_PFC_PIN_NONE,[31] = SH_PFC_PIN_NONE, } }, { /* sentinel */ },}; diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c index 33ecd93398..4e6f406214 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77970.c +++ b/drivers/pinctrl/renesas/pfc-r8a77970.c @@ -5,7 +5,7 @@
- Copyright (C) 2016 Renesas Electronics Corp.
- Copyright (C) 2017 Cogent Embedded, Inc. source@cogentembedded.com
- This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
- This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
- R-Car Gen3 processor support - PFC hardware block.
@@ -20,7 +20,7 @@
#include "sh_pfc.h"
-#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ PORT_GP_28(1, fn, sfx), \ PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ @@ -206,8 +206,8 @@ #define IP6_19_16 FM(VI1_DATA8) F_(0, 0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_23_20 FM(VI1_DATA9) F_(0, 0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_27_24 FM(VI1_DATA10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -632,14 +632,12 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP6_31_28, SCL4), PINMUX_IPSR_GPSR(IP6_31_28, IRQ4), PINMUX_IPSR_GPSR(IP6_31_28, D14),
PINMUX_IPSR_GPSR(IP6_31_28, MMC_WP), /* IPSR7 */ PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD), PINMUX_IPSR_GPSR(IP7_3_0, SDA4), PINMUX_IPSR_GPSR(IP7_3_0, IRQ5), PINMUX_IPSR_GPSR(IP7_3_0, D15),PINMUX_IPSR_GPSR(IP7_3_0, MMC_CD), PINMUX_IPSR_GPSR(IP7_7_4, SCL0), PINMUX_IPSR_GPSR(IP7_7_4, DU_DR0),@@ -1122,20 +1120,6 @@ static const unsigned int mmc_ctrl_pins[] = { static const unsigned int mmc_ctrl_mux[] = { MMC_CLK_MARK, MMC_CMD_MARK, }; -static const unsigned int mmc_cd_pins[] = {
/* CD */RCAR_GP_PIN(3, 16),-}; -static const unsigned int mmc_cd_mux[] = {
MMC_CD_MARK,-}; -static const unsigned int mmc_wp_pins[] = {
/* WP */RCAR_GP_PIN(3, 15),-}; -static const unsigned int mmc_wp_mux[] = {
MMC_WP_MARK,-};
/* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { @@ -1433,6 +1417,64 @@ static const unsigned int qspi1_data4_mux[] = { QSPI1_IO2_MARK, QSPI1_IO3_MARK };
+/* - RPC -------------------------------------------------------------------- */ +static const unsigned int rpc_clk1_pins[] = {
/* Octal-SPI flash: C/SCLK */RCAR_GP_PIN(5, 0),+}; +static const unsigned int rpc_clk1_mux[] = {
QSPI0_SPCLK_MARK,+}; +static const unsigned int rpc_clk2_pins[] = {
/* HyperFlash: CK, CK# */RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),+}; +static const unsigned int rpc_clk2_mux[] = {
QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,+}; +static const unsigned int rpc_ctrl_pins[] = {
/* Octal-SPI flash: S#/CS, DQS *//* HyperFlash: CS#, RDS */RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),+}; +static const unsigned int rpc_ctrl_mux[] = {
QSPI0_SSL_MARK, QSPI1_SSL_MARK,+}; +static const unsigned int rpc_data_pins[] = {
/* DQ[0:7] */RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),+}; +static const unsigned int rpc_data_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,QSPI0_IO2_MARK, QSPI0_IO3_MARK,QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,QSPI1_IO2_MARK, QSPI1_IO3_MARK,+}; +static const unsigned int rpc_reset_pins[] = {
/* RPC_RESET# */RCAR_GP_PIN(5, 12),+}; +static const unsigned int rpc_reset_mux[] = {
RPC_RESET_N_MARK,+}; +static const unsigned int rpc_int_pins[] = {
/* RPC_INT# */RCAR_GP_PIN(5, 14),+}; +static const unsigned int rpc_int_mux[] = {
RPC_INT_N_MARK,+}; +static const unsigned int rpc_wp_pins[] = {
/* RPC_WP# */RCAR_GP_PIN(5, 13),+}; +static const unsigned int rpc_wp_mux[] = {
RPC_WP_N_MARK,+};
/* - SCIF Clock ------------------------------------------------------------- */ static const unsigned int scif_clk_a_pins[] = { /* SCIF_CLK */ @@ -1727,8 +1769,6 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc_data4), SH_PFC_PIN_GROUP(mmc_data8), SH_PFC_PIN_GROUP(mmc_ctrl),
SH_PFC_PIN_GROUP(mmc_cd),SH_PFC_PIN_GROUP(mmc_wp), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1),@@ -1769,6 +1809,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(qspi1_ctrl), SH_PFC_PIN_GROUP(qspi1_data2), SH_PFC_PIN_GROUP(qspi1_data4),
SH_PFC_PIN_GROUP(rpc_clk1),SH_PFC_PIN_GROUP(rpc_clk2),SH_PFC_PIN_GROUP(rpc_ctrl),SH_PFC_PIN_GROUP(rpc_data),SH_PFC_PIN_GROUP(rpc_reset),SH_PFC_PIN_GROUP(rpc_int),SH_PFC_PIN_GROUP(rpc_wp), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), SH_PFC_PIN_GROUP(scif0_data),@@ -1898,8 +1945,6 @@ static const char * const mmc_groups[] = { "mmc_data4", "mmc_data8", "mmc_ctrl",
"mmc_cd","mmc_wp",};
static const char * const msiof0_groups[] = { @@ -1975,6 +2020,16 @@ static const char * const qspi1_groups[] = { "qspi1_data4", };
+static const char * const rpc_groups[] = {
"rpc_clk1","rpc_clk2","rpc_ctrl","rpc_data","rpc_reset","rpc_int","rpc_wp",+};
static const char * const scif_clk_groups[] = { "scif_clk_a", "scif_clk_b", @@ -2060,6 +2115,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(rpc), SH_PFC_FUNCTION(scif_clk), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1),diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c index 32efb4409c..2d15500f0f 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77980.c +++ b/drivers/pinctrl/renesas/pfc-r8a77980.c @@ -5,7 +5,7 @@
- Copyright (C) 2018 Renesas Electronics Corp.
- Copyright (C) 2018 Cogent Embedded, Inc.
- This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
- This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
- R-Car Gen3 processor support - PFC hardware block.
@@ -20,7 +20,7 @@
#include "sh_pfc.h"
-#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ PORT_GP_28(1, fn, sfx), \ PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ @@ -1711,6 +1711,64 @@ static const unsigned int qspi1_data4_mux[] = { QSPI1_IO2_MARK, QSPI1_IO3_MARK };
+/* - RPC -------------------------------------------------------------------- */ +static const unsigned int rpc_clk1_pins[] = {
/* Octal-SPI flash: C/SCLK */RCAR_GP_PIN(5, 0),+}; +static const unsigned int rpc_clk1_mux[] = {
QSPI0_SPCLK_MARK,+}; +static const unsigned int rpc_clk2_pins[] = {
/* HyperFlash: CK, CK# */RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),+}; +static const unsigned int rpc_clk2_mux[] = {
QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,+}; +static const unsigned int rpc_ctrl_pins[] = {
/* Octal-SPI flash: S#/CS, DQS *//* HyperFlash: CS#, RDS */RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),+}; +static const unsigned int rpc_ctrl_mux[] = {
QSPI0_SSL_MARK, QSPI1_SSL_MARK,+}; +static const unsigned int rpc_data_pins[] = {
/* DQ[0:7] */RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),+}; +static const unsigned int rpc_data_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,QSPI0_IO2_MARK, QSPI0_IO3_MARK,QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,QSPI1_IO2_MARK, QSPI1_IO3_MARK,+}; +static const unsigned int rpc_reset_pins[] = {
/* RPC_RESET# */RCAR_GP_PIN(5, 12),+}; +static const unsigned int rpc_reset_mux[] = {
RPC_RESET_N_MARK,+}; +static const unsigned int rpc_int_pins[] = {
/* RPC_INT# */RCAR_GP_PIN(5, 14),+}; +static const unsigned int rpc_int_mux[] = {
RPC_INT_N_MARK,+}; +static const unsigned int rpc_wp_pins[] = {
/* RPC_WP# */RCAR_GP_PIN(5, 13),+}; +static const unsigned int rpc_wp_mux[] = {
RPC_WP_N_MARK,+};
/* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX0, TX0 */ @@ -2127,6 +2185,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(qspi1_ctrl), SH_PFC_PIN_GROUP(qspi1_data2), SH_PFC_PIN_GROUP(qspi1_data4),
SH_PFC_PIN_GROUP(rpc_clk1),SH_PFC_PIN_GROUP(rpc_clk2),SH_PFC_PIN_GROUP(rpc_ctrl),SH_PFC_PIN_GROUP(rpc_data),SH_PFC_PIN_GROUP(rpc_reset),SH_PFC_PIN_GROUP(rpc_int),SH_PFC_PIN_GROUP(rpc_wp), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl),@@ -2363,6 +2428,16 @@ static const char * const qspi1_groups[] = { "qspi1_data4", };
+static const char * const rpc_groups[] = {
"rpc_clk1","rpc_clk2","rpc_ctrl","rpc_data","rpc_reset","rpc_int","rpc_wp",+};
static const char * const scif0_groups[] = { "scif0_data", "scif0_clk", @@ -2461,6 +2536,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(rpc), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif3),diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index 572b041b83..78b46de041 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -4,7 +4,7 @@
- Copyright (C) 2018-2019 Renesas Electronics Corp.
- This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
- This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
- R8A7796 processor support - PFC hardware block.
@@ -20,10 +20,9 @@
#include "sh_pfc.h"
-#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP | \
SH_PFC_PIN_CFG_PULL_DOWN)+#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP_DOWN)
-#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \ @@ -44,6 +43,25 @@ PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS)
+#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_MDC, "AVB_MDC", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS), \PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS), \PIN_NOGP_CFG(TCK, "TCK", fn, CFG_FLAGS), \PIN_NOGP_CFG(TDI, "TDI", fn, CFG_FLAGS), \PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \PIN_NOGP_CFG(TRST_N, "TRST_N", fn, CFG_FLAGS)/*
- F_() : just information
- FM() : macro for FN_xxx / xxx_MARK
@@ -1283,41 +1301,16 @@ static const u16 pinmux_data[] = { };
/*
- R8A77990 has 7 banks with 32 GPIOs in each => 224 GPIOs.
- Physical layout rows: A - AE, cols: 1 - 25.
*/
- Pins not associated with a GPIO port.
-#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) -#define PIN_NUMBER(r, c) (((r) - 'A') * 25 + (c) + 300) -#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) -#define PIN_NONE U16_MAX +enum {
GP_ASSIGN_LAST(),NOGP_ALL(),+};
static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(),
/** Pins not associated with a GPIO port.** The pin positions are different between different R8A77990* packages, all that is needed for the pfc driver is a unique* number for each pin. To this end use the pin layout from* R8A77990 to calculate a unique number for each pin.*/SH_PFC_PIN_NAMED_CFG('F', 1, TRST_N, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('F', 3, TMS, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('F', 4, TCK, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('G', 2, TDI, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('G', 3, FSCLKST_N, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('H', 1, ASEBRK, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('N', 1, AVB_TXC, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('N', 2, AVB_TD0, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('N', 3, AVB_TD1, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('N', 5, AVB_TD2, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('N', 6, AVB_TD3, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('P', 3, AVB_TX_CTL, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('P', 4, AVB_MDIO, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('P', 5, AVB_MDC, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG('T', 21, MLB_REF, CFG_FLAGS),SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS),
PINMUX_NOGP_ALL(),};
/* - AUDIO CLOCK ------------------------------------------------------------ */ @@ -5115,15 +5108,15 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [0] = RCAR_GP_PIN(2, 23), /* RD# */ [1] = RCAR_GP_PIN(2, 22), /* BS# */ [2] = RCAR_GP_PIN(2, 21), /* AVB_PHY_INT */
[3] = PIN_NUMBER('P', 5), /* AVB_MDC */[4] = PIN_NUMBER('P', 4), /* AVB_MDIO */
[3] = PIN_AVB_MDC, /* AVB_MDC */[4] = PIN_AVB_MDIO, /* AVB_MDIO */ [5] = RCAR_GP_PIN(2, 20), /* AVB_TXCREFCLK */
[6] = PIN_NUMBER('N', 6), /* AVB_TD3 */[7] = PIN_NUMBER('N', 5), /* AVB_TD2 */[8] = PIN_NUMBER('N', 3), /* AVB_TD1 */[9] = PIN_NUMBER('N', 2), /* AVB_TD0 */[10] = PIN_NUMBER('N', 1), /* AVB_TXC */[11] = PIN_NUMBER('P', 3), /* AVB_TX_CTL */
[6] = PIN_AVB_TD3, /* AVB_TD3 */[7] = PIN_AVB_TD2, /* AVB_TD2 */[8] = PIN_AVB_TD1, /* AVB_TD1 */[9] = PIN_AVB_TD0, /* AVB_TD0 */[10] = PIN_AVB_TXC, /* AVB_TXC */[11] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ [12] = RCAR_GP_PIN(2, 19), /* AVB_RD3 */ [13] = RCAR_GP_PIN(2, 18), /* AVB_RD2 */ [14] = RCAR_GP_PIN(2, 17), /* AVB_RD1 */@@ -5174,33 +5167,33 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [25] = RCAR_GP_PIN(1, 2), /* A2 */ [26] = RCAR_GP_PIN(1, 1), /* A1 */ [27] = RCAR_GP_PIN(1, 0), /* A0 */
[28] = PIN_NONE,[29] = PIN_NONE,
[28] = SH_PFC_PIN_NONE,[29] = SH_PFC_PIN_NONE, [30] = RCAR_GP_PIN(2, 25), /* PUEN_EX_WAIT0 */ [31] = RCAR_GP_PIN(2, 24), /* PUEN_RD/WR# */ } }, { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { [0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ [1] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
[2] = PIN_NUMBER('H', 1), /* ASEBRK */[3] = PIN_NONE,[4] = PIN_NUMBER('G', 2), /* TDI */[5] = PIN_NUMBER('F', 3), /* TMS */[6] = PIN_NUMBER('F', 4), /* TCK */[7] = PIN_NUMBER('F', 1), /* TRST# */[8] = PIN_NONE,[9] = PIN_NONE,[10] = PIN_NONE,[11] = PIN_NONE,[12] = PIN_NONE,[13] = PIN_NONE,[14] = PIN_NONE,[15] = PIN_NUMBER('G', 3), /* FSCLKST# */
[2] = PIN_ASEBRK, /* ASEBRK */[3] = SH_PFC_PIN_NONE,[4] = PIN_TDI, /* TDI */[5] = PIN_TMS, /* TMS */[6] = PIN_TCK, /* TCK */[7] = PIN_TRST_N, /* TRST# */[8] = SH_PFC_PIN_NONE,[9] = SH_PFC_PIN_NONE,[10] = SH_PFC_PIN_NONE,[11] = SH_PFC_PIN_NONE,[12] = SH_PFC_PIN_NONE,[13] = SH_PFC_PIN_NONE,[14] = SH_PFC_PIN_NONE,[15] = PIN_FSCLKST_N, /* FSCLKST# */ [16] = RCAR_GP_PIN(0, 17), /* SDA4 */ [17] = RCAR_GP_PIN(0, 16), /* SCL4 */
[18] = PIN_NONE,[19] = PIN_NONE,[20] = PIN_A_NUMBER('D', 3), /* PRESETOUT# */
[18] = SH_PFC_PIN_NONE,[19] = SH_PFC_PIN_NONE,[20] = PIN_PRESETOUT_N, /* PRESETOUT# */ [21] = RCAR_GP_PIN(0, 15), /* D15 */ [22] = RCAR_GP_PIN(0, 14), /* D14 */ [23] = RCAR_GP_PIN(0, 13), /* D13 */@@ -5219,8 +5212,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */ [3] = RCAR_GP_PIN(5, 2), /* TX0_A */ [4] = RCAR_GP_PIN(5, 1), /* RX0_A */
[5] = PIN_NONE,[6] = PIN_NONE,
[5] = SH_PFC_PIN_NONE,[6] = SH_PFC_PIN_NONE, [7] = RCAR_GP_PIN(3, 15), /* SD1_WP */ [8] = RCAR_GP_PIN(3, 14), /* SD1_CD */ [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */@@ -5264,7 +5257,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [13] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ [14] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ [15] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
[16] = PIN_NUMBER('T', 21), /* MLB_REF */
[16] = PIN_MLB_REF, /* MLB_REF */ [17] = RCAR_GP_PIN(5, 19), /* MLB_DAT */ [18] = RCAR_GP_PIN(5, 18), /* MLB_SIG */ [19] = RCAR_GP_PIN(5, 17), /* MLB_CLK */@@ -5282,36 +5275,36 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [31] = RCAR_GP_PIN(5, 5), /* RX1 */ } }, { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
[0] = PIN_NONE,[1] = PIN_NONE,[2] = PIN_NONE,[3] = PIN_NONE,[4] = PIN_NONE,[5] = PIN_NONE,[6] = PIN_NONE,[7] = PIN_NONE,[8] = PIN_NONE,[9] = PIN_NONE,[10] = PIN_NONE,[11] = PIN_NONE,[12] = PIN_NONE,[13] = PIN_NONE,[14] = PIN_NONE,[15] = PIN_NONE,[16] = PIN_NONE,[17] = PIN_NONE,[18] = PIN_NONE,[19] = PIN_NONE,[20] = PIN_NONE,[21] = PIN_NONE,[22] = PIN_NONE,[23] = PIN_NONE,[24] = PIN_NONE,[25] = PIN_NONE,[26] = PIN_NONE,[27] = PIN_NONE,[28] = PIN_NONE,[29] = PIN_NONE,
[0] = SH_PFC_PIN_NONE,[1] = SH_PFC_PIN_NONE,[2] = SH_PFC_PIN_NONE,[3] = SH_PFC_PIN_NONE,[4] = SH_PFC_PIN_NONE,[5] = SH_PFC_PIN_NONE,[6] = SH_PFC_PIN_NONE,[7] = SH_PFC_PIN_NONE,[8] = SH_PFC_PIN_NONE,[9] = SH_PFC_PIN_NONE,[10] = SH_PFC_PIN_NONE,[11] = SH_PFC_PIN_NONE,[12] = SH_PFC_PIN_NONE,[13] = SH_PFC_PIN_NONE,[14] = SH_PFC_PIN_NONE,[15] = SH_PFC_PIN_NONE,[16] = SH_PFC_PIN_NONE,[17] = SH_PFC_PIN_NONE,[18] = SH_PFC_PIN_NONE,[19] = SH_PFC_PIN_NONE,[20] = SH_PFC_PIN_NONE,[21] = SH_PFC_PIN_NONE,[22] = SH_PFC_PIN_NONE,[23] = SH_PFC_PIN_NONE,[24] = SH_PFC_PIN_NONE,[25] = SH_PFC_PIN_NONE,[26] = SH_PFC_PIN_NONE,[27] = SH_PFC_PIN_NONE,[28] = SH_PFC_PIN_NONE,[29] = SH_PFC_PIN_NONE, [30] = RCAR_GP_PIN(6, 9), /* PUEN_USB30_OVC */ [31] = RCAR_GP_PIN(6, 17), /* PUEN_USB30_PWEN */ } },diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c index 724cf4ae3c..4ff1b76588 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77995.c +++ b/drivers/pinctrl/renesas/pfc-r8a77995.c @@ -4,7 +4,7 @@
- Copyright (C) 2017 Renesas Electronics Corp.
- This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
- This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
- R-Car Gen3 processor support - PFC hardware block.
@@ -19,7 +19,7 @@
#include "sh_pfc.h"
-#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_9(0, fn, sfx), \ PORT_GP_32(1, fn, sfx), \ PORT_GP_32(2, fn, sfx), \ diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index f563916f10..9d74f5fb4e 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -1,11 +1,8 @@ -/* +/* SPDX-License-Identifier: GPL-2.0
- SuperH Pin Function Controller Support
- Copyright (c) 2008 Magnus Damm
- This file is subject to the terms and conditions of the GNU General Public
- License. See the file "COPYING" in the main directory of this archive
*/
- for more details.
#ifndef __SH_PFC_H @@ -21,19 +18,32 @@ enum { PINMUX_TYPE_INPUT, };
+#define SH_PFC_PIN_NONE U16_MAX
#define SH_PFC_PIN_CFG_INPUT (1 << 0) #define SH_PFC_PIN_CFG_OUTPUT (1 << 1) #define SH_PFC_PIN_CFG_PULL_UP (1 << 2) #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) +#define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \
SH_PFC_PIN_CFG_PULL_DOWN)#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4) #define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
+#define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6) +#define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6)
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
SH_PFC_PIN_VOLTAGE_18_33)+#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
SH_PFC_PIN_VOLTAGE_25_33)#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
struct sh_pfc_pin {
u16 pin;u16 enum_id; const char *name; unsigned int configs;
u16 pin;u16 enum_id;};
#define SH_PFC_PIN_GROUP_ALIAS(alias, n) \ @@ -393,12 +403,12 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; /*
- Describe a pinmux configuration in which a pin is physically multiplexed
- with other pins.
- ipsr: IPSR field (unused, for documentation purposes only)
*/
- ipsr: IPSR field
- fn: Function name
- psel: Physical multiplexing selector
#define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
PINMUX_DATA(fn##_MARK, FN_##psel)
PINMUX_DATA(fn##_MARK, FN_##psel, FN_##ipsr)/*
- Describe a pinmux configuration for a single-function pin with GPIO
@@ -416,9 +426,13 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; fn(bank, pin, GP_##bank##_##pin, sfx, cfg) #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
-#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_2(bank, fn, sfx, cfg) \ PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)+#define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0)
+#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
PORT_GP_CFG_2(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0) @@ -517,9 +531,13 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; PORT_GP_CFG_1(bank, 25, fn, sfx, cfg) #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
-#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_27(bank, fn, sfx, cfg) \ PORT_GP_CFG_26(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 26, fn, sfx, cfg)+#define PORT_GP_27(bank, fn, sfx) PORT_GP_CFG_27(bank, fn, sfx, 0)
+#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
PORT_GP_CFG_27(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
@@ -533,9 +551,13 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; PORT_GP_CFG_1(bank, 29, fn, sfx, cfg) #define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
-#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_31(bank, fn, sfx, cfg) \ PORT_GP_CFG_30(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 30, fn, sfx, cfg)+#define PORT_GP_31(bank, fn, sfx) PORT_GP_CFG_31(bank, fn, sfx, 0)
+#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
PORT_GP_CFG_31(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
@@ -559,7 +581,7 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */ #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx -#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str) +#define GP_ALL(str) CPU_ALL_GP(_GP_ALL, str)
/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ #define _GP_GPIO(bank, _pin, _name, sfx, cfg) \ @@ -569,11 +591,29 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; .enum_id = _name##_DATA, \ .configs = cfg, \ } -#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */ #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN) -#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_GP(_GP_DATA, unused)
+/*
- GP_ASSIGN_LAST() - Expand to an enum definition for the last GP pin
- The largest GP pin index is obtained by taking the size of a union,
- containing one array per GP pin, sized by the corresponding pin index.
- As the fields in the CPU_ALL_GP() macro definition are separated by commas,
- while the members of a union must be terminated by semicolons, the commas
- are absorbed by wrapping them inside dummy attributes.
- */
+#define _GP_ENTRY(bank, pin, name, sfx, cfg) \
deprecated)); char name[(bank * 32) + pin] __attribute__((deprecated+#define GP_ASSIGN_LAST() \
GP_LAST = sizeof(union { \char dummy[0] __attribute__((deprecated, \CPU_ALL_GP(_GP_ENTRY, unused), \deprecated)); \})/*
- PORT style (linear pin space)
@@ -616,22 +656,6 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; .configs = cfgs, \ }
-/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */ -#define SH_PFC_PIN_NAMED(row, col, _name) \
{ \.pin = PIN_NUMBER(row, col), \.name = __stringify(PIN_##_name), \.configs = SH_PFC_PIN_CFG_NO_GPIO, \}-/* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */ -#define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \
{ \.pin = PIN_NUMBER(row, col), \.name = __stringify(PIN_##_name), \.configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \}/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
PORT_name_OUT, PORT_name_IN marks*/ @@ -640,6 +664,24 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; PORT##pfx##_OUT, PORT##pfx##_IN) #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
+/*
- PORT_ASSIGN_LAST() - Expand to an enum definition for the last PORT pin
- The largest PORT pin index is obtained by taking the size of a union,
- containing one array per PORT pin, sized by the corresponding pin index.
- As the fields in the CPU_ALL_PORT() macro definition are separated by
- commas, while the members of a union must be terminated by semicolons, the
- commas are absorbed by wrapping them inside dummy attributes.
- */
+#define _PORT_ENTRY(pn, pfx, sfx) \
deprecated)); char pfx[pn] __attribute__((deprecated+#define PORT_ASSIGN_LAST() \
PORT_LAST = sizeof(union { \char dummy[0] __attribute__((deprecated, \CPU_ALL_PORT(_PORT_ENTRY, PORT, unused), \deprecated)); \})/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */ #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ [gpio - (base)] = { \ @@ -649,6 +691,26 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; #define GPIO_FN(str) \ PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
+/*
- Pins not associated with a GPIO port
- */
+#define PIN_NOGP_CFG(pin, name, fn, cfg) fn(pin, name, cfg) +#define PIN_NOGP(pin, name, fn) fn(pin, name, 0)
+/* NOGP_ALL - Expand to a list of PIN_id */ +#define _NOGP_ALL(pin, name, cfg) PIN_##pin +#define NOGP_ALL() CPU_ALL_NOGP(_NOGP_ALL)
+/* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */ +#define _NOGP_PINMUX(_pin, _name, cfg) \
{ \.pin = PIN_##_pin, \.name = "PIN_" _name, \.configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \}+#define PINMUX_NOGP_ALL() CPU_ALL_NOGP(_NOGP_PINMUX)
/*
- PORTnCR helper macro for SH-Mobile/R-Mobile
*/
2.30.2
The help text in the Kconfig file was always a copy of the same thing. Move single copy into the common PFC driver entry instead. Also fix a copy-paste error in the PFC help text, which identified PFC as clock.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- drivers/pinctrl/renesas/Kconfig | 74 +++------------------------------ 1 file changed, 5 insertions(+), 69 deletions(-)
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 8fb9cba387..c3a6594ebe 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -5,7 +5,11 @@ config PINCTRL_PFC depends on DM && ARCH_RMOBILE default n if CPU_RZA1 help - Enable support for clock present on Renesas RCar SoCs. + Support pin multiplexing control on Renesas SoCs. + + These drivers are controlled by a device tree node which contains + both the GPIO definitions and pin control functions for each + available multiplex function.
config PINCTRL_PFC_R8A7790 bool "Renesas RCar Gen2 R8A7790 pin control driver" @@ -13,160 +17,96 @@ config PINCTRL_PFC_R8A7790 help Support pin multiplexing control on Renesas RCar Gen3 R8A7790 SoCs.
- The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A7791 bool "Renesas RCar Gen2 R8A7791 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RCar Gen3 R8A7791 SoCs.
- The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A7792 bool "Renesas RCar Gen2 R8A7792 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RCar Gen3 R8A7792 SoCs.
- The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A7793 bool "Renesas RCar Gen2 R8A7793 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RCar Gen3 R8A7793 SoCs.
- The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A7794 bool "Renesas RCar Gen2 R8A7794 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RCar Gen3 R8A7794 SoCs.
- The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A774A1 bool "Renesas RZ/G2 R8A774A1 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RZ/G2M R8A774A1 SoCs.
- The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A774B1 bool "Renesas RZ/G2 R8A774B1 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RZ/G2N R8A774B1 SoCs.
- The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A774C0 bool "Renesas RZ/G2 R8A774C0 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RZ/G2E R8A774C0 SoCs.
- The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A774E1 bool "Renesas RZ/G2 R8A774E1 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RZ/G2H R8A774E1 SoCs.
- The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A7795 bool "Renesas RCar Gen3 R8A7795 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RCar Gen3 R8A7795 SoCs.
- The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A7796 bool "Renesas RCar Gen3 R8A7796 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RCar Gen3 R8A7796 SoCs.
- The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A77965 bool "Renesas RCar Gen3 R8A77965 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RCar Gen3 R8A77965 SoCs.
- The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A77970 bool "Renesas RCar Gen3 R8A77970 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RCar Gen3 R8A77970 SoCs.
- The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A77980 bool "Renesas RCar Gen3 R8A77980 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RCar Gen3 R8A77980 SoCs.
- The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A77990 bool "Renesas RCar Gen3 R8A77990 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RCar Gen3 R8A77990 SoCs.
- The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R8A77995 bool "Renesas RCar Gen3 R8A77995 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RCar Gen3 R8A77995 SoCs.
- The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - config PINCTRL_PFC_R7S72100 bool "Renesas RZ/A1 R7S72100 pin control driver" depends on CPU_RZA1 @@ -174,8 +114,4 @@ config PINCTRL_PFC_R7S72100 help Support pin multiplexing control on Renesas RZ/A1 R7S72100 SoCs.
- The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - endif
The help text for Gen2 entries had a copy paste error, still containing the Gen3 string, while the description was correctly listing Gen2. Fix the help text.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- drivers/pinctrl/renesas/Kconfig | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index c3a6594ebe..35f10e2c2b 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -15,31 +15,31 @@ config PINCTRL_PFC_R8A7790 bool "Renesas RCar Gen2 R8A7790 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A7790 SoCs. + Support pin multiplexing control on Renesas RCar Gen2 R8A7790 SoCs.
config PINCTRL_PFC_R8A7791 bool "Renesas RCar Gen2 R8A7791 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A7791 SoCs. + Support pin multiplexing control on Renesas RCar Gen2 R8A7791 SoCs.
config PINCTRL_PFC_R8A7792 bool "Renesas RCar Gen2 R8A7792 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A7792 SoCs. + Support pin multiplexing control on Renesas RCar Gen2 R8A7792 SoCs.
config PINCTRL_PFC_R8A7793 bool "Renesas RCar Gen2 R8A7793 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A7793 SoCs. + Support pin multiplexing control on Renesas RCar Gen2 R8A7793 SoCs.
config PINCTRL_PFC_R8A7794 bool "Renesas RCar Gen2 R8A7794 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A7794 SoCs. + Support pin multiplexing control on Renesas RCar Gen2 R8A7794 SoCs.
config PINCTRL_PFC_R8A774A1 bool "Renesas RZ/G2 R8A774A1 pin control driver"
The V3U SoC has several unlock registers, one per register group. They reside at offset zero in each 0x200 bytes-sized block.
To avoid adding yet another table to the PFC implementation, this patch adds the option to specify an address mask instead of the fixed address in sh_pfc_soc_info::unlock_reg.
This is a direct port of Linux 5.12 commit e127ef2ed0a6 ("pinctrl: renesas: Implement unlock register masks") by Ulrich Hecht uli+renesas@fpond.eu
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- drivers/pinctrl/renesas/pfc.c | 39 ++++++++++++++++---------------- drivers/pinctrl/renesas/sh_pfc.h | 2 +- 2 files changed, 20 insertions(+), 21 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index 07fcc3d393..2498eb5716 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -131,14 +131,25 @@ u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg) return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32); }
-void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data) +static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data) { - void __iomem *unlock_reg = - (void __iomem *)(uintptr_t)pfc->info->unlock_reg; + u32 unlock; + + if (!pfc->info->unlock_reg) + return;
- if (pfc->info->unlock_reg) - sh_pfc_write_raw_reg(unlock_reg, 32, ~data); + if (pfc->info->unlock_reg >= 0x80000000UL) + unlock = pfc->info->unlock_reg; + else + /* unlock_reg is a mask */ + unlock = reg & ~pfc->info->unlock_reg; + + sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)unlock, 32, ~data); +}
+void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data) +{ + sh_pfc_unlock_reg(pfc, reg, data); sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data); }
@@ -168,8 +179,6 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, unsigned int field, u32 value) { void __iomem *mapped_reg; - void __iomem *unlock_reg = - (void __iomem *)(uintptr_t)pfc->info->unlock_reg; unsigned int pos; u32 mask, data;
@@ -186,9 +195,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, data &= mask; data |= value;
- if (pfc->info->unlock_reg) - sh_pfc_write_raw_reg(unlock_reg, 32, ~data); - + sh_pfc_unlock_reg(pfc, crp->reg, data); sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); }
@@ -679,8 +686,6 @@ static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc, unsigned int size; unsigned int step; void __iomem *reg; - void __iomem *unlock_reg = - (void __iomem *)(uintptr_t)pfc->info->unlock_reg; u32 val;
reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size); @@ -701,9 +706,7 @@ static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc, val &= ~GENMASK(offset + 4 - 1, offset); val |= strength << offset;
- if (unlock_reg) - sh_pfc_write_raw_reg(unlock_reg, 32, ~val); - + sh_pfc_unlock_reg(pfc, (uintptr_t)reg, val); sh_pfc_write_raw_reg(reg, 32, val);
return 0; @@ -743,8 +746,6 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin, { struct sh_pfc *pfc = pmx->pfc; void __iomem *pocctrl; - void __iomem *unlock_reg = - (void __iomem *)(uintptr_t)pfc->info->unlock_reg; u32 addr, val; int bit, ret;
@@ -790,9 +791,7 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin, else val &= ~BIT(bit);
- if (unlock_reg) - sh_pfc_write_raw_reg(unlock_reg, 32, ~val); - + sh_pfc_unlock_reg(pfc, addr, val); sh_pfc_write_raw_reg(pocctrl, 32, val);
break; diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 9d74f5fb4e..48d737a141 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -294,7 +294,7 @@ struct sh_pfc_soc_info { const struct pinmux_irq *gpio_irq; unsigned int gpio_irq_size;
- u32 unlock_reg; + u32 unlock_reg; /* can be literal address or mask */ };
u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg);
Hi Marek,
Thank you for the patch.
On Wed, Apr 28, 2021 at 8:33 PM Marek Vasut marek.vasut@gmail.com wrote:
The V3U SoC has several unlock registers, one per register group. They reside at offset zero in each 0x200 bytes-sized block.
To avoid adding yet another table to the PFC implementation, this patch adds the option to specify an address mask instead of the fixed address in sh_pfc_soc_info::unlock_reg.
This is a direct port of Linux 5.12 commit e127ef2ed0a6 ("pinctrl: renesas: Implement unlock register masks") by Ulrich Hecht uli+renesas@fpond.eu
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com
drivers/pinctrl/renesas/pfc.c | 39 ++++++++++++++++---------------- drivers/pinctrl/renesas/sh_pfc.h | 2 +- 2 files changed, 20 insertions(+), 21 deletions(-)
Tested on RZ/G2{EHMN} boards
Tested-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
Cheers, Prabhakar
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index 07fcc3d393..2498eb5716 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -131,14 +131,25 @@ u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg) return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32); }
-void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data) +static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data) {
void __iomem *unlock_reg =(void __iomem *)(uintptr_t)pfc->info->unlock_reg;
u32 unlock;if (!pfc->info->unlock_reg)return;
if (pfc->info->unlock_reg)sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
if (pfc->info->unlock_reg >= 0x80000000UL)unlock = pfc->info->unlock_reg;else/* unlock_reg is a mask */unlock = reg & ~pfc->info->unlock_reg;sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)unlock, 32, ~data);+}
+void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data) +{
sh_pfc_unlock_reg(pfc, reg, data); sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data);}
@@ -168,8 +179,6 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, unsigned int field, u32 value) { void __iomem *mapped_reg;
void __iomem *unlock_reg =(void __iomem *)(uintptr_t)pfc->info->unlock_reg; unsigned int pos; u32 mask, data;@@ -186,9 +195,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, data &= mask; data |= value;
if (pfc->info->unlock_reg)sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
sh_pfc_unlock_reg(pfc, crp->reg, data); sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);}
@@ -679,8 +686,6 @@ static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc, unsigned int size; unsigned int step; void __iomem *reg;
void __iomem *unlock_reg =(void __iomem *)(uintptr_t)pfc->info->unlock_reg; u32 val; reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);@@ -701,9 +706,7 @@ static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc, val &= ~GENMASK(offset + 4 - 1, offset); val |= strength << offset;
if (unlock_reg)sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
sh_pfc_unlock_reg(pfc, (uintptr_t)reg, val); sh_pfc_write_raw_reg(reg, 32, val); return 0;@@ -743,8 +746,6 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin, { struct sh_pfc *pfc = pmx->pfc; void __iomem *pocctrl;
void __iomem *unlock_reg =(void __iomem *)(uintptr_t)pfc->info->unlock_reg; u32 addr, val; int bit, ret;@@ -790,9 +791,7 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin, else val &= ~BIT(bit);
if (unlock_reg)sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
sh_pfc_unlock_reg(pfc, addr, val); sh_pfc_write_raw_reg(pocctrl, 32, val); break;diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 9d74f5fb4e..48d737a141 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -294,7 +294,7 @@ struct sh_pfc_soc_info { const struct pinmux_irq *gpio_irq; unsigned int gpio_irq_size;
u32 unlock_reg;
u32 unlock_reg; /* can be literal address or mask */};
u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg);
2.30.2
Import R8A779A0 V3U PFC tables from Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Add parts of PFC table integration from pinctrl: renesas: Add R8A779A0 V3U PFC tables by Hai Pham hai.pham.ud@renesas.com" .
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- drivers/pinctrl/renesas/Kconfig | 6 + drivers/pinctrl/renesas/Makefile | 1 + drivers/pinctrl/renesas/pfc-r8a779a0.c | 4503 ++++++++++++++++++++++++ drivers/pinctrl/renesas/pfc.c | 12 + drivers/pinctrl/renesas/sh_pfc.h | 1 + 5 files changed, 4523 insertions(+) create mode 100644 drivers/pinctrl/renesas/pfc-r8a779a0.c
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 35f10e2c2b..1fedf63252 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -107,6 +107,12 @@ config PINCTRL_PFC_R8A77995 help Support pin multiplexing control on Renesas RCar Gen3 R8A77995 SoCs.
+config PINCTRL_PFC_R8A779A0 + bool "Renesas RCar Gen3 R8A779A0 pin control driver" + depends on PINCTRL_PFC + help + Support pin multiplexing control on Renesas RCar Gen3 R8A779A0 SoCs. + config PINCTRL_PFC_R7S72100 bool "Renesas RZ/A1 R7S72100 pin control driver" depends on CPU_RZA1 diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile index 0e2ac3c513..1c65505eff 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -15,4 +15,5 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o +obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c new file mode 100644 index 0000000000..d99b6e2e07 --- /dev/null +++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c @@ -0,0 +1,4503 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R8A779A0 processor support - PFC hardware block. + * + * Copyright (C) 2020 Renesas Electronics Corp. + * + * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <dm/pinctrl.h> +#include <linux/bitops.h> +#include <linux/kernel.h> + +#include "sh_pfc.h" + +#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) + +#define CPU_ALL_GP(fn, sfx) \ + PORT_GP_CFG_15(0, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(0, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 16, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 17, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 18, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 19, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 20, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 21, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 22, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 23, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 24, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 25, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 26, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(0, 27, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_31(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_2(2, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(2, 2, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 5, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 6, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 7, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 10, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 11, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 12, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 13, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 14, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(2, 16, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(2, 17, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(2, 18, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(2, 19, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(2, 20, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(2, 21, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(2, 22, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(2, 23, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(2, 24, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_17(3, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ + PORT_GP_CFG_1(4, 18, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(4, 19, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(4, 20, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(4, 21, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(4, 22, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(4, 23, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(4, 24, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(4, 25, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(4, 26, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_18(5, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ + PORT_GP_CFG_1(5, 18, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(5, 19, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(5, 20, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ + PORT_GP_CFG_1(6, 18, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(6, 19, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(6, 20, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_18(7, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ + PORT_GP_CFG_1(7, 18, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(7, 19, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(7, 20, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_18(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ + PORT_GP_CFG_1(8, 18, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(8, 19, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(8, 20, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_18(9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\ + PORT_GP_CFG_1(9, 18, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(9, 19, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(9, 20, fn, sfx, CFG_FLAGS) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(DCUTRST_N_LPDRST_N, "DCUTRST#_LPDRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) + +/* + * F_() : just information + * FM() : macro for FN_xxx / xxx_MARK + */ + +/* GPSR0 */ +#define GPSR0_27 FM(MMC_D7) +#define GPSR0_26 FM(MMC_D6) +#define GPSR0_25 FM(MMC_D5) +#define GPSR0_24 FM(MMC_D4) +#define GPSR0_23 FM(MMC_SD_CLK) +#define GPSR0_22 FM(MMC_SD_D3) +#define GPSR0_21 FM(MMC_SD_D2) +#define GPSR0_20 FM(MMC_SD_D1) +#define GPSR0_19 FM(MMC_SD_D0) +#define GPSR0_18 FM(MMC_SD_CMD) +#define GPSR0_17 FM(MMC_DS) +#define GPSR0_16 FM(SD_CD) +#define GPSR0_15 FM(SD_WP) +#define GPSR0_14 FM(RPC_INT_N) +#define GPSR0_13 FM(RPC_WP_N) +#define GPSR0_12 FM(RPC_RESET_N) +#define GPSR0_11 FM(QSPI1_SSL) +#define GPSR0_10 FM(QSPI1_IO3) +#define GPSR0_9 FM(QSPI1_IO2) +#define GPSR0_8 FM(QSPI1_MISO_IO1) +#define GPSR0_7 FM(QSPI1_MOSI_IO0) +#define GPSR0_6 FM(QSPI1_SPCLK) +#define GPSR0_5 FM(QSPI0_SSL) +#define GPSR0_4 FM(QSPI0_IO3) +#define GPSR0_3 FM(QSPI0_IO2) +#define GPSR0_2 FM(QSPI0_MISO_IO1) +#define GPSR0_1 FM(QSPI0_MOSI_IO0) +#define GPSR0_0 FM(QSPI0_SPCLK) + +/* GPSR1 */ +#define GPSR1_30 F_(GP1_30, IP3SR1_27_24) +#define GPSR1_29 F_(GP1_29, IP3SR1_23_20) +#define GPSR1_28 F_(GP1_28, IP3SR1_19_16) +#define GPSR1_27 F_(IRQ3, IP3SR1_15_12) +#define GPSR1_26 F_(IRQ2, IP3SR1_11_8) +#define GPSR1_25 F_(IRQ1, IP3SR1_7_4) +#define GPSR1_24 F_(IRQ0, IP3SR1_3_0) +#define GPSR1_23 F_(MSIOF2_SS2, IP2SR1_31_28) +#define GPSR1_22 F_(MSIOF2_SS1, IP2SR1_27_24) +#define GPSR1_21 F_(MSIOF2_SYNC, IP2SR1_23_20) +#define GPSR1_20 F_(MSIOF2_SCK, IP2SR1_19_16) +#define GPSR1_19 F_(MSIOF2_TXD, IP2SR1_15_12) +#define GPSR1_18 F_(MSIOF2_RXD, IP2SR1_11_8) +#define GPSR1_17 F_(MSIOF1_SS2, IP2SR1_7_4) +#define GPSR1_16 F_(MSIOF1_SS1, IP2SR1_3_0) +#define GPSR1_15 F_(MSIOF1_SYNC, IP1SR1_31_28) +#define GPSR1_14 F_(MSIOF1_SCK, IP1SR1_27_24) +#define GPSR1_13 F_(MSIOF1_TXD, IP1SR1_23_20) +#define GPSR1_12 F_(MSIOF1_RXD, IP1SR1_19_16) +#define GPSR1_11 F_(MSIOF0_SS2, IP1SR1_15_12) +#define GPSR1_10 F_(MSIOF0_SS1, IP1SR1_11_8) +#define GPSR1_9 F_(MSIOF0_SYNC, IP1SR1_7_4) +#define GPSR1_8 F_(MSIOF0_SCK, IP1SR1_3_0) +#define GPSR1_7 F_(MSIOF0_TXD, IP0SR1_31_28) +#define GPSR1_6 F_(MSIOF0_RXD, IP0SR1_27_24) +#define GPSR1_5 F_(HTX0, IP0SR1_23_20) +#define GPSR1_4 F_(HCTS0_N, IP0SR1_19_16) +#define GPSR1_3 F_(HRTS0_N, IP0SR1_15_12) +#define GPSR1_2 F_(HSCK0, IP0SR1_11_8) +#define GPSR1_1 F_(HRX0, IP0SR1_7_4) +#define GPSR1_0 F_(SCIF_CLK, IP0SR1_3_0) + +/* GPSR2 */ +#define GPSR2_24 FM(TCLK2_A) +#define GPSR2_23 F_(TCLK1_A, IP2SR2_31_28) +#define GPSR2_22 F_(TPU0TO1, IP2SR2_27_24) +#define GPSR2_21 F_(TPU0TO0, IP2SR2_23_20) +#define GPSR2_20 F_(CLK_EXTFXR, IP2SR2_19_16) +#define GPSR2_19 F_(RXDB_EXTFXR, IP2SR2_15_12) +#define GPSR2_18 F_(FXR_TXDB, IP2SR2_11_8) +#define GPSR2_17 F_(RXDA_EXTFXR_A, IP2SR2_7_4) +#define GPSR2_16 F_(FXR_TXDA_A, IP2SR2_3_0) +#define GPSR2_15 F_(GP2_15, IP1SR2_31_28) +#define GPSR2_14 F_(GP2_14, IP1SR2_27_24) +#define GPSR2_13 F_(GP2_13, IP1SR2_23_20) +#define GPSR2_12 F_(GP2_12, IP1SR2_19_16) +#define GPSR2_11 F_(GP2_11, IP1SR2_15_12) +#define GPSR2_10 F_(GP2_10, IP1SR2_11_8) +#define GPSR2_9 F_(GP2_09, IP1SR2_7_4) +#define GPSR2_8 F_(GP2_08, IP1SR2_3_0) +#define GPSR2_7 F_(GP2_07, IP0SR2_31_28) +#define GPSR2_6 F_(GP2_06, IP0SR2_27_24) +#define GPSR2_5 F_(GP2_05, IP0SR2_23_20) +#define GPSR2_4 F_(GP2_04, IP0SR2_19_16) +#define GPSR2_3 F_(GP2_03, IP0SR2_15_12) +#define GPSR2_2 F_(GP2_02, IP0SR2_11_8) +#define GPSR2_1 F_(IPC_CLKOUT, IP0SR2_7_4) +#define GPSR2_0 F_(IPC_CLKIN, IP0SR2_3_0) + +/* GPSR3 */ +#define GPSR3_16 FM(CANFD7_RX) +#define GPSR3_15 FM(CANFD7_TX) +#define GPSR3_14 FM(CANFD6_RX) +#define GPSR3_13 F_(CANFD6_TX, IP1SR3_23_20) +#define GPSR3_12 F_(CANFD5_RX, IP1SR3_19_16) +#define GPSR3_11 F_(CANFD5_TX, IP1SR3_15_12) +#define GPSR3_10 F_(CANFD4_RX, IP1SR3_11_8) +#define GPSR3_9 F_(CANFD4_TX, IP1SR3_7_4) +#define GPSR3_8 F_(CANFD3_RX, IP1SR3_3_0) +#define GPSR3_7 F_(CANFD3_TX, IP0SR3_31_28) +#define GPSR3_6 F_(CANFD2_RX, IP0SR3_27_24) +#define GPSR3_5 F_(CANFD2_TX, IP0SR3_23_20) +#define GPSR3_4 FM(CANFD1_RX) +#define GPSR3_3 FM(CANFD1_TX) +#define GPSR3_2 F_(CANFD0_RX, IP0SR3_11_8) +#define GPSR3_1 F_(CANFD0_TX, IP0SR3_7_4) +#define GPSR3_0 FM(CAN_CLK) + +/* GPSR4 */ +#define GPSR4_26 FM(AVS1) +#define GPSR4_25 FM(AVS0) +#define GPSR4_24 FM(PCIE3_CLKREQ_N) +#define GPSR4_23 FM(PCIE2_CLKREQ_N) +#define GPSR4_22 FM(PCIE1_CLKREQ_N) +#define GPSR4_21 FM(PCIE0_CLKREQ_N) +#define GPSR4_20 F_(AVB0_AVTP_PPS, IP2SR4_19_16) +#define GPSR4_19 F_(AVB0_AVTP_CAPTURE, IP2SR4_15_12) +#define GPSR4_18 F_(AVB0_AVTP_MATCH, IP2SR4_11_8) +#define GPSR4_17 F_(AVB0_LINK, IP2SR4_7_4) +#define GPSR4_16 FM(AVB0_PHY_INT) +#define GPSR4_15 F_(AVB0_MAGIC, IP1SR4_31_28) +#define GPSR4_14 F_(AVB0_MDC, IP1SR4_27_24) +#define GPSR4_13 F_(AVB0_MDIO, IP1SR4_23_20) +#define GPSR4_12 F_(AVB0_TXCREFCLK, IP1SR4_19_16) +#define GPSR4_11 F_(AVB0_TD3, IP1SR4_15_12) +#define GPSR4_10 F_(AVB0_TD2, IP1SR4_11_8) +#define GPSR4_9 F_(AVB0_TD1, IP1SR4_7_4) +#define GPSR4_8 F_(AVB0_TD0, IP1SR4_3_0) +#define GPSR4_7 F_(AVB0_TXC, IP0SR4_31_28) +#define GPSR4_6 F_(AVB0_TX_CTL, IP0SR4_27_24) +#define GPSR4_5 F_(AVB0_RD3, IP0SR4_23_20) +#define GPSR4_4 F_(AVB0_RD2, IP0SR4_19_16) +#define GPSR4_3 F_(AVB0_RD1, IP0SR4_15_12) +#define GPSR4_2 F_(AVB0_RD0, IP0SR4_11_8) +#define GPSR4_1 F_(AVB0_RXC, IP0SR4_7_4) +#define GPSR4_0 F_(AVB0_RX_CTL, IP0SR4_3_0) + +/* GPSR5 */ +#define GPSR5_20 F_(AVB1_AVTP_PPS, IP2SR5_19_16) +#define GPSR5_19 F_(AVB1_AVTP_CAPTURE, IP2SR5_15_12) +#define GPSR5_18 F_(AVB1_AVTP_MATCH, IP2SR5_11_8) +#define GPSR5_17 F_(AVB1_LINK, IP2SR5_7_4) +#define GPSR5_16 FM(AVB1_PHY_INT) +#define GPSR5_15 F_(AVB1_MAGIC, IP1SR5_31_28) +#define GPSR5_14 F_(AVB1_MDC, IP1SR5_27_24) +#define GPSR5_13 F_(AVB1_MDIO, IP1SR5_23_20) +#define GPSR5_12 F_(AVB1_TXCREFCLK, IP1SR5_19_16) +#define GPSR5_11 F_(AVB1_TD3, IP1SR5_15_12) +#define GPSR5_10 F_(AVB1_TD2, IP1SR5_11_8) +#define GPSR5_9 F_(AVB1_TD1, IP1SR5_7_4) +#define GPSR5_8 F_(AVB1_TD0, IP1SR5_3_0) +#define GPSR5_7 F_(AVB1_TXC, IP0SR5_31_28) +#define GPSR5_6 F_(AVB1_TX_CTL, IP0SR5_27_24) +#define GPSR5_5 F_(AVB1_RD3, IP0SR5_23_20) +#define GPSR5_4 F_(AVB1_RD2, IP0SR5_19_16) +#define GPSR5_3 F_(AVB1_RD1, IP0SR5_15_12) +#define GPSR5_2 F_(AVB1_RD0, IP0SR5_11_8) +#define GPSR5_1 F_(AVB1_RXC, IP0SR5_7_4) +#define GPSR5_0 F_(AVB1_RX_CTL, IP0SR5_3_0) + +/* GPSR6 */ +#define GPSR6_20 FM(AVB2_AVTP_PPS) +#define GPSR6_19 FM(AVB2_AVTP_CAPTURE) +#define GPSR6_18 FM(AVB2_AVTP_MATCH) +#define GPSR6_17 FM(AVB2_LINK) +#define GPSR6_16 FM(AVB2_PHY_INT) +#define GPSR6_15 FM(AVB2_MAGIC) +#define GPSR6_14 FM(AVB2_MDC) +#define GPSR6_13 FM(AVB2_MDIO) +#define GPSR6_12 FM(AVB2_TXCREFCLK) +#define GPSR6_11 FM(AVB2_TD3) +#define GPSR6_10 FM(AVB2_TD2) +#define GPSR6_9 FM(AVB2_TD1) +#define GPSR6_8 FM(AVB2_TD0) +#define GPSR6_7 FM(AVB2_TXC) +#define GPSR6_6 FM(AVB2_TX_CTL) +#define GPSR6_5 FM(AVB2_RD3) +#define GPSR6_4 FM(AVB2_RD2) +#define GPSR6_3 FM(AVB2_RD1) +#define GPSR6_2 FM(AVB2_RD0) +#define GPSR6_1 FM(AVB2_RXC) +#define GPSR6_0 FM(AVB2_RX_CTL) + +/* GPSR7 */ +#define GPSR7_20 FM(AVB3_AVTP_PPS) +#define GPSR7_19 FM(AVB3_AVTP_CAPTURE) +#define GPSR7_18 FM(AVB3_AVTP_MATCH) +#define GPSR7_17 FM(AVB3_LINK) +#define GPSR7_16 FM(AVB3_PHY_INT) +#define GPSR7_15 FM(AVB3_MAGIC) +#define GPSR7_14 FM(AVB3_MDC) +#define GPSR7_13 FM(AVB3_MDIO) +#define GPSR7_12 FM(AVB3_TXCREFCLK) +#define GPSR7_11 FM(AVB3_TD3) +#define GPSR7_10 FM(AVB3_TD2) +#define GPSR7_9 FM(AVB3_TD1) +#define GPSR7_8 FM(AVB3_TD0) +#define GPSR7_7 FM(AVB3_TXC) +#define GPSR7_6 FM(AVB3_TX_CTL) +#define GPSR7_5 FM(AVB3_RD3) +#define GPSR7_4 FM(AVB3_RD2) +#define GPSR7_3 FM(AVB3_RD1) +#define GPSR7_2 FM(AVB3_RD0) +#define GPSR7_1 FM(AVB3_RXC) +#define GPSR7_0 FM(AVB3_RX_CTL) + +/* GPSR8 */ +#define GPSR8_20 FM(AVB4_AVTP_PPS) +#define GPSR8_19 FM(AVB4_AVTP_CAPTURE) +#define GPSR8_18 FM(AVB4_AVTP_MATCH) +#define GPSR8_17 FM(AVB4_LINK) +#define GPSR8_16 FM(AVB4_PHY_INT) +#define GPSR8_15 FM(AVB4_MAGIC) +#define GPSR8_14 FM(AVB4_MDC) +#define GPSR8_13 FM(AVB4_MDIO) +#define GPSR8_12 FM(AVB4_TXCREFCLK) +#define GPSR8_11 FM(AVB4_TD3) +#define GPSR8_10 FM(AVB4_TD2) +#define GPSR8_9 FM(AVB4_TD1) +#define GPSR8_8 FM(AVB4_TD0) +#define GPSR8_7 FM(AVB4_TXC) +#define GPSR8_6 FM(AVB4_TX_CTL) +#define GPSR8_5 FM(AVB4_RD3) +#define GPSR8_4 FM(AVB4_RD2) +#define GPSR8_3 FM(AVB4_RD1) +#define GPSR8_2 FM(AVB4_RD0) +#define GPSR8_1 FM(AVB4_RXC) +#define GPSR8_0 FM(AVB4_RX_CTL) + +/* GPSR9 */ +#define GPSR9_20 FM(AVB5_AVTP_PPS) +#define GPSR9_19 FM(AVB5_AVTP_CAPTURE) +#define GPSR9_18 FM(AVB5_AVTP_MATCH) +#define GPSR9_17 FM(AVB5_LINK) +#define GPSR9_16 FM(AVB5_PHY_INT) +#define GPSR9_15 FM(AVB5_MAGIC) +#define GPSR9_14 FM(AVB5_MDC) +#define GPSR9_13 FM(AVB5_MDIO) +#define GPSR9_12 FM(AVB5_TXCREFCLK) +#define GPSR9_11 FM(AVB5_TD3) +#define GPSR9_10 FM(AVB5_TD2) +#define GPSR9_9 FM(AVB5_TD1) +#define GPSR9_8 FM(AVB5_TD0) +#define GPSR9_7 FM(AVB5_TXC) +#define GPSR9_6 FM(AVB5_TX_CTL) +#define GPSR9_5 FM(AVB5_RD3) +#define GPSR9_4 FM(AVB5_RD2) +#define GPSR9_3 FM(AVB5_RD1) +#define GPSR9_2 FM(AVB5_RD0) +#define GPSR9_1 FM(AVB5_RXC) +#define GPSR9_0 FM(AVB5_RX_CTL) + +/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP0SR1_3_0 FM(SCIF_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_7_4 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_11_8 FM(HSCK0) FM(SCK0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_15_12 FM(HRTS0_N) FM(RTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_19_16 FM(HCTS0_N) FM(CTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_23_20 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_27_24 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_31_28 FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR3) FM(A7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP1SR1_3_0 FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR4) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_7_4 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_11_8 FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_15_12 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR7) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_19_16 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DG2) FM(A12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_23_20 FM(MSIOF1_TXD) FM(HRX3) FM(SCK3) F_(0, 0) FM(DU_DG3) FM(A13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_27_24 FM(MSIOF1_SCK) FM(HSCK3) FM(CTS3_N) F_(0, 0) FM(DU_DG4) FM(A14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR1_31_28 FM(MSIOF1_SYNC) FM(HRTS3_N) FM(RTS3_N) F_(0, 0) FM(DU_DG5) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP2SR1_3_0 FM(MSIOF1_SS1) FM(HCTS3_N) FM(RX3) F_(0, 0) FM(DU_DG6) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_7_4 FM(MSIOF1_SS2) FM(HTX3) FM(TX3) F_(0, 0) FM(DU_DG7) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) FM(DU_DB2) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_15_12 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) FM(DU_DB3) FM(A19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_19_16 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) FM(DU_DB4) FM(A20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_23_20 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1_A) F_(0, 0) FM(DU_DB5) FM(A21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1_A) F_(0, 0) FM(DU_DB6) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR1_31_28 FM(MSIOF2_SS2) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(DU_DB7) FM(A23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP3SR1_3_0 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKOUT) FM(A24) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_7_4 FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_HSYNC) FM(A25) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_11_8 FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_VSYNC) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_15_12 FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_ODDF_DISP_CDE) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_19_16 FM(GP1_28) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_23_20 FM(GP1_29) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_27_24 FM(GP1_30) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3SR1_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP0SR2_3_0 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_7_4 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_11_8 FM(GP2_02) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_15_12 FM(GP2_03) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_19_16 FM(GP2_04) F_(0, 0) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) FM(D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_23_20 FM(GP2_05) FM(HSCK2) FM(MSIOF4_TXD) FM(SCK4) F_(0, 0) FM(D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_27_24 FM(GP2_06) FM(HCTS2_N) FM(MSIOF4_SCK) FM(CTS4_N) F_(0, 0) FM(D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR2_31_28 FM(GP2_07) FM(HRTS2_N) FM(MSIOF4_SYNC) FM(RTS4_N) F_(0, 0) FM(D8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP1SR2_3_0 FM(GP2_08) FM(HRX2) FM(MSIOF4_SS1) FM(RX4) F_(0, 0) FM(D9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_7_4 FM(GP2_09) FM(HTX2) FM(MSIOF4_SS2) FM(TX4) F_(0, 0) FM(D10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_11_8 FM(GP2_10) FM(TCLK2_B) FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) FM(D11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_15_12 FM(GP2_11) FM(TCLK3) FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) FM(D12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_19_16 FM(GP2_12) FM(TCLK4) FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) FM(D13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_23_20 FM(GP2_13) F_(0, 0) FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_27_24 FM(GP2_14) FM(IRQ4) FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR2_31_28 FM(GP2_15) FM(IRQ5) FM(MSIOF5_SS2) FM(CPG_CPCKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP2SR2_3_0 FM(FXR_TXDA_A) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR2_7_4 FM(RXDA_EXTFXR_A) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) FM(BS_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR2_11_8 FM(FXR_TXDB) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(RD_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR2_15_12 FM(RXDB_EXTFXR) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(WE0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR2_19_16 FM(CLK_EXTFXR) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR2_23_20 FM(TPU0TO0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(RD_WR_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR2_27_24 FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR2_31_28 FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(EX_WAIT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP0SR3_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_7_4 FM(CANFD0_TX) FM(FXR_TXDA_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_11_8 FM(CANFD0_RX) FM(RXDA_EXTFXR_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_15_12 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_19_16 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_23_20 FM(CANFD2_TX) FM(TPU0TO2) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_27_24 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR3_31_28 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP1SR3_3_0 FM(CANFD3_RX) F_(0, 0) FM(PWM3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_7_4 FM(CANFD4_TX) F_(0, 0) FM(PWM4) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_11_8 FM(CANFD4_RX) F_(0, 0) F_(0, 0) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_15_12 FM(CANFD5_TX) F_(0, 0) F_(0, 0) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_19_16 FM(CANFD5_RX) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_23_20 FM(CANFD6_TX) F_(0, 0) F_(0, 0) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR3_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP0SR4_3_0 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_7_4 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_15_12 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_23_20 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_27_24 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR4_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP1SR4_3_0 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_7_4 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_11_8 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_19_16 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_23_20 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_27_24 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR4_31_28 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP2SR4_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_7_4 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_15_12 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_19_16 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR4_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP0SR5_3_0 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_7_4 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_11_8 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_15_12 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_19_16 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_23_20 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_27_24 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR5_31_28 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP1SR5_3_0 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_7_4 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_11_8 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_15_12 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_23_20 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_27_24 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR5_31_28 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP2SR5_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_7_4 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_11_8 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_19_16 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR5_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +#define PINMUX_GPSR \ + \ + GPSR1_30 \ + GPSR1_29 \ + GPSR1_28 \ +GPSR0_27 GPSR1_27 \ +GPSR0_26 GPSR1_26 GPSR4_26 \ +GPSR0_25 GPSR1_25 GPSR4_25 \ +GPSR0_24 GPSR1_24 GPSR2_24 GPSR4_24 \ +GPSR0_23 GPSR1_23 GPSR2_23 GPSR4_23 \ +GPSR0_22 GPSR1_22 GPSR2_22 GPSR4_22 \ +GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \ +GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 GPSR6_20 GPSR7_20 GPSR8_20 GPSR9_20 \ +GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 GPSR6_19 GPSR7_19 GPSR8_19 GPSR9_19 \ +GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 GPSR6_18 GPSR7_18 GPSR8_18 GPSR9_18 \ +GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 GPSR6_17 GPSR7_17 GPSR8_17 GPSR9_17 \ +GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 GPSR5_16 GPSR6_16 GPSR7_16 GPSR8_16 GPSR9_16 \ +GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 GPSR8_15 GPSR9_15 \ +GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 GPSR8_14 GPSR9_14 \ +GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 GPSR8_13 GPSR9_13 \ +GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 GPSR8_12 GPSR9_12 \ +GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 GPSR8_11 GPSR9_11 \ +GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 GPSR8_10 GPSR9_10 \ +GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 GPSR8_9 GPSR9_9 \ +GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 GPSR8_8 GPSR9_8 \ +GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 GPSR8_7 GPSR9_7 \ +GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 GPSR8_6 GPSR9_6 \ +GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 GPSR8_5 GPSR9_5 \ +GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 GPSR8_4 GPSR9_4 \ +GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 GPSR8_3 GPSR9_3 \ +GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 GPSR8_2 GPSR9_2 \ +GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 GPSR8_1 GPSR9_1 \ +GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 GPSR8_0 GPSR9_0 + +#define PINMUX_IPSR \ +\ +FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \ +FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \ +FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \ +FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \ +FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \ +FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 FM(IP3SR1_23_20) IP3SR1_23_20 \ +FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 FM(IP3SR1_27_24) IP3SR1_27_24 \ +FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 FM(IP3SR1_31_28) IP3SR1_31_28 \ +\ +FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \ +FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \ +FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 FM(IP2SR2_11_8) IP2SR2_11_8 \ +FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \ +FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 FM(IP2SR2_19_16) IP2SR2_19_16 \ +FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 FM(IP2SR2_23_20) IP2SR2_23_20 \ +FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 FM(IP2SR2_27_24) IP2SR2_27_24 \ +FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 FM(IP2SR2_31_28) IP2SR2_31_28 \ +\ +FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 \ +FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 \ +FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 \ +FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 \ +FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 \ +FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 \ +FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 \ +FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 \ +\ +FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP2SR4_3_0) IP2SR4_3_0 \ +FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 FM(IP2SR4_7_4) IP2SR4_7_4 \ +FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 FM(IP2SR4_11_8) IP2SR4_11_8 \ +FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 FM(IP2SR4_15_12) IP2SR4_15_12 \ +FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 FM(IP2SR4_19_16) IP2SR4_19_16 \ +FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \ +FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 FM(IP2SR4_27_24) IP2SR4_27_24 \ +FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \ +\ +FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \ +FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \ +FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \ +FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \ +FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \ +FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 FM(IP2SR5_23_20) IP2SR5_23_20 \ +FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 FM(IP2SR5_27_24) IP2SR5_27_24 \ +FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 FM(IP2SR5_31_28) IP2SR5_31_28 + +/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ +#define MOD_SEL2_14_15 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3) +#define MOD_SEL2_12_13 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3) +#define MOD_SEL2_10_11 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3) +#define MOD_SEL2_8_9 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3) +#define MOD_SEL2_6_7 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3) +#define MOD_SEL2_4_5 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3) +#define MOD_SEL2_2_3 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3) + +#define PINMUX_MOD_SELS \ +\ +MOD_SEL2_14_15 \ +MOD_SEL2_12_13 \ +MOD_SEL2_10_11 \ +MOD_SEL2_8_9 \ +MOD_SEL2_6_7 \ +MOD_SEL2_4_5 \ +MOD_SEL2_2_3 + +#define PINMUX_PHYS \ + FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \ + FM(SCL4) FM(SDA4) FM(SCL5) FM(SDA5) FM(SCL6) FM(SDA6) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + +#define F_(x, y) +#define FM(x) FN_##x, + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_FUNCTION_END, +#undef F_ +#undef FM + +#define F_(x, y) +#define FM(x) x##_MARK, + PINMUX_MARK_BEGIN, + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_PHYS + PINMUX_MARK_END, +#undef F_ +#undef FM +}; + +static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), + + PINMUX_SINGLE(MMC_D7), + PINMUX_SINGLE(MMC_D6), + PINMUX_SINGLE(MMC_D5), + PINMUX_SINGLE(MMC_D4), + PINMUX_SINGLE(MMC_SD_CLK), + PINMUX_SINGLE(MMC_SD_D3), + PINMUX_SINGLE(MMC_SD_D2), + PINMUX_SINGLE(MMC_SD_D1), + PINMUX_SINGLE(MMC_SD_D0), + PINMUX_SINGLE(MMC_SD_CMD), + PINMUX_SINGLE(MMC_DS), + + PINMUX_SINGLE(SD_CD), + PINMUX_SINGLE(SD_WP), + + PINMUX_SINGLE(RPC_INT_N), + PINMUX_SINGLE(RPC_WP_N), + PINMUX_SINGLE(RPC_RESET_N), + + PINMUX_SINGLE(QSPI1_SSL), + PINMUX_SINGLE(QSPI1_IO3), + PINMUX_SINGLE(QSPI1_IO2), + PINMUX_SINGLE(QSPI1_MISO_IO1), + PINMUX_SINGLE(QSPI1_MOSI_IO0), + PINMUX_SINGLE(QSPI1_SPCLK), + PINMUX_SINGLE(QSPI0_SSL), + PINMUX_SINGLE(QSPI0_IO3), + PINMUX_SINGLE(QSPI0_IO2), + PINMUX_SINGLE(QSPI0_MISO_IO1), + PINMUX_SINGLE(QSPI0_MOSI_IO0), + PINMUX_SINGLE(QSPI0_SPCLK), + + PINMUX_SINGLE(TCLK2_A), + + PINMUX_SINGLE(CANFD7_RX), + PINMUX_SINGLE(CANFD7_TX), + PINMUX_SINGLE(CANFD6_RX), + PINMUX_SINGLE(CANFD1_RX), + PINMUX_SINGLE(CANFD1_TX), + PINMUX_SINGLE(CAN_CLK), + + PINMUX_SINGLE(AVS1), + PINMUX_SINGLE(AVS0), + + PINMUX_SINGLE(PCIE3_CLKREQ_N), + PINMUX_SINGLE(PCIE2_CLKREQ_N), + PINMUX_SINGLE(PCIE1_CLKREQ_N), + PINMUX_SINGLE(PCIE0_CLKREQ_N), + + PINMUX_SINGLE(AVB0_PHY_INT), + PINMUX_SINGLE(AVB0_MAGIC), + PINMUX_SINGLE(AVB0_MDC), + PINMUX_SINGLE(AVB0_MDIO), + PINMUX_SINGLE(AVB0_TXCREFCLK), + + PINMUX_SINGLE(AVB1_PHY_INT), + PINMUX_SINGLE(AVB1_MAGIC), + PINMUX_SINGLE(AVB1_MDC), + PINMUX_SINGLE(AVB1_MDIO), + PINMUX_SINGLE(AVB1_TXCREFCLK), + + PINMUX_SINGLE(AVB2_AVTP_PPS), + PINMUX_SINGLE(AVB2_AVTP_CAPTURE), + PINMUX_SINGLE(AVB2_AVTP_MATCH), + PINMUX_SINGLE(AVB2_LINK), + PINMUX_SINGLE(AVB2_PHY_INT), + PINMUX_SINGLE(AVB2_MAGIC), + PINMUX_SINGLE(AVB2_MDC), + PINMUX_SINGLE(AVB2_MDIO), + PINMUX_SINGLE(AVB2_TXCREFCLK), + PINMUX_SINGLE(AVB2_TD3), + PINMUX_SINGLE(AVB2_TD2), + PINMUX_SINGLE(AVB2_TD1), + PINMUX_SINGLE(AVB2_TD0), + PINMUX_SINGLE(AVB2_TXC), + PINMUX_SINGLE(AVB2_TX_CTL), + PINMUX_SINGLE(AVB2_RD3), + PINMUX_SINGLE(AVB2_RD2), + PINMUX_SINGLE(AVB2_RD1), + PINMUX_SINGLE(AVB2_RD0), + PINMUX_SINGLE(AVB2_RXC), + PINMUX_SINGLE(AVB2_RX_CTL), + + PINMUX_SINGLE(AVB3_AVTP_PPS), + PINMUX_SINGLE(AVB3_AVTP_CAPTURE), + PINMUX_SINGLE(AVB3_AVTP_MATCH), + PINMUX_SINGLE(AVB3_LINK), + PINMUX_SINGLE(AVB3_PHY_INT), + PINMUX_SINGLE(AVB3_MAGIC), + PINMUX_SINGLE(AVB3_MDC), + PINMUX_SINGLE(AVB3_MDIO), + PINMUX_SINGLE(AVB3_TXCREFCLK), + PINMUX_SINGLE(AVB3_TD3), + PINMUX_SINGLE(AVB3_TD2), + PINMUX_SINGLE(AVB3_TD1), + PINMUX_SINGLE(AVB3_TD0), + PINMUX_SINGLE(AVB3_TXC), + PINMUX_SINGLE(AVB3_TX_CTL), + PINMUX_SINGLE(AVB3_RD3), + PINMUX_SINGLE(AVB3_RD2), + PINMUX_SINGLE(AVB3_RD1), + PINMUX_SINGLE(AVB3_RD0), + PINMUX_SINGLE(AVB3_RXC), + PINMUX_SINGLE(AVB3_RX_CTL), + + PINMUX_SINGLE(AVB4_AVTP_PPS), + PINMUX_SINGLE(AVB4_AVTP_CAPTURE), + PINMUX_SINGLE(AVB4_AVTP_MATCH), + PINMUX_SINGLE(AVB4_LINK), + PINMUX_SINGLE(AVB4_PHY_INT), + PINMUX_SINGLE(AVB4_MAGIC), + PINMUX_SINGLE(AVB4_MDC), + PINMUX_SINGLE(AVB4_MDIO), + PINMUX_SINGLE(AVB4_TXCREFCLK), + PINMUX_SINGLE(AVB4_TD3), + PINMUX_SINGLE(AVB4_TD2), + PINMUX_SINGLE(AVB4_TD1), + PINMUX_SINGLE(AVB4_TD0), + PINMUX_SINGLE(AVB4_TXC), + PINMUX_SINGLE(AVB4_TX_CTL), + PINMUX_SINGLE(AVB4_RD3), + PINMUX_SINGLE(AVB4_RD2), + PINMUX_SINGLE(AVB4_RD1), + PINMUX_SINGLE(AVB4_RD0), + PINMUX_SINGLE(AVB4_RXC), + PINMUX_SINGLE(AVB4_RX_CTL), + + PINMUX_SINGLE(AVB5_AVTP_PPS), + PINMUX_SINGLE(AVB5_AVTP_CAPTURE), + PINMUX_SINGLE(AVB5_AVTP_MATCH), + PINMUX_SINGLE(AVB5_LINK), + PINMUX_SINGLE(AVB5_PHY_INT), + PINMUX_SINGLE(AVB5_MAGIC), + PINMUX_SINGLE(AVB5_MDC), + PINMUX_SINGLE(AVB5_MDIO), + PINMUX_SINGLE(AVB5_TXCREFCLK), + PINMUX_SINGLE(AVB5_TD3), + PINMUX_SINGLE(AVB5_TD2), + PINMUX_SINGLE(AVB5_TD1), + PINMUX_SINGLE(AVB5_TD0), + PINMUX_SINGLE(AVB5_TXC), + PINMUX_SINGLE(AVB5_TX_CTL), + PINMUX_SINGLE(AVB5_RD3), + PINMUX_SINGLE(AVB5_RD2), + PINMUX_SINGLE(AVB5_RD1), + PINMUX_SINGLE(AVB5_RD0), + PINMUX_SINGLE(AVB5_RXC), + PINMUX_SINGLE(AVB5_RX_CTL), + + /* IP0SR1 */ + PINMUX_IPSR_GPSR(IP0SR1_3_0, SCIF_CLK), + PINMUX_IPSR_GPSR(IP0SR1_3_0, A0), + + PINMUX_IPSR_GPSR(IP0SR1_7_4, HRX0), + PINMUX_IPSR_GPSR(IP0SR1_7_4, RX0), + PINMUX_IPSR_GPSR(IP0SR1_7_4, A1), + + PINMUX_IPSR_GPSR(IP0SR1_11_8, HSCK0), + PINMUX_IPSR_GPSR(IP0SR1_11_8, SCK0), + PINMUX_IPSR_GPSR(IP0SR1_11_8, A2), + + PINMUX_IPSR_GPSR(IP0SR1_15_12, HRTS0_N), + PINMUX_IPSR_GPSR(IP0SR1_15_12, RTS0_N), + PINMUX_IPSR_GPSR(IP0SR1_15_12, A3), + + PINMUX_IPSR_GPSR(IP0SR1_19_16, HCTS0_N), + PINMUX_IPSR_GPSR(IP0SR1_19_16, CTS0_N), + PINMUX_IPSR_GPSR(IP0SR1_19_16, A4), + + PINMUX_IPSR_GPSR(IP0SR1_23_20, HTX0), + PINMUX_IPSR_GPSR(IP0SR1_23_20, TX0), + PINMUX_IPSR_GPSR(IP0SR1_23_20, A5), + + PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_RXD), + PINMUX_IPSR_GPSR(IP0SR1_27_24, DU_DR2), + PINMUX_IPSR_GPSR(IP0SR1_27_24, A6), + + PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_TXD), + PINMUX_IPSR_GPSR(IP0SR1_31_28, DU_DR3), + PINMUX_IPSR_GPSR(IP0SR1_31_28, A7), + + /* IP1SR1 */ + PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SCK), + PINMUX_IPSR_GPSR(IP1SR1_3_0, DU_DR4), + PINMUX_IPSR_GPSR(IP1SR1_3_0, A8), + + PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_SYNC), + PINMUX_IPSR_GPSR(IP1SR1_7_4, DU_DR5), + PINMUX_IPSR_GPSR(IP1SR1_7_4, A9), + + PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SS1), + PINMUX_IPSR_GPSR(IP1SR1_11_8, DU_DR6), + PINMUX_IPSR_GPSR(IP1SR1_11_8, A10), + + PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_SS2), + PINMUX_IPSR_GPSR(IP1SR1_15_12, DU_DR7), + PINMUX_IPSR_GPSR(IP1SR1_15_12, A11), + + PINMUX_IPSR_GPSR(IP1SR1_19_16, MSIOF1_RXD), + PINMUX_IPSR_GPSR(IP1SR1_19_16, DU_DG2), + PINMUX_IPSR_GPSR(IP1SR1_19_16, A12), + + PINMUX_IPSR_GPSR(IP1SR1_23_20, MSIOF1_TXD), + PINMUX_IPSR_GPSR(IP1SR1_23_20, HRX3), + PINMUX_IPSR_GPSR(IP1SR1_23_20, SCK3), + PINMUX_IPSR_GPSR(IP1SR1_23_20, DU_DG3), + PINMUX_IPSR_GPSR(IP1SR1_23_20, A13), + + PINMUX_IPSR_GPSR(IP1SR1_27_24, MSIOF1_SCK), + PINMUX_IPSR_GPSR(IP1SR1_27_24, HSCK3), + PINMUX_IPSR_GPSR(IP1SR1_27_24, CTS3_N), + PINMUX_IPSR_GPSR(IP1SR1_27_24, DU_DG4), + PINMUX_IPSR_GPSR(IP1SR1_27_24, A14), + + PINMUX_IPSR_GPSR(IP1SR1_31_28, MSIOF1_SYNC), + PINMUX_IPSR_GPSR(IP1SR1_31_28, HRTS3_N), + PINMUX_IPSR_GPSR(IP1SR1_31_28, RTS3_N), + PINMUX_IPSR_GPSR(IP1SR1_31_28, DU_DG5), + PINMUX_IPSR_GPSR(IP1SR1_31_28, A15), + + /* IP2SR1 */ + PINMUX_IPSR_GPSR(IP2SR1_3_0, MSIOF1_SS1), + PINMUX_IPSR_GPSR(IP2SR1_3_0, HCTS3_N), + PINMUX_IPSR_GPSR(IP2SR1_3_0, RX3), + PINMUX_IPSR_GPSR(IP2SR1_3_0, DU_DG6), + PINMUX_IPSR_GPSR(IP2SR1_3_0, A16), + + PINMUX_IPSR_GPSR(IP2SR1_7_4, MSIOF1_SS2), + PINMUX_IPSR_GPSR(IP2SR1_7_4, HTX3), + PINMUX_IPSR_GPSR(IP2SR1_7_4, TX3), + PINMUX_IPSR_GPSR(IP2SR1_7_4, DU_DG7), + PINMUX_IPSR_GPSR(IP2SR1_7_4, A17), + + PINMUX_IPSR_GPSR(IP2SR1_11_8, MSIOF2_RXD), + PINMUX_IPSR_GPSR(IP2SR1_11_8, HSCK1), + PINMUX_IPSR_GPSR(IP2SR1_11_8, SCK1), + PINMUX_IPSR_GPSR(IP2SR1_11_8, DU_DB2), + PINMUX_IPSR_GPSR(IP2SR1_11_8, A18), + + PINMUX_IPSR_GPSR(IP2SR1_15_12, MSIOF2_TXD), + PINMUX_IPSR_GPSR(IP2SR1_15_12, HCTS1_N), + PINMUX_IPSR_GPSR(IP2SR1_15_12, CTS1_N), + PINMUX_IPSR_GPSR(IP2SR1_15_12, DU_DB3), + PINMUX_IPSR_GPSR(IP2SR1_15_12, A19), + + PINMUX_IPSR_GPSR(IP2SR1_19_16, MSIOF2_SCK), + PINMUX_IPSR_GPSR(IP2SR1_19_16, HRTS1_N), + PINMUX_IPSR_GPSR(IP2SR1_19_16, RTS1_N), + PINMUX_IPSR_GPSR(IP2SR1_19_16, DU_DB4), + PINMUX_IPSR_GPSR(IP2SR1_19_16, A20), + + PINMUX_IPSR_GPSR(IP2SR1_23_20, MSIOF2_SYNC), + PINMUX_IPSR_GPSR(IP2SR1_23_20, HRX1), + PINMUX_IPSR_GPSR(IP2SR1_23_20, RX1_A), + PINMUX_IPSR_GPSR(IP2SR1_23_20, DU_DB5), + PINMUX_IPSR_GPSR(IP2SR1_23_20, A21), + + PINMUX_IPSR_GPSR(IP2SR1_27_24, MSIOF2_SS1), + PINMUX_IPSR_GPSR(IP2SR1_27_24, HTX1), + PINMUX_IPSR_GPSR(IP2SR1_27_24, TX1_A), + PINMUX_IPSR_GPSR(IP2SR1_27_24, DU_DB6), + PINMUX_IPSR_GPSR(IP2SR1_27_24, A22), + + PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF2_SS2), + PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK1_B), + PINMUX_IPSR_GPSR(IP2SR1_31_28, DU_DB7), + PINMUX_IPSR_GPSR(IP2SR1_31_28, A23), + + /* IP3SR1 */ + PINMUX_IPSR_GPSR(IP3SR1_3_0, IRQ0), + PINMUX_IPSR_GPSR(IP3SR1_3_0, DU_DOTCLKOUT), + PINMUX_IPSR_GPSR(IP3SR1_3_0, A24), + + PINMUX_IPSR_GPSR(IP3SR1_7_4, IRQ1), + PINMUX_IPSR_GPSR(IP3SR1_7_4, DU_HSYNC), + PINMUX_IPSR_GPSR(IP3SR1_7_4, A25), + + PINMUX_IPSR_GPSR(IP3SR1_11_8, IRQ2), + PINMUX_IPSR_GPSR(IP3SR1_11_8, DU_VSYNC), + PINMUX_IPSR_GPSR(IP3SR1_11_8, CS1_N_A26), + + PINMUX_IPSR_GPSR(IP3SR1_15_12, IRQ3), + PINMUX_IPSR_GPSR(IP3SR1_15_12, DU_ODDF_DISP_CDE), + PINMUX_IPSR_GPSR(IP3SR1_15_12, CS0_N), + + PINMUX_IPSR_GPSR(IP3SR1_19_16, GP1_28), + PINMUX_IPSR_GPSR(IP3SR1_19_16, D0), + + PINMUX_IPSR_GPSR(IP3SR1_23_20, GP1_29), + PINMUX_IPSR_GPSR(IP3SR1_23_20, D1), + + PINMUX_IPSR_GPSR(IP3SR1_27_24, GP1_30), + PINMUX_IPSR_GPSR(IP3SR1_27_24, D2), + + /* IP0SR2 */ + PINMUX_IPSR_GPSR(IP0SR2_3_0, IPC_CLKIN), + PINMUX_IPSR_GPSR(IP0SR2_3_0, IPC_CLKEN_IN), + PINMUX_IPSR_GPSR(IP0SR2_3_0, DU_DOTCLKIN), + + PINMUX_IPSR_GPSR(IP0SR2_7_4, IPC_CLKOUT), + PINMUX_IPSR_GPSR(IP0SR2_7_4, IPC_CLKEN_OUT), + + /* GP2_02 = SCL0 */ + PINMUX_IPSR_MSEL(IP0SR2_11_8, GP2_02, SEL_I2C0_0), + PINMUX_IPSR_MSEL(IP0SR2_11_8, D3, SEL_I2C0_0), + PINMUX_IPSR_PHYS(IP0SR2_11_8, SCL0, SEL_I2C0_3), + + /* GP2_03 = SDA0 */ + PINMUX_IPSR_MSEL(IP0SR2_15_12, GP2_03, SEL_I2C0_0), + PINMUX_IPSR_MSEL(IP0SR2_15_12, D4, SEL_I2C0_0), + PINMUX_IPSR_PHYS(IP0SR2_15_12, SDA0, SEL_I2C0_3), + + /* GP2_04 = SCL1 */ + PINMUX_IPSR_MSEL(IP0SR2_19_16, GP2_04, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR2_19_16, MSIOF4_RXD, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR2_19_16, D5, SEL_I2C1_0), + PINMUX_IPSR_PHYS(IP0SR2_19_16, SCL1, SEL_I2C1_3), + + /* GP2_05 = SDA1 */ + PINMUX_IPSR_MSEL(IP0SR2_23_20, GP2_05, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR2_23_20, HSCK2, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR2_23_20, MSIOF4_TXD, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR2_23_20, SCK4, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR2_23_20, D6, SEL_I2C1_0), + PINMUX_IPSR_PHYS(IP0SR2_23_20, SDA1, SEL_I2C1_3), + + /* GP2_06 = SCL2 */ + PINMUX_IPSR_MSEL(IP0SR2_27_24, GP2_06, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR2_27_24, HCTS2_N, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR2_27_24, MSIOF4_SCK, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR2_27_24, CTS4_N, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR2_27_24, D7, SEL_I2C2_0), + PINMUX_IPSR_PHYS(IP0SR2_27_24, SCL2, SEL_I2C2_3), + + /* GP2_07 = SDA2 */ + PINMUX_IPSR_MSEL(IP0SR2_31_28, GP2_07, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR2_31_28, HRTS2_N, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR2_31_28, MSIOF4_SYNC, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR2_31_28, RTS4_N, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR2_31_28, D8, SEL_I2C2_0), + PINMUX_IPSR_PHYS(IP0SR2_31_28, SDA2, SEL_I2C2_3), + + /* GP2_08 = SCL3 */ + PINMUX_IPSR_MSEL(IP1SR2_3_0, GP2_08, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP1SR2_3_0, HRX2, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP1SR2_3_0, MSIOF4_SS1, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP1SR2_3_0, RX4, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP1SR2_3_0, D9, SEL_I2C3_0), + PINMUX_IPSR_PHYS(IP1SR2_3_0, SCL3, SEL_I2C3_3), + + /* GP2_09 = SDA3 */ + PINMUX_IPSR_MSEL(IP1SR2_7_4, GP2_09, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP1SR2_7_4, HTX2, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP1SR2_7_4, MSIOF4_SS2, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP1SR2_7_4, TX4, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP1SR2_7_4, D10, SEL_I2C3_0), + PINMUX_IPSR_PHYS(IP1SR2_7_4, SDA3, SEL_I2C3_3), + + /* GP2_10 = SCL4 */ + PINMUX_IPSR_MSEL(IP1SR2_11_8, GP2_10, SEL_I2C4_0), + PINMUX_IPSR_MSEL(IP1SR2_11_8, TCLK2_B, SEL_I2C4_0), + PINMUX_IPSR_MSEL(IP1SR2_11_8, MSIOF5_RXD, SEL_I2C4_0), + PINMUX_IPSR_MSEL(IP1SR2_11_8, D11, SEL_I2C4_0), + PINMUX_IPSR_PHYS(IP1SR2_11_8, SCL4, SEL_I2C4_3), + + /* GP2_11 = SDA4 */ + PINMUX_IPSR_MSEL(IP1SR2_15_12, GP2_11, SEL_I2C4_0), + PINMUX_IPSR_MSEL(IP1SR2_15_12, TCLK3, SEL_I2C4_0), + PINMUX_IPSR_MSEL(IP1SR2_15_12, MSIOF5_TXD, SEL_I2C4_0), + PINMUX_IPSR_MSEL(IP1SR2_15_12, D12, SEL_I2C4_0), + PINMUX_IPSR_PHYS(IP1SR2_15_12, SDA4, SEL_I2C4_3), + + /* GP2_12 = SCL5 */ + PINMUX_IPSR_MSEL(IP1SR2_19_16, GP2_12, SEL_I2C5_0), + PINMUX_IPSR_MSEL(IP1SR2_19_16, TCLK4, SEL_I2C5_0), + PINMUX_IPSR_MSEL(IP1SR2_19_16, MSIOF5_SCK, SEL_I2C5_0), + PINMUX_IPSR_MSEL(IP1SR2_19_16, D13, SEL_I2C5_0), + PINMUX_IPSR_PHYS(IP1SR2_19_16, SCL5, SEL_I2C5_3), + + /* GP2_13 = SDA5 */ + PINMUX_IPSR_MSEL(IP1SR2_23_20, GP2_13, SEL_I2C5_0), + PINMUX_IPSR_MSEL(IP1SR2_23_20, MSIOF5_SYNC, SEL_I2C5_0), + PINMUX_IPSR_MSEL(IP1SR2_23_20, D14, SEL_I2C5_0), + PINMUX_IPSR_PHYS(IP1SR2_23_20, SDA5, SEL_I2C5_3), + + /* GP2_14 = SCL6 */ + PINMUX_IPSR_MSEL(IP1SR2_27_24, GP2_14, SEL_I2C6_0), + PINMUX_IPSR_MSEL(IP1SR2_27_24, IRQ4, SEL_I2C6_0), + PINMUX_IPSR_MSEL(IP1SR2_27_24, MSIOF5_SS1, SEL_I2C6_0), + PINMUX_IPSR_MSEL(IP1SR2_27_24, D15, SEL_I2C6_0), + PINMUX_IPSR_PHYS(IP1SR2_27_24, SCL6, SEL_I2C6_3), + + /* GP2_15 = SDA6 */ + PINMUX_IPSR_MSEL(IP1SR2_31_28, GP2_15, SEL_I2C6_0), + PINMUX_IPSR_MSEL(IP1SR2_31_28, IRQ5, SEL_I2C6_0), + PINMUX_IPSR_MSEL(IP1SR2_31_28, MSIOF5_SS2, SEL_I2C6_0), + PINMUX_IPSR_MSEL(IP1SR2_31_28, CPG_CPCKOUT, SEL_I2C6_0), + PINMUX_IPSR_PHYS(IP1SR2_31_28, SDA6, SEL_I2C6_3), + + /* IP2SR2 */ + PINMUX_IPSR_GPSR(IP2SR2_3_0, FXR_TXDA_A), + PINMUX_IPSR_GPSR(IP2SR2_3_0, MSIOF3_SS1), + + PINMUX_IPSR_GPSR(IP2SR2_7_4, RXDA_EXTFXR_A), + PINMUX_IPSR_GPSR(IP2SR2_7_4, MSIOF3_SS2), + PINMUX_IPSR_GPSR(IP2SR2_7_4, BS_N), + + PINMUX_IPSR_GPSR(IP2SR2_11_8, FXR_TXDB), + PINMUX_IPSR_GPSR(IP2SR2_11_8, MSIOF3_RXD), + PINMUX_IPSR_GPSR(IP2SR2_11_8, RD_N), + + PINMUX_IPSR_GPSR(IP2SR2_15_12, RXDB_EXTFXR), + PINMUX_IPSR_GPSR(IP2SR2_15_12, MSIOF3_TXD), + PINMUX_IPSR_GPSR(IP2SR2_15_12, WE0_N), + + PINMUX_IPSR_GPSR(IP2SR2_19_16, CLK_EXTFXR), + PINMUX_IPSR_GPSR(IP2SR2_19_16, MSIOF3_SCK), + PINMUX_IPSR_GPSR(IP2SR2_19_16, WE1_N), + + PINMUX_IPSR_GPSR(IP2SR2_23_20, TPU0TO0), + PINMUX_IPSR_GPSR(IP2SR2_23_20, MSIOF3_SYNC), + PINMUX_IPSR_GPSR(IP2SR2_23_20, RD_WR_N), + + PINMUX_IPSR_GPSR(IP2SR2_27_24, TPU0TO1), + PINMUX_IPSR_GPSR(IP2SR2_27_24, CLKOUT), + + PINMUX_IPSR_GPSR(IP2SR2_31_28, TCLK1_A), + PINMUX_IPSR_GPSR(IP2SR2_31_28, EX_WAIT0), + + /* IP0SR3 */ + PINMUX_IPSR_GPSR(IP0SR3_7_4, CANFD0_TX), + PINMUX_IPSR_GPSR(IP0SR3_7_4, FXR_TXDA_B), + PINMUX_IPSR_GPSR(IP0SR3_7_4, TX1_B), + + PINMUX_IPSR_GPSR(IP0SR3_11_8, CANFD0_RX), + PINMUX_IPSR_GPSR(IP0SR3_11_8, RXDA_EXTFXR_B), + PINMUX_IPSR_GPSR(IP0SR3_11_8, RX1_B), + + PINMUX_IPSR_GPSR(IP0SR3_23_20, CANFD2_TX), + PINMUX_IPSR_GPSR(IP0SR3_23_20, TPU0TO2), + PINMUX_IPSR_GPSR(IP0SR3_23_20, PWM0), + + PINMUX_IPSR_GPSR(IP0SR3_27_24, CANFD2_RX), + PINMUX_IPSR_GPSR(IP0SR3_27_24, TPU0TO3), + PINMUX_IPSR_GPSR(IP0SR3_27_24, PWM1), + + PINMUX_IPSR_GPSR(IP0SR3_31_28, CANFD3_TX), + PINMUX_IPSR_GPSR(IP0SR3_31_28, PWM2), + + /* IP1SR3 */ + PINMUX_IPSR_GPSR(IP1SR3_3_0, CANFD3_RX), + PINMUX_IPSR_GPSR(IP1SR3_3_0, PWM3), + + PINMUX_IPSR_GPSR(IP1SR3_7_4, CANFD4_TX), + PINMUX_IPSR_GPSR(IP1SR3_7_4, PWM4), + PINMUX_IPSR_GPSR(IP1SR3_7_4, FXR_CLKOUT1), + + PINMUX_IPSR_GPSR(IP1SR3_11_8, CANFD4_RX), + PINMUX_IPSR_GPSR(IP1SR3_11_8, FXR_CLKOUT2), + + PINMUX_IPSR_GPSR(IP1SR3_15_12, CANFD5_TX), + PINMUX_IPSR_GPSR(IP1SR3_15_12, FXR_TXENA_N), + + PINMUX_IPSR_GPSR(IP1SR3_19_16, CANFD5_RX), + PINMUX_IPSR_GPSR(IP1SR3_19_16, FXR_TXENB_N), + + PINMUX_IPSR_GPSR(IP1SR3_23_20, CANFD6_TX), + PINMUX_IPSR_GPSR(IP1SR3_23_20, STPWT_EXTFXR), + + /* IP0SR4 */ + PINMUX_IPSR_GPSR(IP0SR4_3_0, AVB0_RX_CTL), + PINMUX_IPSR_GPSR(IP0SR4_3_0, AVB0_MII_RX_DV), + + PINMUX_IPSR_GPSR(IP0SR4_7_4, AVB0_RXC), + PINMUX_IPSR_GPSR(IP0SR4_7_4, AVB0_MII_RXC), + + PINMUX_IPSR_GPSR(IP0SR4_11_8, AVB0_RD0), + PINMUX_IPSR_GPSR(IP0SR4_11_8, AVB0_MII_RD0), + + PINMUX_IPSR_GPSR(IP0SR4_15_12, AVB0_RD1), + PINMUX_IPSR_GPSR(IP0SR4_15_12, AVB0_MII_RD1), + + PINMUX_IPSR_GPSR(IP0SR4_19_16, AVB0_RD2), + PINMUX_IPSR_GPSR(IP0SR4_19_16, AVB0_MII_RD2), + + PINMUX_IPSR_GPSR(IP0SR4_23_20, AVB0_RD3), + PINMUX_IPSR_GPSR(IP0SR4_23_20, AVB0_MII_RD3), + + PINMUX_IPSR_GPSR(IP0SR4_27_24, AVB0_TX_CTL), + PINMUX_IPSR_GPSR(IP0SR4_27_24, AVB0_MII_TX_EN), + + PINMUX_IPSR_GPSR(IP0SR4_31_28, AVB0_TXC), + PINMUX_IPSR_GPSR(IP0SR4_31_28, AVB0_MII_TXC), + + /* IP1SR4 */ + PINMUX_IPSR_GPSR(IP1SR4_3_0, AVB0_TD0), + PINMUX_IPSR_GPSR(IP1SR4_3_0, AVB0_MII_TD0), + + PINMUX_IPSR_GPSR(IP1SR4_7_4, AVB0_TD1), + PINMUX_IPSR_GPSR(IP1SR4_7_4, AVB0_MII_TD1), + + PINMUX_IPSR_GPSR(IP1SR4_11_8, AVB0_TD2), + PINMUX_IPSR_GPSR(IP1SR4_11_8, AVB0_MII_TD2), + + PINMUX_IPSR_GPSR(IP1SR4_15_12, AVB0_TD3), + PINMUX_IPSR_GPSR(IP1SR4_15_12, AVB0_MII_TD3), + + PINMUX_IPSR_GPSR(IP1SR4_19_16, AVB0_TXCREFCLK), + + PINMUX_IPSR_GPSR(IP1SR4_23_20, AVB0_MDIO), + + PINMUX_IPSR_GPSR(IP1SR4_27_24, AVB0_MDC), + + PINMUX_IPSR_GPSR(IP1SR4_31_28, AVB0_MAGIC), + + /* IP2SR4 */ + PINMUX_IPSR_GPSR(IP2SR4_7_4, AVB0_LINK), + PINMUX_IPSR_GPSR(IP2SR4_7_4, AVB0_MII_TX_ER), + + PINMUX_IPSR_GPSR(IP2SR4_11_8, AVB0_AVTP_MATCH), + PINMUX_IPSR_GPSR(IP2SR4_11_8, AVB0_MII_RX_ER), + PINMUX_IPSR_GPSR(IP2SR4_11_8, CC5_OSCOUT), + + PINMUX_IPSR_GPSR(IP2SR4_15_12, AVB0_AVTP_CAPTURE), + PINMUX_IPSR_GPSR(IP2SR4_15_12, AVB0_MII_CRS), + + PINMUX_IPSR_GPSR(IP2SR4_19_16, AVB0_AVTP_PPS), + PINMUX_IPSR_GPSR(IP2SR4_19_16, AVB0_MII_COL), + + /* IP0SR5 */ + PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB1_RX_CTL), + PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB1_MII_RX_DV), + + PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB1_RXC), + PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB1_MII_RXC), + + PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB1_RD0), + PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB1_MII_RD0), + + PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB1_RD1), + PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB1_MII_RD1), + + PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB1_RD2), + PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB1_MII_RD2), + + PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB1_RD3), + PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB1_MII_RD3), + + PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB1_TX_CTL), + PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB1_MII_TX_EN), + + PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB1_TXC), + PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB1_MII_TXC), + + /* IP1SR5 */ + PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB1_TD0), + PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB1_MII_TD0), + + PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB1_TD1), + PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB1_MII_TD1), + + PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB1_TD2), + PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB1_MII_TD2), + + PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB1_TD3), + PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB1_MII_TD3), + + PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB1_TXCREFCLK), + + PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB1_MDIO), + + PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB1_MDC), + + PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB1_MAGIC), + + /* IP2SR5 */ + PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB1_LINK), + PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB1_MII_TX_ER), + + PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB1_AVTP_MATCH), + PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB1_MII_RX_ER), + + PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB1_AVTP_CAPTURE), + PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB1_MII_CRS), + + PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB1_AVTP_PPS), + PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB1_MII_COL), +}; + +/* + * Pins not associated with a GPIO port. + */ +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; + +static const struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), +}; + +/* - AVB0 ------------------------------------------------ */ +static const unsigned int avb0_link_pins[] = { + /* AVB0_LINK */ + RCAR_GP_PIN(4, 17), +}; +static const unsigned int avb0_link_mux[] = { + AVB0_LINK_MARK, +}; +static const unsigned int avb0_magic_pins[] = { + /* AVB0_MAGIC */ + RCAR_GP_PIN(4, 15), +}; +static const unsigned int avb0_magic_mux[] = { + AVB0_MAGIC_MARK, +}; +static const unsigned int avb0_phy_int_pins[] = { + /* AVB0_PHY_INT */ + RCAR_GP_PIN(4, 16), +}; +static const unsigned int avb0_phy_int_mux[] = { + AVB0_PHY_INT_MARK, +}; +static const unsigned int avb0_mdio_pins[] = { + /* AVB0_MDC, AVB0_MDIO */ + RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), +}; +static const unsigned int avb0_mdio_mux[] = { + AVB0_MDC_MARK, AVB0_MDIO_MARK, +}; +static const unsigned int avb0_rgmii_pins[] = { + /* + * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3, + * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3, + */ + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), + RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), + RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), +}; +static const unsigned int avb0_rgmii_mux[] = { + AVB0_TX_CTL_MARK, AVB0_TXC_MARK, + AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK, + AVB0_RX_CTL_MARK, AVB0_RXC_MARK, + AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK, +}; +static const unsigned int avb0_txcrefclk_pins[] = { + /* AVB0_TXCREFCLK */ + RCAR_GP_PIN(4, 12), +}; +static const unsigned int avb0_txcrefclk_mux[] = { + AVB0_TXCREFCLK_MARK, +}; +static const unsigned int avb0_avtp_pps_pins[] = { + /* AVB0_AVTP_PPS */ + RCAR_GP_PIN(4, 20), +}; +static const unsigned int avb0_avtp_pps_mux[] = { + AVB0_AVTP_PPS_MARK, +}; +static const unsigned int avb0_avtp_capture_pins[] = { + /* AVB0_AVTP_CAPTURE */ + RCAR_GP_PIN(4, 19), +}; +static const unsigned int avb0_avtp_capture_mux[] = { + AVB0_AVTP_CAPTURE_MARK, +}; +static const unsigned int avb0_avtp_match_pins[] = { + /* AVB0_AVTP_MATCH */ + RCAR_GP_PIN(4, 18), +}; +static const unsigned int avb0_avtp_match_mux[] = { + AVB0_AVTP_MATCH_MARK, +}; + +/* - AVB1 ------------------------------------------------ */ +static const unsigned int avb1_link_pins[] = { + /* AVB1_LINK */ + RCAR_GP_PIN(5, 17), +}; +static const unsigned int avb1_link_mux[] = { + AVB1_LINK_MARK, +}; +static const unsigned int avb1_magic_pins[] = { + /* AVB1_MAGIC */ + RCAR_GP_PIN(5, 15), +}; +static const unsigned int avb1_magic_mux[] = { + AVB1_MAGIC_MARK, +}; +static const unsigned int avb1_phy_int_pins[] = { + /* AVB1_PHY_INT */ + RCAR_GP_PIN(5, 16), +}; +static const unsigned int avb1_phy_int_mux[] = { + AVB1_PHY_INT_MARK, +}; +static const unsigned int avb1_mdio_pins[] = { + /* AVB1_MDC, AVB1_MDIO */ + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 13), +}; +static const unsigned int avb1_mdio_mux[] = { + AVB1_MDC_MARK, AVB1_MDIO_MARK, +}; +static const unsigned int avb1_rgmii_pins[] = { + /* + * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3, + * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3, + */ + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), + RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), + RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3), + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), +}; +static const unsigned int avb1_rgmii_mux[] = { + AVB1_TX_CTL_MARK, AVB1_TXC_MARK, + AVB1_TD0_MARK, AVB1_TD1_MARK, AVB1_TD2_MARK, AVB1_TD3_MARK, + AVB1_RX_CTL_MARK, AVB1_RXC_MARK, + AVB1_RD0_MARK, AVB1_RD1_MARK, AVB1_RD2_MARK, AVB1_RD3_MARK, +}; +static const unsigned int avb1_txcrefclk_pins[] = { + /* AVB1_TXCREFCLK */ + RCAR_GP_PIN(5, 12), +}; +static const unsigned int avb1_txcrefclk_mux[] = { + AVB1_TXCREFCLK_MARK, +}; +static const unsigned int avb1_avtp_pps_pins[] = { + /* AVB1_AVTP_PPS */ + RCAR_GP_PIN(5, 20), +}; +static const unsigned int avb1_avtp_pps_mux[] = { + AVB1_AVTP_PPS_MARK, +}; +static const unsigned int avb1_avtp_capture_pins[] = { + /* AVB1_AVTP_CAPTURE */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int avb1_avtp_capture_mux[] = { + AVB1_AVTP_CAPTURE_MARK, +}; +static const unsigned int avb1_avtp_match_pins[] = { + /* AVB1_AVTP_MATCH */ + RCAR_GP_PIN(5, 18), +}; +static const unsigned int avb1_avtp_match_mux[] = { + AVB1_AVTP_MATCH_MARK, +}; + +/* - AVB2 ------------------------------------------------ */ +static const unsigned int avb2_link_pins[] = { + /* AVB2_LINK */ + RCAR_GP_PIN(6, 17), +}; +static const unsigned int avb2_link_mux[] = { + AVB2_LINK_MARK, +}; +static const unsigned int avb2_magic_pins[] = { + /* AVB2_MAGIC */ + RCAR_GP_PIN(6, 15), +}; +static const unsigned int avb2_magic_mux[] = { + AVB2_MAGIC_MARK, +}; +static const unsigned int avb2_phy_int_pins[] = { + /* AVB2_PHY_INT */ + RCAR_GP_PIN(6, 16), +}; +static const unsigned int avb2_phy_int_mux[] = { + AVB2_PHY_INT_MARK, +}; +static const unsigned int avb2_mdio_pins[] = { + /* AVB2_MDC, AVB2_MDIO */ + RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 13), +}; +static const unsigned int avb2_mdio_mux[] = { + AVB2_MDC_MARK, AVB2_MDIO_MARK, +}; +static const unsigned int avb2_rgmii_pins[] = { + /* + * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3, + * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3, + */ + RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7), + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), + RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), + RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), + RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), +}; +static const unsigned int avb2_rgmii_mux[] = { + AVB2_TX_CTL_MARK, AVB2_TXC_MARK, + AVB2_TD0_MARK, AVB2_TD1_MARK, AVB2_TD2_MARK, AVB2_TD3_MARK, + AVB2_RX_CTL_MARK, AVB2_RXC_MARK, + AVB2_RD0_MARK, AVB2_RD1_MARK, AVB2_RD2_MARK, AVB2_RD3_MARK, +}; +static const unsigned int avb2_txcrefclk_pins[] = { + /* AVB2_TXCREFCLK */ + RCAR_GP_PIN(6, 12), +}; +static const unsigned int avb2_txcrefclk_mux[] = { + AVB2_TXCREFCLK_MARK, +}; +static const unsigned int avb2_avtp_pps_pins[] = { + /* AVB2_AVTP_PPS */ + RCAR_GP_PIN(6, 20), +}; +static const unsigned int avb2_avtp_pps_mux[] = { + AVB2_AVTP_PPS_MARK, +}; +static const unsigned int avb2_avtp_capture_pins[] = { + /* AVB2_AVTP_CAPTURE */ + RCAR_GP_PIN(6, 19), +}; +static const unsigned int avb2_avtp_capture_mux[] = { + AVB2_AVTP_CAPTURE_MARK, +}; +static const unsigned int avb2_avtp_match_pins[] = { + /* AVB2_AVTP_MATCH */ + RCAR_GP_PIN(6, 18), +}; +static const unsigned int avb2_avtp_match_mux[] = { + AVB2_AVTP_MATCH_MARK, +}; + +/* - AVB3 ------------------------------------------------ */ +static const unsigned int avb3_link_pins[] = { + /* AVB3_LINK */ + RCAR_GP_PIN(7, 17), +}; +static const unsigned int avb3_link_mux[] = { + AVB3_LINK_MARK, +}; +static const unsigned int avb3_magic_pins[] = { + /* AVB3_MAGIC */ + RCAR_GP_PIN(7, 15), +}; +static const unsigned int avb3_magic_mux[] = { + AVB3_MAGIC_MARK, +}; +static const unsigned int avb3_phy_int_pins[] = { + /* AVB3_PHY_INT */ + RCAR_GP_PIN(7, 16), +}; +static const unsigned int avb3_phy_int_mux[] = { + AVB3_PHY_INT_MARK, +}; +static const unsigned int avb3_mdio_pins[] = { + /* AVB3_MDC, AVB3_MDIO */ + RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 13), +}; +static const unsigned int avb3_mdio_mux[] = { + AVB3_MDC_MARK, AVB3_MDIO_MARK, +}; +static const unsigned int avb3_rgmii_pins[] = { + /* + * AVB3_TX_CTL, AVB3_TXC, AVB3_TD0, AVB3_TD1, AVB3_TD2, AVB3_TD3, + * AVB3_RX_CTL, AVB3_RXC, AVB3_RD0, AVB3_RD1, AVB3_RD2, AVB3_RD3, + */ + RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7), + RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), + RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11), + RCAR_GP_PIN(7, 0), RCAR_GP_PIN(7, 1), + RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3), + RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5), +}; +static const unsigned int avb3_rgmii_mux[] = { + AVB3_TX_CTL_MARK, AVB3_TXC_MARK, + AVB3_TD0_MARK, AVB3_TD1_MARK, AVB3_TD2_MARK, AVB3_TD3_MARK, + AVB3_RX_CTL_MARK, AVB3_RXC_MARK, + AVB3_RD0_MARK, AVB3_RD1_MARK, AVB3_RD2_MARK, AVB3_RD3_MARK, +}; +static const unsigned int avb3_txcrefclk_pins[] = { + /* AVB3_TXCREFCLK */ + RCAR_GP_PIN(7, 12), +}; +static const unsigned int avb3_txcrefclk_mux[] = { + AVB3_TXCREFCLK_MARK, +}; +static const unsigned int avb3_avtp_pps_pins[] = { + /* AVB3_AVTP_PPS */ + RCAR_GP_PIN(7, 20), +}; +static const unsigned int avb3_avtp_pps_mux[] = { + AVB3_AVTP_PPS_MARK, +}; +static const unsigned int avb3_avtp_capture_pins[] = { + /* AVB3_AVTP_CAPTURE */ + RCAR_GP_PIN(7, 19), +}; +static const unsigned int avb3_avtp_capture_mux[] = { + AVB3_AVTP_CAPTURE_MARK, +}; +static const unsigned int avb3_avtp_match_pins[] = { + /* AVB3_AVTP_MATCH */ + RCAR_GP_PIN(7, 18), +}; +static const unsigned int avb3_avtp_match_mux[] = { + AVB3_AVTP_MATCH_MARK, +}; + +/* - AVB4 ------------------------------------------------ */ +static const unsigned int avb4_link_pins[] = { + /* AVB4_LINK */ + RCAR_GP_PIN(8, 17), +}; +static const unsigned int avb4_link_mux[] = { + AVB4_LINK_MARK, +}; +static const unsigned int avb4_magic_pins[] = { + /* AVB4_MAGIC */ + RCAR_GP_PIN(8, 15), +}; +static const unsigned int avb4_magic_mux[] = { + AVB4_MAGIC_MARK, +}; +static const unsigned int avb4_phy_int_pins[] = { + /* AVB4_PHY_INT */ + RCAR_GP_PIN(8, 16), +}; +static const unsigned int avb4_phy_int_mux[] = { + AVB4_PHY_INT_MARK, +}; +static const unsigned int avb4_mdio_pins[] = { + /* AVB4_MDC, AVB4_MDIO */ + RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 13), +}; +static const unsigned int avb4_mdio_mux[] = { + AVB4_MDC_MARK, AVB4_MDIO_MARK, +}; +static const unsigned int avb4_rgmii_pins[] = { + /* + * AVB4_TX_CTL, AVB4_TXC, AVB4_TD0, AVB4_TD1, AVB4_TD2, AVB4_TD3, + * AVB4_RX_CTL, AVB4_RXC, AVB4_RD0, AVB4_RD1, AVB4_RD2, AVB4_RD3, + */ + RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7), + RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9), + RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11), + RCAR_GP_PIN(8, 0), RCAR_GP_PIN(8, 1), + RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3), + RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5), +}; +static const unsigned int avb4_rgmii_mux[] = { + AVB4_TX_CTL_MARK, AVB4_TXC_MARK, + AVB4_TD0_MARK, AVB4_TD1_MARK, AVB4_TD2_MARK, AVB4_TD3_MARK, + AVB4_RX_CTL_MARK, AVB4_RXC_MARK, + AVB4_RD0_MARK, AVB4_RD1_MARK, AVB4_RD2_MARK, AVB4_RD3_MARK, +}; +static const unsigned int avb4_txcrefclk_pins[] = { + /* AVB4_TXCREFCLK */ + RCAR_GP_PIN(8, 12), +}; +static const unsigned int avb4_txcrefclk_mux[] = { + AVB4_TXCREFCLK_MARK, +}; +static const unsigned int avb4_avtp_pps_pins[] = { + /* AVB4_AVTP_PPS */ + RCAR_GP_PIN(8, 20), +}; +static const unsigned int avb4_avtp_pps_mux[] = { + AVB4_AVTP_PPS_MARK, +}; +static const unsigned int avb4_avtp_capture_pins[] = { + /* AVB4_AVTP_CAPTURE */ + RCAR_GP_PIN(8, 19), +}; +static const unsigned int avb4_avtp_capture_mux[] = { + AVB4_AVTP_CAPTURE_MARK, +}; +static const unsigned int avb4_avtp_match_pins[] = { + /* AVB4_AVTP_MATCH */ + RCAR_GP_PIN(8, 18), +}; +static const unsigned int avb4_avtp_match_mux[] = { + AVB4_AVTP_MATCH_MARK, +}; + +/* - AVB5 ------------------------------------------------ */ +static const unsigned int avb5_link_pins[] = { + /* AVB5_LINK */ + RCAR_GP_PIN(9, 17), +}; +static const unsigned int avb5_link_mux[] = { + AVB5_LINK_MARK, +}; +static const unsigned int avb5_magic_pins[] = { + /* AVB5_MAGIC */ + RCAR_GP_PIN(9, 15), +}; +static const unsigned int avb5_magic_mux[] = { + AVB5_MAGIC_MARK, +}; +static const unsigned int avb5_phy_int_pins[] = { + /* AVB5_PHY_INT */ + RCAR_GP_PIN(9, 16), +}; +static const unsigned int avb5_phy_int_mux[] = { + AVB5_PHY_INT_MARK, +}; +static const unsigned int avb5_mdio_pins[] = { + /* AVB5_MDC, AVB5_MDIO */ + RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 13), +}; +static const unsigned int avb5_mdio_mux[] = { + AVB5_MDC_MARK, AVB5_MDIO_MARK, +}; +static const unsigned int avb5_rgmii_pins[] = { + /* + * AVB5_TX_CTL, AVB5_TXC, AVB5_TD0, AVB5_TD1, AVB5_TD2, AVB5_TD3, + * AVB5_RX_CTL, AVB5_RXC, AVB5_RD0, AVB5_RD1, AVB5_RD2, AVB5_RD3, + */ + RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7), + RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9), + RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11), + RCAR_GP_PIN(9, 0), RCAR_GP_PIN(9, 1), + RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3), + RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5), +}; +static const unsigned int avb5_rgmii_mux[] = { + AVB5_TX_CTL_MARK, AVB5_TXC_MARK, + AVB5_TD0_MARK, AVB5_TD1_MARK, AVB5_TD2_MARK, AVB5_TD3_MARK, + AVB5_RX_CTL_MARK, AVB5_RXC_MARK, + AVB5_RD0_MARK, AVB5_RD1_MARK, AVB5_RD2_MARK, AVB5_RD3_MARK, +}; +static const unsigned int avb5_txcrefclk_pins[] = { + /* AVB5_TXCREFCLK */ + RCAR_GP_PIN(9, 12), +}; +static const unsigned int avb5_txcrefclk_mux[] = { + AVB5_TXCREFCLK_MARK, +}; +static const unsigned int avb5_avtp_pps_pins[] = { + /* AVB5_AVTP_PPS */ + RCAR_GP_PIN(9, 20), +}; +static const unsigned int avb5_avtp_pps_mux[] = { + AVB5_AVTP_PPS_MARK, +}; +static const unsigned int avb5_avtp_capture_pins[] = { + /* AVB5_AVTP_CAPTURE */ + RCAR_GP_PIN(9, 19), +}; +static const unsigned int avb5_avtp_capture_mux[] = { + AVB5_AVTP_CAPTURE_MARK, +}; +static const unsigned int avb5_avtp_match_pins[] = { + /* AVB5_AVTP_MATCH */ + RCAR_GP_PIN(9, 18), +}; +static const unsigned int avb5_avtp_match_mux[] = { + AVB5_AVTP_MATCH_MARK, +}; + +/* - CANFD0 ----------------------------------------------------------------- */ +static const unsigned int canfd0_data_pins[] = { + /* CANFD0_TX, CANFD0_RX */ + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), +}; +static const unsigned int canfd0_data_mux[] = { + CANFD0_TX_MARK, CANFD0_RX_MARK, +}; + +/* - CANFD1 ----------------------------------------------------------------- */ +static const unsigned int canfd1_data_pins[] = { + /* CANFD1_TX, CANFD1_RX */ + RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), +}; +static const unsigned int canfd1_data_mux[] = { + CANFD1_TX_MARK, CANFD1_RX_MARK, +}; + +/* - CANFD2 ----------------------------------------------------------------- */ +static const unsigned int canfd2_data_pins[] = { + /* CANFD2_TX, CANFD2_RX */ + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), +}; +static const unsigned int canfd2_data_mux[] = { + CANFD2_TX_MARK, CANFD2_RX_MARK, +}; + +/* - CANFD3 ----------------------------------------------------------------- */ +static const unsigned int canfd3_data_pins[] = { + /* CANFD3_TX, CANFD3_RX */ + RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), +}; +static const unsigned int canfd3_data_mux[] = { + CANFD3_TX_MARK, CANFD3_RX_MARK, +}; + +/* - CANFD4 ----------------------------------------------------------------- */ +static const unsigned int canfd4_data_pins[] = { + /* CANFD4_TX, CANFD4_RX */ + RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), +}; +static const unsigned int canfd4_data_mux[] = { + CANFD4_TX_MARK, CANFD4_RX_MARK, +}; + +/* - CANFD5 ----------------------------------------------------------------- */ +static const unsigned int canfd5_data_pins[] = { + /* CANFD5_TX, CANFD5_RX */ + RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), +}; +static const unsigned int canfd5_data_mux[] = { + CANFD5_TX_MARK, CANFD5_RX_MARK, +}; + +/* - CANFD6 ----------------------------------------------------------------- */ +static const unsigned int canfd6_data_pins[] = { + /* CANFD6_TX, CANFD6_RX */ + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), +}; +static const unsigned int canfd6_data_mux[] = { + CANFD6_TX_MARK, CANFD6_RX_MARK, +}; + +/* - CANFD7 ----------------------------------------------------------------- */ +static const unsigned int canfd7_data_pins[] = { + /* CANFD7_TX, CANFD7_RX */ + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), +}; +static const unsigned int canfd7_data_mux[] = { + CANFD7_TX_MARK, CANFD7_RX_MARK, +}; + +/* - CANFD Clock ------------------------------------------------------------ */ +static const unsigned int can_clk_pins[] = { + /* CAN_CLK */ + RCAR_GP_PIN(3, 0), +}; +static const unsigned int can_clk_mux[] = { + CAN_CLK_MARK, +}; + +/* - DU --------------------------------------------------------------------- */ +static const unsigned int du_rgb888_pins[] = { + /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */ + RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), +}; +static const unsigned int du_rgb888_mux[] = { + DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, + DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK, + DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, + DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK, + DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, + DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK, +}; +static const unsigned int du_clk_out_pins[] = { + /* DU_DOTCLKOUT */ + RCAR_GP_PIN(1, 24), +}; +static const unsigned int du_clk_out_mux[] = { + DU_DOTCLKOUT_MARK, +}; +static const unsigned int du_sync_pins[] = { + /* DU_HSYNC, DU_VSYNC */ + RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 26), +}; +static const unsigned int du_sync_mux[] = { + DU_HSYNC_MARK, DU_VSYNC_MARK, +}; +static const unsigned int du_oddf_pins[] = { + /* DU_EXODDF/DU_ODDF/DISP/CDE */ + RCAR_GP_PIN(1, 27), +}; +static const unsigned int du_oddf_mux[] = { + DU_ODDF_DISP_CDE_MARK, +}; + +/* - HSCIF0 ----------------------------------------------------------------- */ +static const unsigned int hscif0_data_pins[] = { + /* HRX0, HTX0 */ + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5), +}; +static const unsigned int hscif0_data_mux[] = { + HRX0_MARK, HTX0_MARK, +}; +static const unsigned int hscif0_clk_pins[] = { + /* HSCK0 */ + RCAR_GP_PIN(1, 2), +}; +static const unsigned int hscif0_clk_mux[] = { + HSCK0_MARK, +}; +static const unsigned int hscif0_ctrl_pins[] = { + /* HRTS0#, HCTS0# */ + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4), +}; +static const unsigned int hscif0_ctrl_mux[] = { + HRTS0_N_MARK, HCTS0_N_MARK, +}; + +/* - HSCIF1 ----------------------------------------------------------------- */ +static const unsigned int hscif1_data_pins[] = { + /* HRX1, HTX1 */ + RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), +}; +static const unsigned int hscif1_data_mux[] = { + HRX1_MARK, HTX1_MARK, +}; +static const unsigned int hscif1_clk_pins[] = { + /* HSCK1 */ + RCAR_GP_PIN(1, 18), +}; +static const unsigned int hscif1_clk_mux[] = { + HSCK1_MARK, +}; +static const unsigned int hscif1_ctrl_pins[] = { + /* HRTS1#, HCTS1# */ + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), +}; +static const unsigned int hscif1_ctrl_mux[] = { + HRTS1_N_MARK, HCTS1_N_MARK, +}; + +/* - HSCIF2 ----------------------------------------------------------------- */ +static const unsigned int hscif2_data_pins[] = { + /* HRX2, HTX2 */ + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), +}; +static const unsigned int hscif2_data_mux[] = { + HRX2_MARK, HTX2_MARK, +}; +static const unsigned int hscif2_clk_pins[] = { + /* HSCK2 */ + RCAR_GP_PIN(2, 5), +}; +static const unsigned int hscif2_clk_mux[] = { + HSCK2_MARK, +}; +static const unsigned int hscif2_ctrl_pins[] = { + /* HRTS2#, HCTS2# */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), +}; +static const unsigned int hscif2_ctrl_mux[] = { + HRTS2_N_MARK, HCTS2_N_MARK, +}; + +/* - HSCIF3 ----------------------------------------------------------------- */ +static const unsigned int hscif3_data_pins[] = { + /* HRX3, HTX3 */ + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 17), +}; +static const unsigned int hscif3_data_mux[] = { + HRX3_MARK, HTX3_MARK, +}; +static const unsigned int hscif3_clk_pins[] = { + /* HSCK3 */ + RCAR_GP_PIN(1, 14), +}; +static const unsigned int hscif3_clk_mux[] = { + HSCK3_MARK, +}; +static const unsigned int hscif3_ctrl_pins[] = { + /* HRTS3#, HCTS3# */ + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), +}; +static const unsigned int hscif3_ctrl_mux[] = { + HRTS3_N_MARK, HCTS3_N_MARK, +}; + +/* - I2C0 ------------------------------------------------------------------- */ +static const unsigned int i2c0_pins[] = { + /* SDA0, SCL0 */ + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), +}; +static const unsigned int i2c0_mux[] = { + SDA0_MARK, SCL0_MARK, +}; + +/* - I2C1 ------------------------------------------------------------------- */ +static const unsigned int i2c1_pins[] = { + /* SDA1, SCL1 */ + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), +}; +static const unsigned int i2c1_mux[] = { + SDA1_MARK, SCL1_MARK, +}; + +/* - I2C2 ------------------------------------------------------------------- */ +static const unsigned int i2c2_pins[] = { + /* SDA2, SCL2 */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), +}; +static const unsigned int i2c2_mux[] = { + SDA2_MARK, SCL2_MARK, +}; + +/* - I2C3 ------------------------------------------------------------------- */ +static const unsigned int i2c3_pins[] = { + /* SDA3, SCL3 */ + RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8), +}; +static const unsigned int i2c3_mux[] = { + SDA3_MARK, SCL3_MARK, +}; + +/* - I2C4 ------------------------------------------------------------------- */ +static const unsigned int i2c4_pins[] = { + /* SDA4, SCL4 */ + RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), +}; +static const unsigned int i2c4_mux[] = { + SDA4_MARK, SCL4_MARK, +}; + +/* - I2C5 ------------------------------------------------------------------- */ +static const unsigned int i2c5_pins[] = { + /* SDA5, SCL5 */ + RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12), +}; +static const unsigned int i2c5_mux[] = { + SDA5_MARK, SCL5_MARK, +}; + +/* - I2C6 ------------------------------------------------------------------- */ +static const unsigned int i2c6_pins[] = { + /* SDA6, SCL6 */ + RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), +}; +static const unsigned int i2c6_mux[] = { + SDA6_MARK, SCL6_MARK, +}; + +/* - INTC-EX ---------------------------------------------------------------- */ +static const unsigned int intc_ex_irq0_pins[] = { + /* IRQ0 */ + RCAR_GP_PIN(1, 24), +}; +static const unsigned int intc_ex_irq0_mux[] = { + IRQ0_MARK, +}; +static const unsigned int intc_ex_irq1_pins[] = { + /* IRQ1 */ + RCAR_GP_PIN(1, 25), +}; +static const unsigned int intc_ex_irq1_mux[] = { + IRQ1_MARK, +}; +static const unsigned int intc_ex_irq2_pins[] = { + /* IRQ2 */ + RCAR_GP_PIN(1, 26), +}; +static const unsigned int intc_ex_irq2_mux[] = { + IRQ2_MARK, +}; +static const unsigned int intc_ex_irq3_pins[] = { + /* IRQ3 */ + RCAR_GP_PIN(1, 27), +}; +static const unsigned int intc_ex_irq3_mux[] = { + IRQ3_MARK, +}; +static const unsigned int intc_ex_irq4_pins[] = { + /* IRQ4 */ + RCAR_GP_PIN(2, 14), +}; +static const unsigned int intc_ex_irq4_mux[] = { + IRQ4_MARK, +}; +static const unsigned int intc_ex_irq5_pins[] = { + /* IRQ5 */ + RCAR_GP_PIN(2, 15), +}; +static const unsigned int intc_ex_irq5_mux[] = { + IRQ5_MARK, +}; + +/* - MMC -------------------------------------------------------------------- */ +static const unsigned int mmc_data1_pins[] = { + /* MMC_SD_D0 */ + RCAR_GP_PIN(0, 19), +}; +static const unsigned int mmc_data1_mux[] = { + MMC_SD_D0_MARK, +}; +static const unsigned int mmc_data4_pins[] = { + /* MMC_SD_D[0:3] */ + RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), + RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22), +}; +static const unsigned int mmc_data4_mux[] = { + MMC_SD_D0_MARK, MMC_SD_D1_MARK, + MMC_SD_D2_MARK, MMC_SD_D3_MARK, +}; +static const unsigned int mmc_data8_pins[] = { + /* MMC_SD_D[0:3], MMC_D[4:7] */ + RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), + RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22), + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), + RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 27), +}; +static const unsigned int mmc_data8_mux[] = { + MMC_SD_D0_MARK, MMC_SD_D1_MARK, + MMC_SD_D2_MARK, MMC_SD_D3_MARK, + MMC_D4_MARK, MMC_D5_MARK, + MMC_D6_MARK, MMC_D7_MARK, +}; +static const unsigned int mmc_ctrl_pins[] = { + /* MMC_SD_CLK, MMC_SD_CMD */ + RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 18), +}; +static const unsigned int mmc_ctrl_mux[] = { + MMC_SD_CLK_MARK, MMC_SD_CMD_MARK, +}; +static const unsigned int mmc_cd_pins[] = { + /* SD_CD */ + RCAR_GP_PIN(0, 16), +}; +static const unsigned int mmc_cd_mux[] = { + SD_CD_MARK, +}; +static const unsigned int mmc_wp_pins[] = { + /* SD_WP */ + RCAR_GP_PIN(0, 15), +}; +static const unsigned int mmc_wp_mux[] = { + SD_WP_MARK, +}; +static const unsigned int mmc_ds_pins[] = { + /* MMC_DS */ + RCAR_GP_PIN(0, 17), +}; +static const unsigned int mmc_ds_mux[] = { + MMC_DS_MARK, +}; + +/* - MSIOF0 ----------------------------------------------------------------- */ +static const unsigned int msiof0_clk_pins[] = { + /* MSIOF0_SCK */ + RCAR_GP_PIN(1, 8), +}; +static const unsigned int msiof0_clk_mux[] = { + MSIOF0_SCK_MARK, +}; +static const unsigned int msiof0_sync_pins[] = { + /* MSIOF0_SYNC */ + RCAR_GP_PIN(1, 9), +}; +static const unsigned int msiof0_sync_mux[] = { + MSIOF0_SYNC_MARK, +}; +static const unsigned int msiof0_ss1_pins[] = { + /* MSIOF0_SS1 */ + RCAR_GP_PIN(1, 10), +}; +static const unsigned int msiof0_ss1_mux[] = { + MSIOF0_SS1_MARK, +}; +static const unsigned int msiof0_ss2_pins[] = { + /* MSIOF0_SS2 */ + RCAR_GP_PIN(1, 11), +}; +static const unsigned int msiof0_ss2_mux[] = { + MSIOF0_SS2_MARK, +}; +static const unsigned int msiof0_txd_pins[] = { + /* MSIOF0_TXD */ + RCAR_GP_PIN(1, 7), +}; +static const unsigned int msiof0_txd_mux[] = { + MSIOF0_TXD_MARK, +}; +static const unsigned int msiof0_rxd_pins[] = { + /* MSIOF0_RXD */ + RCAR_GP_PIN(1, 6), +}; +static const unsigned int msiof0_rxd_mux[] = { + MSIOF0_RXD_MARK, +}; + +/* - MSIOF1 ----------------------------------------------------------------- */ +static const unsigned int msiof1_clk_pins[] = { + /* MSIOF1_SCK */ + RCAR_GP_PIN(1, 14), +}; +static const unsigned int msiof1_clk_mux[] = { + MSIOF1_SCK_MARK, +}; +static const unsigned int msiof1_sync_pins[] = { + /* MSIOF1_SYNC */ + RCAR_GP_PIN(1, 15), +}; +static const unsigned int msiof1_sync_mux[] = { + MSIOF1_SYNC_MARK, +}; +static const unsigned int msiof1_ss1_pins[] = { + /* MSIOF1_SS1 */ + RCAR_GP_PIN(1, 16), +}; +static const unsigned int msiof1_ss1_mux[] = { + MSIOF1_SS1_MARK, +}; +static const unsigned int msiof1_ss2_pins[] = { + /* MSIOF1_SS2 */ + RCAR_GP_PIN(1, 17), +}; +static const unsigned int msiof1_ss2_mux[] = { + MSIOF1_SS2_MARK, +}; +static const unsigned int msiof1_txd_pins[] = { + /* MSIOF1_TXD */ + RCAR_GP_PIN(1, 13), +}; +static const unsigned int msiof1_txd_mux[] = { + MSIOF1_TXD_MARK, +}; +static const unsigned int msiof1_rxd_pins[] = { + /* MSIOF1_RXD */ + RCAR_GP_PIN(1, 12), +}; +static const unsigned int msiof1_rxd_mux[] = { + MSIOF1_RXD_MARK, +}; + +/* - MSIOF2 ----------------------------------------------------------------- */ +static const unsigned int msiof2_clk_pins[] = { + /* MSIOF2_SCK */ + RCAR_GP_PIN(1, 20), +}; +static const unsigned int msiof2_clk_mux[] = { + MSIOF2_SCK_MARK, +}; +static const unsigned int msiof2_sync_pins[] = { + /* MSIOF2_SYNC */ + RCAR_GP_PIN(1, 21), +}; +static const unsigned int msiof2_sync_mux[] = { + MSIOF2_SYNC_MARK, +}; +static const unsigned int msiof2_ss1_pins[] = { + /* MSIOF2_SS1 */ + RCAR_GP_PIN(1, 22), +}; +static const unsigned int msiof2_ss1_mux[] = { + MSIOF2_SS1_MARK, +}; +static const unsigned int msiof2_ss2_pins[] = { + /* MSIOF2_SS2 */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int msiof2_ss2_mux[] = { + MSIOF2_SS2_MARK, +}; +static const unsigned int msiof2_txd_pins[] = { + /* MSIOF2_TXD */ + RCAR_GP_PIN(1, 19), +}; +static const unsigned int msiof2_txd_mux[] = { + MSIOF2_TXD_MARK, +}; +static const unsigned int msiof2_rxd_pins[] = { + /* MSIOF2_RXD */ + RCAR_GP_PIN(1, 18), +}; +static const unsigned int msiof2_rxd_mux[] = { + MSIOF2_RXD_MARK, +}; + +/* - MSIOF3 ----------------------------------------------------------------- */ +static const unsigned int msiof3_clk_pins[] = { + /* MSIOF3_SCK */ + RCAR_GP_PIN(2, 20), +}; +static const unsigned int msiof3_clk_mux[] = { + MSIOF3_SCK_MARK, +}; +static const unsigned int msiof3_sync_pins[] = { + /* MSIOF3_SYNC */ + RCAR_GP_PIN(2, 21), +}; +static const unsigned int msiof3_sync_mux[] = { + MSIOF3_SYNC_MARK, +}; +static const unsigned int msiof3_ss1_pins[] = { + /* MSIOF3_SS1 */ + RCAR_GP_PIN(2, 16), +}; +static const unsigned int msiof3_ss1_mux[] = { + MSIOF3_SS1_MARK, +}; +static const unsigned int msiof3_ss2_pins[] = { + /* MSIOF3_SS2 */ + RCAR_GP_PIN(2, 17), +}; +static const unsigned int msiof3_ss2_mux[] = { + MSIOF3_SS2_MARK, +}; +static const unsigned int msiof3_txd_pins[] = { + /* MSIOF3_TXD */ + RCAR_GP_PIN(2, 19), +}; +static const unsigned int msiof3_txd_mux[] = { + MSIOF3_TXD_MARK, +}; +static const unsigned int msiof3_rxd_pins[] = { + /* MSIOF3_RXD */ + RCAR_GP_PIN(2, 18), +}; +static const unsigned int msiof3_rxd_mux[] = { + MSIOF3_RXD_MARK, +}; + +/* - MSIOF4 ----------------------------------------------------------------- */ +static const unsigned int msiof4_clk_pins[] = { + /* MSIOF4_SCK */ + RCAR_GP_PIN(2, 6), +}; +static const unsigned int msiof4_clk_mux[] = { + MSIOF4_SCK_MARK, +}; +static const unsigned int msiof4_sync_pins[] = { + /* MSIOF4_SYNC */ + RCAR_GP_PIN(2, 7), +}; +static const unsigned int msiof4_sync_mux[] = { + MSIOF4_SYNC_MARK, +}; +static const unsigned int msiof4_ss1_pins[] = { + /* MSIOF4_SS1 */ + RCAR_GP_PIN(2, 8), +}; +static const unsigned int msiof4_ss1_mux[] = { + MSIOF4_SS1_MARK, +}; +static const unsigned int msiof4_ss2_pins[] = { + /* MSIOF4_SS2 */ + RCAR_GP_PIN(2, 9), +}; +static const unsigned int msiof4_ss2_mux[] = { + MSIOF4_SS2_MARK, +}; +static const unsigned int msiof4_txd_pins[] = { + /* MSIOF4_TXD */ + RCAR_GP_PIN(2, 5), +}; +static const unsigned int msiof4_txd_mux[] = { + MSIOF4_TXD_MARK, +}; +static const unsigned int msiof4_rxd_pins[] = { + /* MSIOF4_RXD */ + RCAR_GP_PIN(2, 4), +}; +static const unsigned int msiof4_rxd_mux[] = { + MSIOF4_RXD_MARK, +}; + +/* - MSIOF5 ----------------------------------------------------------------- */ +static const unsigned int msiof5_clk_pins[] = { + /* MSIOF5_SCK */ + RCAR_GP_PIN(2, 12), +}; +static const unsigned int msiof5_clk_mux[] = { + MSIOF5_SCK_MARK, +}; +static const unsigned int msiof5_sync_pins[] = { + /* MSIOF5_SYNC */ + RCAR_GP_PIN(2, 13), +}; +static const unsigned int msiof5_sync_mux[] = { + MSIOF5_SYNC_MARK, +}; +static const unsigned int msiof5_ss1_pins[] = { + /* MSIOF5_SS1 */ + RCAR_GP_PIN(2, 14), +}; +static const unsigned int msiof5_ss1_mux[] = { + MSIOF5_SS1_MARK, +}; +static const unsigned int msiof5_ss2_pins[] = { + /* MSIOF5_SS2 */ + RCAR_GP_PIN(2, 15), +}; +static const unsigned int msiof5_ss2_mux[] = { + MSIOF5_SS2_MARK, +}; +static const unsigned int msiof5_txd_pins[] = { + /* MSIOF5_TXD */ + RCAR_GP_PIN(2, 11), +}; +static const unsigned int msiof5_txd_mux[] = { + MSIOF5_TXD_MARK, +}; +static const unsigned int msiof5_rxd_pins[] = { + /* MSIOF5_RXD */ + RCAR_GP_PIN(2, 10), +}; +static const unsigned int msiof5_rxd_mux[] = { + MSIOF5_RXD_MARK, +}; + +/* - PWM0 ------------------------------------------------------------------- */ +static const unsigned int pwm0_pins[] = { + /* PWM0 */ + RCAR_GP_PIN(3, 5), +}; +static const unsigned int pwm0_mux[] = { + PWM0_MARK, +}; + +/* - PWM1 ------------------------------------------------------------------- */ +static const unsigned int pwm1_pins[] = { + /* PWM1 */ + RCAR_GP_PIN(3, 6), +}; +static const unsigned int pwm1_mux[] = { + PWM1_MARK, +}; + +/* - PWM2 ------------------------------------------------------------------- */ +static const unsigned int pwm2_pins[] = { + /* PWM2 */ + RCAR_GP_PIN(3, 7), +}; +static const unsigned int pwm2_mux[] = { + PWM2_MARK, +}; + +/* - PWM3 ------------------------------------------------------------------- */ +static const unsigned int pwm3_pins[] = { + /* PWM3 */ + RCAR_GP_PIN(3, 8), +}; +static const unsigned int pwm3_mux[] = { + PWM3_MARK, +}; + +/* - PWM4 ------------------------------------------------------------------- */ +static const unsigned int pwm4_pins[] = { + /* PWM4 */ + RCAR_GP_PIN(3, 9), +}; +static const unsigned int pwm4_mux[] = { + PWM4_MARK, +}; + +/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 5), +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), +}; +static const unsigned int qspi0_data2_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, +}; +static const unsigned int qspi0_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), + RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), +}; +static const unsigned int qspi0_data4_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK +}; + +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 11), +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), +}; +static const unsigned int qspi1_data2_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +}; +static const unsigned int qspi1_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), +}; +static const unsigned int qspi1_data4_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK +}; + +/* - SCIF0 ------------------------------------------------------------------ */ +static const unsigned int scif0_data_pins[] = { + /* RX0, TX0 */ + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5), +}; +static const unsigned int scif0_data_mux[] = { + RX0_MARK, TX0_MARK, +}; +static const unsigned int scif0_clk_pins[] = { + /* SCK0 */ + RCAR_GP_PIN(1, 2), +}; +static const unsigned int scif0_clk_mux[] = { + SCK0_MARK, +}; +static const unsigned int scif0_ctrl_pins[] = { + /* RTS0#, CTS0# */ + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4), +}; +static const unsigned int scif0_ctrl_mux[] = { + RTS0_N_MARK, CTS0_N_MARK, +}; + +/* - SCIF1 ------------------------------------------------------------------ */ +static const unsigned int scif1_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), +}; +static const unsigned int scif1_data_a_mux[] = { + RX1_A_MARK, TX1_A_MARK, +}; +static const unsigned int scif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 1), +}; +static const unsigned int scif1_data_b_mux[] = { + RX1_B_MARK, TX1_B_MARK, +}; +static const unsigned int scif1_clk_pins[] = { + /* SCK1 */ + RCAR_GP_PIN(1, 18), +}; +static const unsigned int scif1_clk_mux[] = { + SCK1_MARK, +}; +static const unsigned int scif1_ctrl_pins[] = { + /* RTS1#, CTS1# */ + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), +}; +static const unsigned int scif1_ctrl_mux[] = { + RTS1_N_MARK, CTS1_N_MARK, +}; + +/* - SCIF3 ------------------------------------------------------------------ */ +static const unsigned int scif3_data_pins[] = { + /* RX3, TX3 */ + RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), +}; +static const unsigned int scif3_data_mux[] = { + RX3_MARK, TX3_MARK, +}; +static const unsigned int scif3_clk_pins[] = { + /* SCK3 */ + RCAR_GP_PIN(1, 13), +}; +static const unsigned int scif3_clk_mux[] = { + SCK3_MARK, +}; +static const unsigned int scif3_ctrl_pins[] = { + /* RTS3#, CTS3# */ + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), +}; +static const unsigned int scif3_ctrl_mux[] = { + RTS3_N_MARK, CTS3_N_MARK, +}; + +/* - SCIF4 ------------------------------------------------------------------ */ +static const unsigned int scif4_data_pins[] = { + /* RX4, TX4 */ + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), +}; +static const unsigned int scif4_data_mux[] = { + RX4_MARK, TX4_MARK, +}; +static const unsigned int scif4_clk_pins[] = { + /* SCK4 */ + RCAR_GP_PIN(2, 5), +}; +static const unsigned int scif4_clk_mux[] = { + SCK4_MARK, +}; +static const unsigned int scif4_ctrl_pins[] = { + /* RTS4#, CTS4# */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), +}; +static const unsigned int scif4_ctrl_mux[] = { + RTS4_N_MARK, CTS4_N_MARK, +}; + +/* - SCIF Clock ------------------------------------------------------------- */ +static const unsigned int scif_clk_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(1, 0), +}; +static const unsigned int scif_clk_mux[] = { + SCIF_CLK_MARK, +}; + +/* - TMU -------------------------------------------------------------------- */ +static const unsigned int tmu_tclk1_a_pins[] = { + /* TCLK1 */ + RCAR_GP_PIN(2, 23), +}; +static const unsigned int tmu_tclk1_a_mux[] = { + TCLK1_A_MARK, +}; +static const unsigned int tmu_tclk1_b_pins[] = { + /* TCLK1 */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int tmu_tclk1_b_mux[] = { + TCLK1_B_MARK, +}; + +static const unsigned int tmu_tclk2_a_pins[] = { + /* TCLK2 */ + RCAR_GP_PIN(2, 24), +}; +static const unsigned int tmu_tclk2_a_mux[] = { + TCLK2_A_MARK, +}; +static const unsigned int tmu_tclk2_b_pins[] = { + /* TCLK2 */ + RCAR_GP_PIN(2, 10), +}; +static const unsigned int tmu_tclk2_b_mux[] = { + TCLK2_B_MARK, +}; + +static const unsigned int tmu_tclk3_pins[] = { + /* TCLK3 */ + RCAR_GP_PIN(2, 11), +}; +static const unsigned int tmu_tclk3_mux[] = { + TCLK3_MARK, +}; + +static const unsigned int tmu_tclk4_pins[] = { + /* TCLK4 */ + RCAR_GP_PIN(2, 12), +}; +static const unsigned int tmu_tclk4_mux[] = { + TCLK4_MARK, +}; + +/* - TPU ------------------------------------------------------------------- */ +static const unsigned int tpu_to0_pins[] = { + /* TPU0TO0 */ + RCAR_GP_PIN(2, 21), +}; +static const unsigned int tpu_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu_to1_pins[] = { + /* TPU0TO1 */ + RCAR_GP_PIN(2, 22), +}; +static const unsigned int tpu_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu_to2_pins[] = { + /* TPU0TO2 */ + RCAR_GP_PIN(3, 5), +}; +static const unsigned int tpu_to2_mux[] = { + TPU0TO2_MARK, +}; +static const unsigned int tpu_to3_pins[] = { + /* TPU0TO3 */ + RCAR_GP_PIN(3, 6), +}; +static const unsigned int tpu_to3_mux[] = { + TPU0TO3_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(avb0_link), + SH_PFC_PIN_GROUP(avb0_magic), + SH_PFC_PIN_GROUP(avb0_phy_int), + SH_PFC_PIN_GROUP(avb0_mdio), + SH_PFC_PIN_GROUP(avb0_rgmii), + SH_PFC_PIN_GROUP(avb0_txcrefclk), + SH_PFC_PIN_GROUP(avb0_avtp_pps), + SH_PFC_PIN_GROUP(avb0_avtp_capture), + SH_PFC_PIN_GROUP(avb0_avtp_match), + + SH_PFC_PIN_GROUP(avb1_link), + SH_PFC_PIN_GROUP(avb1_magic), + SH_PFC_PIN_GROUP(avb1_phy_int), + SH_PFC_PIN_GROUP(avb1_mdio), + SH_PFC_PIN_GROUP(avb1_rgmii), + SH_PFC_PIN_GROUP(avb1_txcrefclk), + SH_PFC_PIN_GROUP(avb1_avtp_pps), + SH_PFC_PIN_GROUP(avb1_avtp_capture), + SH_PFC_PIN_GROUP(avb1_avtp_match), + + SH_PFC_PIN_GROUP(avb2_link), + SH_PFC_PIN_GROUP(avb2_magic), + SH_PFC_PIN_GROUP(avb2_phy_int), + SH_PFC_PIN_GROUP(avb2_mdio), + SH_PFC_PIN_GROUP(avb2_rgmii), + SH_PFC_PIN_GROUP(avb2_txcrefclk), + SH_PFC_PIN_GROUP(avb2_avtp_pps), + SH_PFC_PIN_GROUP(avb2_avtp_capture), + SH_PFC_PIN_GROUP(avb2_avtp_match), + + SH_PFC_PIN_GROUP(avb3_link), + SH_PFC_PIN_GROUP(avb3_magic), + SH_PFC_PIN_GROUP(avb3_phy_int), + SH_PFC_PIN_GROUP(avb3_mdio), + SH_PFC_PIN_GROUP(avb3_rgmii), + SH_PFC_PIN_GROUP(avb3_txcrefclk), + SH_PFC_PIN_GROUP(avb3_avtp_pps), + SH_PFC_PIN_GROUP(avb3_avtp_capture), + SH_PFC_PIN_GROUP(avb3_avtp_match), + + SH_PFC_PIN_GROUP(avb4_link), + SH_PFC_PIN_GROUP(avb4_magic), + SH_PFC_PIN_GROUP(avb4_phy_int), + SH_PFC_PIN_GROUP(avb4_mdio), + SH_PFC_PIN_GROUP(avb4_rgmii), + SH_PFC_PIN_GROUP(avb4_txcrefclk), + SH_PFC_PIN_GROUP(avb4_avtp_pps), + SH_PFC_PIN_GROUP(avb4_avtp_capture), + SH_PFC_PIN_GROUP(avb4_avtp_match), + + SH_PFC_PIN_GROUP(avb5_link), + SH_PFC_PIN_GROUP(avb5_magic), + SH_PFC_PIN_GROUP(avb5_phy_int), + SH_PFC_PIN_GROUP(avb5_mdio), + SH_PFC_PIN_GROUP(avb5_rgmii), + SH_PFC_PIN_GROUP(avb5_txcrefclk), + SH_PFC_PIN_GROUP(avb5_avtp_pps), + SH_PFC_PIN_GROUP(avb5_avtp_capture), + SH_PFC_PIN_GROUP(avb5_avtp_match), + + SH_PFC_PIN_GROUP(canfd0_data), + SH_PFC_PIN_GROUP(canfd1_data), + SH_PFC_PIN_GROUP(canfd2_data), + SH_PFC_PIN_GROUP(canfd3_data), + SH_PFC_PIN_GROUP(canfd4_data), + SH_PFC_PIN_GROUP(canfd5_data), + SH_PFC_PIN_GROUP(canfd6_data), + SH_PFC_PIN_GROUP(canfd7_data), + SH_PFC_PIN_GROUP(can_clk), + + SH_PFC_PIN_GROUP(du_rgb888), + SH_PFC_PIN_GROUP(du_clk_out), + SH_PFC_PIN_GROUP(du_sync), + SH_PFC_PIN_GROUP(du_oddf), + + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif1_data), + SH_PFC_PIN_GROUP(hscif1_clk), + SH_PFC_PIN_GROUP(hscif1_ctrl), + SH_PFC_PIN_GROUP(hscif2_data), + SH_PFC_PIN_GROUP(hscif2_clk), + SH_PFC_PIN_GROUP(hscif2_ctrl), + SH_PFC_PIN_GROUP(hscif3_data), + SH_PFC_PIN_GROUP(hscif3_clk), + SH_PFC_PIN_GROUP(hscif3_ctrl), + + SH_PFC_PIN_GROUP(i2c0), + SH_PFC_PIN_GROUP(i2c1), + SH_PFC_PIN_GROUP(i2c2), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c4), + SH_PFC_PIN_GROUP(i2c5), + SH_PFC_PIN_GROUP(i2c6), + + SH_PFC_PIN_GROUP(intc_ex_irq0), + SH_PFC_PIN_GROUP(intc_ex_irq1), + SH_PFC_PIN_GROUP(intc_ex_irq2), + SH_PFC_PIN_GROUP(intc_ex_irq3), + SH_PFC_PIN_GROUP(intc_ex_irq4), + SH_PFC_PIN_GROUP(intc_ex_irq5), + + SH_PFC_PIN_GROUP(mmc_data1), + SH_PFC_PIN_GROUP(mmc_data4), + SH_PFC_PIN_GROUP(mmc_data8), + SH_PFC_PIN_GROUP(mmc_ctrl), + SH_PFC_PIN_GROUP(mmc_cd), + SH_PFC_PIN_GROUP(mmc_wp), + SH_PFC_PIN_GROUP(mmc_ds), + + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_txd), + SH_PFC_PIN_GROUP(msiof0_rxd), + SH_PFC_PIN_GROUP(msiof1_clk), + SH_PFC_PIN_GROUP(msiof1_sync), + SH_PFC_PIN_GROUP(msiof1_ss1), + SH_PFC_PIN_GROUP(msiof1_ss2), + SH_PFC_PIN_GROUP(msiof1_txd), + SH_PFC_PIN_GROUP(msiof1_rxd), + SH_PFC_PIN_GROUP(msiof2_clk), + SH_PFC_PIN_GROUP(msiof2_sync), + SH_PFC_PIN_GROUP(msiof2_ss1), + SH_PFC_PIN_GROUP(msiof2_ss2), + SH_PFC_PIN_GROUP(msiof2_txd), + SH_PFC_PIN_GROUP(msiof2_rxd), + SH_PFC_PIN_GROUP(msiof3_clk), + SH_PFC_PIN_GROUP(msiof3_sync), + SH_PFC_PIN_GROUP(msiof3_ss1), + SH_PFC_PIN_GROUP(msiof3_ss2), + SH_PFC_PIN_GROUP(msiof3_txd), + SH_PFC_PIN_GROUP(msiof3_rxd), + SH_PFC_PIN_GROUP(msiof4_clk), + SH_PFC_PIN_GROUP(msiof4_sync), + SH_PFC_PIN_GROUP(msiof4_ss1), + SH_PFC_PIN_GROUP(msiof4_ss2), + SH_PFC_PIN_GROUP(msiof4_txd), + SH_PFC_PIN_GROUP(msiof4_rxd), + SH_PFC_PIN_GROUP(msiof5_clk), + SH_PFC_PIN_GROUP(msiof5_sync), + SH_PFC_PIN_GROUP(msiof5_ss1), + SH_PFC_PIN_GROUP(msiof5_ss2), + SH_PFC_PIN_GROUP(msiof5_txd), + SH_PFC_PIN_GROUP(msiof5_rxd), + + SH_PFC_PIN_GROUP(pwm0), + SH_PFC_PIN_GROUP(pwm1), + SH_PFC_PIN_GROUP(pwm2), + SH_PFC_PIN_GROUP(pwm3), + SH_PFC_PIN_GROUP(pwm4), + + SH_PFC_PIN_GROUP(qspi0_ctrl), + SH_PFC_PIN_GROUP(qspi0_data2), + SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + SH_PFC_PIN_GROUP(qspi1_data2), + SH_PFC_PIN_GROUP(qspi1_data4), + + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif1_data_a), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif3_data), + SH_PFC_PIN_GROUP(scif3_clk), + SH_PFC_PIN_GROUP(scif3_ctrl), + SH_PFC_PIN_GROUP(scif4_data), + SH_PFC_PIN_GROUP(scif4_clk), + SH_PFC_PIN_GROUP(scif4_ctrl), + SH_PFC_PIN_GROUP(scif_clk), + + SH_PFC_PIN_GROUP(tmu_tclk1_a), + SH_PFC_PIN_GROUP(tmu_tclk1_b), + SH_PFC_PIN_GROUP(tmu_tclk2_a), + SH_PFC_PIN_GROUP(tmu_tclk2_b), + SH_PFC_PIN_GROUP(tmu_tclk3), + SH_PFC_PIN_GROUP(tmu_tclk4), + + SH_PFC_PIN_GROUP(tpu_to0), + SH_PFC_PIN_GROUP(tpu_to1), + SH_PFC_PIN_GROUP(tpu_to2), + SH_PFC_PIN_GROUP(tpu_to3), +}; + +static const char * const avb0_groups[] = { + "avb0_link", + "avb0_magic", + "avb0_phy_int", + "avb0_mdio", + "avb0_rgmii", + "avb0_txcrefclk", + "avb0_avtp_pps", + "avb0_avtp_capture", + "avb0_avtp_match", +}; + +static const char * const avb1_groups[] = { + "avb1_link", + "avb1_magic", + "avb1_phy_int", + "avb1_mdio", + "avb1_rgmii", + "avb1_txcrefclk", + "avb1_avtp_pps", + "avb1_avtp_capture", + "avb1_avtp_match", +}; + +static const char * const avb2_groups[] = { + "avb2_link", + "avb2_magic", + "avb2_phy_int", + "avb2_mdio", + "avb2_rgmii", + "avb2_txcrefclk", + "avb2_avtp_pps", + "avb2_avtp_capture", + "avb2_avtp_match", +}; + +static const char * const avb3_groups[] = { + "avb3_link", + "avb3_magic", + "avb3_phy_int", + "avb3_mdio", + "avb3_rgmii", + "avb3_txcrefclk", + "avb3_avtp_pps", + "avb3_avtp_capture", + "avb3_avtp_match", +}; + +static const char * const avb4_groups[] = { + "avb4_link", + "avb4_magic", + "avb4_phy_int", + "avb4_mdio", + "avb4_rgmii", + "avb4_txcrefclk", + "avb4_avtp_pps", + "avb4_avtp_capture", + "avb4_avtp_match", +}; + +static const char * const avb5_groups[] = { + "avb5_link", + "avb5_magic", + "avb5_phy_int", + "avb5_mdio", + "avb5_rgmii", + "avb5_txcrefclk", + "avb5_avtp_pps", + "avb5_avtp_capture", + "avb5_avtp_match", +}; + +static const char * const canfd0_groups[] = { + "canfd0_data", +}; + +static const char * const canfd1_groups[] = { + "canfd1_data", +}; + +static const char * const canfd2_groups[] = { + "canfd2_data", +}; + +static const char * const canfd3_groups[] = { + "canfd3_data", +}; + +static const char * const canfd4_groups[] = { + "canfd4_data", +}; + +static const char * const canfd5_groups[] = { + "canfd5_data", +}; + +static const char * const canfd6_groups[] = { + "canfd6_data", +}; + +static const char * const canfd7_groups[] = { + "canfd7_data", +}; + +static const char * const can_clk_groups[] = { + "can_clk", +}; + +static const char * const du_groups[] = { + "du_rgb888", + "du_clk_out", + "du_sync", + "du_oddf", +}; + +static const char * const hscif0_groups[] = { + "hscif0_data", + "hscif0_clk", + "hscif0_ctrl", +}; + +static const char * const hscif1_groups[] = { + "hscif1_data", + "hscif1_clk", + "hscif1_ctrl", +}; + +static const char * const hscif2_groups[] = { + "hscif2_data", + "hscif2_clk", + "hscif2_ctrl", +}; + +static const char * const hscif3_groups[] = { + "hscif3_data", + "hscif3_clk", + "hscif3_ctrl", +}; + +static const char * const i2c0_groups[] = { + "i2c0", +}; + +static const char * const i2c1_groups[] = { + "i2c1", +}; + +static const char * const i2c2_groups[] = { + "i2c2", +}; + +static const char * const i2c3_groups[] = { + "i2c3", +}; + +static const char * const i2c4_groups[] = { + "i2c4", +}; + +static const char * const i2c5_groups[] = { + "i2c5", +}; + +static const char * const i2c6_groups[] = { + "i2c6", +}; + +static const char * const intc_ex_groups[] = { + "intc_ex_irq0", + "intc_ex_irq1", + "intc_ex_irq2", + "intc_ex_irq3", + "intc_ex_irq4", + "intc_ex_irq5", +}; + +static const char * const mmc_groups[] = { + "mmc_data1", + "mmc_data4", + "mmc_data8", + "mmc_ctrl", + "mmc_cd", + "mmc_wp", + "mmc_ds", +}; + +static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", + "msiof0_ss1", + "msiof0_ss2", + "msiof0_txd", + "msiof0_rxd", +}; + +static const char * const msiof1_groups[] = { + "msiof1_clk", + "msiof1_sync", + "msiof1_ss1", + "msiof1_ss2", + "msiof1_txd", + "msiof1_rxd", +}; + +static const char * const msiof2_groups[] = { + "msiof2_clk", + "msiof2_sync", + "msiof2_ss1", + "msiof2_ss2", + "msiof2_txd", + "msiof2_rxd", +}; + +static const char * const msiof3_groups[] = { + "msiof3_clk", + "msiof3_sync", + "msiof3_ss1", + "msiof3_ss2", + "msiof3_txd", + "msiof3_rxd", +}; + +static const char * const msiof4_groups[] = { + "msiof4_clk", + "msiof4_sync", + "msiof4_ss1", + "msiof4_ss2", + "msiof4_txd", + "msiof4_rxd", +}; + +static const char * const msiof5_groups[] = { + "msiof5_clk", + "msiof5_sync", + "msiof5_ss1", + "msiof5_ss2", + "msiof5_txd", + "msiof5_rxd", +}; + +static const char * const pwm0_groups[] = { + "pwm0", +}; + +static const char * const pwm1_groups[] = { + "pwm1", +}; + +static const char * const pwm2_groups[] = { + "pwm2", +}; + +static const char * const pwm3_groups[] = { + "pwm3", +}; + +static const char * const pwm4_groups[] = { + "pwm4", +}; + +static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + +static const char * const scif0_groups[] = { + "scif0_data", + "scif0_clk", + "scif0_ctrl", +}; + +static const char * const scif1_groups[] = { + "scif1_data_a", + "scif1_data_b", + "scif1_clk", + "scif1_ctrl", +}; + +static const char * const scif3_groups[] = { + "scif3_data", + "scif3_clk", + "scif3_ctrl", +}; + +static const char * const scif4_groups[] = { + "scif4_data", + "scif4_clk", + "scif4_ctrl", +}; + +static const char * const scif_clk_groups[] = { + "scif_clk", +}; + +static const char * const tmu_groups[] = { + "tmu_tclk1_a", + "tmu_tclk1_b", + "tmu_tclk2_a", + "tmu_tclk2_b", + "tmu_tclk3", + "tmu_tclk4", +}; + +static const char * const tpu_groups[] = { + "tpu_to0", + "tpu_to1", + "tpu_to2", + "tpu_to3", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(avb0), + SH_PFC_FUNCTION(avb1), + SH_PFC_FUNCTION(avb2), + SH_PFC_FUNCTION(avb3), + SH_PFC_FUNCTION(avb4), + SH_PFC_FUNCTION(avb5), + + SH_PFC_FUNCTION(canfd0), + SH_PFC_FUNCTION(canfd1), + SH_PFC_FUNCTION(canfd2), + SH_PFC_FUNCTION(canfd3), + SH_PFC_FUNCTION(canfd4), + SH_PFC_FUNCTION(canfd5), + SH_PFC_FUNCTION(canfd6), + SH_PFC_FUNCTION(canfd7), + SH_PFC_FUNCTION(can_clk), + + SH_PFC_FUNCTION(du), + + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hscif2), + SH_PFC_FUNCTION(hscif3), + + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c4), + SH_PFC_FUNCTION(i2c5), + SH_PFC_FUNCTION(i2c6), + + SH_PFC_FUNCTION(intc_ex), + + SH_PFC_FUNCTION(mmc), + + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(msiof4), + SH_PFC_FUNCTION(msiof5), + + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), + + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif_clk), + + SH_PFC_FUNCTION(tmu), + + SH_PFC_FUNCTION(tpu), +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { +#define F_(x, y) FN_##y +#define FM(x) FN_##x + { PINMUX_CFG_REG("GPSR0", 0xe6058040, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_0_27_FN, GPSR0_27, + GP_0_26_FN, GPSR0_26, + GP_0_25_FN, GPSR0_25, + GP_0_24_FN, GPSR0_24, + GP_0_23_FN, GPSR0_23, + GP_0_22_FN, GPSR0_22, + GP_0_21_FN, GPSR0_21, + GP_0_20_FN, GPSR0_20, + GP_0_19_FN, GPSR0_19, + GP_0_18_FN, GPSR0_18, + GP_0_17_FN, GPSR0_17, + GP_0_16_FN, GPSR0_16, + GP_0_15_FN, GPSR0_15, + GP_0_14_FN, GPSR0_14, + GP_0_13_FN, GPSR0_13, + GP_0_12_FN, GPSR0_12, + GP_0_11_FN, GPSR0_11, + GP_0_10_FN, GPSR0_10, + GP_0_9_FN, GPSR0_9, + GP_0_8_FN, GPSR0_8, + GP_0_7_FN, GPSR0_7, + GP_0_6_FN, GPSR0_6, + GP_0_5_FN, GPSR0_5, + GP_0_4_FN, GPSR0_4, + GP_0_3_FN, GPSR0_3, + GP_0_2_FN, GPSR0_2, + GP_0_1_FN, GPSR0_1, + GP_0_0_FN, GPSR0_0, )) + }, + { PINMUX_CFG_REG("GPSR1", 0xe6050040, 32, 1, GROUP( + 0, 0, + GP_1_30_FN, GPSR1_30, + GP_1_29_FN, GPSR1_29, + GP_1_28_FN, GPSR1_28, + GP_1_27_FN, GPSR1_27, + GP_1_26_FN, GPSR1_26, + GP_1_25_FN, GPSR1_25, + GP_1_24_FN, GPSR1_24, + GP_1_23_FN, GPSR1_23, + GP_1_22_FN, GPSR1_22, + GP_1_21_FN, GPSR1_21, + GP_1_20_FN, GPSR1_20, + GP_1_19_FN, GPSR1_19, + GP_1_18_FN, GPSR1_18, + GP_1_17_FN, GPSR1_17, + GP_1_16_FN, GPSR1_16, + GP_1_15_FN, GPSR1_15, + GP_1_14_FN, GPSR1_14, + GP_1_13_FN, GPSR1_13, + GP_1_12_FN, GPSR1_12, + GP_1_11_FN, GPSR1_11, + GP_1_10_FN, GPSR1_10, + GP_1_9_FN, GPSR1_9, + GP_1_8_FN, GPSR1_8, + GP_1_7_FN, GPSR1_7, + GP_1_6_FN, GPSR1_6, + GP_1_5_FN, GPSR1_5, + GP_1_4_FN, GPSR1_4, + GP_1_3_FN, GPSR1_3, + GP_1_2_FN, GPSR1_2, + GP_1_1_FN, GPSR1_1, + GP_1_0_FN, GPSR1_0, )) + }, + { PINMUX_CFG_REG("GPSR2", 0xe6050840, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_2_24_FN, GPSR2_24, + GP_2_23_FN, GPSR2_23, + GP_2_22_FN, GPSR2_22, + GP_2_21_FN, GPSR2_21, + GP_2_20_FN, GPSR2_20, + GP_2_19_FN, GPSR2_19, + GP_2_18_FN, GPSR2_18, + GP_2_17_FN, GPSR2_17, + GP_2_16_FN, GPSR2_16, + GP_2_15_FN, GPSR2_15, + GP_2_14_FN, GPSR2_14, + GP_2_13_FN, GPSR2_13, + GP_2_12_FN, GPSR2_12, + GP_2_11_FN, GPSR2_11, + GP_2_10_FN, GPSR2_10, + GP_2_9_FN, GPSR2_9, + GP_2_8_FN, GPSR2_8, + GP_2_7_FN, GPSR2_7, + GP_2_6_FN, GPSR2_6, + GP_2_5_FN, GPSR2_5, + GP_2_4_FN, GPSR2_4, + GP_2_3_FN, GPSR2_3, + GP_2_2_FN, GPSR2_2, + GP_2_1_FN, GPSR2_1, + GP_2_0_FN, GPSR2_0, )) + }, + { PINMUX_CFG_REG("GPSR3", 0xe6058840, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_3_16_FN, GPSR3_16, + GP_3_15_FN, GPSR3_15, + GP_3_14_FN, GPSR3_14, + GP_3_13_FN, GPSR3_13, + GP_3_12_FN, GPSR3_12, + GP_3_11_FN, GPSR3_11, + GP_3_10_FN, GPSR3_10, + GP_3_9_FN, GPSR3_9, + GP_3_8_FN, GPSR3_8, + GP_3_7_FN, GPSR3_7, + GP_3_6_FN, GPSR3_6, + GP_3_5_FN, GPSR3_5, + GP_3_4_FN, GPSR3_4, + GP_3_3_FN, GPSR3_3, + GP_3_2_FN, GPSR3_2, + GP_3_1_FN, GPSR3_1, + GP_3_0_FN, GPSR3_0, )) + }, + { PINMUX_CFG_REG("GPSR4", 0xe6060040, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_4_26_FN, GPSR4_26, + GP_4_25_FN, GPSR4_25, + GP_4_24_FN, GPSR4_24, + GP_4_23_FN, GPSR4_23, + GP_4_22_FN, GPSR4_22, + GP_4_21_FN, GPSR4_21, + GP_4_20_FN, GPSR4_20, + GP_4_19_FN, GPSR4_19, + GP_4_18_FN, GPSR4_18, + GP_4_17_FN, GPSR4_17, + GP_4_16_FN, GPSR4_16, + GP_4_15_FN, GPSR4_15, + GP_4_14_FN, GPSR4_14, + GP_4_13_FN, GPSR4_13, + GP_4_12_FN, GPSR4_12, + GP_4_11_FN, GPSR4_11, + GP_4_10_FN, GPSR4_10, + GP_4_9_FN, GPSR4_9, + GP_4_8_FN, GPSR4_8, + GP_4_7_FN, GPSR4_7, + GP_4_6_FN, GPSR4_6, + GP_4_5_FN, GPSR4_5, + GP_4_4_FN, GPSR4_4, + GP_4_3_FN, GPSR4_3, + GP_4_2_FN, GPSR4_2, + GP_4_1_FN, GPSR4_1, + GP_4_0_FN, GPSR4_0, )) + }, + { PINMUX_CFG_REG("GPSR5", 0xe6060840, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_5_20_FN, GPSR5_20, + GP_5_19_FN, GPSR5_19, + GP_5_18_FN, GPSR5_18, + GP_5_17_FN, GPSR5_17, + GP_5_16_FN, GPSR5_16, + GP_5_15_FN, GPSR5_15, + GP_5_14_FN, GPSR5_14, + GP_5_13_FN, GPSR5_13, + GP_5_12_FN, GPSR5_12, + GP_5_11_FN, GPSR5_11, + GP_5_10_FN, GPSR5_10, + GP_5_9_FN, GPSR5_9, + GP_5_8_FN, GPSR5_8, + GP_5_7_FN, GPSR5_7, + GP_5_6_FN, GPSR5_6, + GP_5_5_FN, GPSR5_5, + GP_5_4_FN, GPSR5_4, + GP_5_3_FN, GPSR5_3, + GP_5_2_FN, GPSR5_2, + GP_5_1_FN, GPSR5_1, + GP_5_0_FN, GPSR5_0, )) + }, + { PINMUX_CFG_REG("GPSR6", 0xe6068040, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_6_20_FN, GPSR6_20, + GP_6_19_FN, GPSR6_19, + GP_6_18_FN, GPSR6_18, + GP_6_17_FN, GPSR6_17, + GP_6_16_FN, GPSR6_16, + GP_6_15_FN, GPSR6_15, + GP_6_14_FN, GPSR6_14, + GP_6_13_FN, GPSR6_13, + GP_6_12_FN, GPSR6_12, + GP_6_11_FN, GPSR6_11, + GP_6_10_FN, GPSR6_10, + GP_6_9_FN, GPSR6_9, + GP_6_8_FN, GPSR6_8, + GP_6_7_FN, GPSR6_7, + GP_6_6_FN, GPSR6_6, + GP_6_5_FN, GPSR6_5, + GP_6_4_FN, GPSR6_4, + GP_6_3_FN, GPSR6_3, + GP_6_2_FN, GPSR6_2, + GP_6_1_FN, GPSR6_1, + GP_6_0_FN, GPSR6_0, )) + }, + { PINMUX_CFG_REG("GPSR7", 0xe6068840, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_7_20_FN, GPSR7_20, + GP_7_19_FN, GPSR7_19, + GP_7_18_FN, GPSR7_18, + GP_7_17_FN, GPSR7_17, + GP_7_16_FN, GPSR7_16, + GP_7_15_FN, GPSR7_15, + GP_7_14_FN, GPSR7_14, + GP_7_13_FN, GPSR7_13, + GP_7_12_FN, GPSR7_12, + GP_7_11_FN, GPSR7_11, + GP_7_10_FN, GPSR7_10, + GP_7_9_FN, GPSR7_9, + GP_7_8_FN, GPSR7_8, + GP_7_7_FN, GPSR7_7, + GP_7_6_FN, GPSR7_6, + GP_7_5_FN, GPSR7_5, + GP_7_4_FN, GPSR7_4, + GP_7_3_FN, GPSR7_3, + GP_7_2_FN, GPSR7_2, + GP_7_1_FN, GPSR7_1, + GP_7_0_FN, GPSR7_0, )) + }, + { PINMUX_CFG_REG("GPSR8", 0xe6069040, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_8_20_FN, GPSR8_20, + GP_8_19_FN, GPSR8_19, + GP_8_18_FN, GPSR8_18, + GP_8_17_FN, GPSR8_17, + GP_8_16_FN, GPSR8_16, + GP_8_15_FN, GPSR8_15, + GP_8_14_FN, GPSR8_14, + GP_8_13_FN, GPSR8_13, + GP_8_12_FN, GPSR8_12, + GP_8_11_FN, GPSR8_11, + GP_8_10_FN, GPSR8_10, + GP_8_9_FN, GPSR8_9, + GP_8_8_FN, GPSR8_8, + GP_8_7_FN, GPSR8_7, + GP_8_6_FN, GPSR8_6, + GP_8_5_FN, GPSR8_5, + GP_8_4_FN, GPSR8_4, + GP_8_3_FN, GPSR8_3, + GP_8_2_FN, GPSR8_2, + GP_8_1_FN, GPSR8_1, + GP_8_0_FN, GPSR8_0, )) + }, + { PINMUX_CFG_REG("GPSR9", 0xe6069840, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_9_20_FN, GPSR9_20, + GP_9_19_FN, GPSR9_19, + GP_9_18_FN, GPSR9_18, + GP_9_17_FN, GPSR9_17, + GP_9_16_FN, GPSR9_16, + GP_9_15_FN, GPSR9_15, + GP_9_14_FN, GPSR9_14, + GP_9_13_FN, GPSR9_13, + GP_9_12_FN, GPSR9_12, + GP_9_11_FN, GPSR9_11, + GP_9_10_FN, GPSR9_10, + GP_9_9_FN, GPSR9_9, + GP_9_8_FN, GPSR9_8, + GP_9_7_FN, GPSR9_7, + GP_9_6_FN, GPSR9_6, + GP_9_5_FN, GPSR9_5, + GP_9_4_FN, GPSR9_4, + GP_9_3_FN, GPSR9_3, + GP_9_2_FN, GPSR9_2, + GP_9_1_FN, GPSR9_1, + GP_9_0_FN, GPSR9_0, )) + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG("IP0SR1", 0xe6050060, 32, 4, GROUP( + IP0SR1_31_28 + IP0SR1_27_24 + IP0SR1_23_20 + IP0SR1_19_16 + IP0SR1_15_12 + IP0SR1_11_8 + IP0SR1_7_4 + IP0SR1_3_0)) + }, + { PINMUX_CFG_REG("IP1SR1", 0xe6050064, 32, 4, GROUP( + IP1SR1_31_28 + IP1SR1_27_24 + IP1SR1_23_20 + IP1SR1_19_16 + IP1SR1_15_12 + IP1SR1_11_8 + IP1SR1_7_4 + IP1SR1_3_0)) + }, + { PINMUX_CFG_REG("IP2SR1", 0xe6050068, 32, 4, GROUP( + IP2SR1_31_28 + IP2SR1_27_24 + IP2SR1_23_20 + IP2SR1_19_16 + IP2SR1_15_12 + IP2SR1_11_8 + IP2SR1_7_4 + IP2SR1_3_0)) + }, + { PINMUX_CFG_REG("IP3SR1", 0xe605006c, 32, 4, GROUP( + IP3SR1_31_28 + IP3SR1_27_24 + IP3SR1_23_20 + IP3SR1_19_16 + IP3SR1_15_12 + IP3SR1_11_8 + IP3SR1_7_4 + IP3SR1_3_0)) + }, + { PINMUX_CFG_REG("IP0SR2", 0xe6050860, 32, 4, GROUP( + IP0SR2_31_28 + IP0SR2_27_24 + IP0SR2_23_20 + IP0SR2_19_16 + IP0SR2_15_12 + IP0SR2_11_8 + IP0SR2_7_4 + IP0SR2_3_0)) + }, + { PINMUX_CFG_REG("IP1SR2", 0xe6050864, 32, 4, GROUP( + IP1SR2_31_28 + IP1SR2_27_24 + IP1SR2_23_20 + IP1SR2_19_16 + IP1SR2_15_12 + IP1SR2_11_8 + IP1SR2_7_4 + IP1SR2_3_0)) + }, + { PINMUX_CFG_REG("IP2SR2", 0xe6050868, 32, 4, GROUP( + IP2SR2_31_28 + IP2SR2_27_24 + IP2SR2_23_20 + IP2SR2_19_16 + IP2SR2_15_12 + IP2SR2_11_8 + IP2SR2_7_4 + IP2SR2_3_0)) + }, + { PINMUX_CFG_REG("IP0SR3", 0xe6058860, 32, 4, GROUP( + IP0SR3_31_28 + IP0SR3_27_24 + IP0SR3_23_20 + IP0SR3_19_16 + IP0SR3_15_12 + IP0SR3_11_8 + IP0SR3_7_4 + IP0SR3_3_0)) + }, + { PINMUX_CFG_REG("IP1SR3", 0xe6058864, 32, 4, GROUP( + IP1SR3_31_28 + IP1SR3_27_24 + IP1SR3_23_20 + IP1SR3_19_16 + IP1SR3_15_12 + IP1SR3_11_8 + IP1SR3_7_4 + IP1SR3_3_0)) + }, + { PINMUX_CFG_REG("IP0SR4", 0xe6060060, 32, 4, GROUP( + IP0SR4_31_28 + IP0SR4_27_24 + IP0SR4_23_20 + IP0SR4_19_16 + IP0SR4_15_12 + IP0SR4_11_8 + IP0SR4_7_4 + IP0SR4_3_0)) + }, + { PINMUX_CFG_REG("IP1SR4", 0xe6060064, 32, 4, GROUP( + IP1SR4_31_28 + IP1SR4_27_24 + IP1SR4_23_20 + IP1SR4_19_16 + IP1SR4_15_12 + IP1SR4_11_8 + IP1SR4_7_4 + IP1SR4_3_0)) + }, + { PINMUX_CFG_REG("IP2SR4", 0xe6060068, 32, 4, GROUP( + IP2SR4_31_28 + IP2SR4_27_24 + IP2SR4_23_20 + IP2SR4_19_16 + IP2SR4_15_12 + IP2SR4_11_8 + IP2SR4_7_4 + IP2SR4_3_0)) + }, + { PINMUX_CFG_REG("IP0SR5", 0xe6060860, 32, 4, GROUP( + IP0SR5_31_28 + IP0SR5_27_24 + IP0SR5_23_20 + IP0SR5_19_16 + IP0SR5_15_12 + IP0SR5_11_8 + IP0SR5_7_4 + IP0SR5_3_0)) + }, + { PINMUX_CFG_REG("IP1SR5", 0xe6060864, 32, 4, GROUP( + IP1SR5_31_28 + IP1SR5_27_24 + IP1SR5_23_20 + IP1SR5_19_16 + IP1SR5_15_12 + IP1SR5_11_8 + IP1SR5_7_4 + IP1SR5_3_0)) + }, + { PINMUX_CFG_REG("IP2SR5", 0xe6060868, 32, 4, GROUP( + IP2SR5_31_28 + IP2SR5_27_24 + IP2SR5_23_20 + IP2SR5_19_16 + IP2SR5_15_12 + IP2SR5_11_8 + IP2SR5_7_4 + IP2SR5_3_0)) + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6050900, 32, + GROUP(4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 1, 1), + GROUP( + /* RESERVED 31, 30, 29, 28 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 27, 26, 25, 24 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 23, 22, 21, 20 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 19, 18, 17, 16 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + MOD_SEL2_14_15 + MOD_SEL2_12_13 + MOD_SEL2_10_11 + MOD_SEL2_8_9 + MOD_SEL2_6_7 + MOD_SEL2_4_5 + MOD_SEL2_2_3 + 0, 0, + 0, 0, )) + }, + { }, +}; + +static const struct pinmux_drive_reg pinmux_drive_regs[] = { + { PINMUX_DRIVE_REG("DRV0CTRL0", 0xe6058080) { + { RCAR_GP_PIN(0, 7), 28, 2 }, /* QSPI1_MOSI_IO0 */ + { RCAR_GP_PIN(0, 6), 24, 2 }, /* QSPI1_SPCLK */ + { RCAR_GP_PIN(0, 5), 20, 2 }, /* QSPI0_SSL */ + { RCAR_GP_PIN(0, 4), 16, 2 }, /* QSPI0_IO3 */ + { RCAR_GP_PIN(0, 3), 12, 2 }, /* QSPI0_IO2 */ + { RCAR_GP_PIN(0, 2), 8, 2 }, /* QSPI0_MISO_IO1 */ + { RCAR_GP_PIN(0, 1), 4, 2 }, /* QSPI0_MOSI_IO0 */ + { RCAR_GP_PIN(0, 0), 0, 2 }, /* QSPI0_SPCLK */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL0", 0xe6058084) { + { RCAR_GP_PIN(0, 15), 28, 3 }, /* SD_WP */ + { RCAR_GP_PIN(0, 14), 24, 2 }, /* RPC_INT_N */ + { RCAR_GP_PIN(0, 13), 20, 2 }, /* RPC_WP_N */ + { RCAR_GP_PIN(0, 12), 16, 2 }, /* RPC_RESET_N */ + { RCAR_GP_PIN(0, 11), 12, 2 }, /* QSPI1_SSL */ + { RCAR_GP_PIN(0, 10), 8, 2 }, /* QSPI1_IO3 */ + { RCAR_GP_PIN(0, 9), 4, 2 }, /* QSPI1_IO2 */ + { RCAR_GP_PIN(0, 8), 0, 2 }, /* QSPI1_MISO_IO1 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL0", 0xe6058088) { + { RCAR_GP_PIN(0, 23), 28, 3 }, /* MMC_SD_CLK */ + { RCAR_GP_PIN(0, 22), 24, 3 }, /* MMC_SD_D3 */ + { RCAR_GP_PIN(0, 21), 20, 3 }, /* MMC_SD_D2 */ + { RCAR_GP_PIN(0, 20), 16, 3 }, /* MMC_SD_D1 */ + { RCAR_GP_PIN(0, 19), 12, 3 }, /* MMC_SD_D0 */ + { RCAR_GP_PIN(0, 18), 8, 3 }, /* MMC_SD_CMD */ + { RCAR_GP_PIN(0, 17), 4, 3 }, /* MMC_DS */ + { RCAR_GP_PIN(0, 16), 0, 3 }, /* SD_CD */ + } }, + { PINMUX_DRIVE_REG("DRV3CTRL0", 0xe605808c) { + { RCAR_GP_PIN(0, 27), 12, 3 }, /* MMC_D7 */ + { RCAR_GP_PIN(0, 26), 8, 3 }, /* MMC_D6 */ + { RCAR_GP_PIN(0, 25), 4, 3 }, /* MMC_D5 */ + { RCAR_GP_PIN(0, 24), 0, 3 }, /* MMC_D4 */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL1", 0xe6050080) { + { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_TXD */ + { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_RXD */ + { RCAR_GP_PIN(1, 5), 20, 3 }, /* HTX0 */ + { RCAR_GP_PIN(1, 4), 16, 3 }, /* HCTS0_N */ + { RCAR_GP_PIN(1, 3), 12, 3 }, /* HRTS0_N */ + { RCAR_GP_PIN(1, 2), 8, 3 }, /* HSCK0 */ + { RCAR_GP_PIN(1, 1), 4, 3 }, /* HRX0 */ + { RCAR_GP_PIN(1, 0), 0, 3 }, /* SCIF_CLK */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL1", 0xe6050084) { + { RCAR_GP_PIN(1, 15), 28, 3 }, /* MSIOF1_SYNC */ + { RCAR_GP_PIN(1, 14), 24, 3 }, /* MSIOF1_SCK */ + { RCAR_GP_PIN(1, 13), 20, 3 }, /* MSIOF1_TXD */ + { RCAR_GP_PIN(1, 12), 16, 3 }, /* MSIOF1_RXD */ + { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_SS2 */ + { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SS1 */ + { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_SYNC */ + { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SCK */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL1", 0xe6050088) { + { RCAR_GP_PIN(1, 23), 28, 3 }, /* MSIOF2_SS2 */ + { RCAR_GP_PIN(1, 22), 24, 3 }, /* MSIOF2_SS1 */ + { RCAR_GP_PIN(1, 21), 20, 3 }, /* MSIOF2_SYNC */ + { RCAR_GP_PIN(1, 20), 16, 3 }, /* MSIOF2_SCK */ + { RCAR_GP_PIN(1, 19), 12, 3 }, /* MSIOF2_TXD */ + { RCAR_GP_PIN(1, 18), 8, 3 }, /* MSIOF2_RXD */ + { RCAR_GP_PIN(1, 17), 4, 3 }, /* MSIOF1_SS2 */ + { RCAR_GP_PIN(1, 16), 0, 3 }, /* MSIOF1_SS1 */ + } }, + { PINMUX_DRIVE_REG("DRV3CTRL1", 0xe605008c) { + { RCAR_GP_PIN(1, 30), 24, 3 }, /* GP1_30 */ + { RCAR_GP_PIN(1, 29), 20, 3 }, /* GP1_29 */ + { RCAR_GP_PIN(1, 28), 16, 3 }, /* GP1_28 */ + { RCAR_GP_PIN(1, 27), 12, 3 }, /* IRQ3 */ + { RCAR_GP_PIN(1, 26), 8, 3 }, /* IRQ2 */ + { RCAR_GP_PIN(1, 25), 4, 3 }, /* IRQ1 */ + { RCAR_GP_PIN(1, 24), 0, 3 }, /* IRQ0 */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL2", 0xe6050880) { + { RCAR_GP_PIN(2, 7), 28, 3 }, /* GP2_07 */ + { RCAR_GP_PIN(2, 6), 24, 3 }, /* GP2_06 */ + { RCAR_GP_PIN(2, 5), 20, 3 }, /* GP2_05 */ + { RCAR_GP_PIN(2, 4), 16, 3 }, /* GP2_04 */ + { RCAR_GP_PIN(2, 3), 12, 3 }, /* GP2_03 */ + { RCAR_GP_PIN(2, 2), 8, 3 }, /* GP2_02 */ + { RCAR_GP_PIN(2, 1), 4, 2 }, /* IPC_CLKOUT */ + { RCAR_GP_PIN(2, 0), 0, 2 }, /* IPC_CLKIN */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL2", 0xe6050884) { + { RCAR_GP_PIN(2, 15), 28, 3 }, /* GP2_15 */ + { RCAR_GP_PIN(2, 14), 24, 3 }, /* GP2_14 */ + { RCAR_GP_PIN(2, 13), 20, 3 }, /* GP2_13 */ + { RCAR_GP_PIN(2, 12), 16, 3 }, /* GP2_12 */ + { RCAR_GP_PIN(2, 11), 12, 3 }, /* GP2_11 */ + { RCAR_GP_PIN(2, 10), 8, 3 }, /* GP2_10 */ + { RCAR_GP_PIN(2, 9), 4, 3 }, /* GP2_9 */ + { RCAR_GP_PIN(2, 8), 0, 3 }, /* GP2_8 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL2", 0xe6050888) { + { RCAR_GP_PIN(2, 23), 28, 3 }, /* TCLK1_A */ + { RCAR_GP_PIN(2, 22), 24, 3 }, /* TPU0TO1 */ + { RCAR_GP_PIN(2, 21), 20, 3 }, /* TPU0TO0 */ + { RCAR_GP_PIN(2, 20), 16, 3 }, /* CLK_EXTFXR */ + { RCAR_GP_PIN(2, 19), 12, 3 }, /* RXDB_EXTFXR */ + { RCAR_GP_PIN(2, 18), 8, 3 }, /* FXR_TXDB */ + { RCAR_GP_PIN(2, 17), 4, 3 }, /* RXDA_EXTFXR_A */ + { RCAR_GP_PIN(2, 16), 0, 3 }, /* FXR_TXDA_A */ + } }, + { PINMUX_DRIVE_REG("DRV3CTRL2", 0xe605088c) { + { RCAR_GP_PIN(2, 24), 0, 3 }, /* TCLK2_A */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL3", 0xe6058880) { + { RCAR_GP_PIN(3, 7), 28, 3 }, /* CANFD3_TX */ + { RCAR_GP_PIN(3, 6), 24, 3 }, /* CANFD2_RX */ + { RCAR_GP_PIN(3, 5), 20, 3 }, /* CANFD2_TX */ + { RCAR_GP_PIN(3, 4), 16, 3 }, /* CANFD1_RX */ + { RCAR_GP_PIN(3, 3), 12, 3 }, /* CANFD1_TX */ + { RCAR_GP_PIN(3, 2), 8, 3 }, /* CANFD0_RX */ + { RCAR_GP_PIN(3, 1), 4, 2 }, /* CANFD0_TX */ + { RCAR_GP_PIN(3, 0), 0, 2 }, /* CAN_CLK */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL3", 0xe6058884) { + { RCAR_GP_PIN(3, 15), 28, 3 }, /* CANFD7_TX */ + { RCAR_GP_PIN(3, 14), 24, 3 }, /* CANFD6_RX */ + { RCAR_GP_PIN(3, 13), 20, 3 }, /* CANFD6_TX */ + { RCAR_GP_PIN(3, 12), 16, 3 }, /* CANFD5_RX */ + { RCAR_GP_PIN(3, 11), 12, 3 }, /* CANFD5_TX */ + { RCAR_GP_PIN(3, 10), 8, 3 }, /* CANFD4_RX */ + { RCAR_GP_PIN(3, 9), 4, 3 }, /* CANFD4_TX*/ + { RCAR_GP_PIN(3, 8), 0, 3 }, /* CANFD3_RX */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6058888) { + { RCAR_GP_PIN(3, 16), 0, 3 }, /* CANFD7_RX */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL4", 0xe6060080) { + { RCAR_GP_PIN(4, 7), 28, 3 }, /* AVB0_TXC */ + { RCAR_GP_PIN(4, 6), 24, 3 }, /* AVB0_TX_CTL */ + { RCAR_GP_PIN(4, 5), 20, 3 }, /* AVB0_RD3 */ + { RCAR_GP_PIN(4, 4), 16, 3 }, /* AVB0_RD2 */ + { RCAR_GP_PIN(4, 3), 12, 3 }, /* AVB0_RD1 */ + { RCAR_GP_PIN(4, 2), 8, 3 }, /* AVB0_RD0 */ + { RCAR_GP_PIN(4, 1), 4, 3 }, /* AVB0_RXC */ + { RCAR_GP_PIN(4, 0), 0, 3 }, /* AVB0_RX_CTL */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL4", 0xe6060084) { + { RCAR_GP_PIN(4, 15), 28, 3 }, /* AVB0_MAGIC */ + { RCAR_GP_PIN(4, 14), 24, 3 }, /* AVB0_MDC */ + { RCAR_GP_PIN(4, 13), 20, 3 }, /* AVB0_MDIO */ + { RCAR_GP_PIN(4, 12), 16, 3 }, /* AVB0_TXCREFCLK */ + { RCAR_GP_PIN(4, 11), 12, 3 }, /* AVB0_TD3 */ + { RCAR_GP_PIN(4, 10), 8, 3 }, /* AVB0_TD2 */ + { RCAR_GP_PIN(4, 9), 4, 3 }, /* AVB0_TD1*/ + { RCAR_GP_PIN(4, 8), 0, 3 }, /* AVB0_TD0 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL4", 0xe6060088) { + { RCAR_GP_PIN(4, 23), 28, 3 }, /* PCIE2_CLKREQ_N */ + { RCAR_GP_PIN(4, 22), 24, 3 }, /* PCIE1_CLKREQ_N */ + { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */ + { RCAR_GP_PIN(4, 20), 16, 3 }, /* AVB0_AVTP_PPS */ + { RCAR_GP_PIN(4, 19), 12, 3 }, /* AVB0_AVTP_CAPTURE */ + { RCAR_GP_PIN(4, 18), 8, 3 }, /* AVB0_AVTP_MATCH */ + { RCAR_GP_PIN(4, 17), 4, 3 }, /* AVB0_LINK */ + { RCAR_GP_PIN(4, 16), 0, 3 }, /* AVB0_PHY_INT */ + } }, + { PINMUX_DRIVE_REG("DRV3CTRL4", 0xe606008c) { + { RCAR_GP_PIN(4, 26), 8, 3 }, /* AVS1 */ + { RCAR_GP_PIN(4, 25), 4, 3 }, /* AVS0 */ + { RCAR_GP_PIN(4, 24), 0, 3 }, /* PCIE3_CLKREQ_N */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL5", 0xe6060880) { + { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB1_TXC */ + { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB1_TX_CTL */ + { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB1_RD3 */ + { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB1_RD2 */ + { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB1_RD1 */ + { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB1_RD0 */ + { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB1_RXC */ + { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB1_RX_CTL */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL5", 0xe6060884) { + { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB1_MAGIC */ + { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB1_MDC */ + { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB1_MDIO */ + { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB1_TXCREFCLK */ + { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB1_TD3 */ + { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB1_TD2 */ + { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB1_TD1*/ + { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB1_TD0 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL5", 0xe6060888) { + { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB1_AVTP_PPS */ + { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB1_AVTP_CAPTURE */ + { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB1_AVTP_MATCH */ + { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB1_LINK */ + { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB1_PHY_INT */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL6", 0xe6068080) { + { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB2_TXC */ + { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB2_TX_CTL */ + { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB2_RD3 */ + { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB2_RD2 */ + { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB2_RD1 */ + { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB2_RD0 */ + { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB2_RXC */ + { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB2_RX_CTL */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL6", 0xe6068084) { + { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB2_MAGIC */ + { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB2_MDC */ + { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB2_MDIO */ + { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB2_TXCREFCLK */ + { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB2_TD3 */ + { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB2_TD2 */ + { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB2_TD1*/ + { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB2_TD0 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL6", 0xe6068088) { + { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB2_AVTP_PPS */ + { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB2_AVTP_CAPTURE */ + { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB2_AVTP_MATCH */ + { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB2_LINK */ + { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB2_PHY_INT */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL7", 0xe6068880) { + { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB3_TXC */ + { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB3_TX_CTL */ + { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB3_RD3 */ + { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB3_RD2 */ + { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB3_RD1 */ + { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB3_RD0 */ + { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB3_RXC */ + { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB3_RX_CTL */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL7", 0xe6068884) { + { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB3_MAGIC */ + { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB3_MDC */ + { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB3_MDIO */ + { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB3_TXCREFCLK */ + { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB3_TD3 */ + { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB3_TD2 */ + { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB3_TD1*/ + { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB3_TD0 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL7", 0xe6068888) { + { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB3_AVTP_PPS */ + { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB3_AVTP_CAPTURE */ + { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB3_AVTP_MATCH */ + { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB3_LINK */ + { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB3_PHY_INT */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL8", 0xe6069080) { + { RCAR_GP_PIN(8, 7), 28, 3 }, /* AVB4_TXC */ + { RCAR_GP_PIN(8, 6), 24, 3 }, /* AVB4_TX_CTL */ + { RCAR_GP_PIN(8, 5), 20, 3 }, /* AVB4_RD3 */ + { RCAR_GP_PIN(8, 4), 16, 3 }, /* AVB4_RD2 */ + { RCAR_GP_PIN(8, 3), 12, 3 }, /* AVB4_RD1 */ + { RCAR_GP_PIN(8, 2), 8, 3 }, /* AVB4_RD0 */ + { RCAR_GP_PIN(8, 1), 4, 3 }, /* AVB4_RXC */ + { RCAR_GP_PIN(8, 0), 0, 3 }, /* AVB4_RX_CTL */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL8", 0xe6069084) { + { RCAR_GP_PIN(8, 15), 28, 3 }, /* AVB4_MAGIC */ + { RCAR_GP_PIN(8, 14), 24, 3 }, /* AVB4_MDC */ + { RCAR_GP_PIN(8, 13), 20, 3 }, /* AVB4_MDIO */ + { RCAR_GP_PIN(8, 12), 16, 3 }, /* AVB4_TXCREFCLK */ + { RCAR_GP_PIN(8, 11), 12, 3 }, /* AVB4_TD3 */ + { RCAR_GP_PIN(8, 10), 8, 3 }, /* AVB4_TD2 */ + { RCAR_GP_PIN(8, 9), 4, 3 }, /* AVB4_TD1*/ + { RCAR_GP_PIN(8, 8), 0, 3 }, /* AVB4_TD0 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL8", 0xe6069088) { + { RCAR_GP_PIN(8, 20), 16, 3 }, /* AVB4_AVTP_PPS */ + { RCAR_GP_PIN(8, 19), 12, 3 }, /* AVB4_AVTP_CAPTURE */ + { RCAR_GP_PIN(8, 18), 8, 3 }, /* AVB4_AVTP_MATCH */ + { RCAR_GP_PIN(8, 17), 4, 3 }, /* AVB4_LINK */ + { RCAR_GP_PIN(8, 16), 0, 3 }, /* AVB4_PHY_INT */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL9", 0xe6069880) { + { RCAR_GP_PIN(9, 7), 28, 3 }, /* AVB5_TXC */ + { RCAR_GP_PIN(9, 6), 24, 3 }, /* AVB5_TX_CTL */ + { RCAR_GP_PIN(9, 5), 20, 3 }, /* AVB5_RD3 */ + { RCAR_GP_PIN(9, 4), 16, 3 }, /* AVB5_RD2 */ + { RCAR_GP_PIN(9, 3), 12, 3 }, /* AVB5_RD1 */ + { RCAR_GP_PIN(9, 2), 8, 3 }, /* AVB5_RD0 */ + { RCAR_GP_PIN(9, 1), 4, 3 }, /* AVB5_RXC */ + { RCAR_GP_PIN(9, 0), 0, 3 }, /* AVB5_RX_CTL */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL9", 0xe6069884) { + { RCAR_GP_PIN(9, 15), 28, 3 }, /* AVB5_MAGIC */ + { RCAR_GP_PIN(9, 14), 24, 3 }, /* AVB5_MDC */ + { RCAR_GP_PIN(9, 13), 20, 3 }, /* AVB5_MDIO */ + { RCAR_GP_PIN(9, 12), 16, 3 }, /* AVB5_TXCREFCLK */ + { RCAR_GP_PIN(9, 11), 12, 3 }, /* AVB5_TD3 */ + { RCAR_GP_PIN(9, 10), 8, 3 }, /* AVB5_TD2 */ + { RCAR_GP_PIN(9, 9), 4, 3 }, /* AVB5_TD1*/ + { RCAR_GP_PIN(9, 8), 0, 3 }, /* AVB5_TD0 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL9", 0xe6069888) { + { RCAR_GP_PIN(9, 20), 16, 3 }, /* AVB5_AVTP_PPS */ + { RCAR_GP_PIN(9, 19), 12, 3 }, /* AVB5_AVTP_CAPTURE */ + { RCAR_GP_PIN(9, 18), 8, 3 }, /* AVB5_AVTP_MATCH */ + { RCAR_GP_PIN(9, 17), 4, 3 }, /* AVB5_LINK */ + { RCAR_GP_PIN(9, 16), 0, 3 }, /* AVB5_PHY_INT */ + } }, + { }, +}; + +enum ioctrl_regs { + POC0, + POC1, + POC2, + POC4, + POC5, + POC6, + POC7, + POC8, + POC9, + TD1SEL0, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [POC0] = { 0xe60580a0, }, + [POC1] = { 0xe60500a0, }, + [POC2] = { 0xe60508a0, }, + [POC4] = { 0xe60600a0, }, + [POC5] = { 0xe60608a0, }, + [POC6] = { 0xe60680a0, }, + [POC7] = { 0xe60688a0, }, + [POC8] = { 0xe60690a0, }, + [POC9] = { 0xe60698a0, }, + [TD1SEL0] = { 0xe6058124, }, + { /* sentinel */ }, +}; + +static int r8a779a0_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, + u32 *pocctrl) +{ + int bit = pin & 0x1f; + + *pocctrl = pinmux_ioctrl_regs[POC0].reg; + if (pin >= RCAR_GP_PIN(0, 15) && pin <= RCAR_GP_PIN(0, 27)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[POC1].reg; + if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 30)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[POC2].reg; + if (pin >= RCAR_GP_PIN(2, 2) && pin <= RCAR_GP_PIN(2, 15)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[POC4].reg; + if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[POC5].reg; + if (pin >= RCAR_GP_PIN(5, 0) && pin <= RCAR_GP_PIN(5, 17)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[POC6].reg; + if (pin >= RCAR_GP_PIN(6, 0) && pin <= RCAR_GP_PIN(6, 17)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[POC7].reg; + if (pin >= RCAR_GP_PIN(7, 0) && pin <= RCAR_GP_PIN(7, 17)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[POC8].reg; + if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 17)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[POC9].reg; + if (pin >= RCAR_GP_PIN(9, 0) && pin <= RCAR_GP_PIN(9, 17)) + return bit; + + return -EINVAL; +} + +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUEN0", 0xe60580c0, "PUD0", 0xe60580e0) { + [ 0] = RCAR_GP_PIN(0, 0), /* QSPI0_SPCLK */ + [ 1] = RCAR_GP_PIN(0, 1), /* QSPI0_MOSI_IO0 */ + [ 2] = RCAR_GP_PIN(0, 2), /* QSPI0_MISO_IO1 */ + [ 3] = RCAR_GP_PIN(0, 3), /* QSPI0_IO2 */ + [ 4] = RCAR_GP_PIN(0, 4), /* QSPI0_IO3 */ + [ 5] = RCAR_GP_PIN(0, 5), /* QSPI0_SSL */ + [ 6] = RCAR_GP_PIN(0, 6), /* QSPI1_SPCLK */ + [ 7] = RCAR_GP_PIN(0, 7), /* QSPI1_MOSI_IO0 */ + [ 8] = RCAR_GP_PIN(0, 8), /* QSPI1_MISO_IO1 */ + [ 9] = RCAR_GP_PIN(0, 9), /* QSPI1_IO2 */ + [10] = RCAR_GP_PIN(0, 10), /* QSPI1_IO3 */ + [11] = RCAR_GP_PIN(0, 11), /* QSPI1_SSL */ + [12] = RCAR_GP_PIN(0, 12), /* RPC_RESET_N */ + [13] = RCAR_GP_PIN(0, 13), /* RPC_WP_N */ + [14] = RCAR_GP_PIN(0, 14), /* RPC_INT_N */ + [15] = RCAR_GP_PIN(0, 15), /* SD_WP */ + [16] = RCAR_GP_PIN(0, 16), /* SD_CD */ + [17] = RCAR_GP_PIN(0, 17), /* MMC_DS */ + [18] = RCAR_GP_PIN(0, 18), /* MMC_SD_CMD */ + [19] = RCAR_GP_PIN(0, 19), /* MMC_SD_D0 */ + [20] = RCAR_GP_PIN(0, 20), /* MMC_SD_D1 */ + [21] = RCAR_GP_PIN(0, 21), /* MMC_SD_D2 */ + [22] = RCAR_GP_PIN(0, 22), /* MMC_SD_D3 */ + [23] = RCAR_GP_PIN(0, 23), /* MMC_SD_CLK */ + [24] = RCAR_GP_PIN(0, 24), /* MMC_D4 */ + [25] = RCAR_GP_PIN(0, 25), /* MMC_D5 */ + [26] = RCAR_GP_PIN(0, 26), /* MMC_D6 */ + [27] = RCAR_GP_PIN(0, 27), /* MMC_D7 */ + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN1", 0xe60500c0, "PUD1", 0xe60500e0) { + [ 0] = RCAR_GP_PIN(1, 0), /* SCIF_CLK */ + [ 1] = RCAR_GP_PIN(1, 1), /* HRX0 */ + [ 2] = RCAR_GP_PIN(1, 2), /* HSCK0 */ + [ 3] = RCAR_GP_PIN(1, 3), /* HRTS0_N */ + [ 4] = RCAR_GP_PIN(1, 4), /* HCTS0_N */ + [ 5] = RCAR_GP_PIN(1, 5), /* HTX0 */ + [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_RXD */ + [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_TXD */ + [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SCK */ + [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_SYNC */ + [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SS1 */ + [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_SS2 */ + [12] = RCAR_GP_PIN(1, 12), /* MSIOF1_RXD */ + [13] = RCAR_GP_PIN(1, 13), /* MSIOF1_TXD */ + [14] = RCAR_GP_PIN(1, 14), /* MSIOF1_SCK */ + [15] = RCAR_GP_PIN(1, 15), /* MSIOF1_SYNC */ + [16] = RCAR_GP_PIN(1, 16), /* MSIOF1_SS1 */ + [17] = RCAR_GP_PIN(1, 17), /* MSIOF1_SS2 */ + [18] = RCAR_GP_PIN(1, 18), /* MSIOF2_RXD */ + [19] = RCAR_GP_PIN(1, 19), /* MSIOF2_TXD */ + [20] = RCAR_GP_PIN(1, 20), /* MSIOF2_SCK */ + [21] = RCAR_GP_PIN(1, 21), /* MSIOF2_SYNC */ + [22] = RCAR_GP_PIN(1, 22), /* MSIOF2_SS1 */ + [23] = RCAR_GP_PIN(1, 23), /* MSIOF2_SS2 */ + [24] = RCAR_GP_PIN(1, 24), /* IRQ0 */ + [25] = RCAR_GP_PIN(1, 25), /* IRQ1 */ + [26] = RCAR_GP_PIN(1, 26), /* IRQ2 */ + [27] = RCAR_GP_PIN(1, 27), /* IRQ3 */ + [28] = RCAR_GP_PIN(1, 28), /* GP1_28 */ + [29] = RCAR_GP_PIN(1, 29), /* GP1_29 */ + [30] = RCAR_GP_PIN(1, 30), /* GP1_30 */ + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN2", 0xe60508c0, "PUD2", 0xe60508e0) { + [ 0] = RCAR_GP_PIN(2, 0), /* IPC_CLKIN */ + [ 1] = RCAR_GP_PIN(2, 1), /* IPC_CLKOUT */ + [ 2] = RCAR_GP_PIN(2, 2), /* GP2_02 */ + [ 3] = RCAR_GP_PIN(2, 3), /* GP2_03 */ + [ 4] = RCAR_GP_PIN(2, 4), /* GP2_04 */ + [ 5] = RCAR_GP_PIN(2, 5), /* GP2_05 */ + [ 6] = RCAR_GP_PIN(2, 6), /* GP2_06 */ + [ 7] = RCAR_GP_PIN(2, 7), /* GP2_07 */ + [ 8] = RCAR_GP_PIN(2, 8), /* GP2_08 */ + [ 9] = RCAR_GP_PIN(2, 9), /* GP2_09 */ + [10] = RCAR_GP_PIN(2, 10), /* GP2_10 */ + [11] = RCAR_GP_PIN(2, 11), /* GP2_11 */ + [12] = RCAR_GP_PIN(2, 12), /* GP2_12 */ + [13] = RCAR_GP_PIN(2, 13), /* GP2_13 */ + [14] = RCAR_GP_PIN(2, 14), /* GP2_14 */ + [15] = RCAR_GP_PIN(2, 15), /* GP2_15 */ + [16] = RCAR_GP_PIN(2, 16), /* FXR_TXDA_A */ + [17] = RCAR_GP_PIN(2, 17), /* RXDA_EXTFXR_A */ + [18] = RCAR_GP_PIN(2, 18), /* FXR_TXDB */ + [19] = RCAR_GP_PIN(2, 19), /* RXDB_EXTFXR */ + [20] = RCAR_GP_PIN(2, 20), /* CLK_EXTFXR */ + [21] = RCAR_GP_PIN(2, 21), /* TPU0TO0 */ + [22] = RCAR_GP_PIN(2, 22), /* TPU0TO1 */ + [23] = RCAR_GP_PIN(2, 23), /* TCLK1_A */ + [24] = RCAR_GP_PIN(2, 24), /* TCLK2_A */ + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN3", 0xe60588c0, "PUD3", 0xe60588e0) { + [ 0] = RCAR_GP_PIN(3, 0), /* CAN_CLK */ + [ 1] = RCAR_GP_PIN(3, 1), /* CANFD0_TX */ + [ 2] = RCAR_GP_PIN(3, 2), /* CANFD0_RX */ + [ 3] = RCAR_GP_PIN(3, 3), /* CANFD1_TX */ + [ 4] = RCAR_GP_PIN(3, 4), /* CANFD1_RX */ + [ 5] = RCAR_GP_PIN(3, 5), /* CANFD2_TX */ + [ 6] = RCAR_GP_PIN(3, 6), /* CANFD2_RX */ + [ 7] = RCAR_GP_PIN(3, 7), /* CANFD3_TX */ + [ 8] = RCAR_GP_PIN(3, 8), /* CANFD3_RX */ + [ 9] = RCAR_GP_PIN(3, 9), /* CANFD4_TX */ + [10] = RCAR_GP_PIN(3, 10), /* CANFD4_RX */ + [11] = RCAR_GP_PIN(3, 11), /* CANFD5_TX */ + [12] = RCAR_GP_PIN(3, 12), /* CANFD5_RX */ + [13] = RCAR_GP_PIN(3, 13), /* CANFD6_TX */ + [14] = RCAR_GP_PIN(3, 14), /* CANFD6_RX */ + [15] = RCAR_GP_PIN(3, 15), /* CANFD7_TX */ + [16] = RCAR_GP_PIN(3, 16), /* CANFD7_RX */ + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN4", 0xe60600c0, "PUD4", 0xe60600e0) { + [ 0] = RCAR_GP_PIN(4, 0), /* AVB0_RX_CTL */ + [ 1] = RCAR_GP_PIN(4, 1), /* AVB0_RXC */ + [ 2] = RCAR_GP_PIN(4, 2), /* AVB0_RD0 */ + [ 3] = RCAR_GP_PIN(4, 3), /* AVB0_RD1 */ + [ 4] = RCAR_GP_PIN(4, 4), /* AVB0_RD2 */ + [ 5] = RCAR_GP_PIN(4, 5), /* AVB0_RD3 */ + [ 6] = RCAR_GP_PIN(4, 6), /* AVB0_TX_CTL */ + [ 7] = RCAR_GP_PIN(4, 7), /* AVB0_TXC */ + [ 8] = RCAR_GP_PIN(4, 8), /* AVB0_TD0 */ + [ 9] = RCAR_GP_PIN(4, 9), /* AVB0_TD1 */ + [10] = RCAR_GP_PIN(4, 10), /* AVB0_TD2 */ + [11] = RCAR_GP_PIN(4, 11), /* AVB0_TD3 */ + [12] = RCAR_GP_PIN(4, 12), /* AVB0_TXREFCLK */ + [13] = RCAR_GP_PIN(4, 13), /* AVB0_MDIO */ + [14] = RCAR_GP_PIN(4, 14), /* AVB0_MDC */ + [15] = RCAR_GP_PIN(4, 15), /* AVB0_MAGIC */ + [16] = RCAR_GP_PIN(4, 16), /* AVB0_PHY_INT */ + [17] = RCAR_GP_PIN(4, 17), /* AVB0_LINK */ + [18] = RCAR_GP_PIN(4, 18), /* AVB0_AVTP_MATCH */ + [19] = RCAR_GP_PIN(4, 19), /* AVB0_AVTP_CAPTURE */ + [20] = RCAR_GP_PIN(4, 20), /* AVB0_AVTP_PPS */ + [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */ + [22] = RCAR_GP_PIN(4, 22), /* PCIE1_CLKREQ_N */ + [23] = RCAR_GP_PIN(4, 23), /* PCIE2_CLKREQ_N */ + [24] = RCAR_GP_PIN(4, 24), /* PCIE3_CLKREQ_N */ + [25] = RCAR_GP_PIN(4, 25), /* AVS0 */ + [26] = RCAR_GP_PIN(4, 26), /* AVS1 */ + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN5", 0xe60608c0, "PUD5", 0xe60608e0) { + [ 0] = RCAR_GP_PIN(5, 0), /* AVB1_RX_CTL */ + [ 1] = RCAR_GP_PIN(5, 1), /* AVB1_RXC */ + [ 2] = RCAR_GP_PIN(5, 2), /* AVB1_RD0 */ + [ 3] = RCAR_GP_PIN(5, 3), /* AVB1_RD1 */ + [ 4] = RCAR_GP_PIN(5, 4), /* AVB1_RD2 */ + [ 5] = RCAR_GP_PIN(5, 5), /* AVB1_RD3 */ + [ 6] = RCAR_GP_PIN(5, 6), /* AVB1_TX_CTL */ + [ 7] = RCAR_GP_PIN(5, 7), /* AVB1_TXC */ + [ 8] = RCAR_GP_PIN(5, 8), /* AVB1_TD0 */ + [ 9] = RCAR_GP_PIN(5, 9), /* AVB1_TD1 */ + [10] = RCAR_GP_PIN(5, 10), /* AVB1_TD2 */ + [11] = RCAR_GP_PIN(5, 11), /* AVB1_TD3 */ + [12] = RCAR_GP_PIN(5, 12), /* AVB1_TXCREFCLK */ + [13] = RCAR_GP_PIN(5, 13), /* AVB1_MDIO */ + [14] = RCAR_GP_PIN(5, 14), /* AVB1_MDC */ + [15] = RCAR_GP_PIN(5, 15), /* AVB1_MAGIC */ + [16] = RCAR_GP_PIN(5, 16), /* AVB1_PHY_INT */ + [17] = RCAR_GP_PIN(5, 17), /* AVB1_LINK */ + [18] = RCAR_GP_PIN(5, 18), /* AVB1_AVTP_MATCH */ + [19] = RCAR_GP_PIN(5, 19), /* AVB1_AVTP_CAPTURE */ + [20] = RCAR_GP_PIN(5, 20), /* AVB1_AVTP_PPS */ + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN6", 0xe60680c0, "PUD6", 0xe60680e0) { + [ 0] = RCAR_GP_PIN(6, 0), /* AVB2_RX_CTL */ + [ 1] = RCAR_GP_PIN(6, 1), /* AVB2_RXC */ + [ 2] = RCAR_GP_PIN(6, 2), /* AVB2_RD0 */ + [ 3] = RCAR_GP_PIN(6, 3), /* AVB2_RD1 */ + [ 4] = RCAR_GP_PIN(6, 4), /* AVB2_RD2 */ + [ 5] = RCAR_GP_PIN(6, 5), /* AVB2_RD3 */ + [ 6] = RCAR_GP_PIN(6, 6), /* AVB2_TX_CTL */ + [ 7] = RCAR_GP_PIN(6, 7), /* AVB2_TXC */ + [ 8] = RCAR_GP_PIN(6, 8), /* AVB2_TD0 */ + [ 9] = RCAR_GP_PIN(6, 9), /* AVB2_TD1 */ + [10] = RCAR_GP_PIN(6, 10), /* AVB2_TD2 */ + [11] = RCAR_GP_PIN(6, 11), /* AVB2_TD3 */ + [12] = RCAR_GP_PIN(6, 12), /* AVB2_TXCREFCLK */ + [13] = RCAR_GP_PIN(6, 13), /* AVB2_MDIO */ + [14] = RCAR_GP_PIN(6, 14), /* AVB2_MDC*/ + [15] = RCAR_GP_PIN(6, 15), /* AVB2_MAGIC */ + [16] = RCAR_GP_PIN(6, 16), /* AVB2_PHY_INT */ + [17] = RCAR_GP_PIN(6, 17), /* AVB2_LINK */ + [18] = RCAR_GP_PIN(6, 18), /* AVB2_AVTP_MATCH */ + [19] = RCAR_GP_PIN(6, 19), /* AVB2_AVTP_CAPTURE */ + [20] = RCAR_GP_PIN(6, 20), /* AVB2_AVTP_PPS */ + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN7", 0xe60688c0, "PUD7", 0xe60688e0) { + [ 0] = RCAR_GP_PIN(7, 0), /* AVB3_RX_CTL */ + [ 1] = RCAR_GP_PIN(7, 1), /* AVB3_RXC */ + [ 2] = RCAR_GP_PIN(7, 2), /* AVB3_RD0 */ + [ 3] = RCAR_GP_PIN(7, 3), /* AVB3_RD1 */ + [ 4] = RCAR_GP_PIN(7, 4), /* AVB3_RD2 */ + [ 5] = RCAR_GP_PIN(7, 5), /* AVB3_RD3 */ + [ 6] = RCAR_GP_PIN(7, 6), /* AVB3_TX_CTL */ + [ 7] = RCAR_GP_PIN(7, 7), /* AVB3_TXC */ + [ 8] = RCAR_GP_PIN(7, 8), /* AVB3_TD0 */ + [ 9] = RCAR_GP_PIN(7, 9), /* AVB3_TD1 */ + [10] = RCAR_GP_PIN(7, 10), /* AVB3_TD2 */ + [11] = RCAR_GP_PIN(7, 11), /* AVB3_TD3 */ + [12] = RCAR_GP_PIN(7, 12), /* AVB3_TXCREFCLK */ + [13] = RCAR_GP_PIN(7, 13), /* AVB3_MDIO */ + [14] = RCAR_GP_PIN(7, 14), /* AVB3_MDC */ + [15] = RCAR_GP_PIN(7, 15), /* AVB3_MAGIC */ + [16] = RCAR_GP_PIN(7, 16), /* AVB3_PHY_INT */ + [17] = RCAR_GP_PIN(7, 17), /* AVB3_LINK */ + [18] = RCAR_GP_PIN(7, 18), /* AVB3_AVTP_MATCH */ + [19] = RCAR_GP_PIN(7, 19), /* AVB3_AVTP_CAPTURE */ + [20] = RCAR_GP_PIN(7, 20), /* AVB3_AVTP_PPS */ + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN8", 0xe60690c0, "PUD8", 0xe60690e0) { + [ 0] = RCAR_GP_PIN(8, 0), /* AVB4_RX_CTL */ + [ 1] = RCAR_GP_PIN(8, 1), /* AVB4_RXC */ + [ 2] = RCAR_GP_PIN(8, 2), /* AVB4_RD0 */ + [ 3] = RCAR_GP_PIN(8, 3), /* AVB4_RD1 */ + [ 4] = RCAR_GP_PIN(8, 4), /* AVB4_RD2 */ + [ 5] = RCAR_GP_PIN(8, 5), /* AVB4_RD3 */ + [ 6] = RCAR_GP_PIN(8, 6), /* AVB4_TX_CTL */ + [ 7] = RCAR_GP_PIN(8, 7), /* AVB4_TXC */ + [ 8] = RCAR_GP_PIN(8, 8), /* AVB4_TD0 */ + [ 9] = RCAR_GP_PIN(8, 9), /* AVB4_TD1 */ + [10] = RCAR_GP_PIN(8, 10), /* AVB4_TD2 */ + [11] = RCAR_GP_PIN(8, 11), /* AVB4_TD3 */ + [12] = RCAR_GP_PIN(8, 12), /* AVB4_TXCREFCLK */ + [13] = RCAR_GP_PIN(8, 13), /* AVB4_MDIO */ + [14] = RCAR_GP_PIN(8, 14), /* AVB4_MDC */ + [15] = RCAR_GP_PIN(8, 15), /* AVB4_MAGIC */ + [16] = RCAR_GP_PIN(8, 16), /* AVB4_PHY_INT */ + [17] = RCAR_GP_PIN(8, 17), /* AVB4_LINK */ + [18] = RCAR_GP_PIN(8, 18), /* AVB4_AVTP_MATCH */ + [19] = RCAR_GP_PIN(8, 19), /* AVB4_AVTP_CAPTURE */ + [20] = RCAR_GP_PIN(8, 20), /* AVB4_AVTP_PPS */ + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN9", 0xe60698c0, "PUD9", 0xe60698e0) { + [ 0] = RCAR_GP_PIN(9, 0), /* AVB5_RX_CTL */ + [ 1] = RCAR_GP_PIN(9, 1), /* AVB5_RXC */ + [ 2] = RCAR_GP_PIN(9, 2), /* AVB5_RD0 */ + [ 3] = RCAR_GP_PIN(9, 3), /* AVB5_RD1 */ + [ 4] = RCAR_GP_PIN(9, 4), /* AVB5_RD2 */ + [ 5] = RCAR_GP_PIN(9, 5), /* AVB5_RD3 */ + [ 6] = RCAR_GP_PIN(9, 6), /* AVB5_TX_CTL */ + [ 7] = RCAR_GP_PIN(9, 7), /* AVB5_TXC */ + [ 8] = RCAR_GP_PIN(9, 8), /* AVB5_TD0 */ + [ 9] = RCAR_GP_PIN(9, 9), /* AVB5_TD1 */ + [10] = RCAR_GP_PIN(9, 10), /* AVB5_TD2 */ + [11] = RCAR_GP_PIN(9, 11), /* AVB5_TD3 */ + [12] = RCAR_GP_PIN(9, 12), /* AVB5_TXCREFCLK */ + [13] = RCAR_GP_PIN(9, 13), /* AVB5_MDIO */ + [14] = RCAR_GP_PIN(9, 14), /* AVB5_MDC */ + [15] = RCAR_GP_PIN(9, 15), /* AVB5_MAGIC */ + [16] = RCAR_GP_PIN(9, 16), /* AVB5_PHY_INT */ + [17] = RCAR_GP_PIN(9, 17), /* AVB5_LINK */ + [18] = RCAR_GP_PIN(9, 18), /* AVB5_AVTP_MATCH */ + [19] = RCAR_GP_PIN(9, 19), /* AVB5_AVTP_CAPTURE */ + [20] = RCAR_GP_PIN(9, 20), /* AVB5_AVTP_PPS */ + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { /* sentinel */ }, +}; + +static unsigned int r8a779a0_pinmux_get_bias(struct sh_pfc *pfc, + unsigned int pin) +{ + const struct pinmux_bias_reg *reg; + unsigned int bit; + + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) + return PIN_CONFIG_BIAS_DISABLE; + + if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) + return PIN_CONFIG_BIAS_DISABLE; + else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) + return PIN_CONFIG_BIAS_PULL_UP; + else + return PIN_CONFIG_BIAS_PULL_DOWN; +} + +static void r8a779a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + const struct pinmux_bias_reg *reg; + u32 enable, updown; + unsigned int bit; + + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) + return; + + enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); + if (bias != PIN_CONFIG_BIAS_DISABLE) + enable |= BIT(bit); + + updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); + if (bias == PIN_CONFIG_BIAS_PULL_UP) + updown |= BIT(bit); + + sh_pfc_write(pfc, reg->pud, updown); + sh_pfc_write(pfc, reg->puen, enable); +} + +static const struct sh_pfc_soc_operations pinmux_ops = { + .pin_to_pocctrl = r8a779a0_pin_to_pocctrl, + .get_bias = r8a779a0_pinmux_get_bias, + .set_bias = r8a779a0_pinmux_set_bias, +}; + +const struct sh_pfc_soc_info r8a779a0_pinmux_info = { + .name = "r8a779a0_pfc", + .ops = &pinmux_ops, + .unlock_reg = 0x1ff, /* PMMRn mask */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + .drive_regs = pinmux_drive_regs, + .bias_regs = pinmux_bias_regs, + .ioctrl_regs = pinmux_ioctrl_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index 2498eb5716..490d34e56b 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -41,6 +41,7 @@ enum sh_pfc_model { SH_PFC_R8A77980, SH_PFC_R8A77990, SH_PFC_R8A77995, + SH_PFC_R8A779A0, };
struct sh_pfc_pin_config { @@ -955,6 +956,10 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev) if (model == SH_PFC_R8A77995) priv->pfc.info = &r8a77995_pinmux_info; #endif +#ifdef CONFIG_PINCTRL_PFC_R8A779A0 + if (model == SH_PFC_R8A779A0) + priv->pfc.info = &r8a779a0_pinmux_info; +#endif
priv->pmx.pfc = &priv->pfc; sh_pfc_init_ranges(&priv->pfc); @@ -1060,6 +1065,13 @@ static const struct udevice_id sh_pfc_pinctrl_ids[] = { .data = SH_PFC_R8A77995, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A779A0 + { + .compatible = "renesas,pfc-r8a779a0", + .data = SH_PFC_R8A779A0, + }, +#endif + { }, };
diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 48d737a141..c94757b9a2 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -319,6 +319,7 @@ extern const struct sh_pfc_soc_info r8a77970_pinmux_info; extern const struct sh_pfc_soc_info r8a77980_pinmux_info; extern const struct sh_pfc_soc_info r8a77990_pinmux_info; extern const struct sh_pfc_soc_info r8a77995_pinmux_info; +extern const struct sh_pfc_soc_info r8a779a0_pinmux_info;
/* ----------------------------------------------------------------------------- * Helper macros to create pin and port lists
Import R8A779A0 V3U DTs and headers from Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- arch/arm/dts/r8a779a0.dtsi | 970 ++++++++++++++++++ include/dt-bindings/clock/r8a779a0-cpg-mssr.h | 55 + include/dt-bindings/power/r8a779a0-sysc.h | 59 ++ 3 files changed, 1084 insertions(+) create mode 100644 arch/arm/dts/r8a779a0.dtsi create mode 100644 include/dt-bindings/clock/r8a779a0-cpg-mssr.h create mode 100644 include/dt-bindings/power/r8a779a0-sysc.h
diff --git a/arch/arm/dts/r8a779a0.dtsi b/arch/arm/dts/r8a779a0.dtsi new file mode 100644 index 0000000000..dfd6ae8b56 --- /dev/null +++ b/arch/arm/dts/r8a779a0.dtsi @@ -0,0 +1,970 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the R-Car V3U (R8A779A0) SoC + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include <dt-bindings/clock/r8a779a0-cpg-mssr.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/r8a779a0-sysc.h> + +/ { + compatible = "renesas,r8a779a0"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a76_0: cpu@0 { + compatible = "arm,cortex-a76"; + reg = <0>; + device_type = "cpu"; + power-domains = <&sysc R8A779A0_PD_A1E0D0C0>; + next-level-cache = <&L3_CA76_0>; + }; + + L3_CA76_0: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A779A0_PD_A2E0D0>; + cache-unified; + cache-level = <3>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + pmu_a76 { + compatible = "arm,cortex-a76-pmu"; + interrupts-extended = <&gic GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a779a0-wdt", + "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 907>; + status = "disabled"; + }; + + pfc: pin-controller@e6050000 { + compatible = "renesas,pfc-r8a779a0"; + reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, + <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, + <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, + <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>, + <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>; + }; + + gpio0: gpio@e6058180 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6058180 0 0x54>; + interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 916>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 0 28>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@e6050180 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6050180 0 0x54>; + interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 32 31>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@e6050980 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6050980 0 0x54>; + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 64 25>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@e6058980 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6058980 0 0x54>; + interrupts = <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 916>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 96 17>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@e6060180 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6060180 0 0x54>; + interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 128 27>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@e6060980 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6060980 0 0x54>; + interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 160 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@e6068180 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6068180 0 0x54>; + interrupts = <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 918>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 192 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@e6068980 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6068980 0 0x54>; + interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 918>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 224 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio8: gpio@e6069180 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6069180 0 0x54>; + interrupts = <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 918>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 256 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio9: gpio@e6069980 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6069980 0 0x54>; + interrupts = <GIC_SPI 868 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 918>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 288 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a779a0-cpg-mssr"; + reg = <0 0xe6150000 0 0x4000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a779a0-rst"; + reg = <0 0xe6160000 0 0x4000>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a779a0-sysc"; + reg = <0 0xe6180000 0 0x4000>; + #power-domain-cells = <1>; + }; + + i2c0: i2c@e6500000 { + compatible = "renesas,i2c-r8a779a0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 518>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 518>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + compatible = "renesas,i2c-r8a779a0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 519>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 519>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + compatible = "renesas,i2c-r8a779a0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 520>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 520>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + compatible = "renesas,i2c-r8a779a0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 521>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 521>; + dmas = <&dmac1 0x97>, <&dmac1 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + compatible = "renesas,i2c-r8a779a0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 522>; + dmas = <&dmac1 0x99>, <&dmac1 0x98>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + compatible = "renesas,i2c-r8a779a0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 523>; + dmas = <&dmac1 0x9b>, <&dmac1 0x9a>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@e66e8000 { + compatible = "renesas,i2c-r8a779a0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e8000 0 0x40>; + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 524>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 524>; + dmas = <&dmac1 0x9d>, <&dmac1 0x9c>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a779a0", + "renesas,rcar-gen3-hscif", "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 514>, + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 514>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a779a0", + "renesas,rcar-gen3-hscif", "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 515>, + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 515>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a779a0", + "renesas,rcar-gen3-hscif", "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a779a0", + "renesas,rcar-gen3-hscif", "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x37>, <&dmac1 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + avb0: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a779a0", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 211>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 211>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb1: ethernet@e6810000 { + compatible = "renesas,etheravb-r8a779a0", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6810000 0 0x800>; + interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 212>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 212>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb2: ethernet@e6820000 { + compatible = "renesas,etheravb-r8a779a0", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6820000 0 0x1000>; + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 213>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 213>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb3: ethernet@e6830000 { + compatible = "renesas,etheravb-r8a779a0", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6830000 0 0x1000>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 214>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 214>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb4: ethernet@e6840000 { + compatible = "renesas,etheravb-r8a779a0", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6840000 0 0x1000>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 215>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 215>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb5: ethernet@e6850000 { + compatible = "renesas,etheravb-r8a779a0", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6850000 0 0x1000>; + interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 216>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 216>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a779a0", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>, + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a779a0", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a779a0", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>, + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x57>, <&dmac1 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a779a0", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 705>, + <&cpg CPG_CORE R8A779A0_CLK_S1D2>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x59>, <&dmac1 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 705>; + status = "disabled"; + }; + + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a779a0", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 618>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 618>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a779a0", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 619>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 619>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a779a0", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 620>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 620>; + dmas = <&dmac1 0x45>, <&dmac1 0x44>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a779a0", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 621>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 621>; + dmas = <&dmac1 0x47>, <&dmac1 0x46>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof4: spi@e6c20000 { + compatible = "renesas,msiof-r8a779a0", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c20000 0 0x0064>; + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 622>; + dmas = <&dmac1 0x49>, <&dmac1 0x48>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof5: spi@e6c28000 { + compatible = "renesas,msiof-r8a779a0", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c28000 0 0x0064>; + interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 623>; + dmas = <&dmac1 0x4b>, <&dmac1 0x4a>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dmac1: dma-controller@e7350000 { + compatible = "renesas,dmac-r8a779a0"; + reg = <0 0xe7350000 0 0x1000>, + <0 0xe7300000 0 0x10000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", "ch12", "ch13", + "ch14", "ch15"; + clocks = <&cpg CPG_MOD 709>; + clock-names = "fck"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 709>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac2: dma-controller@e7351000 { + compatible = "renesas,dmac-r8a779a0"; + reg = <0 0xe7351000 0 0x1000>, + <0 0xe7310000 0 0x10000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7"; + clocks = <&cpg CPG_MOD 710>; + clock-names = "fck"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 710>; + #dma-cells = <1>; + dma-channels = <8>; + }; + + mmc0: mmc@ee140000 { + compatible = "renesas,sdhi-r8a779a0", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 706>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 706>; + max-frequency = <200000000>; + status = "disabled"; + }; + + gic: interrupt-controller@f1000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1000000 0 0x20000>, + <0x0 0xf1060000 0 0x110000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h new file mode 100644 index 0000000000..f1d737ca7c --- /dev/null +++ b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a779A0 CPG Core Clocks */ +#define R8A779A0_CLK_Z0 0 +#define R8A779A0_CLK_ZX 1 +#define R8A779A0_CLK_Z1 2 +#define R8A779A0_CLK_ZR 3 +#define R8A779A0_CLK_ZS 4 +#define R8A779A0_CLK_ZT 5 +#define R8A779A0_CLK_ZTR 6 +#define R8A779A0_CLK_S1D1 7 +#define R8A779A0_CLK_S1D2 8 +#define R8A779A0_CLK_S1D4 9 +#define R8A779A0_CLK_S1D8 10 +#define R8A779A0_CLK_S1D12 11 +#define R8A779A0_CLK_S3D1 12 +#define R8A779A0_CLK_S3D2 13 +#define R8A779A0_CLK_S3D4 14 +#define R8A779A0_CLK_LB 15 +#define R8A779A0_CLK_CP 16 +#define R8A779A0_CLK_CL 17 +#define R8A779A0_CLK_CL16MCK 18 +#define R8A779A0_CLK_ZB30 19 +#define R8A779A0_CLK_ZB30D2 20 +#define R8A779A0_CLK_ZB30D4 21 +#define R8A779A0_CLK_ZB31 22 +#define R8A779A0_CLK_ZB31D2 23 +#define R8A779A0_CLK_ZB31D4 24 +#define R8A779A0_CLK_SD0H 25 +#define R8A779A0_CLK_SD0 26 +#define R8A779A0_CLK_RPC 27 +#define R8A779A0_CLK_RPCD2 28 +#define R8A779A0_CLK_MSO 29 +#define R8A779A0_CLK_CANFD 30 +#define R8A779A0_CLK_CSI0 31 +#define R8A779A0_CLK_FRAY 32 +#define R8A779A0_CLK_DSI 33 +#define R8A779A0_CLK_VIP 34 +#define R8A779A0_CLK_ADGH 35 +#define R8A779A0_CLK_CNNDSP 36 +#define R8A779A0_CLK_ICU 37 +#define R8A779A0_CLK_ICUD2 38 +#define R8A779A0_CLK_VCBUS 39 +#define R8A779A0_CLK_CBFUSA 40 +#define R8A779A0_CLK_R 41 +#define R8A779A0_CLK_OSC 42 + +#endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/power/r8a779a0-sysc.h b/include/dt-bindings/power/r8a779a0-sysc.h new file mode 100644 index 0000000000..57929e459a --- /dev/null +++ b/include/dt-bindings/power/r8a779a0-sysc.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ + +/* + * These power domain indices match the Power Domain Register Numbers (PDR) + */ + +#define R8A779A0_PD_A1E0D0C0 0 +#define R8A779A0_PD_A1E0D0C1 1 +#define R8A779A0_PD_A1E0D1C0 2 +#define R8A779A0_PD_A1E0D1C1 3 +#define R8A779A0_PD_A1E1D0C0 4 +#define R8A779A0_PD_A1E1D0C1 5 +#define R8A779A0_PD_A1E1D1C0 6 +#define R8A779A0_PD_A1E1D1C1 7 +#define R8A779A0_PD_A2E0D0 16 +#define R8A779A0_PD_A2E0D1 17 +#define R8A779A0_PD_A2E1D0 18 +#define R8A779A0_PD_A2E1D1 19 +#define R8A779A0_PD_A3E0 20 +#define R8A779A0_PD_A3E1 21 +#define R8A779A0_PD_3DG_A 24 +#define R8A779A0_PD_3DG_B 25 +#define R8A779A0_PD_A1CNN2 32 +#define R8A779A0_PD_A1DSP0 33 +#define R8A779A0_PD_A2IMP01 34 +#define R8A779A0_PD_A2DP0 35 +#define R8A779A0_PD_A2CV0 36 +#define R8A779A0_PD_A2CV1 37 +#define R8A779A0_PD_A2CV4 38 +#define R8A779A0_PD_A2CV6 39 +#define R8A779A0_PD_A2CN2 40 +#define R8A779A0_PD_A1CNN0 41 +#define R8A779A0_PD_A2CN0 42 +#define R8A779A0_PD_A3IR 43 +#define R8A779A0_PD_A1CNN1 44 +#define R8A779A0_PD_A1DSP1 45 +#define R8A779A0_PD_A2IMP23 46 +#define R8A779A0_PD_A2DP1 47 +#define R8A779A0_PD_A2CV2 48 +#define R8A779A0_PD_A2CV3 49 +#define R8A779A0_PD_A2CV5 50 +#define R8A779A0_PD_A2CV7 51 +#define R8A779A0_PD_A2CN1 52 +#define R8A779A0_PD_A3VIP0 56 +#define R8A779A0_PD_A3VIP1 57 +#define R8A779A0_PD_A3VIP2 58 +#define R8A779A0_PD_A3VIP3 59 +#define R8A779A0_PD_A3ISP01 60 +#define R8A779A0_PD_A3ISP23 61 + +/* Always-on power area */ +#define R8A779A0_PD_ALWAYS_ON 64 + +#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ */
Import R8A779A0 V3U Falcon DTs from Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- arch/arm/dts/r8a779a0-falcon-cpu.dtsi | 184 ++++++++++++++++++++++++++ arch/arm/dts/r8a779a0-falcon.dts | 28 ++++ 2 files changed, 212 insertions(+) create mode 100644 arch/arm/dts/r8a779a0-falcon-cpu.dtsi create mode 100644 arch/arm/dts/r8a779a0-falcon.dts
diff --git a/arch/arm/dts/r8a779a0-falcon-cpu.dtsi b/arch/arm/dts/r8a779a0-falcon-cpu.dtsi new file mode 100644 index 0000000000..fa284a7260 --- /dev/null +++ b/arch/arm/dts/r8a779a0-falcon-cpu.dtsi @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Falcon CPU board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> +#include "r8a779a0.dtsi" + +/ { + model = "Renesas Falcon CPU board"; + compatible = "renesas,falcon-cpu", "renesas,r8a779a0"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@500000000 { + device_type = "memory"; + reg = <0x5 0x00000000 0x0 0x80000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x0 0x80000000>; + }; + + memory@700000000 { + device_type = "memory"; + reg = <0x7 0x00000000 0x0 0x80000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&avb0 { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + tx-internal-delay-ps = <2000>; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio4>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; +}; + +&i2c6 { + pinctrl-0 = <&i2c6_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; +}; + +&mmc0 { + pinctrl-0 = <&mmc_pins>; + pinctrl-1 = <&mmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + avb0_pins: avb0 { + mux { + groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; + function = "avb0"; + }; + + pins_mdio { + groups = "avb0_mdio"; + drive-strength = <21>; + }; + + pins_mii { + groups = "avb0_rgmii"; + drive-strength = <21>; + }; + + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + + i2c6_pins: i2c6 { + groups = "i2c6"; + function = "i2c6"; + }; + + mmc_pins: mmc { + groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; + function = "mmc"; + power-source = <1800>; + }; + + scif0_pins: scif0 { + groups = "scif0_data", "scif0_ctrl"; + function = "scif0"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&scif_clk { + clock-frequency = <24000000>; +}; diff --git a/arch/arm/dts/r8a779a0-falcon.dts b/arch/arm/dts/r8a779a0-falcon.dts new file mode 100644 index 0000000000..5617b81dd7 --- /dev/null +++ b/arch/arm/dts/r8a779a0-falcon.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Falcon CPU and BreakOut boards + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a779a0-falcon-cpu.dtsi" + +/ { + model = "Renesas Falcon CPU and Breakout boards based on r8a779a0"; + compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0"; + + aliases { + ethernet0 = &avb0; + serial0 = &scif0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +};
From: Hai Pham hai.pham.ud@renesas.com
Add R8A779A0 V3U DT extras for U-Boot.
Based on "ARM: dts: renesas: Add R8A779A0 V3U DTs" by Hai Pham hai.pham.ud@renesas.com
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- arch/arm/dts/r8a779a0-u-boot.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 arch/arm/dts/r8a779a0-u-boot.dtsi
diff --git a/arch/arm/dts/r8a779a0-u-boot.dtsi b/arch/arm/dts/r8a779a0-u-boot.dtsi new file mode 100644 index 0000000000..f6101289e8 --- /dev/null +++ b/arch/arm/dts/r8a779a0-u-boot.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot on R-Car R8A779A0 SoC + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include "r8a779x-u-boot.dtsi" + +&extalr_clk { + u-boot,dm-pre-reloc; +};
The R-Car V3U does support RPC interface, however the support for it is missing in upstream Linux DTs as of commit 9f4ad9e425a1 ("Linux 5.12"), add the node into u-boot.dtsi to let U-Boot access the SPI NOR or HF.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- arch/arm/dts/r8a779a0-u-boot.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/arch/arm/dts/r8a779a0-u-boot.dtsi b/arch/arm/dts/r8a779a0-u-boot.dtsi index f6101289e8..83dbe3f20e 100644 --- a/arch/arm/dts/r8a779a0-u-boot.dtsi +++ b/arch/arm/dts/r8a779a0-u-boot.dtsi @@ -7,6 +7,19 @@
#include "r8a779x-u-boot.dtsi"
+/ { + soc { + rpc: spi@ee200000 { + compatible = "renesas,rpc-r8a779a0", "renesas,rcar-gen3-rpc"; + reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>; + clocks = <&cpg CPG_MOD 629>; + bank-width = <2>; + num-cs = <1>; + status = "disabled"; + }; + }; +}; + &extalr_clk { u-boot,dm-pre-reloc; };
From: Hai Pham hai.pham.ud@renesas.com
Add platform code to support R8A779A0 V3U SoC.
Signed-off-by: Hai Pham hai.pham.ud@renesas.com Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- arch/arm/mach-rmobile/Kconfig.64 | 5 +++++ arch/arm/mach-rmobile/cpu_info.c | 1 + arch/arm/mach-rmobile/include/mach/rmobile.h | 1 + 3 files changed, 7 insertions(+)
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index 3f7ec05379..e22012e3b8 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -57,6 +57,11 @@ config R8A77995 imply CLK_R8A77995 imply PINCTRL_PFC_R8A77995
+config R8A779A0 + bool "Renesas SoC R8A779A0" + imply CLK_R8A779A0 + imply PINCTRL_PFC_R8A779A0 + config RZ_G2 bool "Renesas ARM SoCs RZ/G2 (64bit)"
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index 9ec622bdb5..2bb6d502b8 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -76,6 +76,7 @@ static const struct { { RMOBILE_CPU_TYPE_R8A77980, "R8A77980" }, { RMOBILE_CPU_TYPE_R8A77990, "R8A77990" }, { RMOBILE_CPU_TYPE_R8A77995, "R8A77995" }, + { RMOBILE_CPU_TYPE_R8A779A0, "R8A779A0" }, { 0x0, "CPU" }, };
diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h index a688636141..dc6f87631b 100644 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -39,6 +39,7 @@ #define RMOBILE_CPU_TYPE_R8A77980 0x56 #define RMOBILE_CPU_TYPE_R8A77990 0x57 #define RMOBILE_CPU_TYPE_R8A77995 0x58 +#define RMOBILE_CPU_TYPE_R8A779A0 0x59
#ifndef __ASSEMBLY__ const u8 *rzg_get_cpu_name(void);
From: Hai Pham hai.pham.ud@renesas.com
Add board code for the R8A779A0 V3U Falcon board.
Signed-off-by: Hai Pham hai.pham.ud@renesas.com Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com -- Marek: - various small rebase fixes and clean ups --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/r8a779a0-falcon-u-boot.dts | 32 +++++++++++++ arch/arm/mach-rmobile/Kconfig.64 | 7 +++ board/renesas/falcon/Kconfig | 15 ++++++ board/renesas/falcon/MAINTAINERS | 6 +++ board/renesas/falcon/Makefile | 13 +++++ board/renesas/falcon/falcon.c | 47 ++++++++++++++++++ configs/r8a779a0_falcon_defconfig | 64 +++++++++++++++++++++++++ include/configs/falcon.h | 25 ++++++++++ 9 files changed, 211 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/r8a779a0-falcon-u-boot.dts create mode 100644 board/renesas/falcon/Kconfig create mode 100644 board/renesas/falcon/MAINTAINERS create mode 100644 board/renesas/falcon/Makefile create mode 100644 board/renesas/falcon/falcon.c create mode 100644 configs/r8a779a0_falcon_defconfig create mode 100644 include/configs/falcon.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index aec5020a0f..5b4ffc9ee6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -879,7 +879,8 @@ dtb-$(CONFIG_RCAR_GEN3) += \ r8a77970-eagle-u-boot.dtb \ r8a77980-condor-u-boot.dtb \ r8a77990-ebisu-u-boot.dtb \ - r8a77995-draak-u-boot.dtb + r8a77995-draak-u-boot.dtb \ + r8a779a0-falcon-u-boot.dtb
ifdef CONFIG_RCAR_GEN3 DTC_FLAGS += -R 4 -p 0x1000 diff --git a/arch/arm/dts/r8a779a0-falcon-u-boot.dts b/arch/arm/dts/r8a779a0-falcon-u-boot.dts new file mode 100644 index 0000000000..06d3922a38 --- /dev/null +++ b/arch/arm/dts/r8a779a0-falcon-u-boot.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the Falcon board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include "r8a779a0-falcon.dts" +#include "r8a779a0-u-boot.dtsi" + +/ { + aliases { + spi0 = &rpc; + }; +}; + +&rpc { + #address-cells = <1>; + #size-cells = <0>; + num-cs = <1>; + spi-max-frequency = <50000000>; + status = "okay"; + + spi-flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + status = "okay"; + }; +}; diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index e22012e3b8..8df90acb4e 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -110,6 +110,12 @@ config TARGET_EBISU help Support for Renesas R-Car Gen3 Ebisu platform
+config TARGET_FALCON + bool "Falcon board" + imply R8A779A0 + help + Support for Renesas R-Car Gen3 Falcon platform + config TARGET_HIHOPE_RZG2 bool "HiHope RZ/G2 board" imply R8A774A1 @@ -160,6 +166,7 @@ source "board/renesas/condor/Kconfig" source "board/renesas/draak/Kconfig" source "board/renesas/eagle/Kconfig" source "board/renesas/ebisu/Kconfig" +source "board/renesas/falcon/Kconfig" source "board/renesas/salvator-x/Kconfig" source "board/renesas/ulcb/Kconfig" source "board/beacon/beacon-rzg2m/Kconfig" diff --git a/board/renesas/falcon/Kconfig b/board/renesas/falcon/Kconfig new file mode 100644 index 0000000000..1fcefa7e3c --- /dev/null +++ b/board/renesas/falcon/Kconfig @@ -0,0 +1,15 @@ +if TARGET_FALCON + +config SYS_SOC + default "rmobile" + +config SYS_BOARD + default "falcon" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "falcon" + +endif diff --git a/board/renesas/falcon/MAINTAINERS b/board/renesas/falcon/MAINTAINERS new file mode 100644 index 0000000000..2cacc91494 --- /dev/null +++ b/board/renesas/falcon/MAINTAINERS @@ -0,0 +1,6 @@ +FALCON BOARD +M: Marek Vasut marek.vasut+renesas@gmail.com +S: Maintained +F: board/renesas/falcon/ +F: include/configs/falcon.h +F: configs/r8a779a0_falcon_defconfig diff --git a/board/renesas/falcon/Makefile b/board/renesas/falcon/Makefile new file mode 100644 index 0000000000..3b202c24fb --- /dev/null +++ b/board/renesas/falcon/Makefile @@ -0,0 +1,13 @@ +# +# board/renesas/falcon/Makefile +# +# Copyright (C) 2020 Renesas Electronics Corp. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y := ../rcar-common/gen3-spl.o +else +obj-y := falcon.o ../rcar-common/common.o +endif diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c new file mode 100644 index 0000000000..3e591e4b42 --- /dev/null +++ b/board/renesas/falcon/falcon.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * board/renesas/falcon/falcon.c + * This file is Falcon board support. + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include <common.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/sys_proto.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/mach-types.h> +#include <asm/processor.h> +#include <linux/errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define CPGWPR 0xE6150000 +#define CPGWPCR 0xE6150004 + +int board_early_init_f(void) +{ + /* Unlock CPG access */ + writel(0x5A5AFFFF, CPGWPR); + writel(0xA5A50000, CPGWPCR); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; + + return 0; +} + +#define RST_BASE 0xE6160000 /* Domain0 */ +#define RST_SRESCR0 (RST_BASE + 0x18) +#define RST_SPRES 0x5AA58000 + +void reset_cpu(void) +{ + writel(RST_SPRES, RST_SRESCR0); +} diff --git a/configs/r8a779a0_falcon_defconfig b/configs/r8a779a0_falcon_defconfig new file mode 100644 index 0000000000..dad8b77acf --- /dev/null +++ b/configs/r8a779a0_falcon_defconfig @@ -0,0 +1,64 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_RMOBILE=y +CONFIG_SYS_TEXT_BASE=0x50000000 +CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_OFFSET=0xC00000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0xe6338000 +CONFIG_RCAR_GEN3=y +CONFIG_TARGET_FALCON=y +# CONFIG_PSCI_RESET is not set +CONFIG_DEFAULT_DEVICE_TREE="r8a779a0-falcon-u-boot" +CONFIG_FIT=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" +CONFIG_DEFAULT_FDT_FILE="r8a779a0-falcon.dtb" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_VERSION_VARIABLE=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_CLK_RENESAS=y +CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_IIC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_RENESAS_RAVB=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SCIF_CONSOLE=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_RENESAS_RPC_SPI=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/include/configs/falcon.h b/include/configs/falcon.h new file mode 100644 index 0000000000..b9c82a7674 --- /dev/null +++ b/include/configs/falcon.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/falcon.h + * This file is Falcon board configuration. + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#ifndef __FALCON_H +#define __FALCON_H + +#include "rcar-gen3-common.h" + +/* Ethernet RAVB */ +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +/* XTAL_CLK : 16.66MHz */ +#define CONFIG_SYS_CLK_FREQ 16666666u + +/* Generic Timer Definitions (use in assembler source) */ +#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ + +#endif /* __FALCON_H */
From: Koji Matsuoka koji.matsuoka.xm@renesas.com
Init the Generic Timer for V3U Falcon in early phase
Signed-off-by: Koji Matsuoka koji.matsuoka.xm@renesas.com Signed-off-by: Hai Pham hai.pham.ud@renesas.com Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- board/renesas/falcon/falcon.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)
diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c index 3e591e4b42..c3241bc21d 100644 --- a/board/renesas/falcon/falcon.c +++ b/board/renesas/falcon/falcon.c @@ -20,6 +20,31 @@ DECLARE_GLOBAL_DATA_PTR; #define CPGWPR 0xE6150000 #define CPGWPCR 0xE6150004
+#define EXTAL_CLK 16666600u +#define CNTCR_BASE 0xE6080000 +#define CNTFID0 (CNTCR_BASE + 0x020) +#define CNTCR_EN BIT(0) + +static void init_generic_timer(void) +{ + u32 freq; + + /* Set frequency data in CNTFID0 */ + freq = EXTAL_CLK; + + /* Update memory mapped and register based freqency */ + asm volatile ("msr cntfrq_el0, %0" :: "r" (freq)); + writel(freq, CNTFID0); + + /* Enable counter */ + setbits_le32(CNTCR_BASE, CNTCR_EN); +} + +void s_init(void) +{ + init_generic_timer(); +} + int board_early_init_f(void) { /* Unlock CPG access */
From: Koji Matsuoka koji.matsuoka.xm@renesas.com
Init GICv3 for V3U Falcon in early phase
Signed-off-by: Koji Matsuoka koji.matsuoka.xm@renesas.com Signed-off-by: Hai Pham hai.pham.ud@renesas.com Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- board/renesas/falcon/falcon.c | 29 +++++++++++++++++++++++++++++ include/configs/falcon.h | 11 +++++++++++ 2 files changed, 40 insertions(+)
diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c index c3241bc21d..3e74384716 100644 --- a/board/renesas/falcon/falcon.c +++ b/board/renesas/falcon/falcon.c @@ -40,6 +40,33 @@ static void init_generic_timer(void) setbits_le32(CNTCR_BASE, CNTCR_EN); }
+/* Distributor Registers */ +#define GICD_BASE 0xF1000000 + +/* ReDistributor Registers for Control and Physical LPIs */ +#define GICR_LPI_BASE 0xF1060000 +#define GICR_WAKER 0x0014 +#define GICR_PWRR 0x0024 +#define GICR_LPI_WAKER (GICR_LPI_BASE + GICR_WAKER) +#define GICR_LPI_PWRR (GICR_LPI_BASE + GICR_PWRR) + +/* ReDistributor Registers for SGIs and PPIs */ +#define GICR_SGI_BASE 0xF1070000 +#define GICR_IGROUPR0 0x0080 + +static void init_gic_v3(void) +{ + /* GIC v3 power on */ + writel(0x00000002, (GICR_LPI_PWRR)); + + /* Wait till the WAKER_CA_BIT changes to 0 */ + writel(readl(GICR_LPI_WAKER) & ~0x00000002, (GICR_LPI_WAKER)); + while (readl(GICR_LPI_WAKER) & 0x00000004) + ; + + writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0); +} + void s_init(void) { init_generic_timer(); @@ -59,6 +86,8 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+ init_gic_v3(); + return 0; }
diff --git a/include/configs/falcon.h b/include/configs/falcon.h index b9c82a7674..5ecbd1d3ed 100644 --- a/include/configs/falcon.h +++ b/include/configs/falcon.h @@ -11,6 +11,17 @@
#include "rcar-gen3-common.h"
+/* Generic Interrupt Controller Definitions */ +#ifdef CONFIG_GICV2 +#undef CONFIG_GICV2 +#undef GICD_BASE +#undef GICC_BASE +#undef GICR_BASE +#endif +#define CONFIG_GICV3 +#define GICD_BASE 0xF1000000 +#define GICR_BASE 0xF1060000 + /* Ethernet RAVB */ #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI
From: Hai Pham hai.pham.ud@renesas.com
Enable basic PSCI support for R8A779A0 V3U Falcon
Signed-off-by: Hai Pham hai.pham.ud@renesas.com Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com --- arch/arm/mach-rmobile/Makefile | 4 +++ arch/arm/mach-rmobile/psci-r8a779a0.c | 49 +++++++++++++++++++++++++++ configs/r8a779a0_falcon_defconfig | 1 + 3 files changed, 54 insertions(+) create mode 100644 arch/arm/mach-rmobile/psci-r8a779a0.c
diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile index 81a0dedb41..195bbeb5c8 100644 --- a/arch/arm/mach-rmobile/Makefile +++ b/arch/arm/mach-rmobile/Makefile @@ -15,6 +15,10 @@ obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o
+ifneq ($(CONFIG_R8A779A0),) +obj-$(CONFIG_ARMV8_PSCI) += psci-r8a779a0.o +endif + OBJCOPYFLAGS_u-boot-spl.srec := -O srec quiet_cmd_objcopy = OBJCOPY $@ cmd_objcopy = $(OBJCOPY) --gap-fill=0x00 $(OBJCOPYFLAGS) \ diff --git a/arch/arm/mach-rmobile/psci-r8a779a0.c b/arch/arm/mach-rmobile/psci-r8a779a0.c new file mode 100644 index 0000000000..6a85eb22ca --- /dev/null +++ b/arch/arm/mach-rmobile/psci-r8a779a0.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * This file implements basic PSCI support for Renesas r8a779a0 SoC + * + * Copyright (C) 2020 Renesas Electronics Corp. + * + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/psci.h> +#include <asm/secure.h> + +int __secure psci_features(u32 function_id, u32 psci_fid) +{ + switch (psci_fid) { + case ARM_PSCI_0_2_FN_PSCI_VERSION: + case ARM_PSCI_0_2_FN_SYSTEM_RESET: + return 0x0; + } + /* case ARM_PSCI_0_2_FN_CPU_ON: */ + /* case ARM_PSCI_0_2_FN_CPU_OFF: */ + /* case ARM_PSCI_0_2_FN_AFFINITY_INFO: */ + /* case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE: */ + /* case ARM_PSCI_0_2_FN_SYSTEM_OFF: */ + return ARM_PSCI_RET_NI; +} + +u32 __secure psci_version(void) +{ + return ARM_PSCI_VER_0_2; +} + +#define RST_BASE 0xE6160000 /* Domain0 */ +#define RST_SRESCR0 (RST_BASE + 0x18) +#define RST_SPRES 0x5AA58000 + +void __secure __noreturn psci_system_reset(void) +{ + writel(RST_SPRES, RST_SRESCR0); + + while (1) + ; +} + +int psci_update_dt(void *fdt) +{ + return 0; +} diff --git a/configs/r8a779a0_falcon_defconfig b/configs/r8a779a0_falcon_defconfig index dad8b77acf..8df647acfb 100644 --- a/configs/r8a779a0_falcon_defconfig +++ b/configs/r8a779a0_falcon_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_TEXT_BASE=0xe6338000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_FALCON=y # CONFIG_PSCI_RESET is not set +CONFIG_ARMV8_PSCI=y CONFIG_DEFAULT_DEVICE_TREE="r8a779a0-falcon-u-boot" CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y
Hi Marek,
Thank you for the patch.
On Wed, Apr 28, 2021 at 8:30 PM Marek Vasut marek.vasut@gmail.com wrote:
Synchronize RZ/G2 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com
drivers/clk/renesas/r8a774a1-cpg-mssr.c | 14 +++++++++----- drivers/clk/renesas/r8a774b1-cpg-mssr.c | 8 ++++++++ drivers/clk/renesas/r8a774c0-cpg-mssr.c | 9 +++++++++ 3 files changed, 26 insertions(+), 5 deletions(-)
Tested on RZ/G2{EMN} boards.
Tested-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
Cheers, Prabhakar
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index 1c54eca6c0..ef2bb6d777 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -68,13 +68,18 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC,CLK_RPCSRC),DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,R8A774A1_CLK_RPC), DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */
DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),@@ -99,7 +104,6 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = { DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078), DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268), DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c),
DEF_GEN3_RPC("rpc", R8A774A1_CLK_RPC, CLK_RPCSRC, 0x238), DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1),@@ -203,7 +207,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] = { DEF_MOD("can-fd", 914, R8A774A1_CLK_S3D2), DEF_MOD("can-if1", 915, R8A774A1_CLK_S3D4), DEF_MOD("can-if0", 916, R8A774A1_CLK_S3D4),
DEF_MOD("rpc", 917, R8A774A1_CLK_RPC),
DEF_MOD("rpc-if", 917, R8A774A1_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6), DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6), DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP),diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c index 03851d0b5a..a8b242dc47 100644 --- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c @@ -39,6 +39,7 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC,
CLK_RPCSRC, CLK_RINT, /* Module Clocks */@@ -64,6 +65,12 @@ static const struct cpg_core_clk r8a774b1_core_clks[] = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC,CLK_RPCSRC),DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,R8A774B1_CLK_RPC), DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),@@ -195,6 +202,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] = { DEF_MOD("can-fd", 914, R8A774B1_CLK_S3D2), DEF_MOD("can-if1", 915, R8A774B1_CLK_S3D4), DEF_MOD("can-if0", 916, R8A774B1_CLK_S3D4),
DEF_MOD("rpc-if", 917, R8A774B1_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6), DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6), DEF_MOD("i2c-dvfs", 926, R8A774B1_CLK_CP),diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c index 37a7123f73..6e9558a107 100644 --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c @@ -44,6 +44,7 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC,
CLK_RPCSRC, CLK_RINT, CLK_OCO,@@ -74,6 +75,13 @@ static const struct cpg_core_clk r8a774c0_core_clks[] = { DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC,CLK_RPCSRC),DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,R8A774C0_CLK_RPC),DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),@@ -199,6 +207,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] = { DEF_MOD("can-fd", 914, R8A774C0_CLK_S3D2), DEF_MOD("can-if1", 915, R8A774C0_CLK_S3D4), DEF_MOD("can-if0", 916, R8A774C0_CLK_S3D4),
DEF_MOD("rpc-if", 917, R8A774C0_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2), DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2), DEF_MOD("i2c-dvfs", 926, R8A774C0_CLK_CP),-- 2.30.2
participants (2)
-
Lad, Prabhakar -
Marek Vasut