[PATCH 00/14] arm64: xilinx: Sync with Linux kernel

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Michal Simek

22 Sep 2023 22 Sep '23

12:35 p.m.

Hi,

this series is syncing DTs with Linux kernel. A lot of patches are simply taken from the Linux kernel and taken to U-Boot. But there are also some new one which are trying to fix violations. There is still some work to happen to be 100% in sync but we are getting closer and closer.

Thanks, Michal

Laurent Pinchart (2): arm64: dts: zynqmp: zcu106a: Describe DisplayPort connector arm64: dts: zynqmp: Add ports for the DisplayPort subsystem

Michal Simek (11): arm64: zynqmp: Describe interrupts by using macros arm64: xilinx: Remove address/size-cells from flash node arm64: xilinx: Use lower case for partition address arm64: zynqmp: Describe bus-width for SD card on KV260 arm64: zynqmp: Fix Siva's email address format arm64: xilinx: Put ethernet phys to mdio node arm64: xilinx: Remove address/size-cells from gem nodes arm64: zynqmp: Convert kv260-revA overlay to ASCII text arm64: zynqmp: Sync licenses with Linux kernel ARM: zynq: Describe nand device in DT arm64: zynqmp: Aligned QSPI configuration with latest spec

Tanmay Shah (1): arm64: dts: xilinx: zynqmp: Add RPU subsystem device node

arch/arm/dts/avnet-ultra96-rev1.dts | 2 +- arch/arm/dts/bitmain-antminer-s9.dts | 3 + arch/arm/dts/versal-mini-emmc0.dts | 2 +- arch/arm/dts/versal-mini-emmc1.dts | 2 +- arch/arm/dts/versal-mini-ospi.dtsi | 2 +- arch/arm/dts/versal-mini-qspi.dtsi | 2 +- arch/arm/dts/versal-mini.dts | 2 +- arch/arm/dts/zynq-zc770-xm011.dts | 3 + arch/arm/dts/zynqmp-clk-ccf.dtsi | 3 +- arch/arm/dts/zynqmp-dlc21-revA.dts | 10 +- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 10 +- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 10 +- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 10 +- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 10 +- arch/arm/dts/zynqmp-mini-emmc0.dts | 2 +- arch/arm/dts/zynqmp-mini-emmc1.dts | 2 +- arch/arm/dts/zynqmp-mini-nand.dts | 2 +- arch/arm/dts/zynqmp-mini-qspi.dts | 2 +- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 10 +- arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 11 +- arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 5 +- arch/arm/dts/zynqmp-sm-k26-revA.dts | 6 +- arch/arm/dts/zynqmp-zc1254-revA.dts | 4 +- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 15 +- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 19 +- arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 8 +- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 26 ++- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 10 +- arch/arm/dts/zynqmp-zcu102-rev1.0.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revA.dts | 7 +- arch/arm/dts/zynqmp-zcu102-revB.dts | 3 +- arch/arm/dts/zynqmp-zcu104-revA.dts | 3 +- arch/arm/dts/zynqmp-zcu104-revC.dts | 5 +- arch/arm/dts/zynqmp-zcu106-revA.dts | 27 ++- arch/arm/dts/zynqmp-zcu111-revA.dts | 7 +- arch/arm/dts/zynqmp-zcu1275-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu1275-revB.dts | 2 +- arch/arm/dts/zynqmp-zcu1285-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu208-revA.dts | 4 +- arch/arm/dts/zynqmp-zcu216-revA.dts | 4 +- arch/arm/dts/zynqmp.dtsi | 249 +++++++++++++++-------- arch/arm/mach-versal/mp.c | 2 +- drivers/fpga/zynqmppl.c | 2 +- 43 files changed, 345 insertions(+), 169 deletions(-)

-- 2.36.1

Show replies by date

Michal Simek

22 Sep 22 Sep

12:35 p.m.

New subject: [PATCH 01/14] arm64: zynqmp: Describe interrupts by using macros

Use arm-gic.h and irq.h for interrupt description. It helps to improve readability of device tree file.

Suggested-by: Laurent Pinchart laurent.pinchart@ideasonboard.com Signed-off-by: Michal Simek michal.simek@amd.com ---

arch/arm/dts/zynqmp.dtsi | 184 +++++++++++++++++++++++---------------- 1 file changed, 110 insertions(+), 74 deletions(-)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 8d3501018455..951f3f795e97 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -14,6 +14,8 @@

#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h>

@@ -122,7 +124,7 @@ bootph-all; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; - interrupts = <0 35 4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; xlnx,ipi-id = <0>; #address-cells = <2>; #size-cells = <2>; @@ -152,10 +154,10 @@ pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; - interrupts = <0 143 4>, - <0 144 4>, - <0 145 4>, - <0 146 4>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, @@ -183,7 +185,7 @@ bootph-all; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; - interrupts = <0 35 4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; @@ -227,10 +229,10 @@ timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; };

edac { @@ -258,7 +260,7 @@ status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; - interrupts = <0 23 4>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; @@ -271,7 +273,7 @@ status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; - interrupts = <0 24 4>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; @@ -291,11 +293,11 @@ compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; - interrupts = <0 123 4>, - <0 123 4>, - <0 123 4>, - <0 123 4>, - <0 123 4>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; }; };

@@ -305,7 +307,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 124 4>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -318,7 +320,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 125 4>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -331,7 +333,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 126 4>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -344,7 +346,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 127 4>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -357,7 +359,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 128 4>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -370,7 +372,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 129 4>; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -383,7 +385,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 130 4>; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -396,7 +398,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 131 4>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -413,7 +415,7 @@ <0x0 0xf9060000 0x0 0x20000>; interrupt-controller; interrupt-parent = <&gic>; - interrupts = <1 9 0xf04>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; };

gpu: gpu@fd4b0000 { @@ -421,7 +423,12 @@ compatible = "xlnx,zynqmp-mali", "arm,mali-400"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; - interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; clock-names = "bus", "core"; power-domains = <&zynqmp_firmware PD_GPU>; @@ -436,7 +443,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 77 4>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -449,7 +456,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 78 4>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -462,7 +469,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 79 4>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -475,7 +482,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 80 4>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -488,7 +495,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 81 4>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -501,7 +508,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 82 4>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -514,7 +521,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 83 4>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -527,7 +534,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 84 4>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -539,7 +546,7 @@ compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; - interrupts = <0 112 4>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; };

nand0: nand-controller@ff100000 { @@ -548,7 +555,7 @@ reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "controller", "bus"; interrupt-parent = <&gic>; - interrupts = <0 14 4>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x872>; @@ -559,7 +566,8 @@ compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 57 4>, <0 57 4>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; @@ -574,7 +582,8 @@ compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 59 4>, <0 59 4>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; @@ -589,7 +598,8 @@ compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 61 4>, <0 61 4>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; @@ -604,7 +614,8 @@ compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 63 4>, <0 63 4>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; @@ -621,7 +632,7 @@ #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; - interrupts = <0 16 4>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; @@ -632,7 +643,7 @@ compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 17 4>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <400000>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; @@ -644,7 +655,7 @@ compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 18 4>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <400000>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; @@ -668,11 +679,11 @@ msi-controller; device_type = "pci"; interrupt-parent = <&gic>; - interrupts = <0 118 4>, - <0 117 4>, - <0 116 4>, - <0 115 4>, /* MSI_1 [63...32] */ - <0 114 4>; /* MSI_0 [31...0] */ + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, /* MSI_1 [63...32] */ + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; @@ -702,7 +713,7 @@ compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; - interrupts = <0 15 4>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, @@ -727,7 +738,8 @@ status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; - interrupts = <0 26 4>, <0 27 4>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "alarm", "sec"; calibration = <0x7FFF>; }; @@ -737,7 +749,7 @@ status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; - interrupts = <0 133 4>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, @@ -750,7 +762,7 @@ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 48 4>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; iommus = <&smmu 0x870>; @@ -765,7 +777,7 @@ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 49 4>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; iommus = <&smmu 0x871>; @@ -782,18 +794,30 @@ status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; - interrupts = <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; };

spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 19 4>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; @@ -805,7 +829,7 @@ compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 20 4>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; @@ -817,7 +841,9 @@ compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 36 4>, <0 37 4>, <0 38 4>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_0>; @@ -827,7 +853,9 @@ compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 39 4>, <0 40 4>, <0 41 4>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_1>; @@ -837,7 +865,9 @@ compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 42 4>, <0 43 4>, <0 44 4>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_2>; @@ -847,7 +877,9 @@ compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 45 4>, <0 46 4>, <0 47 4>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_3>; @@ -858,7 +890,7 @@ compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 21 4>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_0>; @@ -869,7 +901,7 @@ compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 22 4>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_1>; @@ -896,7 +928,9 @@ reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; - interrupts = <0 65 4>, <0 69 4>, <0 75 4>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; @@ -927,7 +961,9 @@ reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; - interrupts = <0 70 4>, <0 74 4>, <0 76 4>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; @@ -942,7 +978,7 @@ compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 113 1>; + interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <60>; reset-on-timeout; @@ -952,7 +988,7 @@ compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 52 1>; + interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>; reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <10>; }; @@ -961,7 +997,7 @@ compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 56 4>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xffa50000 0x0 0x800>; #address-cells = <1>; #size-cells = <1>; @@ -987,7 +1023,7 @@ compatible = "xlnx,zynqmp-dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; - interrupts = <0 122 4>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; @@ -1003,7 +1039,7 @@ <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf", "aud"; - interrupts = <0 119 4>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in";

-- 2.36.1

Michal Simek

12:35 p.m.

New subject: [PATCH 02/14] arm64: dts: xilinx: zynqmp: Add RPU subsystem device node

From: Tanmay Shah tanmay.shah@amd.com

RPU subsystem can be configured in cluster-mode or split mode. Also each r5 core has separate power domains.

Signed-off-by: Tanmay Shah tanmay.shah@amd.com Signed-off-by: Michal Simek michal.simek@amd.com ---

arch/arm/dts/zynqmp.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 951f3f795e97..5c67c6f602f2 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -120,6 +120,22 @@ }; };

+ reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rproc_0_fw_image: memory@3ed00000 { + no-map; + reg = <0x0 0x3ed00000 0x0 0x40000>; + }; + + rproc_1_fw_image: memory@3ef00000 { + no-map; + reg = <0x0 0x3ef00000 0x0 0x40000>; + }; + }; + zynqmp_ipi: zynqmp-ipi { bootph-all; compatible = "xlnx,zynqmp-ipi-mailbox"; @@ -248,6 +264,23 @@ power-domains = <&zynqmp_firmware PD_PL>; };

+ remoteproc { + compatible = "xlnx,zynqmp-r5fss"; + xlnx,cluster-mode = <1>; + + r5f-0 { + compatible = "xlnx,zynqmp-r5f"; + power-domains = <&zynqmp_firmware PD_RPU_0>; + memory-region = <&rproc_0_fw_image>; + }; + + r5f-1 { + compatible = "xlnx,zynqmp-r5f"; + power-domains = <&zynqmp_firmware PD_RPU_1>; + memory-region = <&rproc_1_fw_image>; + }; + }; + amba: axi { compatible = "simple-bus"; bootph-all;

-- 2.36.1

Michal Simek

12:35 p.m.

New subject: [PATCH 03/14] arm64: xilinx: Remove address/size-cells from flash node

Partitions are described via fixed-partitions that's why there is no need to have address/size-cells in flash node.

Signed-off-by: Michal Simek michal.simek@amd.com ---

arch/arm/dts/zynqmp-sm-k26-revA.dts | 2 -- 1 file changed, 2 deletions(-)

diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 80b9face7483..47e8e747ba36 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -145,8 +145,6 @@ status = "okay"; spi_flash: flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>;

-- 2.36.1

Michal Simek

12:35 p.m.

New subject: [PATCH 04/14] arm64: xilinx: Use lower case for partition address

Lower case should be used for register address. Issue is reported as: flash@0: partitions: Unevaluated properties are not allowed ('partition@22A0000' was unexpected)

Signed-off-by: Michal Simek michal.simek@amd.com ---

arch/arm/dts/zynqmp-sm-k26-revA.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 47e8e747ba36..1d62c48e062e 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -233,9 +233,9 @@ label = "Secure OS Storage"; reg = <0x2280000 0x20000>; /* 128KB */ }; - partition@22A0000 { + partition@22a0000 { label = "User"; - reg = <0x22A0000 0x1d60000>; /* 29.375 MB */ + reg = <0x22a0000 0x1d60000>; /* 29.375 MB */ }; }; };

-- 2.36.1

Michal Simek

12:35 p.m.

New subject: [PATCH 05/14] arm64: zynqmp: Describe bus-width for SD card on KV260

SD card is connected with 4 data lines which should be described properly.

Signed-off-by: Michal Simek michal.simek@amd.com ---

arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 2 +- arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index 55bef1df75d0..72361f6f9e4a 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -156,7 +156,7 @@ disable-wp; xlnx,mio-bank = <1>; assigned-clock-rates = <187498123>; - bus-width = <8>; + bus-width = <4>; };

&gem3 { diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index 1b1d9e772f55..44738cef23be 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -144,7 +144,7 @@ clk-phase-uhs-sdr25 = <120>, <60>; clk-phase-uhs-ddr50 = <126>, <48>; assigned-clock-rates = <187498123>; - bus-width = <8>; + bus-width = <4>; };

&gem3 {

-- 2.36.1

Michal Simek

12:35 p.m.

New subject: [PATCH 06/14] arm64: zynqmp: Fix Siva's email address format

Some patches didn't have his full name and also there was one more ">" at the end of email address. That's why correct both of these issues.

Fixes: 174d728471d5 ("arm64: zynqmp: Switch to amd.com emails") Signed-off-by: Michal Simek michal.simek@amd.com ---

diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts index bd685ddfdb42..60b1c0e1fc44 100644 --- a/arch/arm/dts/versal-mini-emmc0.dts +++ b/arch/arm/dts/versal-mini-emmc0.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad siva.durga.prasad.paladugu@amd.com> + * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com * Michal Simek michal.simek@amd.com */

diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts index fbdcf5d77f56..751cc38ee5c0 100644 --- a/arch/arm/dts/versal-mini-emmc1.dts +++ b/arch/arm/dts/versal-mini-emmc1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad siva.durga.prasad.paladugu@amd.com> + * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com * Michal Simek michal.simek@amd.com */

diff --git a/arch/arm/dts/versal-mini-ospi.dtsi b/arch/arm/dts/versal-mini-ospi.dtsi index 5683a2306bde..1abe44f40426 100644 --- a/arch/arm/dts/versal-mini-ospi.dtsi +++ b/arch/arm/dts/versal-mini-ospi.dtsi @@ -4,7 +4,7 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad siva.durga.prasad.paladugu@amd.com> + * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com * Michal Simek michal.simek@amd.com */

diff --git a/arch/arm/dts/versal-mini-qspi.dtsi b/arch/arm/dts/versal-mini-qspi.dtsi index 2fec92ce3ec8..9347ea32c9cb 100644 --- a/arch/arm/dts/versal-mini-qspi.dtsi +++ b/arch/arm/dts/versal-mini-qspi.dtsi @@ -4,7 +4,7 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad siva.durga.prasad.paladugu@amd.com> + * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com * Michal Simek michal.simek@amd.com */

diff --git a/arch/arm/dts/versal-mini.dts b/arch/arm/dts/versal-mini.dts index a213b745bc26..844e3840acec 100644 --- a/arch/arm/dts/versal-mini.dts +++ b/arch/arm/dts/versal-mini.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com> + * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com */

/dts-v1/; diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts index 08ec2f7b4a9a..02e80bd85e1a 100644 --- a/arch/arm/dts/zynqmp-mini-emmc0.dts +++ b/arch/arm/dts/zynqmp-mini-emmc0.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Siva Durga Prasad siva.durga.prasad.paladugu@amd.com> + * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com */

/dts-v1/; diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts index 905de08fdb0b..ce1cdb207538 100644 --- a/arch/arm/dts/zynqmp-mini-emmc1.dts +++ b/arch/arm/dts/zynqmp-mini-emmc1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Siva Durga Prasad siva.durga.prasad.paladugu@amd.com> + * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com */

/dts-v1/; diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts index e5688fd703e6..e0517cf46017 100644 --- a/arch/arm/dts/zynqmp-mini-nand.dts +++ b/arch/arm/dts/zynqmp-mini-nand.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Siva Durga Prasad siva.durga.prasad.paladugu@amd.com> + * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com * Michal Simek michal.simek@amd.com */

diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts index fc0a2e801e49..ee8be5360004 100644 --- a/arch/arm/dts/zynqmp-mini-qspi.dts +++ b/arch/arm/dts/zynqmp-mini-qspi.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2020, Xilinx, Inc. * - * Siva Durga Prasad siva.durga.prasad.paladugu@amd.com> + * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com * Michal Simek michal.simek@amd.com */

diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts index 5c4acd17cc5d..c6a63201c1c4 100644 --- a/arch/arm/dts/zynqmp-zc1254-revA.dts +++ b/arch/arm/dts/zynqmp-zc1254-revA.dts @@ -5,7 +5,7 @@ * (C) Copyright 2015 - 2020, Xilinx, Inc. * * Michal Simek michal.simek@amd.com - * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com> + * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com */

/dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index 74a5b020e863..0d2ea9c09a0a 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Siva Durga Prasad siva.durga.prasad.paladugu@amd.com> + * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com * Michal Simek michal.simek@amd.com */

diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index 9404c139a24b..095c972f1322 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -5,7 +5,7 @@ * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek michal.simek@amd.com - * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com> + * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com */

/dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index c06d262506d0..4060dc3613a2 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -5,7 +5,7 @@ * (C) Copyright 2018 - 2021, Xilinx, Inc. * * Michal Simek michal.simek@amd.com - * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com> + * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com */

/dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts index 99ea143c02ea..4f85837e64f6 100644 --- a/arch/arm/dts/zynqmp-zcu1285-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts @@ -5,7 +5,7 @@ * (C) Copyright 2018 - 2021, Xilinx, Inc. * * Michal Simek michal.simek@amd.com - * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com> + * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com */

/dts-v1/; diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c index 7bd39289fac5..2487b482ddb1 100644 --- a/arch/arm/mach-versal/mp.c +++ b/arch/arm/mach-versal/mp.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * (C) Copyright 2019 Xilinx, Inc. - * Siva Durga Prasad siva.durga.prasad.paladugu@amd.com> + * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com */

#include <common.h> diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index b1f201fb18ba..2656f5fc5ecf 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -2,7 +2,7 @@ /* * (C) Copyright 2015 - 2016, Xilinx, Inc, * Michal Simek michal.simek@amd.com - * Siva Durga Prasad siva.durga.prasad.paladugu@amd.com> + * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com */

#include <console.h>

-- 2.36.1

Michal Simek

12:35 p.m.

New subject: [PATCH 07/14] arm64: xilinx: Put ethernet phys to mdio node

All zynqmp boards have been already described via mdio node that's why also convert the rest of the boards. With using mdio node there is an option to add reset property for the whole mdio bus which is reflected by 's/phy-reset-gpios/reset-gpios/g' for some boards.

Signed-off-by: Michal Simek michal.simek@amd.com ---

we will investigate if we can remove also that xlnx,phy-type if it is deprecated now. --- arch/arm/dts/zynqmp-dlc21-revA.dts | 10 ++++++--- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 10 ++++++--- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 10 ++++++--- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 10 ++++++--- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 10 ++++++--- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 10 ++++++--- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 8 ++++++-- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 16 +++++++++------ arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 8 ++++++-- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 26 ++++++++++++++---------- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 8 ++++++-- 11 files changed, 85 insertions(+), 41 deletions(-)

diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts index 016081ef7b99..f737004d7943 100644 --- a/arch/arm/dts/zynqmp-dlc21-revA.dts +++ b/arch/arm/dts/zynqmp-dlc21-revA.dts @@ -88,9 +88,13 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; - /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ - phy0: ethernet-phy@0 { - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ + phy0: ethernet-phy@0 { + reg = <0>; + }; }; };

diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index d5cfc61faf71..36a0db44fd28 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -81,10 +81,14 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; - phy0: ethernet-phy@0 { /* marwell m88e1512 */ - reg = <0>; - reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { /* marwell m88e1512 */ + reg = <0>; + reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; /* xlnx,phy-type = <PHY_TYPE_SGMII>; */ + }; }; };

diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index 56653ec234ee..24573f7b6c2a 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -110,10 +110,14 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ - phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; - phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; + phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ + reg = <0>; /* xlnx,phy-type = <PHY_TYPE_SGMII>; */ + }; }; };

diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index 4c8ae80f6f17..58566fbea78e 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -106,9 +106,13 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; - phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; - phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; + phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ + reg = <0>; + }; }; };

diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index 4bdf58d11e11..529c98cf543d 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -106,9 +106,13 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; - phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; - phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; + phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ + reg = <0>; + }; }; };

diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index 64a676c13257..c456c375ac80 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -91,9 +91,13 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; - /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ - phy0: ethernet-phy@0 { - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ + phy0: ethernet-phy@0 { + reg = <0>; + }; }; };

diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index cffad447406b..5b592324021a 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -97,8 +97,12 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@0 { - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; }; };

diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index bb0477825a93..83648c2a1c54 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -90,12 +90,16 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; - phy0: ethernet-phy@5 { - reg = <5>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@5 { + reg = <5>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + }; }; };

diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index 69ad58039e79..b97f7ee8d44f 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -88,8 +88,12 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: ethernet-phy@0 { /* VSC8211 */ - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { /* VSC8211 */ + reg = <0>; + }; }; };

diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index 3017c9b29a2b..2b66abc9f7e6 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -116,17 +116,21 @@ status = "okay"; phy-mode = "rgmii-id"; phy-handle = <&ethernet_phy0>; - ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ - reg = <0>; - }; - ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ - reg = <7>; - }; - ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ - reg = <3>; - }; - ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ - reg = <8>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ + reg = <0>; + }; + ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ + reg = <7>; + }; + ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ + reg = <3>; + }; + ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ + reg = <8>; + }; }; };

diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index 0d2ea9c09a0a..b1857e17ab7e 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -77,8 +77,12 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem1_default>; - phy0: ethernet-phy@0 { - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; }; };

-- 2.36.1

Michal Simek

12:35 p.m.

New subject: [PATCH 08/14] arm64: xilinx: Remove address/size-cells from gem nodes

Some boards are using one mdio bus which holds multiple phys and also boards are using mdio node for bus description. That's why there are cases where address/size-cells are unnecessary which is also reported by make W=1 dtbs. That's why remove them from zynqmp.dtsi and let board DTSes to handle it based on used description.

Error log: /axi/ethernet@ff0e0000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property

Signed-off-by: Michal Simek michal.simek@amd.com ---

arch/arm/dts/zynqmp.dtsi | 8 -------- 1 file changed, 8 deletions(-)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 5c67c6f602f2..20a954e69db0 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -603,8 +603,6 @@ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - #address-cells = <1>; - #size-cells = <0>; iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware PD_ETH_0>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; @@ -619,8 +617,6 @@ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - #address-cells = <1>; - #size-cells = <0>; iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware PD_ETH_1>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; @@ -635,8 +631,6 @@ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - #address-cells = <1>; - #size-cells = <0>; iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware PD_ETH_2>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; @@ -651,8 +645,6 @@ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - #address-cells = <1>; - #size-cells = <0>; iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware PD_ETH_3>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;

-- 2.36.1

Michal Simek

12:35 p.m.

New subject: [PATCH 09/14] arm64: dts: zynqmp: zcu106a: Describe DisplayPort connector

From: Laurent Pinchart laurent.pinchart@ideasonboard.com

Add a device tree node to describe the DisplayPort connector, and connect it to the DPSUB output.

Signed-off-by: Laurent Pinchart laurent.pinchart@ideasonboard.com Signed-off-by: Michal Simek michal.simek@amd.com ---

arch/arm/dts/zynqmp-zcu106-revA.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)

diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index f8019c592a7f..4b8c69407ff6 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -150,6 +150,18 @@ #clock-cells = <0>; clock-frequency = <114285000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; };

&can1 { @@ -1065,4 +1077,12 @@ phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 3>, <&psgtr 0 PHY_TYPE_DP 1 3>; + + ports { + port@5 { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; + }; + }; };

-- 2.36.1

Michal Simek

12:35 p.m.

New subject: [PATCH 10/14] arm64: dts: zynqmp: Add ports for the DisplayPort subsystem

From: Laurent Pinchart laurent.pinchart@ideasonboard.com

The DPSUB DT bindings now specify ports to model the connections with the programmable logic and the DisplayPort output. Add them to the device tree.

Signed-off-by: Laurent Pinchart laurent.pinchart@ideasonboard.com Acked-by: Michal Simek michal.simek@amd.com Link: https://lore.kernel.org/r/1f367ee9554af5d67c86f206e1d6889cc99f6f45.169504977... Signed-off-by: Michal Simek michal.simek@amd.com ---

arch/arm/dts/zynqmp.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 20a954e69db0..f03c201caee9 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -1075,6 +1075,30 @@ <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + port@2 { + reg = <2>; + }; + port@3 { + reg = <3>; + }; + port@4 { + reg = <4>; + }; + port@5 { + reg = <5>; + }; + }; }; }; };

-- 2.36.1

Michal Simek

12:35 p.m.

New subject: [PATCH 11/14] arm64: zynqmp: Convert kv260-revA overlay to ASCII text

File was in UTF-8 format but there is no reason for it. Convert it to ASCII/plain text.

Signed-off-by: Michal Simek michal.simek@amd.com ---

arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index 72361f6f9e4a..530bc9076d94 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -5,9 +5,9 @@ * (C) Copyright 2020 - 2021, Xilinx, Inc. * * SD level shifter: - * "A" – A01 board un-modified (NXP) - * "Y" – A01 board modified with legacy interposer (Nexperia) - * "Z" – A01 board modified with Diode interposer + * "A" - A01 board un-modified (NXP) + * "Y" - A01 board modified with legacy interposer (Nexperia) + * "Z" - A01 board modified with Diode interposer * * Michal Simek michal.simek@amd.com */

-- 2.36.1

Michal Simek

12:35 p.m.

New subject: [PATCH 12/14] arm64: zynqmp: Sync licenses with Linux kernel

There is difference between licenses in the Linux kernel and there shouldn't be any diff because all changes are coming from the same source at the same time. The difference is really in a time when they were upstreamed. That's why sync it up.

Signed-off-by: Michal Simek michal.simek@amd.com ---

arch/arm/dts/avnet-ultra96-rev1.dts | 2 +- arch/arm/dts/zynqmp-clk-ccf.dtsi | 3 ++- arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 3 ++- arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 3 ++- arch/arm/dts/zynqmp-zc1254-revA.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 3 ++- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 3 ++- arch/arm/dts/zynqmp-zcu102-rev1.0.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revA.dts | 3 ++- arch/arm/dts/zynqmp-zcu102-revB.dts | 3 ++- arch/arm/dts/zynqmp-zcu104-revA.dts | 3 ++- arch/arm/dts/zynqmp-zcu104-revC.dts | 5 +++-- arch/arm/dts/zynqmp-zcu106-revA.dts | 3 ++- arch/arm/dts/zynqmp-zcu111-revA.dts | 3 ++- 14 files changed, 26 insertions(+), 15 deletions(-)

diff --git a/arch/arm/dts/avnet-ultra96-rev1.dts b/arch/arm/dts/avnet-ultra96-rev1.dts index 96a6403efaf3..4c1bd69e7553 100644 --- a/arch/arm/dts/avnet-ultra96-rev1.dts +++ b/arch/arm/dts/avnet-ultra96-rev1.dts @@ -2,7 +2,7 @@ /* * dts file for Avnet Ultra96 rev1 * - * (C) Copyright 2018 - 2020, Xilinx, Inc. + * (C) Copyright 2018, Xilinx, Inc. * * Michal Simek michal.simek@amd.com */ diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 9c0aa073dd94..4044b62d27a2 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek michal.simek@amd.com */ diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index 530bc9076d94..22e7d68d02b3 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -2,7 +2,8 @@ /* * dts file for KV260 revA Carrier Card * - * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2020 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * SD level shifter: * "A" - A01 board un-modified (NXP) diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index 44738cef23be..eadc2563064b 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -2,7 +2,8 @@ /* * dts file for KV260 revA Carrier Card * - * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2020 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek michal.simek@amd.com */ diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts index c6a63201c1c4..cb9ef3746803 100644 --- a/arch/arm/dts/zynqmp-zc1254-revA.dts +++ b/arch/arm/dts/zynqmp-zc1254-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2020, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek michal.simek@amd.com * Siva Durga Prasad Paladugu siva.durga.prasad.paladugu@amd.com diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 5b592324021a..4fcb46605537 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2021, Xilinx, Inc. + * (C) Copyright 2015 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek michal.simek@amd.com */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 83648c2a1c54..23a3ff2fed98 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2021, Xilinx, Inc. + * (C) Copyright 2015 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek michal.simek@amd.com */ diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts index c0a4d913afea..c8f71a1aec89 100644 --- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts +++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016 - 2018, Xilinx, Inc. * * Michal Simek michal.simek@amd.com */ diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 0f7230b9526e..025e6519ea6a 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2021, Xilinx, Inc. + * (C) Copyright 2015 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek michal.simek@amd.com */ diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index ce0a6e5f60a7..3c28130909bc 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek michal.simek@amd.com */ diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 90fbfca87f2b..cdfeea2fdd84 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek michal.simek@amd.com */ diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 69470f8dede3..4b942acd4132 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -1,8 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek michal.simek@amd.com */ diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 4b8c69407ff6..776373d517b3 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek michal.simek@amd.com */ diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index c9ff99f8a830..62a8be9a537f 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek michal.simek@amd.com */

-- 2.36.1

Michal Simek

12:35 p.m.

New subject: [PATCH 13/14] ARM: zynq: Describe nand device in DT

Linux requires to describe nand structure under nand controller. If it is not described nand device is not detected by Linux.

Error shown by Linux kernel: pl35x-nand-controller e1000000.nand-controller: Incorrect number of NAND chips (0) pl35x-nand-controller: probe of e1000000.nand-controller failed with error -22

When wired: nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xda nand: Micron MT29F2G08ABAEAWP nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64

Signed-off-by: Michal Simek michal.simek@amd.com ---

arch/arm/dts/bitmain-antminer-s9.dts | 3 +++ arch/arm/dts/zynq-zc770-xm011.dts | 3 +++ 2 files changed, 6 insertions(+)

diff --git a/arch/arm/dts/bitmain-antminer-s9.dts b/arch/arm/dts/bitmain-antminer-s9.dts index 6c47396ce759..0228b4b30e5b 100644 --- a/arch/arm/dts/bitmain-antminer-s9.dts +++ b/arch/arm/dts/bitmain-antminer-s9.dts @@ -52,6 +52,9 @@

&nfc0 { status = "okay"; + nand@0 { + reg = <0>; + }; };

&smcc { diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index 02214349feb7..d1e971254e51 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -49,6 +49,9 @@

&nfc0 { status = "okay"; + nand@0 { + reg = <0>; + }; };

&smcc {

-- 2.36.1

Michal Simek

12:35 p.m.

New subject: [PATCH 14/14] arm64: zynqmp: Aligned QSPI configuration with latest spec

Official DT binding description for dual stacked/paralllel configurations have been merged that's why switch to it.

Link: https://lore.kernel.org/r/20220126112608.955728-3-miquel.raynal@bootlin.com Signed-off-by: Michal Simek michal.simek@amd.com ---

arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 4 +++- arch/arm/dts/zynqmp-zcu102-revA.dts | 4 +++- arch/arm/dts/zynqmp-zcu106-revA.dts | 4 +++- arch/arm/dts/zynqmp-zcu111-revA.dts | 4 +++- arch/arm/dts/zynqmp-zcu208-revA.dts | 4 +++- arch/arm/dts/zynqmp-zcu216-revA.dts | 4 +++- 6 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 4fcb46605537..e72ed50b1cb2 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -354,11 +354,13 @@

&qspi { status = "okay"; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 025e6519ea6a..be75ca6443d8 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -972,11 +972,13 @@ &qspi { status = "okay"; is-dual = <1>; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 776373d517b3..6cae681dc29f 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -979,11 +979,13 @@ &qspi { status = "okay"; is-dual = <1>; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 62a8be9a537f..d08865203ecf 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -790,11 +790,13 @@ &qspi { status = "okay"; is-dual = <1>; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 01fc3d47f81e..ab3ec80a55f6 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -644,11 +644,13 @@ &qspi { status = "okay"; is-dual = <1>; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; - reg = <0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index 2973e939b0ed..5e076faa254b 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -654,11 +654,13 @@ &qspi { status = "okay"; is-dual = <1>; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */

-- 2.36.1

Michal Simek

2 Oct 2 Oct

12:11 p.m.

On 9/22/23 12:35, Michal Simek wrote:

...

Hi,

this series is syncing DTs with Linux kernel. A lot of patches are simply taken from the Linux kernel and taken to U-Boot. But there are also some new one which are trying to fix violations. There is still some work to happen to be 100% in sync but we are getting closer and closer.

Thanks, Michal

Laurent Pinchart (2): arm64: dts: zynqmp: zcu106a: Describe DisplayPort connector arm64: dts: zynqmp: Add ports for the DisplayPort subsystem

Michal Simek (11): arm64: zynqmp: Describe interrupts by using macros arm64: xilinx: Remove address/size-cells from flash node arm64: xilinx: Use lower case for partition address arm64: zynqmp: Describe bus-width for SD card on KV260 arm64: zynqmp: Fix Siva's email address format arm64: xilinx: Put ethernet phys to mdio node arm64: xilinx: Remove address/size-cells from gem nodes arm64: zynqmp: Convert kv260-revA overlay to ASCII text arm64: zynqmp: Sync licenses with Linux kernel ARM: zynq: Describe nand device in DT arm64: zynqmp: Aligned QSPI configuration with latest spec

Tanmay Shah (1): arm64: dts: xilinx: zynqmp: Add RPU subsystem device node

arch/arm/dts/avnet-ultra96-rev1.dts | 2 +- arch/arm/dts/bitmain-antminer-s9.dts | 3 + arch/arm/dts/versal-mini-emmc0.dts | 2 +- arch/arm/dts/versal-mini-emmc1.dts | 2 +- arch/arm/dts/versal-mini-ospi.dtsi | 2 +- arch/arm/dts/versal-mini-qspi.dtsi | 2 +- arch/arm/dts/versal-mini.dts | 2 +- arch/arm/dts/zynq-zc770-xm011.dts | 3 + arch/arm/dts/zynqmp-clk-ccf.dtsi | 3 +- arch/arm/dts/zynqmp-dlc21-revA.dts | 10 +- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 10 +- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 10 +- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 10 +- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 10 +- arch/arm/dts/zynqmp-mini-emmc0.dts | 2 +- arch/arm/dts/zynqmp-mini-emmc1.dts | 2 +- arch/arm/dts/zynqmp-mini-nand.dts | 2 +- arch/arm/dts/zynqmp-mini-qspi.dts | 2 +- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 10 +- arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 11 +- arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 5 +- arch/arm/dts/zynqmp-sm-k26-revA.dts | 6 +- arch/arm/dts/zynqmp-zc1254-revA.dts | 4 +- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 15 +- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 19 +- arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 8 +- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 26 ++- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 10 +- arch/arm/dts/zynqmp-zcu102-rev1.0.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revA.dts | 7 +- arch/arm/dts/zynqmp-zcu102-revB.dts | 3 +- arch/arm/dts/zynqmp-zcu104-revA.dts | 3 +- arch/arm/dts/zynqmp-zcu104-revC.dts | 5 +- arch/arm/dts/zynqmp-zcu106-revA.dts | 27 ++- arch/arm/dts/zynqmp-zcu111-revA.dts | 7 +- arch/arm/dts/zynqmp-zcu1275-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu1275-revB.dts | 2 +- arch/arm/dts/zynqmp-zcu1285-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu208-revA.dts | 4 +- arch/arm/dts/zynqmp-zcu216-revA.dts | 4 +- arch/arm/dts/zynqmp.dtsi | 249 +++++++++++++++-------- arch/arm/mach-versal/mp.c | 2 +- drivers/fpga/zynqmppl.c | 2 +- 43 files changed, 345 insertions(+), 169 deletions(-)

Applied but removed Link from 10/14 which wasn't correct.

Thanks, Michal

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Michal Simek