[PULL] u-boot-socfpga/master
The following changes since commit 80e99adbe47d1c8590f9b971ac52257fdc51a5ec:
Merge tag 'uniphier-v2020.04-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier (2020-01-31 13:26:28 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to 56c24875d92adcf214d97f5798e11c1b7b5e27fa:
ddr: altera: Add DDR2 support to Gen5 driver (2020-02-02 18:18:05 +0100)
---------------------------------------------------------------- Ley Foon Tan (1): reset: socfpga: Poll for reset status after deassert reset
Marek Vasut (5): ARM: socfpga: Drop last use of socfpga_reset_manager watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig watchdog: designware: Convert to DM and DT probing watchdog: designware: Optionally fetch clock and reset from DT ddr: altera: Add DDR2 support to Gen5 driver
arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 4 ++ arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 4 ++ arch/arm/mach-socfpga/include/mach/sdram_gen5.h | 46 +++++++++++++++---- arch/arm/mach-socfpga/qts-filter.sh | 2 +- arch/arm/mach-socfpga/spl_gen5.c | 5 +-- arch/arm/mach-socfpga/wrap_sdram_config.c | 64 +++++++++++++++++--------- configs/socfpga_stratix10_defconfig | 3 ++ configs/socfpga_vining_fpga_defconfig | 2 + drivers/ddr/altera/sdram_gen5.c | 6 ++- drivers/ddr/altera/sequencer.c | 193 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++--------------- drivers/ddr/altera/sequencer.h | 1 + drivers/reset/reset-socfpga.c | 6 ++- drivers/watchdog/Kconfig | 7 +++ drivers/watchdog/designware_wdt.c | 150 +++++++++++++++++++++++++++++++++++++++++++++++++++---------- include/configs/socfpga_common.h | 3 -- include/configs/socfpga_soc64_common.h | 7 ++- scripts/config_whitelist.txt | 1 - 17 files changed, 399 insertions(+), 105 deletions(-)
On Sun, Feb 02, 2020 at 06:18:53PM +0100, Marek Vasut wrote:
The following changes since commit 80e99adbe47d1c8590f9b971ac52257fdc51a5ec:
Merge tag 'uniphier-v2020.04-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier (2020-01-31 13:26:28 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to 56c24875d92adcf214d97f5798e11c1b7b5e27fa:
ddr: altera: Add DDR2 support to Gen5 driver (2020-02-02 18:18:05 +0100)
A see a ton of failures: aarch64: + socfpga_agilex arm: + socfpga_is1 socfpga_cyclone5 socfpga_de10_nano socfpga_mcvevk socfpga_dbm_soc1 socfpga_arria5 socfpga_de1_soc socfpga_sr1500 socfpga_socrates socfpga_sockit socfpga_vining_fpga socfpga_de0_nano_soc
Thanks!
On 2/2/20 9:26 PM, Tom Rini wrote:
On Sun, Feb 02, 2020 at 06:18:53PM +0100, Marek Vasut wrote:
The following changes since commit 80e99adbe47d1c8590f9b971ac52257fdc51a5ec:
Merge tag 'uniphier-v2020.04-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier (2020-01-31 13:26:28 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to 56c24875d92adcf214d97f5798e11c1b7b5e27fa:
ddr: altera: Add DDR2 support to Gen5 driver (2020-02-02 18:18:05 +0100)
A see a ton of failures: aarch64: + socfpga_agilex arm: + socfpga_is1 socfpga_cyclone5 socfpga_de10_nano socfpga_mcvevk socfpga_dbm_soc1 socfpga_arria5 socfpga_de1_soc socfpga_sr1500 socfpga_socrates socfpga_sockit socfpga_vining_fpga socfpga_de0_nano_soc
I don't see those failures locally.
Thanks!
Thanks!
On 2/3/20 9:24 AM, Marek Vasut wrote:
On 2/2/20 9:26 PM, Tom Rini wrote:
On Sun, Feb 02, 2020 at 06:18:53PM +0100, Marek Vasut wrote:
The following changes since commit 80e99adbe47d1c8590f9b971ac52257fdc51a5ec:
Merge tag 'uniphier-v2020.04-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier (2020-01-31 13:26:28 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to 56c24875d92adcf214d97f5798e11c1b7b5e27fa:
ddr: altera: Add DDR2 support to Gen5 driver (2020-02-02 18:18:05 +0100)
A see a ton of failures: aarch64: + socfpga_agilex
OK, this one I see, let's add this patch
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index da81137e84..87c73457a0 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -150,10 +150,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* * L4 Watchdog */ -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_WATCHDOG -#define CONFIG_HW_WATCHDOG -#else +#ifndef CONFIG_SPL_BUILD #undef CONFIG_HW_WATCHDOG #undef CONFIG_DESIGNWARE_WATCHDOG #endif
On Mon, Feb 03, 2020 at 09:47:04AM +0100, Marek Vasut wrote:
On 2/3/20 9:24 AM, Marek Vasut wrote:
On 2/2/20 9:26 PM, Tom Rini wrote:
On Sun, Feb 02, 2020 at 06:18:53PM +0100, Marek Vasut wrote:
The following changes since commit 80e99adbe47d1c8590f9b971ac52257fdc51a5ec:
Merge tag 'uniphier-v2020.04-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier (2020-01-31 13:26:28 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to 56c24875d92adcf214d97f5798e11c1b7b5e27fa:
ddr: altera: Add DDR2 support to Gen5 driver (2020-02-02 18:18:05 +0100)
A see a ton of failures: aarch64: + socfpga_agilex
OK, this one I see, let's add this patch
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index da81137e84..87c73457a0 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -150,10 +150,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /*
- L4 Watchdog
*/ -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_WATCHDOG -#define CONFIG_HW_WATCHDOG -#else +#ifndef CONFIG_SPL_BUILD #undef CONFIG_HW_WATCHDOG #undef CONFIG_DESIGNWARE_WATCHDOG #endif
To be clear, I'm expecting a new PR, thanks.
The following changes since commit 31a790bee939e227dfc7e6a6a323b2b13180707f:
Merge branch 'master' of git://git.denx.de/u-boot-usb (2020-02-02 15:26:53 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to 9a5a90ad9b3234c4739427cbe11219c51f0e9bd1:
ddr: altera: Add DDR2 support to Gen5 driver (2020-02-05 03:01:57 +0100)
---------------------------------------------------------------- Ley Foon Tan (1): reset: socfpga: Poll for reset status after deassert reset
Marek Vasut (5): ARM: socfpga: Drop last use of socfpga_reset_manager watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig watchdog: designware: Convert to DM and DT probing watchdog: designware: Optionally fetch clock and reset from DT ddr: altera: Add DDR2 support to Gen5 driver
arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 4 ++ arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 4 ++ arch/arm/mach-socfpga/include/mach/sdram_gen5.h | 46 +++++++++++++++---- arch/arm/mach-socfpga/qts-filter.sh | 2 +- arch/arm/mach-socfpga/spl_gen5.c | 5 +-- arch/arm/mach-socfpga/wrap_sdram_config.c | 64 +++++++++++++++++--------- configs/socfpga_stratix10_defconfig | 2 + configs/socfpga_vining_fpga_defconfig | 3 +- drivers/ddr/altera/sdram_gen5.c | 6 ++- drivers/ddr/altera/sequencer.c | 194 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++--------------- drivers/ddr/altera/sequencer.h | 1 + drivers/reset/reset-socfpga.c | 6 ++- drivers/watchdog/Kconfig | 7 +++ drivers/watchdog/designware_wdt.c | 150 +++++++++++++++++++++++++++++++++++++++++++++++++++---------- include/configs/socfpga_common.h | 3 -- include/configs/socfpga_soc64_common.h | 8 ++-- scripts/config_whitelist.txt | 1 - 17 files changed, 398 insertions(+), 108 deletions(-)
On Wed, Feb 05, 2020 at 07:58:12AM +0100, Marek Vasut wrote:
The following changes since commit 31a790bee939e227dfc7e6a6a323b2b13180707f:
Merge branch 'master' of git://git.denx.de/u-boot-usb (2020-02-02 15:26:53 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to 9a5a90ad9b3234c4739427cbe11219c51f0e9bd1:
ddr: altera: Add DDR2 support to Gen5 driver (2020-02-05 03:01:57 +0100)
Applied to u-boot/master, thanks!
participants (2)
-
Marek Vasut -
Tom Rini