[U-Boot] [PATCH v2 0/1] mtd: added missing GigaDevice chips
in kernel tree are additional 2 chips from GigaDevice, which i need for Vocore2 (MT7688)
Jiri Kastner (1): mtd: added missing GigaDevice chips
drivers/mtd/spi/spi-nor-ids.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
Vocore2 (mt7688 based device) has g25q128 chip from GigaDevice, which i've found in kernel tree. added chips are gd25q128 and gd25q256.
Cc: Jagan Teki jteki@openedev.com Cc: Vignesh R vigneshr@ti.com --- drivers/mtd/spi/spi-nor-ids.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 3215e2431d..c1f84df64f 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -106,6 +106,16 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { + INFO("gd25q256", 0xc84019, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */
Hi,
On 18/02/19 3:30 PM, Jiri Kastner wrote:
Vocore2 (mt7688 based device) has g25q128 chip from GigaDevice, which i've found in kernel tree. added chips are gd25q128 and gd25q256.
Cc: Jagan Teki jteki@openedev.com Cc: Vignesh R vigneshr@ti.com
drivers/mtd/spi/spi-nor-ids.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 3215e2431d..c1f84df64f 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -106,6 +106,16 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
- {
INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256,SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)- },
- {
INFO("gd25q256", 0xc84019, 0, 64 * 1024, 512,SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)- },
Have you tested Quad mode on this device? I see gd25q256 uses macronix_quad_enable() and kernel handles this by .quad_enable() callback which isnt supported in U-Boot yet. Could you explain how Quad mode would work in U-Boot with this flash?
On Wed, 20 Feb 2019 10:03:39 +0530, Vignesh R wrote:
Hi,
Have you tested Quad mode on this device? I see gd25q256 uses macronix_quad_enable() and kernel handles this by .quad_enable() callback which isnt supported in U-Boot yet. Could you explain how Quad mode would work in U-Boot with this flash?
hi, if i read correctly between lines, in that case gd25q64 is not tested with quad mode too, as i copied flags from q64 (already being in master).
no chance to test q256 at all.
best regards jiri kastner
On Thu, Feb 21, 2019 at 3:05 AM Jiri Kastner cz172638@gmail.com wrote:
On Wed, 20 Feb 2019 10:03:39 +0530, Vignesh R wrote:
Hi,
Have you tested Quad mode on this device? I see gd25q256 uses macronix_quad_enable() and kernel handles this by .quad_enable() callback which isnt supported in U-Boot yet. Could you explain how Quad mode would work in U-Boot with this flash?
hi, if i read correctly between lines, in that case gd25q64 is not tested with quad mode too, as i copied flags from q64 (already being in master).
no chance to test q256 at all.
Would you test this and update the quad flag?
participants (3)
-
Jagan Teki -
Jiri Kastner -
Vignesh R