[U-Boot] [PATCH v1 0/5] colibri imx8qxp 2gb wb it v1.0b module support
This series fixes the i.MX 8QXP SCFW API header file, adds support for more lpuart instances, cleans-up and extends the Toradex SKU handling and last but not least introduces support for the Toradex Colibri iMX8QXP 2GB WB IT V1.0B module.
This series is available together with my previous series addressing Apalis and Colibri iMX6 as well as Colibri Vybrid aka VF50/VF61 and Colibri iMX6ULL on our git server [1].
[1] http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next
Marcel Ziswiler (5): misc: imx8: remove duplicates from scfw api arm: dts: imx8dx: add lpuart1, lpuart2, lpuart3 board: toradex: tdx-cfg-block: clean-up sku handling board: toradex: tdx-cfg-block: add new skus board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support
arch/arm/dts/Makefile | 4 +- arch/arm/dts/fsl-imx8dx.dtsi | 54 +++ arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi | 112 ++++++ arch/arm/dts/fsl-imx8qxp-colibri.dts | 328 ++++++++++++++++++ arch/arm/include/asm/arch-imx8/sci/sci.h | 4 - arch/arm/mach-imx/imx8/Kconfig | 6 + board/toradex/colibri-imx8qxp/Kconfig | 30 ++ board/toradex/colibri-imx8qxp/MAINTAINERS | 9 + board/toradex/colibri-imx8qxp/Makefile | 7 + board/toradex/colibri-imx8qxp/README | 67 ++++ .../toradex/colibri-imx8qxp/colibri-imx8qxp.c | 211 +++++++++++ board/toradex/colibri-imx8qxp/imximage.cfg | 24 ++ board/toradex/common/tdx-cfg-block.c | 19 +- board/toradex/common/tdx-cfg-block.h | 29 +- configs/colibri-imx8qxp_defconfig | 53 +++ include/configs/colibri-imx8qxp.h | 240 +++++++++++++ 16 files changed, 1178 insertions(+), 19 deletions(-) create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri.dts create mode 100644 board/toradex/colibri-imx8qxp/Kconfig create mode 100644 board/toradex/colibri-imx8qxp/MAINTAINERS create mode 100644 board/toradex/colibri-imx8qxp/Makefile create mode 100644 board/toradex/colibri-imx8qxp/README create mode 100644 board/toradex/colibri-imx8qxp/colibri-imx8qxp.c create mode 100644 board/toradex/colibri-imx8qxp/imximage.cfg create mode 100644 configs/colibri-imx8qxp_defconfig create mode 100644 include/configs/colibri-imx8qxp.h
From: Marcel Ziswiler marcel.ziswiler@toradex.com
Remove duplicate function declarations from the SCFW API header file.
Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com
---
arch/arm/include/asm/arch-imx8/sci/sci.h | 4 ---- 1 file changed, 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h index d1621669e2..97377697f0 100644 --- a/arch/arm/include/asm/arch-imx8/sci/sci.h +++ b/arch/arm/include/asm/arch-imx8/sci/sci.h @@ -62,10 +62,6 @@ int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); -int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, - sc_pm_clock_rate_t *rate); -int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, - sc_pm_clock_rate_t *rate); int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
-----Original Message----- From: Marcel Ziswiler [mailto:marcel@ziswiler.com] Sent: 2019年4月6日 20:47 To: u-boot@lists.denx.de Cc: Marcel Ziswiler marcel.ziswiler@toradex.com; Peng Fan peng.fan@nxp.com; Stefano Babic sbabic@denx.de; Fabio Estevam fabio.estevam@nxp.com; Anatolij Gustschin agust@denx.de; Albert Aribaud albert.u.boot@aribaud.net Subject: [EXT] [PATCH v1 1/5] misc: imx8: remove duplicates from scfw api
WARNING: This email was created outside of NXP. DO NOT CLICK links or attachments unless you recognize the sender and know the content is safe.
From: Marcel Ziswiler marcel.ziswiler@toradex.com
Remove duplicate function declarations from the SCFW API header file.
Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com
arch/arm/include/asm/arch-imx8/sci/sci.h | 4 ---- 1 file changed, 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h index d1621669e2..97377697f0 100644 --- a/arch/arm/include/asm/arch-imx8/sci/sci.h +++ b/arch/arm/include/asm/arch-imx8/sci/sci.h @@ -62,10 +62,6 @@ int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); -int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
sc_pm_clock_rate_t *rate);-int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
sc_pm_clock_rate_t *rate);int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
Reviewed-by: Peng Fan peng.fan@nxp.com
-- 2.20.1
Reviewed-by: Igor Opaniuk igor.opaniuk@toradex.com
On Sat, Apr 6, 2019 at 2:47 PM Marcel Ziswiler marcel@ziswiler.com wrote:
From: Marcel Ziswiler marcel.ziswiler@toradex.com
Remove duplicate function declarations from the SCFW API header file.
Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com
arch/arm/include/asm/arch-imx8/sci/sci.h | 4 ---- 1 file changed, 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h index d1621669e2..97377697f0 100644 --- a/arch/arm/include/asm/arch-imx8/sci/sci.h +++ b/arch/arm/include/asm/arch-imx8/sci/sci.h @@ -62,10 +62,6 @@ int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); -int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
sc_pm_clock_rate_t *rate);-int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
sc_pm_clock_rate_t *rate);int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
-- 2.20.1
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
From: Marcel Ziswiler marcel.ziswiler@toradex.com
Add support for lpuart1, lpuart2 and lpuart3.
Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com
---
arch/arm/dts/fsl-imx8dx.dtsi | 54 ++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+)
diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi index 3b1a2a20e3..715abb413d 100644 --- a/arch/arm/dts/fsl-imx8dx.dtsi +++ b/arch/arm/dts/fsl-imx8dx.dtsi @@ -236,6 +236,21 @@ power-domains = <&pd_dma>; wakeup-irq = <225>; }; + pd_dma_lpuart1: PD_DMA_UART1 { + reg = <SC_R_UART_1>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpuart2: PD_DMA_UART2 { + reg = <SC_R_UART_2>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpuart3: PD_DMA_UART3 { + reg = <SC_R_UART_3>; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; }; };
@@ -402,6 +417,45 @@ status = "disabled"; };
+ lpuart1: serial@5a070000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a070000 0x0 0x1000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_UART1_CLK>, + <&clk IMX8QXP_UART1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart1>; + status = "disabled"; + }; + + lpuart2: serial@5a080000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a080000 0x0 0x1000>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_UART2_CLK>, + <&clk IMX8QXP_UART2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART2_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart2>; + status = "disabled"; + }; + + lpuart3: serial@5a090000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a090000 0x0 0x1000>; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_UART3_CLK>, + <&clk IMX8QXP_UART3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART3_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart3>; + status = "disabled"; + }; + usdhc1: usdhc@5b010000 { compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; interrupt-parent = <&gic>;
-----Original Message----- From: Marcel Ziswiler [mailto:marcel@ziswiler.com] Sent: 2019年4月6日 20:47 To: u-boot@lists.denx.de Cc: Marcel Ziswiler marcel.ziswiler@toradex.com; Simon Glass sjg@chromium.org; Peng Fan peng.fan@nxp.com; Stefano Babic sbabic@denx.de; Fabio Estevam fabio.estevam@nxp.com; Tom Rini trini@konsulko.com; Anatolij Gustschin agust@denx.de; Albert Aribaud albert.u.boot@aribaud.net Subject: [EXT] [PATCH v1 2/5] arm: dts: imx8dx: add lpuart1, lpuart2, lpuart3
WARNING: This email was created outside of NXP. DO NOT CLICK links or attachments unless you recognize the sender and know the content is safe.
From: Marcel Ziswiler marcel.ziswiler@toradex.com
Add support for lpuart1, lpuart2 and lpuart3.
Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com
arch/arm/dts/fsl-imx8dx.dtsi | 54 ++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+)
diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi index 3b1a2a20e3..715abb413d 100644 --- a/arch/arm/dts/fsl-imx8dx.dtsi +++ b/arch/arm/dts/fsl-imx8dx.dtsi @@ -236,6 +236,21 @@ power-domains = <&pd_dma>; wakeup-irq = <225>; };
pd_dma_lpuart1: PD_DMA_UART1 {reg = <SC_R_UART_1>;#power-domain-cells = <0>;power-domains = <&pd_dma>;};pd_dma_lpuart2: PD_DMA_UART2 {reg = <SC_R_UART_2>;#power-domain-cells = <0>;power-domains = <&pd_dma>;};pd_dma_lpuart3: PD_DMA_UART3 {reg = <SC_R_UART_3>;#power-domain-cells = <0>;power-domains = <&pd_dma>;}; }; };@@ -402,6 +417,45 @@ status = "disabled"; };
lpuart1: serial@5a070000 {compatible = "fsl,imx8qm-lpuart";reg = <0x0 0x5a070000 0x0 0x1000>;interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8QXP_UART1_CLK>,<&clk IMX8QXP_UART1_IPG_CLK>;clock-names = "per", "ipg";assigned-clocks = <&clk IMX8QXP_UART1_CLK>;assigned-clock-rates = <80000000>;power-domains = <&pd_dma_lpuart1>;status = "disabled";};lpuart2: serial@5a080000 {compatible = "fsl,imx8qm-lpuart";reg = <0x0 0x5a080000 0x0 0x1000>;interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8QXP_UART2_CLK>,<&clk IMX8QXP_UART2_IPG_CLK>;clock-names = "per", "ipg";assigned-clocks = <&clk IMX8QXP_UART2_CLK>;assigned-clock-rates = <80000000>;power-domains = <&pd_dma_lpuart2>;status = "disabled";};lpuart3: serial@5a090000 {compatible = "fsl,imx8qm-lpuart";reg = <0x0 0x5a090000 0x0 0x1000>;interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8QXP_UART3_CLK>,<&clk IMX8QXP_UART3_IPG_CLK>;clock-names = "per", "ipg";assigned-clocks = <&clk IMX8QXP_UART3_CLK>;assigned-clock-rates = <80000000>;power-domains = <&pd_dma_lpuart3>;status = "disabled";};usdhc1: usdhc@5b010000 { compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; interrupt-parent = <&gic>;
Reviewed-by: Peng Fan peng.fan@nxp.com
-- 2.20.1
Reviewed-by: Igor Opaniuk igor.opaniuk@toradex.com
On Sat, Apr 6, 2019 at 2:48 PM Marcel Ziswiler marcel@ziswiler.com wrote:
From: Marcel Ziswiler marcel.ziswiler@toradex.com
Add support for lpuart1, lpuart2 and lpuart3.
Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com
arch/arm/dts/fsl-imx8dx.dtsi | 54 ++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+)
diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi index 3b1a2a20e3..715abb413d 100644 --- a/arch/arm/dts/fsl-imx8dx.dtsi +++ b/arch/arm/dts/fsl-imx8dx.dtsi @@ -236,6 +236,21 @@ power-domains = <&pd_dma>; wakeup-irq = <225>; };
pd_dma_lpuart1: PD_DMA_UART1 {reg = <SC_R_UART_1>;#power-domain-cells = <0>;power-domains = <&pd_dma>;};pd_dma_lpuart2: PD_DMA_UART2 {reg = <SC_R_UART_2>;#power-domain-cells = <0>;power-domains = <&pd_dma>;};pd_dma_lpuart3: PD_DMA_UART3 {reg = <SC_R_UART_3>;#power-domain-cells = <0>;power-domains = <&pd_dma>;}; }; };@@ -402,6 +417,45 @@ status = "disabled"; };
lpuart1: serial@5a070000 {compatible = "fsl,imx8qm-lpuart";reg = <0x0 0x5a070000 0x0 0x1000>;interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8QXP_UART1_CLK>,<&clk IMX8QXP_UART1_IPG_CLK>;clock-names = "per", "ipg";assigned-clocks = <&clk IMX8QXP_UART1_CLK>;assigned-clock-rates = <80000000>;power-domains = <&pd_dma_lpuart1>;status = "disabled";};lpuart2: serial@5a080000 {compatible = "fsl,imx8qm-lpuart";reg = <0x0 0x5a080000 0x0 0x1000>;interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8QXP_UART2_CLK>,<&clk IMX8QXP_UART2_IPG_CLK>;clock-names = "per", "ipg";assigned-clocks = <&clk IMX8QXP_UART2_CLK>;assigned-clock-rates = <80000000>;power-domains = <&pd_dma_lpuart2>;status = "disabled";};lpuart3: serial@5a090000 {compatible = "fsl,imx8qm-lpuart";reg = <0x0 0x5a090000 0x0 0x1000>;interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;clocks = <&clk IMX8QXP_UART3_CLK>,<&clk IMX8QXP_UART3_IPG_CLK>;clock-names = "per", "ipg";assigned-clocks = <&clk IMX8QXP_UART3_CLK>;assigned-clock-rates = <80000000>;power-domains = <&pd_dma_lpuart3>;status = "disabled";};usdhc1: usdhc@5b010000 { compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; interrupt-parent = <&gic>;-- 2.20.1
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
From: Marcel Ziswiler marcel.ziswiler@toradex.com
Clean-up handling of several SKUs.
Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com
---
board/toradex/common/tdx-cfg-block.c | 12 ++++++++---- board/toradex/common/tdx-cfg-block.h | 22 ++++++++++++---------- 2 files changed, 20 insertions(+), 14 deletions(-)
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 71ff40cfad..7e529afc7f 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -6,7 +6,9 @@ #include <common.h> #include "tdx-cfg-block.h"
-#if defined(CONFIG_TARGET_APALIS_IMX6) || defined(CONFIG_TARGET_COLIBRI_IMX6) +#if defined(CONFIG_TARGET_APALIS_IMX6) || \ + defined(CONFIG_TARGET_COLIBRI_IMX6) || \ + defined(CONFIG_TARGET_COLIBRI_IMX8QXP) #include <asm/arch/sys_proto.h> #else #define is_cpu_type(cpu) (0) @@ -92,10 +94,10 @@ const char * const toradex_modules[] = { [34] = "Apalis TK1 2GB", [35] = "Apalis iMX6 Dual 1GB IT", [36] = "Colibri iMX6ULL 256MB", - [37] = "Apalis iMX8 QuadMax 4GB Wi-Fi / Bluetooth", - [38] = "Colibri iMX8X", + [37] = "Apalis iMX8 QuadMax 4GB Wi-Fi / BT IT", + [38] = "Colibri iMX8 QuadXPlus 2GB Wi-Fi / BT IT", [39] = "Colibri iMX7 Dual 1GB (eMMC)", - [40] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth IT", + [40] = "Colibri iMX6ULL 512MB Wi-Fi / BT IT", [41] = "Colibri iMX7 Dual 512MB EPDC", [42] = "Apalis TK1 4GB", [43] = "Colibri T20 512MB IT SETEK", @@ -340,6 +342,8 @@ static int get_cfgblock_interactive(void) tdx_hw_tag.prodid = COLIBRI_IMX7D; else if (!strcmp("imx7s", soc)) tdx_hw_tag.prodid = COLIBRI_IMX7S; + else if (is_cpu_type(MXC_CPU_IMX8QXP)) + tdx_hw_tag.prodid = COLIBRI_IMX8QXP_WIFI_BT_IT; else if (!strcmp("tegra20", soc)) { if (it == 'y' || it == 'Y') if (gd->ram_size == 0x10000000) diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 961bb4394f..b20b522e1d 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -25,42 +25,44 @@ enum { COLIBRI_PXA270_V1_520MHZ, COLIBRI_PXA320, COLIBRI_PXA300, - COLIBRI_PXA310, + COLIBRI_PXA310, /* 5 */ COLIBRI_PXA320_IT, COLIBRI_PXA300_XT, COLIBRI_PXA270_312MHZ, COLIBRI_PXA270_520MHZ, - COLIBRI_VF50, /* not currently on sale */ - COLIBRI_VF61, + COLIBRI_VF50, /* 10 */ + COLIBRI_VF61, /* not currently on sale */ COLIBRI_VF61_IT, COLIBRI_VF50_IT, COLIBRI_IMX6S, - COLIBRI_IMX6DL, + COLIBRI_IMX6DL, /* 15 */ COLIBRI_IMX6S_IT, COLIBRI_IMX6DL_IT, + /* 18 */ + /* 19 */ COLIBRI_T20_256MB = 20, COLIBRI_T20_512MB, COLIBRI_T20_512MB_IT, COLIBRI_T30, COLIBRI_T20_256MB_IT, - APALIS_T30_2GB, + APALIS_T30_2GB, /* 25 */ APALIS_T30_1GB, APALIS_IMX6Q, APALIS_IMX6Q_IT, APALIS_IMX6D, - COLIBRI_T30_IT, + COLIBRI_T30_IT, /* 30 */ APALIS_T30_IT, COLIBRI_IMX7S, COLIBRI_IMX7D, APALIS_TK1_2GB, - APALIS_IMX6D_IT, + APALIS_IMX6D_IT, /* 35 */ COLIBRI_IMX6ULL, - APALIS_IMX8QM, /* 37 */ - COLIBRI_IMX8X, + APALIS_IMX8QM_WIFI_BT_IT, + COLIBRI_IMX8QXP_WIFI_BT_IT, COLIBRI_IMX7D_EMMC, COLIBRI_IMX6ULL_WIFI_BT_IT, /* 40 */ COLIBRI_IMX7D_EPDC, - APALIS_TK1_4GB, + APALIS_TK1_4GB, /* not currently on sale */ COLIBRI_T20_512MB_IT_SETEK, COLIBRI_IMX6ULL_IT, COLIBRI_IMX6ULL_WIFI_BT, /* 45 */
Reviewed-by: Igor Opaniuk igor.opaniuk@toradex.com
On Sat, Apr 6, 2019 at 2:47 PM Marcel Ziswiler marcel@ziswiler.com wrote:
From: Marcel Ziswiler marcel.ziswiler@toradex.com
Clean-up handling of several SKUs.
Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com
board/toradex/common/tdx-cfg-block.c | 12 ++++++++---- board/toradex/common/tdx-cfg-block.h | 22 ++++++++++++---------- 2 files changed, 20 insertions(+), 14 deletions(-)
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 71ff40cfad..7e529afc7f 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -6,7 +6,9 @@ #include <common.h> #include "tdx-cfg-block.h"
-#if defined(CONFIG_TARGET_APALIS_IMX6) || defined(CONFIG_TARGET_COLIBRI_IMX6) +#if defined(CONFIG_TARGET_APALIS_IMX6) || \
defined(CONFIG_TARGET_COLIBRI_IMX6) || \defined(CONFIG_TARGET_COLIBRI_IMX8QXP)#include <asm/arch/sys_proto.h> #else #define is_cpu_type(cpu) (0) @@ -92,10 +94,10 @@ const char * const toradex_modules[] = { [34] = "Apalis TK1 2GB", [35] = "Apalis iMX6 Dual 1GB IT", [36] = "Colibri iMX6ULL 256MB",
[37] = "Apalis iMX8 QuadMax 4GB Wi-Fi / Bluetooth",[38] = "Colibri iMX8X",
[37] = "Apalis iMX8 QuadMax 4GB Wi-Fi / BT IT",[38] = "Colibri iMX8 QuadXPlus 2GB Wi-Fi / BT IT", [39] = "Colibri iMX7 Dual 1GB (eMMC)",
[40] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth IT",
[40] = "Colibri iMX6ULL 512MB Wi-Fi / BT IT", [41] = "Colibri iMX7 Dual 512MB EPDC", [42] = "Apalis TK1 4GB", [43] = "Colibri T20 512MB IT SETEK",@@ -340,6 +342,8 @@ static int get_cfgblock_interactive(void) tdx_hw_tag.prodid = COLIBRI_IMX7D; else if (!strcmp("imx7s", soc)) tdx_hw_tag.prodid = COLIBRI_IMX7S;
else if (is_cpu_type(MXC_CPU_IMX8QXP))tdx_hw_tag.prodid = COLIBRI_IMX8QXP_WIFI_BT_IT; else if (!strcmp("tegra20", soc)) { if (it == 'y' || it == 'Y') if (gd->ram_size == 0x10000000)diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 961bb4394f..b20b522e1d 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -25,42 +25,44 @@ enum { COLIBRI_PXA270_V1_520MHZ, COLIBRI_PXA320, COLIBRI_PXA300,
COLIBRI_PXA310,
COLIBRI_PXA310, /* 5 */ COLIBRI_PXA320_IT, COLIBRI_PXA300_XT, COLIBRI_PXA270_312MHZ, COLIBRI_PXA270_520MHZ,
COLIBRI_VF50, /* not currently on sale */COLIBRI_VF61,
COLIBRI_VF50, /* 10 */COLIBRI_VF61, /* not currently on sale */ COLIBRI_VF61_IT, COLIBRI_VF50_IT, COLIBRI_IMX6S,
COLIBRI_IMX6DL,
COLIBRI_IMX6DL, /* 15 */ COLIBRI_IMX6S_IT, COLIBRI_IMX6DL_IT,/* 18 *//* 19 */ COLIBRI_T20_256MB = 20, COLIBRI_T20_512MB, COLIBRI_T20_512MB_IT, COLIBRI_T30, COLIBRI_T20_256MB_IT,
APALIS_T30_2GB,
APALIS_T30_2GB, /* 25 */ APALIS_T30_1GB, APALIS_IMX6Q, APALIS_IMX6Q_IT, APALIS_IMX6D,
COLIBRI_T30_IT,
COLIBRI_T30_IT, /* 30 */ APALIS_T30_IT, COLIBRI_IMX7S, COLIBRI_IMX7D, APALIS_TK1_2GB,
APALIS_IMX6D_IT,
APALIS_IMX6D_IT, /* 35 */ COLIBRI_IMX6ULL,
APALIS_IMX8QM, /* 37 */COLIBRI_IMX8X,
APALIS_IMX8QM_WIFI_BT_IT,COLIBRI_IMX8QXP_WIFI_BT_IT, COLIBRI_IMX7D_EMMC, COLIBRI_IMX6ULL_WIFI_BT_IT, /* 40 */ COLIBRI_IMX7D_EPDC,
APALIS_TK1_4GB,
APALIS_TK1_4GB, /* not currently on sale */ COLIBRI_T20_512MB_IT_SETEK, COLIBRI_IMX6ULL_IT, COLIBRI_IMX6ULL_WIFI_BT, /* 45 */-- 2.20.1
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
From: Marcel Ziswiler marcel.ziswiler@toradex.com
Add all the latest new SKUs: - Apalis iMX8 QuadXPlus 2GB Wi-Fi / BT IT - Apalis iMX8 QuadMax 4GB IT - Apalis iMX8 QuadPlus 2GB Wi-Fi / BT - Apalis iMX8 QuadPlus 2GB", - Colibri iMX8 QuadXPlus 2GB IT - Colibri iMX8 DualX 1GB Wi-Fi / Bluetooth - Colibri iMX8 DualX 1GB
Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com
---
board/toradex/common/tdx-cfg-block.c | 7 +++++++ board/toradex/common/tdx-cfg-block.h | 7 +++++++ 2 files changed, 14 insertions(+)
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 7e529afc7f..f69c4433b2 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -103,6 +103,13 @@ const char * const toradex_modules[] = { [43] = "Colibri T20 512MB IT SETEK", [44] = "Colibri iMX6ULL 512MB IT", [45] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth", + [46] = "Apalis iMX8 QuadXPlus 2GB Wi-Fi / BT IT", + [47] = "Apalis iMX8 QuadMax 4GB IT", + [48] = "Apalis iMX8 QuadPlus 2GB Wi-Fi / BT", + [49] = "Apalis iMX8 QuadPlus 2GB", + [50] = "Colibri iMX8 QuadXPlus 2GB IT", + [51] = "Colibri iMX8 DualX 1GB Wi-Fi / Bluetooth", + [52] = "Colibri iMX8 DualX 1GB", };
#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index b20b522e1d..bfdc8b7f70 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -66,6 +66,13 @@ enum { COLIBRI_T20_512MB_IT_SETEK, COLIBRI_IMX6ULL_IT, COLIBRI_IMX6ULL_WIFI_BT, /* 45 */ + APALIS_IMX8QXP_WIFI_BT_IT, + APALIS_IMX8QM_IT, + APALIS_IMX8QP_WIFI_BT, + APALIS_IMX8QP, + COLIBRI_IMX8QXP_IT, /* 50 */ + COLIBRI_IMX8DX_WIFI_BT, + COLIBRI_IMX8DX, };
extern const char * const toradex_modules[];
Reviewed-by: Igor Opaniuk igor.opaniuk@toradex.com
On Sat, Apr 6, 2019 at 2:48 PM Marcel Ziswiler marcel@ziswiler.com wrote:
From: Marcel Ziswiler marcel.ziswiler@toradex.com
Add all the latest new SKUs:
- Apalis iMX8 QuadXPlus 2GB Wi-Fi / BT IT
- Apalis iMX8 QuadMax 4GB IT
- Apalis iMX8 QuadPlus 2GB Wi-Fi / BT
- Apalis iMX8 QuadPlus 2GB",
- Colibri iMX8 QuadXPlus 2GB IT
- Colibri iMX8 DualX 1GB Wi-Fi / Bluetooth
- Colibri iMX8 DualX 1GB
Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com
board/toradex/common/tdx-cfg-block.c | 7 +++++++ board/toradex/common/tdx-cfg-block.h | 7 +++++++ 2 files changed, 14 insertions(+)
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 7e529afc7f..f69c4433b2 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -103,6 +103,13 @@ const char * const toradex_modules[] = { [43] = "Colibri T20 512MB IT SETEK", [44] = "Colibri iMX6ULL 512MB IT", [45] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth",
[46] = "Apalis iMX8 QuadXPlus 2GB Wi-Fi / BT IT",[47] = "Apalis iMX8 QuadMax 4GB IT",[48] = "Apalis iMX8 QuadPlus 2GB Wi-Fi / BT",[49] = "Apalis iMX8 QuadPlus 2GB",[50] = "Colibri iMX8 QuadXPlus 2GB IT",[51] = "Colibri iMX8 DualX 1GB Wi-Fi / Bluetooth",[52] = "Colibri iMX8 DualX 1GB",};
#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index b20b522e1d..bfdc8b7f70 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -66,6 +66,13 @@ enum { COLIBRI_T20_512MB_IT_SETEK, COLIBRI_IMX6ULL_IT, COLIBRI_IMX6ULL_WIFI_BT, /* 45 */
APALIS_IMX8QXP_WIFI_BT_IT,APALIS_IMX8QM_IT,APALIS_IMX8QP_WIFI_BT,APALIS_IMX8QP,COLIBRI_IMX8QXP_IT, /* 50 */COLIBRI_IMX8DX_WIFI_BT,COLIBRI_IMX8DX,};
extern const char * const toradex_modules[];
2.20.1
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
From: Marcel Ziswiler marcel.ziswiler@toradex.com
This commit adds initial support for the Toradex Colibri iMX8QXP 2GB WB IT V1.0B module. Unlike the V1.0A early access samples exclusively booting from SD card, they are now strapped to boot from eFuses which are factory fused to properly boot from their on-module eMMC. U-Boot supports either booting from the on-module eMMC or may be used for recovery purpose using the universal update utility (uuu) aka mfgtools 3.0.
Functionality wise the following is known to be working: - eMMC and MMC/SD card - Ethernet - GPIOs - I2C
Unfortunately, there is no USB functionality for the i.MX 8QXP as of yet.
Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com
---
arch/arm/dts/Makefile | 4 +- arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi | 112 ++++++ arch/arm/dts/fsl-imx8qxp-colibri.dts | 328 ++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 6 + board/toradex/colibri-imx8qxp/Kconfig | 30 ++ board/toradex/colibri-imx8qxp/MAINTAINERS | 9 + board/toradex/colibri-imx8qxp/Makefile | 7 + board/toradex/colibri-imx8qxp/README | 67 ++++ .../toradex/colibri-imx8qxp/colibri-imx8qxp.c | 211 +++++++++++ board/toradex/colibri-imx8qxp/imximage.cfg | 24 ++ configs/colibri-imx8qxp_defconfig | 53 +++ include/configs/colibri-imx8qxp.h | 240 +++++++++++++ 12 files changed, 1090 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri.dts create mode 100644 board/toradex/colibri-imx8qxp/Kconfig create mode 100644 board/toradex/colibri-imx8qxp/MAINTAINERS create mode 100644 board/toradex/colibri-imx8qxp/Makefile create mode 100644 board/toradex/colibri-imx8qxp/README create mode 100644 board/toradex/colibri-imx8qxp/colibri-imx8qxp.c create mode 100644 board/toradex/colibri-imx8qxp/imximage.cfg create mode 100644 configs/colibri-imx8qxp_defconfig create mode 100644 include/configs/colibri-imx8qxp.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d63b6874b5..fa0f28a84a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -562,7 +562,9 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
-dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb +dtb-$(CONFIG_ARCH_IMX8) += \ + fsl-imx8qxp-colibri.dtb \ + fsl-imx8qxp-mek.dtb
dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi new file mode 100644 index 0000000000..f8686befdf --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Toradex AG + */ + +&mu { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&pd_lsio { + u-boot,dm-spl; +}; + +&pd_lsio_gpio0 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio1 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio2 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio3 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio4 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio5 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio6 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio7 { + u-boot,dm-spl; +}; + +&pd_conn { + u-boot,dm-spl; +}; + +&pd_conn_sdch0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch1 { + u-boot,dm-spl; +}; + +&pd_conn_sdch2 { + u-boot,dm-spl; +}; + +&gpio0 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&gpio6 { + u-boot,dm-spl; +}; + +&gpio7 { + u-boot,dm-spl; +}; + +&lpuart3 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts b/arch/arm/dts/fsl-imx8qxp-colibri.dts new file mode 100644 index 0000000000..0c20edf2cf --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts @@ -0,0 +1,328 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Toradex AG + */ + +/dts-v1/; + +#include "fsl-imx8qxp.dtsi" +#include "fsl-imx8qxp-colibri-u-boot.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP"; + compatible = "toradex,colibri-imx8qxp", "fsl,imx8qxp"; + + chosen { + bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200"; + stdout-path = &lpuart3; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_reg>; + regulator-name = "usbh_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>; + + colibri-imx8qxp { + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 + SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 + >; + }; + + pinctrl_lpuart3_ctrl: lpuart3ctrlgrp { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 /* DTR */ + SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x00000020 /* CTS */ + SC_P_SAI1_RXC_LSIO_GPIO0_IO30 0x00000020 /* RTS */ + SC_P_CSI_RESET_LSIO_GPIO3_IO03 0x00000020 /* DSR */ + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000020 /* DCD */ + SC_P_CSI_EN_LSIO_GPIO3_IO02 0x00000020 /* RI */ + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 /* Use pads in 3.3V mode */ + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 /* Use pads in 3.3V mode */ + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x00000061 + >; + }; + + pinctrl_gpio_bl_on: gpio-bl-on { + fsl,pins = < + SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x00000040 + >; + }; + + pinctrl_hog0: hog0grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 /* Use pads in 3.3V mode */ + >; + }; + + pinctrl_hog1: hog1grp { + fsl,pins = < + SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x00000020 /* 45 */ + SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* 65 */ + SC_P_CSI_D07_CI_PI_D09 0x00000061 + SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x00000020 /* 69 */ + SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x00000020 /* 73 */ + SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x00000020 /* 79 */ + SC_P_CSI_D02_CI_PI_D04 0x00000061 + SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* 85 */ + SC_P_CSI_D06_CI_PI_D08 0x00000061 + SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x00000020 /* 95 */ + SC_P_SAI0_RXD_LSIO_GPIO0_IO27 0x00000020 /* 97 */ + SC_P_CSI_D03_CI_PI_D05 0x00000061 + SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x00000020 /* 99 */ + SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 0x00000020 /* 101 */ + SC_P_CSI_D00_CI_PI_D02 0x00000061 + SC_P_SAI0_TXD_LSIO_GPIO0_IO25 0x00000020 /* 103 */ + SC_P_CSI_D01_CI_PI_D03 0x00000061 + SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x00000020 /* 105 */ + SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x00000020 /* 107 */ + SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x00000020 /* 127 */ + SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x00000020 /* 131 */ + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000020 /* 133 */ + SC_P_CSI_PCLK_LSIO_GPIO3_IO00 0x00000020 /* 96 */ + SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x00000020 /* 98 */ + SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 0x00000020 /* 100 */ + SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 0x00000020 /* 102 */ + SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x00000020 /* 104 */ + SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x00000020 /* 106 */ + >; + }; + + pinctrl_hog2: hog2grp { + fsl,pins = < + SC_P_CSI_MCLK_LSIO_GPIO3_IO01 0x00000020 /* 75 */ + SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x00000020 /* 77 */ + SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x00000020 /* 89 */ + SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x00000020 /* 93 */ + >; + }; + + /* Off Module I2C */ + pinctrl_i2c1: i2c1grp { + fsl,pins = < + SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 + SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 + >; + }; + + /*INT*/ + pinctrl_usb3503a: usb3503a-grp { + fsl,pins = < + SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x00000061 + >; + }; + + pinctrl_usbc_det: usbc-det { + fsl,pins = < + SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040 + >; + }; + + pinctrl_usbh1_reg: usbh1-reg { + fsl,pins = < + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&fec1 { + phy-handle = <ðphy0>; + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + reg = <2>; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + status = "okay"; +}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index f76a139684..feea07f135 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -22,6 +22,11 @@ choice prompt "i.MX8 board select" optional
+config TARGET_COLIBRI_IMX8QXP + bool "Support Colibri iMX8QXP module" + select BOARD_LATE_INIT + select IMX8QXP + config TARGET_IMX8QXP_MEK bool "Support i.MX8QXP MEK board" select BOARD_LATE_INIT @@ -30,5 +35,6 @@ config TARGET_IMX8QXP_MEK endchoice
source "board/freescale/imx8qxp_mek/Kconfig" +source "board/toradex/colibri-imx8qxp/Kconfig"
endif diff --git a/board/toradex/colibri-imx8qxp/Kconfig b/board/toradex/colibri-imx8qxp/Kconfig new file mode 100644 index 0000000000..340fe72816 --- /dev/null +++ b/board/toradex/colibri-imx8qxp/Kconfig @@ -0,0 +1,30 @@ +if TARGET_COLIBRI_IMX8QXP + +config SYS_BOARD + default "colibri-imx8qxp" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "colibri-imx8qxp" + +config TDX_CFG_BLOCK + default y + +config TDX_HAVE_MMC + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +config TDX_CFG_BLOCK_PART + default "1" + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +source "board/toradex/common/Kconfig" + +endif diff --git a/board/toradex/colibri-imx8qxp/MAINTAINERS b/board/toradex/colibri-imx8qxp/MAINTAINERS new file mode 100644 index 0000000000..39a9eb79b7 --- /dev/null +++ b/board/toradex/colibri-imx8qxp/MAINTAINERS @@ -0,0 +1,9 @@ +Colibri iMX8QXP +M: Marcel Ziswiler marcel.ziswiler@toradex.com +W: http://developer.toradex.com/software/linux/linux-software +S: Maintained +F: arch/arm/dts/fsl-imx8qxp-colibri.dts +F: arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi +F: board/toradex/colibri-imx8qxp/ +F: configs/colibri-imx8qxp_defconfig +F: include/configs/colibri-imx8qxp.h diff --git a/board/toradex/colibri-imx8qxp/Makefile b/board/toradex/colibri-imx8qxp/Makefile new file mode 100644 index 0000000000..f6342e1dca --- /dev/null +++ b/board/toradex/colibri-imx8qxp/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2019 Toradex +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += colibri-imx8qxp.o diff --git a/board/toradex/colibri-imx8qxp/README b/board/toradex/colibri-imx8qxp/README new file mode 100644 index 0000000000..70fd4f75a7 --- /dev/null +++ b/board/toradex/colibri-imx8qxp/README @@ -0,0 +1,67 @@ +U-Boot for the Toradex Colibri iMX8QXP V1.0B module + +Quick Start +=========== + +- Build the ARM trusted firmware binary +- Get scfw_tcm.bin and ahab-container.img +- Build U-Boot +- Load U-Boot binary using uuu +- Flash U-Boot binary into the eMMC +- Boot + +Get and Build the ARM Trusted Firmware +====================================== + +$ git clone https://source.codeaurora.org/external/imx/imx-atf +$ cd imx-atf/ +$ git checkout -b imx_4.14.78_1.0.0_ga origin/imx_4.14.78_1.0.0_ga +$ make PLAT=imx8qxp bl31 + +Get scfw_tcm.bin and ahab-container.img +======================================= + +$ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.... +$ mv mx8qx-colibri-scfw-tcm.bin?raw=true mx8qx-colibri-scfw-tcm.bin +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.6.bin +$ chmod +x firmware-imx-7.6.bin +$ ./firmware-imx-7.6.bin + +Copy the following binaries to the U-Boot folder: + +$ cp imx-atf/build/imx8qxp/release/bl31.bin . +$ cp u-boot/u-boot.bin . + +Copy the following firmware to the U-Boot folder: + +$ cp firmware-imx-7.6/firmware/seco/ahab-container.img . + +Build U-Boot +============ + +$ make colibri-imx8qxp_defconfig +$ make u-boot-dtb.imx + +Load the U-Boot Binary Using UUU +================================ + +Get the latest version of the universal update utility (uuu) aka mfgtools 3.0: + +https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2F... + +Put the module into USB recovery aka serial downloader mode, connect USB device +to your host and execute uuu: + +sudo ./uuu u-boot/u-boot-dtb.imx + +Flash the U-Boot Binary into the eMMC +===================================== + +Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot area partition: + +load mmc 1:1 $loadaddr u-boot-dtb.imx +setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200 +mmc dev 0 1 +mmc write ${loadaddr} 0x0 ${blkcnt} + +Boot diff --git a/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c new file mode 100644 index 0000000000..98c389c6f7 --- /dev/null +++ b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Toradex + */ +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <netdev.h> +#include <fsl_ifc.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <environment.h> +#include <fsl_esdhc.h> +#include <i2c.h> + +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <dm.h> +#include <usb.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/video.h> +#include <power-domain.h> + +#include "../common/tdx-cfg-block.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart3_pads[] = { + SC_P_FLEXCAN2_RX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_FLEXCAN2_TX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL), + /* Transceiver FORCEOFF# signal, mux to use pullup */ + SC_P_QSPI0B_DQS | MUX_MODE_ALT(4) | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); +} + +int board_early_init_f(void) +{ + sc_pm_clock_rate_t rate; + sc_err_t err = 0; + + /* + * This works around that having only UART3 up the baudrate is 1.2M + * instead of 115.2k. Set UART0 clock root to 80 MHz + */ + rate = 80000000; + err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate); + if (err != SC_ERR_NONE) + return 0; + + /* Power up UART3 */ + err = sc_pm_set_resource_power_mode(-1, SC_R_UART_3, SC_PM_PW_MODE_ON); + if (err != SC_ERR_NONE) + return 0; + + /* Set UART3 clock root to 80 MHz */ + rate = 80000000; + err = sc_pm_set_clock_rate(-1, SC_R_UART_3, SC_PM_CLK_PER, &rate); + if (err != SC_ERR_NONE) + return 0; + + /* Enable UART3 clock root */ + err = sc_pm_clock_enable(-1, SC_R_UART_3, SC_PM_CLK_PER, true, false); + if (err != SC_ERR_NONE) + return 0; + + setup_iomux_uart(); + + return 0; +} + +#undef CONFIG_MXC_GPIO /* TODO */ +#ifdef CONFIG_MXC_GPIO +#define IOEXP_RESET IMX_GPIO_NR(1, 1) + +static iomux_cfg_t board_gpios[] = { + SC_P_SPI2_SDO | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | \ + MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +static void board_gpio_init(void) +{ + struct gpio_desc desc; + int ret; + + ret = dm_gpio_lookup_name("gpio@1a_3", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "bb_per_rst_b"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 0); + udelay(50); + dm_gpio_set_value(&desc, 1); + + imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios)); + + /* enable i2c port expander assert reset line */ + gpio_request(IOEXP_RESET, "ioexp_rst"); + gpio_direction_output(IOEXP_RESET, 1); +} +#else +static inline void board_gpio_init(void) {} +#endif + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include <miiphy.h> + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +void build_info(void) +{ + u32 sc_build = 0, sc_commit = 0; + + /* Get SCFW build and commit id */ + sc_misc_build_info(-1, &sc_build, &sc_commit); + if (!sc_build) { + printf("SCFW does not support build info\n"); + sc_commit = 0; /* Display 0 if build info not supported */ + } + printf("Build: SCFW %x\n", sc_commit); +} + +int checkboard(void) +{ + puts("Model: Toradex Colibri iMX8X\n"); + + build_info(); + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ + board_gpio_init(); + + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + /* TODO */ +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +/* TODO move to common */ + env_set("board_name", "Colibri iMX8QXP"); + env_set("board_rev", "v1.0"); +#endif + + return 0; +} diff --git a/board/toradex/colibri-imx8qxp/imximage.cfg b/board/toradex/colibri-imx8qxp/imximage.cfg new file mode 100644 index 0000000000..ce9e66c64d --- /dev/null +++ b/board/toradex/colibri-imx8qxp/imximage.cfg @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Toradex + * + * Refer doc/README.imx8image for more details about how-to configure + * and create imx8image boot image + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM EMMC_FASTBOOT 0x400 +/* SoC type IMX8QX */ +SOC_TYPE IMX8QX +/* Append seco container image */ +APPEND ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qx-colibri-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 bl31.bin 0x80000000 +/* Add U-Boot image with load attribute */ +DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/configs/colibri-imx8qxp_defconfig b/configs/colibri-imx8qxp_defconfig new file mode 100644 index 0000000000..d697546ed7 --- /dev/null +++ b/configs/colibri-imx8qxp_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_COLIBRI_IMX8QXP=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx8qxp/imximage.cfg" +CONFIG_LOG=y +CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_UUID=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_DM_THERMAL=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/colibri-imx8qxp.h b/include/configs/colibri-imx8qxp.h new file mode 100644 index 0000000000..fe0da35cf5 --- /dev/null +++ b/include/configs/colibri-imx8qxp.h @@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Toradex + */ + +#ifndef __COLIBRI_IMX8QXP_H +#define __COLIBRI_IMX8QXP_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_TEXT_BASE 0x0 +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x250 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x013E000 +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_MALLOC_F_ADDR 0x00120000 + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#define CONFIG_OF_EMBED +#endif /* CONFIG_SPL_BUILD */ + +#define CONFIG_REMAKE_ELF + +#define CONFIG_DISPLAY_BOARDINFO_LATE + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_IP_DEFRAG +#define CONFIG_TFTP_BLOCKSIZE 4096 +#define CONFIG_TFTP_TSIZE + +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.10.1 + +#define MEM_LAYOUT_ENV_SETTINGS \ + "fdt_addr_r=0x84000000\0" \ + "kernel_addr_r=0x82000000\0" \ + "ramdisk_addr_r=0x84100000\0" + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${m4_0_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + +#define MFG_NAND_PARTITION "" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(DHCP, dhcp, na) +#include <config_distro_bootcmd.h> +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START "" + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc g_mass_storage.stall=0 " \ + "g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \ + "g_mass_storage.idProduct=0x37FF " \ + "g_mass_storage.iSerialNumber="" "\ + MFG_NAND_PARTITION \ + "video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off " \ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \ + "${fdt_addr};\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + AHAB_ENV \ + BOOTENV \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + MEM_LAYOUT_ENV_SETTINGS \ + "boot_fdt=try\0" \ + "bootscript=echo Running bootscript from mmc ...; source\0" \ + "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_file=fsl-imx8qxp-colibri-eval-v3.dtb\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "image=Image\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${script};\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=PARTUUID=${uuid} rootwait " \ + "mmcautodetect=yes\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run finduuid; run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \ + "nfsroot=${serverip}:${nfsroot},v3,tcp video=imxdpufb5:off " \ + "video=imxdpufb6:off video=imxdpufb7:off\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" \ + "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \ + "colibri-imx8qxp/${fdt_file}; booti ${loadaddr} - " \ + "${fdt_addr}\0" \ + "panel=NULL\0" \ + "script=boot.scr\0" \ + "video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +#define CONFIG_SYS_MEMTEST_START 0x88000000 +#define CONFIG_SYS_MEMTEST_END 0x89000000 + +/* Environment in eMMC, before config block at the end of 1st "boot sector" */ +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ + CONFIG_TDX_CFG_BLOCK_OFFSET) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 1 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On Colibri iMX8 USDHC1 is eMMC, USDHC2 is 4-bit SD */ +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 eMMC */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_NR_DRAM_BANKS 3 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#define BOOTAUX_RESERVED_MEM_BASE 0x88000000 +#define BOOTAUX_RESERVED_MEM_SIZE 0x08000000 /* Reserve from second 128MB */ + +#endif /* __COLIBRI_IMX8QXP_H */
Hi Marcel,
Just a couple of comments below after a brief look:
On Sat, Apr 6, 2019 at 2:49 PM Marcel Ziswiler marcel@ziswiler.com wrote:
From: Marcel Ziswiler marcel.ziswiler@toradex.com
This commit adds initial support for the Toradex Colibri iMX8QXP 2GB WB IT V1.0B module. Unlike the V1.0A early access samples exclusively booting from SD card, they are now strapped to boot from eFuses which are factory fused to properly boot from their on-module eMMC. U-Boot supports either booting from the on-module eMMC or may be used for recovery purpose using the universal update utility (uuu) aka mfgtools 3.0.
Functionality wise the following is known to be working:
- eMMC and MMC/SD card
- Ethernet
- GPIOs
- I2C
Unfortunately, there is no USB functionality for the i.MX 8QXP as of yet.
Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com
arch/arm/dts/Makefile | 4 +- arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi | 112 ++++++ arch/arm/dts/fsl-imx8qxp-colibri.dts | 328 ++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 6 + board/toradex/colibri-imx8qxp/Kconfig | 30 ++ board/toradex/colibri-imx8qxp/MAINTAINERS | 9 + board/toradex/colibri-imx8qxp/Makefile | 7 + board/toradex/colibri-imx8qxp/README | 67 ++++ .../toradex/colibri-imx8qxp/colibri-imx8qxp.c | 211 +++++++++++ board/toradex/colibri-imx8qxp/imximage.cfg | 24 ++ configs/colibri-imx8qxp_defconfig | 53 +++ include/configs/colibri-imx8qxp.h | 240 +++++++++++++ 12 files changed, 1090 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri.dts create mode 100644 board/toradex/colibri-imx8qxp/Kconfig create mode 100644 board/toradex/colibri-imx8qxp/MAINTAINERS create mode 100644 board/toradex/colibri-imx8qxp/Makefile create mode 100644 board/toradex/colibri-imx8qxp/README create mode 100644 board/toradex/colibri-imx8qxp/colibri-imx8qxp.c create mode 100644 board/toradex/colibri-imx8qxp/imximage.cfg create mode 100644 configs/colibri-imx8qxp_defconfig create mode 100644 include/configs/colibri-imx8qxp.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d63b6874b5..fa0f28a84a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -562,7 +562,9 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
-dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb +dtb-$(CONFIG_ARCH_IMX8) += \
fsl-imx8qxp-colibri.dtb \fsl-imx8qxp-mek.dtbdtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi new file mode 100644 index 0000000000..f8686befdf --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- Copyright 2019 Toradex AG
- */
+&mu {
u-boot,dm-spl;+};
+&clk {
u-boot,dm-spl;+};
+&iomuxc {
u-boot,dm-spl;+};
+&pd_lsio {
u-boot,dm-spl;+};
+&pd_lsio_gpio0 {
u-boot,dm-spl;+};
+&pd_lsio_gpio1 {
u-boot,dm-spl;+};
+&pd_lsio_gpio2 {
u-boot,dm-spl;+};
+&pd_lsio_gpio3 {
u-boot,dm-spl;+};
+&pd_lsio_gpio4 {
u-boot,dm-spl;+};
+&pd_lsio_gpio5 {
u-boot,dm-spl;+};
+&pd_lsio_gpio6 {
u-boot,dm-spl;+};
+&pd_lsio_gpio7 {
u-boot,dm-spl;+};
+&pd_conn {
u-boot,dm-spl;+};
+&pd_conn_sdch0 {
u-boot,dm-spl;+};
+&pd_conn_sdch1 {
u-boot,dm-spl;+};
+&pd_conn_sdch2 {
u-boot,dm-spl;+};
+&gpio0 {
u-boot,dm-spl;+};
+&gpio1 {
u-boot,dm-spl;+};
+&gpio2 {
u-boot,dm-spl;+};
+&gpio3 {
u-boot,dm-spl;+};
+&gpio4 {
u-boot,dm-spl;+};
+&gpio5 {
u-boot,dm-spl;+};
+&gpio6 {
u-boot,dm-spl;+};
+&gpio7 {
u-boot,dm-spl;+};
+&lpuart3 {
u-boot,dm-spl;+};
+&usdhc1 {
u-boot,dm-spl;+};
+&usdhc2 {
u-boot,dm-spl;+}; diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts b/arch/arm/dts/fsl-imx8qxp-colibri.dts new file mode 100644 index 0000000000..0c20edf2cf --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts @@ -0,0 +1,328 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- Copyright 2019 Toradex AG
- */
+/dts-v1/;
+#include "fsl-imx8qxp.dtsi" +#include "fsl-imx8qxp-colibri-u-boot.dtsi"
+/ {
model = "Toradex Colibri iMX8QXP";compatible = "toradex,colibri-imx8qxp", "fsl,imx8qxp";chosen {bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200";stdout-path = &lpuart3;};reg_usbh_vbus: regulator-usbh-vbus {compatible = "regulator-fixed";pinctrl-names = "default";pinctrl-0 = <&pinctrl_usbh1_reg>;regulator-name = "usbh_vbus";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;};+};
+&iomuxc {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>;colibri-imx8qxp {pinctrl_lpuart0: lpuart0grp {fsl,pins = <SC_P_UART0_RX_ADMA_UART0_RX 0x06000020SC_P_UART0_TX_ADMA_UART0_TX 0x06000020>;};pinctrl_lpuart3: lpuart3grp {fsl,pins = <SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020>;};pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {fsl,pins = <SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 /* DTR */SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x00000020 /* CTS */SC_P_SAI1_RXC_LSIO_GPIO0_IO30 0x00000020 /* RTS */SC_P_CSI_RESET_LSIO_GPIO3_IO03 0x00000020 /* DSR */SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000020 /* DCD */SC_P_CSI_EN_LSIO_GPIO3_IO02 0x00000020 /* RI */>;};pinctrl_fec1: fec1grp {fsl,pins = <SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 /* Use pads in 3.3V mode */SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 /* Use pads in 3.3V mode */SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x00000061>;};pinctrl_gpio_bl_on: gpio-bl-on {fsl,pins = <SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x00000040>;};pinctrl_hog0: hog0grp {fsl,pins = <SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 /* Use pads in 3.3V mode */>;};pinctrl_hog1: hog1grp {fsl,pins = <SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x00000020 /* 45 */SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* 65 */SC_P_CSI_D07_CI_PI_D09 0x00000061SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x00000020 /* 69 */SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x00000020 /* 73 */SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x00000020 /* 79 */SC_P_CSI_D02_CI_PI_D04 0x00000061SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* 85 */SC_P_CSI_D06_CI_PI_D08 0x00000061SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x00000020 /* 95 */SC_P_SAI0_RXD_LSIO_GPIO0_IO27 0x00000020 /* 97 */SC_P_CSI_D03_CI_PI_D05 0x00000061SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x00000020 /* 99 */SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 0x00000020 /* 101 */SC_P_CSI_D00_CI_PI_D02 0x00000061SC_P_SAI0_TXD_LSIO_GPIO0_IO25 0x00000020 /* 103 */SC_P_CSI_D01_CI_PI_D03 0x00000061SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x00000020 /* 105 */SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x00000020 /* 107 */SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x00000020 /* 127 */SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x00000020 /* 131 */SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000020 /* 133 */SC_P_CSI_PCLK_LSIO_GPIO3_IO00 0x00000020 /* 96 */SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x00000020 /* 98 */SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 0x00000020 /* 100 */SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 0x00000020 /* 102 */SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x00000020 /* 104 */SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x00000020 /* 106 */>;};pinctrl_hog2: hog2grp {fsl,pins = <SC_P_CSI_MCLK_LSIO_GPIO3_IO01 0x00000020 /* 75 */SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x00000020 /* 77 */SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x00000020 /* 89 */SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x00000020 /* 93 */>;};/* Off Module I2C */pinctrl_i2c1: i2c1grp {fsl,pins = <SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021>;};/*INT*/pinctrl_usb3503a: usb3503a-grp {fsl,pins = <SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x00000061>;};pinctrl_usbc_det: usbc-det {fsl,pins = <SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040>;};pinctrl_usbh1_reg: usbh1-reg {fsl,pins = <SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040>;};pinctrl_usdhc1: usdhc1grp {fsl,pins = <SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021>;};pinctrl_usdhc1_100mhz: usdhc1grp100mhz {fsl,pins = <SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021>;};pinctrl_usdhc1_200mhz: usdhc1grp200mhz {fsl,pins = <SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021>;};pinctrl_usdhc2_gpio: usdhc2gpiogrp {fsl,pins = <SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021>;};pinctrl_usdhc2: usdhc2grp {fsl,pins = <SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>;};pinctrl_usdhc2_100mhz: usdhc2grp100mhz {fsl,pins = <SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>;};pinctrl_usdhc2_200mhz: usdhc2grp200mhz {fsl,pins = <SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>;};};+};
+&lpuart0 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_lpuart0>;status = "okay";+};
+&lpuart3 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;status = "okay";+};
+&gpio0 {
status = "okay";+};
+&gpio1 {
status = "okay";+};
+&gpio3 {
status = "okay";+};
+&gpio4 {
status = "okay";+};
+&fec1 {
phy-handle = <ðphy0>;phy-mode = "rmii";pinctrl-names = "default";pinctrl-0 = <&pinctrl_fec1>;status = "okay";mdio {#address-cells = <1>;#size-cells = <0>;ethphy0: ethernet-phy@2 {compatible = "ethernet-phy-ieee802.3-c22";max-speed = <100>;reg = <2>;};};+};
+&i2c1 {
#address-cells = <1>;#size-cells = <0>;clock-frequency = <100000>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_i2c1>;status = "okay";+};
+&usdhc1 {
bus-width = <8>;non-removable;pinctrl-names = "default", "state_100mhz", "state_200mhz";pinctrl-0 = <&pinctrl_usdhc1>;pinctrl-1 = <&pinctrl_usdhc1_100mhz>;pinctrl-2 = <&pinctrl_usdhc1_200mhz>;status = "okay";+};
+&usdhc2 {
bus-width = <4>;cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;pinctrl-names = "default", "state_100mhz", "state_200mhz";pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;status = "okay";+}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index f76a139684..feea07f135 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -22,6 +22,11 @@ choice prompt "i.MX8 board select" optional
+config TARGET_COLIBRI_IMX8QXP
bool "Support Colibri iMX8QXP module"select BOARD_LATE_INITselect IMX8QXPconfig TARGET_IMX8QXP_MEK bool "Support i.MX8QXP MEK board" select BOARD_LATE_INIT @@ -30,5 +35,6 @@ config TARGET_IMX8QXP_MEK endchoice
source "board/freescale/imx8qxp_mek/Kconfig" +source "board/toradex/colibri-imx8qxp/Kconfig"
endif diff --git a/board/toradex/colibri-imx8qxp/Kconfig b/board/toradex/colibri-imx8qxp/Kconfig new file mode 100644 index 0000000000..340fe72816 --- /dev/null +++ b/board/toradex/colibri-imx8qxp/Kconfig @@ -0,0 +1,30 @@ +if TARGET_COLIBRI_IMX8QXP
+config SYS_BOARD
default "colibri-imx8qxp"+config SYS_VENDOR
default "toradex"+config SYS_CONFIG_NAME
default "colibri-imx8qxp"+config TDX_CFG_BLOCK
default y+config TDX_HAVE_MMC
default y+config TDX_CFG_BLOCK_DEV
default "0"+config TDX_CFG_BLOCK_PART
default "1"+# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET
default "-512"+source "board/toradex/common/Kconfig"
+endif diff --git a/board/toradex/colibri-imx8qxp/MAINTAINERS b/board/toradex/colibri-imx8qxp/MAINTAINERS new file mode 100644 index 0000000000..39a9eb79b7 --- /dev/null +++ b/board/toradex/colibri-imx8qxp/MAINTAINERS @@ -0,0 +1,9 @@ +Colibri iMX8QXP +M: Marcel Ziswiler marcel.ziswiler@toradex.com +W: http://developer.toradex.com/software/linux/linux-software +S: Maintained +F: arch/arm/dts/fsl-imx8qxp-colibri.dts +F: arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi +F: board/toradex/colibri-imx8qxp/ +F: configs/colibri-imx8qxp_defconfig +F: include/configs/colibri-imx8qxp.h diff --git a/board/toradex/colibri-imx8qxp/Makefile b/board/toradex/colibri-imx8qxp/Makefile new file mode 100644 index 0000000000..f6342e1dca --- /dev/null +++ b/board/toradex/colibri-imx8qxp/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2019 Toradex +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y += colibri-imx8qxp.o diff --git a/board/toradex/colibri-imx8qxp/README b/board/toradex/colibri-imx8qxp/README new file mode 100644 index 0000000000..70fd4f75a7 --- /dev/null +++ b/board/toradex/colibri-imx8qxp/README @@ -0,0 +1,67 @@ +U-Boot for the Toradex Colibri iMX8QXP V1.0B module
+Quick Start +===========
+- Build the ARM trusted firmware binary +- Get scfw_tcm.bin and ahab-container.img +- Build U-Boot +- Load U-Boot binary using uuu +- Flash U-Boot binary into the eMMC +- Boot
+Get and Build the ARM Trusted Firmware +======================================
+$ git clone https://source.codeaurora.org/external/imx/imx-atf
Just FYI: $ git clone https://source.codeaurora.org/external/imx/imx-atf imx-atf.git Cloning into 'imx-atf.git'... remote: Counting objects: 57255, done. remote: Compressing objects: 100% (1076/1076), done. remote: Total 57255 (delta 677), reused 594 (delta 247) Receiving objects: 100% (57255/57255), 12.00 MiB | 6.40 MiB/s, done. Resolving deltas: 100% (38758/38758), done. warning: remote HEAD refers to nonexistent ref, unable to checkout.
+$ cd imx-atf/ +$ git checkout -b imx_4.14.78_1.0.0_ga origin/imx_4.14.78_1.0.0_ga +$ make PLAT=imx8qxp bl31
+Get scfw_tcm.bin and ahab-container.img +=======================================
+$ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.... +$ mv mx8qx-colibri-scfw-tcm.bin?raw=true mx8qx-colibri-scfw-tcm.bin +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.6.bin +$ chmod +x firmware-imx-7.6.bin +$ ./firmware-imx-7.6.bin
+Copy the following binaries to the U-Boot folder:
+$ cp imx-atf/build/imx8qxp/release/bl31.bin . +$ cp u-boot/u-boot.bin .
+Copy the following firmware to the U-Boot folder:
+$ cp firmware-imx-7.6/firmware/seco/ahab-container.img .
+Build U-Boot +============
+$ make colibri-imx8qxp_defconfig +$ make u-boot-dtb.imx
+Load the U-Boot Binary Using UUU +================================
+Get the latest version of the universal update utility (uuu) aka mfgtools 3.0:
+https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2F...
+Put the module into USB recovery aka serial downloader mode, connect USB device +to your host and execute uuu:
+sudo ./uuu u-boot/u-boot-dtb.imx
+Flash the U-Boot Binary into the eMMC +=====================================
+Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot area partition:
Maybe it's better to say flash (just to avoid confusion)? I personally perceive burn as something that is written to OTP.
+load mmc 1:1 $loadaddr u-boot-dtb.imx +setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200 +mmc dev 0 1 +mmc write ${loadaddr} 0x0 ${blkcnt}
+Boot diff --git a/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c new file mode 100644 index 0000000000..98c389c6f7 --- /dev/null +++ b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright 2019 Toradex
- */
+#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <netdev.h> +#include <fsl_ifc.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <environment.h> +#include <fsl_esdhc.h> +#include <i2c.h>
Includes in alphabetical order would be nicer (to simplify detecting duplicate include files and finding the right place for adding new ones.)
+#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <dm.h> +#include <usb.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/video.h> +#include <power-domain.h>
+#include "../common/tdx-cfg-block.h"
+DECLARE_GLOBAL_DATA_PTR;
+#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))+#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))+static iomux_cfg_t uart3_pads[] = {
SC_P_FLEXCAN2_RX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),SC_P_FLEXCAN2_TX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),/* Transceiver FORCEOFF# signal, mux to use pullup */SC_P_QSPI0B_DQS | MUX_MODE_ALT(4) | MUX_PAD_CTRL(UART_PAD_CTRL),+};
+static void setup_iomux_uart(void) +{
imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));+}
+int board_early_init_f(void) +{
sc_pm_clock_rate_t rate;sc_err_t err = 0;/** This works around that having only UART3 up the baudrate is 1.2M* instead of 115.2k. Set UART0 clock root to 80 MHz*/rate = 80000000;err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate);if (err != SC_ERR_NONE)return 0;/* Power up UART3 */err = sc_pm_set_resource_power_mode(-1, SC_R_UART_3, SC_PM_PW_MODE_ON);if (err != SC_ERR_NONE)return 0;/* Set UART3 clock root to 80 MHz */rate = 80000000;err = sc_pm_set_clock_rate(-1, SC_R_UART_3, SC_PM_CLK_PER, &rate);if (err != SC_ERR_NONE)return 0;/* Enable UART3 clock root */err = sc_pm_clock_enable(-1, SC_R_UART_3, SC_PM_CLK_PER, true, false);if (err != SC_ERR_NONE)return 0;setup_iomux_uart();return 0;+}
+#undef CONFIG_MXC_GPIO /* TODO */ +#ifdef CONFIG_MXC_GPIO +#define IOEXP_RESET IMX_GPIO_NR(1, 1)
+static iomux_cfg_t board_gpios[] = {
SC_P_SPI2_SDO | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | \MUX_PAD_CTRL(GPIO_PAD_CTRL),+};
+static void board_gpio_init(void) +{
struct gpio_desc desc;int ret;ret = dm_gpio_lookup_name("gpio@1a_3", &desc);if (ret)return;ret = dm_gpio_request(&desc, "bb_per_rst_b");if (ret)return;dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);dm_gpio_set_value(&desc, 0);udelay(50);dm_gpio_set_value(&desc, 1);imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios));/* enable i2c port expander assert reset line */gpio_request(IOEXP_RESET, "ioexp_rst");gpio_direction_output(IOEXP_RESET, 1);+} +#else +static inline void board_gpio_init(void) {} +#endif
+#if IS_ENABLED(CONFIG_FEC_MXC) +#include <miiphy.h>
+int board_phy_config(struct phy_device *phydev) +{
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);if (phydev->drv->config)phydev->drv->config(phydev);return 0;+} +#endif
+void build_info(void) +{
u32 sc_build = 0, sc_commit = 0;/* Get SCFW build and commit id */sc_misc_build_info(-1, &sc_build, &sc_commit);if (!sc_build) {printf("SCFW does not support build info\n");sc_commit = 0; /* Display 0 if build info not supported */}printf("Build: SCFW %x\n", sc_commit);+}
+int checkboard(void) +{
puts("Model: Toradex Colibri iMX8X\n");build_info();print_bootinfo();return 0;+}
+int board_init(void) +{
board_gpio_init();return 0;+}
+void detail_board_ddr_info(void) +{
puts("\nDDR ");+}
+/*
- Board specific reset that is system reset.
- */
+void reset_cpu(ulong addr) +{
/* TODO */+}
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{
return ft_common_board_setup(blob, bd);+} +#endif
+int board_mmc_get_env_dev(int devno) +{
return devno;+}
+int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +/* TODO move to common */
env_set("board_name", "Colibri iMX8QXP");env_set("board_rev", "v1.0");+#endif
return 0;+} diff --git a/board/toradex/colibri-imx8qxp/imximage.cfg b/board/toradex/colibri-imx8qxp/imximage.cfg new file mode 100644 index 0000000000..ce9e66c64d --- /dev/null +++ b/board/toradex/colibri-imx8qxp/imximage.cfg @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright 2019 Toradex
- Refer doc/README.imx8image for more details about how-to configure
- and create imx8image boot image
- */
+#define __ASSEMBLY__
+/* Boot from SD, sector size 0x400 */ +BOOT_FROM EMMC_FASTBOOT 0x400 +/* SoC type IMX8QX */ +SOC_TYPE IMX8QX +/* Append seco container image */ +APPEND ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qx-colibri-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 bl31.bin 0x80000000 +/* Add U-Boot image with load attribute */ +DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/configs/colibri-imx8qxp_defconfig b/configs/colibri-imx8qxp_defconfig new file mode 100644 index 0000000000..d697546ed7 --- /dev/null +++ b/configs/colibri-imx8qxp_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_COLIBRI_IMX8QXP=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx8qxp/imximage.cfg" +CONFIG_LOG=y +CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_UUID=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_DM_THERMAL=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/colibri-imx8qxp.h b/include/configs/colibri-imx8qxp.h new file mode 100644 index 0000000000..fe0da35cf5 --- /dev/null +++ b/include/configs/colibri-imx8qxp.h @@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright 2019 Toradex
- */
+#ifndef __COLIBRI_IMX8QXP_H +#define __COLIBRI_IMX8QXP_H
+#include <linux/sizes.h> +#include <asm/arch/imx-regs.h>
+#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_TEXT_BASE 0x0 +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x250 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x013E000 +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_MALLOC_F_ADDR 0x00120000
Why not to keep these all values in defconfig?
+#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+#define CONFIG_OF_EMBED +#endif /* CONFIG_SPL_BUILD */
+#define CONFIG_REMAKE_ELF
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD
+#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define FEC_QUIRK_ENET_MAC
+#define CONFIG_IP_DEFRAG +#define CONFIG_TFTP_BLOCKSIZE 4096 +#define CONFIG_TFTP_TSIZE
+#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.10.1
+#define MEM_LAYOUT_ENV_SETTINGS \
"fdt_addr_r=0x84000000\0" \"kernel_addr_r=0x82000000\0" \"ramdisk_addr_r=0x84100000\0"+#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif
+/* Boot M4 */ +#define M4_BOOT_ENV \
"m4_0_image=m4_0.bin\0" \"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \"${m4_0_image}\0" \"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \+#define MFG_NAND_PARTITION ""
+#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \func(MMC, mmc, 1) \func(DHCP, dhcp, na)+#include <config_distro_bootcmd.h> +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START ""
+#define CONFIG_MFG_ENV_SETTINGS \
"mfgtool_args=setenv bootargs console=${console},${baudrate} " \"rdinit=/linuxrc g_mass_storage.stall=0 " \"g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \"g_mass_storage.idProduct=0x37FF " \"g_mass_storage.iSerialNumber=\"\" "\MFG_NAND_PARTITION \"video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off " \"clk_ignore_unused "\"\0" \"initrd_addr=0x83800000\0" \"initrd_high=0xffffffff\0" \"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \"${fdt_addr};\0" \+/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \
AHAB_ENV \BOOTENV \CONFIG_MFG_ENV_SETTINGS \M4_BOOT_ENV \MEM_LAYOUT_ENV_SETTINGS \"boot_fdt=try\0" \"bootscript=echo Running bootscript from mmc ...; source\0" \"console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200\0" \"fdt_addr=0x83000000\0" \"fdt_file=fsl-imx8qxp-colibri-eval-v3.dtb\0" \"fdt_high=0xffffffffffffffff\0" \"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \"image=Image\0" \"initrd_addr=0x83800000\0" \"initrd_high=0xffffffffffffffff\0" \"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \"${script};\0" \"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \"mmcargs=setenv bootargs console=${console},${baudrate} " \"root=PARTUUID=${uuid} rootwait " \"mmcautodetect=yes\0" \"mmcboot=echo Booting from mmc ...; " \"run finduuid; run mmcargs; " \"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \"if run loadfdt; then " \"booti ${loadaddr} - ${fdt_addr}; " \"else " \"echo WARN: Cannot load the DT; " \"fi; " \"else " \"echo wait for boot; " \"fi;\0" \"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \"netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \"nfsroot=${serverip}:${nfsroot},v3,tcp video=imxdpufb5:off " \"video=imxdpufb6:off video=imxdpufb7:off\0" \"netboot=echo Booting from net ...; " \"run netargs; " \"if test ${ip_dyn} = yes; then " \"setenv get_cmd dhcp; " \"else " \"setenv get_cmd tftp; " \"fi; " \"${get_cmd} ${loadaddr} ${image}; " \"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \"booti ${loadaddr} - ${fdt_addr}; " \"else " \"echo WARN: Cannot load the DT; " \"fi; " \"else " \"booti; " \"fi;\0" \"nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \"colibri-imx8qxp/${fdt_file}; booti ${loadaddr} - " \"${fdt_addr}\0" \"panel=NULL\0" \"script=boot.scr\0" \"video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0"+#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \"if run loadbootscript; then " \"run bootscript; " \"else " \"if run loadimage; then " \"run mmcboot; " \"else run netboot; " \"fi; " \"fi; " \"else booti ${loadaddr} - ${fdt_addr}; fi"+/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
+#define CONFIG_SYS_MEMTEST_START 0x88000000 +#define CONFIG_SYS_MEMTEST_END 0x89000000
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */ +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
CONFIG_TDX_CFG_BLOCK_OFFSET)+#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 1
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+/* On Colibri iMX8 USDHC1 is eMMC, USDHC2 is 4-bit SD */ +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 eMMC */ +#define CONFIG_SYS_FSL_USDHC_NUM 2
+/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
+#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_NR_DRAM_BANKS 3 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
+/* Serial */ +#define CONFIG_BAUDRATE 115200
+/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)+/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */
+#define BOOTAUX_RESERVED_MEM_BASE 0x88000000 +#define BOOTAUX_RESERVED_MEM_SIZE 0x08000000 /* Reserve from second 128MB */
+#endif /* __COLIBRI_IMX8QXP_H */
2.20.1
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Hi Igor
On Tue, 2019-04-09 at 08:06 +0000, Igor Opaniuk wrote:
Hi Marcel,
Just a couple of comments below after a brief look:
On Sat, Apr 6, 2019 at 2:49 PM Marcel Ziswiler marcel@ziswiler.com wrote:
From: Marcel Ziswiler marcel.ziswiler@toradex.com
This commit adds initial support for the Toradex Colibri iMX8QXP 2GB WB IT V1.0B module. Unlike the V1.0A early access samples exclusively booting from SD card, they are now strapped to boot from eFuses which are factory fused to properly boot from their on-module eMMC. U- Boot supports either booting from the on-module eMMC or may be used for recovery purpose using the universal update utility (uuu) aka mfgtools 3.0.
Functionality wise the following is known to be working:
- eMMC and MMC/SD card
- Ethernet
- GPIOs
- I2C
Unfortunately, there is no USB functionality for the i.MX 8QXP as of yet.
Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com
arch/arm/dts/Makefile | 4 +- arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi | 112 ++++++ arch/arm/dts/fsl-imx8qxp-colibri.dts | 328 ++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 6 + board/toradex/colibri-imx8qxp/Kconfig | 30 ++ board/toradex/colibri-imx8qxp/MAINTAINERS | 9 + board/toradex/colibri-imx8qxp/Makefile | 7 + board/toradex/colibri-imx8qxp/README | 67 ++++ .../toradex/colibri-imx8qxp/colibri-imx8qxp.c | 211 +++++++++++ board/toradex/colibri-imx8qxp/imximage.cfg | 24 ++ configs/colibri-imx8qxp_defconfig | 53 +++ include/configs/colibri-imx8qxp.h | 240 +++++++++++++ 12 files changed, 1090 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri.dts create mode 100644 board/toradex/colibri-imx8qxp/Kconfig create mode 100644 board/toradex/colibri-imx8qxp/MAINTAINERS create mode 100644 board/toradex/colibri-imx8qxp/Makefile create mode 100644 board/toradex/colibri-imx8qxp/README create mode 100644 board/toradex/colibri-imx8qxp/colibri-imx8qxp.c create mode 100644 board/toradex/colibri-imx8qxp/imximage.cfg create mode 100644 configs/colibri-imx8qxp_defconfig create mode 100644 include/configs/colibri-imx8qxp.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d63b6874b5..fa0f28a84a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -562,7 +562,9 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
-dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb +dtb-$(CONFIG_ARCH_IMX8) += \
fsl-imx8qxp-colibri.dtb \fsl-imx8qxp-mek.dtbdtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi new file mode 100644 index 0000000000..f8686befdf --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- Copyright 2019 Toradex AG
- */
+&mu {
u-boot,dm-spl;+};
+&clk {
u-boot,dm-spl;+};
+&iomuxc {
u-boot,dm-spl;+};
+&pd_lsio {
u-boot,dm-spl;+};
+&pd_lsio_gpio0 {
u-boot,dm-spl;+};
+&pd_lsio_gpio1 {
u-boot,dm-spl;+};
+&pd_lsio_gpio2 {
u-boot,dm-spl;+};
+&pd_lsio_gpio3 {
u-boot,dm-spl;+};
+&pd_lsio_gpio4 {
u-boot,dm-spl;+};
+&pd_lsio_gpio5 {
u-boot,dm-spl;+};
+&pd_lsio_gpio6 {
u-boot,dm-spl;+};
+&pd_lsio_gpio7 {
u-boot,dm-spl;+};
+&pd_conn {
u-boot,dm-spl;+};
+&pd_conn_sdch0 {
u-boot,dm-spl;+};
+&pd_conn_sdch1 {
u-boot,dm-spl;+};
+&pd_conn_sdch2 {
u-boot,dm-spl;+};
+&gpio0 {
u-boot,dm-spl;+};
+&gpio1 {
u-boot,dm-spl;+};
+&gpio2 {
u-boot,dm-spl;+};
+&gpio3 {
u-boot,dm-spl;+};
+&gpio4 {
u-boot,dm-spl;+};
+&gpio5 {
u-boot,dm-spl;+};
+&gpio6 {
u-boot,dm-spl;+};
+&gpio7 {
u-boot,dm-spl;+};
+&lpuart3 {
u-boot,dm-spl;+};
+&usdhc1 {
u-boot,dm-spl;+};
+&usdhc2 {
u-boot,dm-spl;+}; diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts b/arch/arm/dts/fsl-imx8qxp-colibri.dts new file mode 100644 index 0000000000..0c20edf2cf --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts @@ -0,0 +1,328 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- Copyright 2019 Toradex AG
- */
+/dts-v1/;
+#include "fsl-imx8qxp.dtsi" +#include "fsl-imx8qxp-colibri-u-boot.dtsi"
+/ {
model = "Toradex Colibri iMX8QXP";compatible = "toradex,colibri-imx8qxp", "fsl,imx8qxp";chosen {bootargs = "console=ttyLP3,115200earlycon=lpuart32,0x5a090000,115200";
stdout-path = &lpuart3;};reg_usbh_vbus: regulator-usbh-vbus {compatible = "regulator-fixed";pinctrl-names = "default";pinctrl-0 = <&pinctrl_usbh1_reg>;regulator-name = "usbh_vbus";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;};+};
+&iomuxc {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>,<&pinctrl_hog2>;
colibri-imx8qxp {pinctrl_lpuart0: lpuart0grp {fsl,pins = <SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
>;};pinctrl_lpuart3: lpuart3grp {fsl,pins = <SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020
SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020
>;};pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {fsl,pins = <SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 /* DTR */
SC_P_SAI1_RXD_LSIO_GPIO0_IO29SC_P_SAI1_RXC_LSIO_GPIO0_IO30SC_P_CSI_RESET_LSIO_GPIO3_IO03SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22SC_P_CSI_EN_LSIO_GPIO3_IO02>;};pinctrl_fec1: fec1grp {fsl,pins = <SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 /* Use pads in 3.3V mode */
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 /* Use pads in 3.3V mode */
SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061
SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061
SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061
SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061
SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061
SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061
SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061
SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x00000061
>;};pinctrl_gpio_bl_on: gpio-bl-on {fsl,pins = <SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12>;};pinctrl_hog0: hog0grp {fsl,pins = <SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 /* Use pads in 3.3V mode */
>;};pinctrl_hog1: hog1grp {fsl,pins = <SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* 65 */
SC_P_CSI_D07_CI_PI_D09SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13SC_P_SAI0_TXC_LSIO_GPIO0_IO26SC_P_CSI_D02_CI_PI_D04SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* 85 */
SC_P_CSI_D06_CI_PI_D08SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17SC_P_SAI0_RXD_LSIO_GPIO0_IO27SC_P_CSI_D03_CI_PI_D05SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18SC_P_SAI0_TXFS_LSIO_GPIO0_IO28SC_P_CSI_D00_CI_PI_D02SC_P_SAI0_TXD_LSIO_GPIO0_IO25SC_P_CSI_D01_CI_PI_D03SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04SC_P_CSI_PCLK_LSIO_GPIO3_IO00SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21SC_P_SAI1_RXFS_LSIO_GPIO0_IO31SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24>;};pinctrl_hog2: hog2grp {fsl,pins = <SC_P_CSI_MCLK_LSIO_GPIO3_IO01SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16>;};/* Off Module I2C */pinctrl_i2c1: i2c1grp {fsl,pins = <SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021
SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021
>;};/*INT*/pinctrl_usb3503a: usb3503a-grp {fsl,pins = <SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x00000061
>;};pinctrl_usbc_det: usbc-det {fsl,pins = <SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040
>;};pinctrl_usbh1_reg: usbh1-reg {fsl,pins = <SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03>;};pinctrl_usdhc1: usdhc1grp {fsl,pins = <SC_P_EMMC0_CLK_CONN_EMMC0_CLKSC_P_EMMC0_CMD_CONN_EMMC0_CMDSC_P_EMMC0_DATA0_CONN_EMMC0_DATA0SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7SC_P_EMMC0_STROBE_CONN_EMMC0_STROBESC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;};pinctrl_usdhc1_100mhz: usdhc1grp100mhz {fsl,pins = <SC_P_EMMC0_CLK_CONN_EMMC0_CLKSC_P_EMMC0_CMD_CONN_EMMC0_CMDSC_P_EMMC0_DATA0_CONN_EMMC0_DATA0SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7SC_P_EMMC0_STROBE_CONN_EMMC0_STROBESC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;};pinctrl_usdhc1_200mhz: usdhc1grp200mhz {fsl,pins = <SC_P_EMMC0_CLK_CONN_EMMC0_CLKSC_P_EMMC0_CMD_CONN_EMMC0_CMDSC_P_EMMC0_DATA0_CONN_EMMC0_DATA0SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7SC_P_EMMC0_STROBE_CONN_EMMC0_STROBESC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;};pinctrl_usdhc2_gpio: usdhc2gpiogrp {fsl,pins = <SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09>;};pinctrl_usdhc2: usdhc2grp {fsl,pins = <SC_P_USDHC1_CLK_CONN_USDHC1_CLKSC_P_USDHC1_CMD_CONN_USDHC1_CMDSC_P_USDHC1_DATA0_CONN_USDHC1_DATA0SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;};pinctrl_usdhc2_100mhz: usdhc2grp100mhz {fsl,pins = <SC_P_USDHC1_CLK_CONN_USDHC1_CLKSC_P_USDHC1_CMD_CONN_USDHC1_CMDSC_P_USDHC1_DATA0_CONN_USDHC1_DATA0SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;};pinctrl_usdhc2_200mhz: usdhc2grp200mhz {fsl,pins = <SC_P_USDHC1_CLK_CONN_USDHC1_CLKSC_P_USDHC1_CMD_CONN_USDHC1_CMDSC_P_USDHC1_DATA0_CONN_USDHC1_DATA0SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;};};+};
+&lpuart0 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_lpuart0>;status = "okay";+};
+&lpuart3 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;status = "okay";+};
+&gpio0 {
status = "okay";+};
+&gpio1 {
status = "okay";+};
+&gpio3 {
status = "okay";+};
+&gpio4 {
status = "okay";+};
+&fec1 {
phy-handle = <ðphy0>;phy-mode = "rmii";pinctrl-names = "default";pinctrl-0 = <&pinctrl_fec1>;status = "okay";mdio {#address-cells = <1>;#size-cells = <0>;ethphy0: ethernet-phy@2 {compatible = "ethernet-phy-ieee802.3-c22";max-speed = <100>;reg = <2>;};};+};
+&i2c1 {
#address-cells = <1>;#size-cells = <0>;clock-frequency = <100000>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_i2c1>;status = "okay";+};
+&usdhc1 {
bus-width = <8>;non-removable;pinctrl-names = "default", "state_100mhz", "state_200mhz";pinctrl-0 = <&pinctrl_usdhc1>;pinctrl-1 = <&pinctrl_usdhc1_100mhz>;pinctrl-2 = <&pinctrl_usdhc1_200mhz>;status = "okay";+};
+&usdhc2 {
bus-width = <4>;cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;pinctrl-names = "default", "state_100mhz", "state_200mhz";pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;pinctrl-1 = <&pinctrl_usdhc2_100mhz>,<&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_usdhc2_gpio>;
status = "okay";+}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach- imx/imx8/Kconfig index f76a139684..feea07f135 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -22,6 +22,11 @@ choice prompt "i.MX8 board select" optional
+config TARGET_COLIBRI_IMX8QXP
bool "Support Colibri iMX8QXP module"select BOARD_LATE_INITselect IMX8QXPconfig TARGET_IMX8QXP_MEK bool "Support i.MX8QXP MEK board" select BOARD_LATE_INIT @@ -30,5 +35,6 @@ config TARGET_IMX8QXP_MEK endchoice
source "board/freescale/imx8qxp_mek/Kconfig" +source "board/toradex/colibri-imx8qxp/Kconfig"
endif diff --git a/board/toradex/colibri-imx8qxp/Kconfig b/board/toradex/colibri-imx8qxp/Kconfig new file mode 100644 index 0000000000..340fe72816 --- /dev/null +++ b/board/toradex/colibri-imx8qxp/Kconfig @@ -0,0 +1,30 @@ +if TARGET_COLIBRI_IMX8QXP
+config SYS_BOARD
default "colibri-imx8qxp"+config SYS_VENDOR
default "toradex"+config SYS_CONFIG_NAME
default "colibri-imx8qxp"+config TDX_CFG_BLOCK
default y+config TDX_HAVE_MMC
default y+config TDX_CFG_BLOCK_DEV
default "0"+config TDX_CFG_BLOCK_PART
default "1"+# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET
default "-512"+source "board/toradex/common/Kconfig"
+endif diff --git a/board/toradex/colibri-imx8qxp/MAINTAINERS b/board/toradex/colibri-imx8qxp/MAINTAINERS new file mode 100644 index 0000000000..39a9eb79b7 --- /dev/null +++ b/board/toradex/colibri-imx8qxp/MAINTAINERS @@ -0,0 +1,9 @@ +Colibri iMX8QXP +M: Marcel Ziswiler marcel.ziswiler@toradex.com +W: http://developer.toradex.com/software/linux/linux-software +S: Maintained +F: arch/arm/dts/fsl-imx8qxp-colibri.dts +F: arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi +F: board/toradex/colibri-imx8qxp/ +F: configs/colibri-imx8qxp_defconfig +F: include/configs/colibri-imx8qxp.h diff --git a/board/toradex/colibri-imx8qxp/Makefile b/board/toradex/colibri-imx8qxp/Makefile new file mode 100644 index 0000000000..f6342e1dca --- /dev/null +++ b/board/toradex/colibri-imx8qxp/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2019 Toradex +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y += colibri-imx8qxp.o diff --git a/board/toradex/colibri-imx8qxp/README b/board/toradex/colibri-imx8qxp/README new file mode 100644 index 0000000000..70fd4f75a7 --- /dev/null +++ b/board/toradex/colibri-imx8qxp/README @@ -0,0 +1,67 @@ +U-Boot for the Toradex Colibri iMX8QXP V1.0B module
+Quick Start +===========
+- Build the ARM trusted firmware binary +- Get scfw_tcm.bin and ahab-container.img +- Build U-Boot +- Load U-Boot binary using uuu +- Flash U-Boot binary into the eMMC +- Boot
+Get and Build the ARM Trusted Firmware +======================================
+$ git clone https://source.codeaurora.org/external/imx/imx-atf
Just FYI: $ git clone https://source.codeaurora.org/external/imx/imx-atf imx- atf.git Cloning into 'imx-atf.git'... remote: Counting objects: 57255, done. remote: Compressing objects: 100% (1076/1076), done. remote: Total 57255 (delta 677), reused 594 (delta 247) Receiving objects: 100% (57255/57255), 12.00 MiB | 6.40 MiB/s, done. Resolving deltas: 100% (38758/38758), done. warning: remote HEAD refers to nonexistent ref, unable to checkout.
That is not really an issue as we ask for a specific branch to be checked out further below. However, I can easily change it to directly check out resp. branch upon cloning.
[zim@marcel-nb-toradex-int tmp]$ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf Cloning into 'imx-atf'... remote: Counting objects: 57255, done. remote: Compressing objects: 100% (1076/1076), done. remote: Total 57255 (delta 677), reused 594 (delta 247) Receiving objects: 100% (57255/57255), 12.00 MiB | 9.50 MiB/s, done. Resolving deltas: 100% (38758/38758), done.
+$ cd imx-atf/ +$ git checkout -b imx_4.14.78_1.0.0_ga origin/imx_4.14.78_1.0.0_ga +$ make PLAT=imx8qxp bl31
+Get scfw_tcm.bin and ahab-container.img +=======================================
+$ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.... +$ mv mx8qx-colibri-scfw-tcm.bin?raw=true mx8qx-colibri-scfw- tcm.bin +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.6.bin +$ chmod +x firmware-imx-7.6.bin +$ ./firmware-imx-7.6.bin
+Copy the following binaries to the U-Boot folder:
+$ cp imx-atf/build/imx8qxp/release/bl31.bin . +$ cp u-boot/u-boot.bin .
+Copy the following firmware to the U-Boot folder:
+$ cp firmware-imx-7.6/firmware/seco/ahab-container.img .
+Build U-Boot +============
+$ make colibri-imx8qxp_defconfig +$ make u-boot-dtb.imx
+Load the U-Boot Binary Using UUU +================================
+Get the latest version of the universal update utility (uuu) aka mfgtools 3.0:
https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2F...
+Put the module into USB recovery aka serial downloader mode, connect USB device +to your host and execute uuu:
+sudo ./uuu u-boot/u-boot-dtb.imx
+Flash the U-Boot Binary into the eMMC +=====================================
+Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot area partition:
Maybe it's better to say flash (just to avoid confusion)? I personally perceive burn as something that is written to OTP.
I don't quite like using flash as it may refer to the noun as well as the verb which may be confusing on its own.
+load mmc 1:1 $loadaddr u-boot-dtb.imx +setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200 +mmc dev 0 1 +mmc write ${loadaddr} 0x0 ${blkcnt}
+Boot diff --git a/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c new file mode 100644 index 0000000000..98c389c6f7 --- /dev/null +++ b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright 2019 Toradex
- */
+#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <netdev.h> +#include <fsl_ifc.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <environment.h> +#include <fsl_esdhc.h> +#include <i2c.h>
Includes in alphabetical order would be nicer (to simplify detecting duplicate include files and finding the right place for adding new ones.)
Yes, I agree. I guess I just copy pasted NXP's stuff (;-p).
+#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <dm.h> +#include <usb.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/video.h> +#include <power-domain.h>
+#include "../common/tdx-cfg-block.h"
+DECLARE_GLOBAL_DATA_PTR;
+#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT)| \
(SC_PAD_28FDSOI_DSE_DV_HIGH <<PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU <<PADRING_PULL_SHIFT))
+#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT)| \
(SC_PAD_28FDSOI_DSE_DV_HIGH <<PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU <<PADRING_PULL_SHIFT))
+static iomux_cfg_t uart3_pads[] = {
SC_P_FLEXCAN2_RX | MUX_MODE_ALT(2) |MUX_PAD_CTRL(UART_PAD_CTRL),
SC_P_FLEXCAN2_TX | MUX_MODE_ALT(2) |MUX_PAD_CTRL(UART_PAD_CTRL),
/* Transceiver FORCEOFF# signal, mux to use pullup */SC_P_QSPI0B_DQS | MUX_MODE_ALT(4) |MUX_PAD_CTRL(UART_PAD_CTRL), +};
+static void setup_iomux_uart(void) +{
imx8_iomux_setup_multiple_pads(uart3_pads,ARRAY_SIZE(uart3_pads)); +}
+int board_early_init_f(void) +{
sc_pm_clock_rate_t rate;sc_err_t err = 0;/** This works around that having only UART3 up the baudrateis 1.2M
* instead of 115.2k. Set UART0 clock root to 80 MHz*/rate = 80000000;err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER,&rate);
if (err != SC_ERR_NONE)return 0;/* Power up UART3 */err = sc_pm_set_resource_power_mode(-1, SC_R_UART_3,SC_PM_PW_MODE_ON);
if (err != SC_ERR_NONE)return 0;/* Set UART3 clock root to 80 MHz */rate = 80000000;err = sc_pm_set_clock_rate(-1, SC_R_UART_3, SC_PM_CLK_PER,&rate);
if (err != SC_ERR_NONE)return 0;/* Enable UART3 clock root */err = sc_pm_clock_enable(-1, SC_R_UART_3, SC_PM_CLK_PER,true, false);
if (err != SC_ERR_NONE)return 0;setup_iomux_uart();return 0;+}
+#undef CONFIG_MXC_GPIO /* TODO */ +#ifdef CONFIG_MXC_GPIO +#define IOEXP_RESET IMX_GPIO_NR(1, 1)
+static iomux_cfg_t board_gpios[] = {
SC_P_SPI2_SDO | MUX_MODE_ALT(4) |MUX_PAD_CTRL(GPIO_PAD_CTRL),
SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | \MUX_PAD_CTRL(GPIO_PAD_CTRL),+};
+static void board_gpio_init(void) +{
struct gpio_desc desc;int ret;ret = dm_gpio_lookup_name("gpio@1a_3", &desc);if (ret)return;ret = dm_gpio_request(&desc, "bb_per_rst_b");if (ret)return;dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);dm_gpio_set_value(&desc, 0);udelay(50);dm_gpio_set_value(&desc, 1);imx8_iomux_setup_multiple_pads(board_gpios,ARRAY_SIZE(board_gpios));
/* enable i2c port expander assert reset line */gpio_request(IOEXP_RESET, "ioexp_rst");gpio_direction_output(IOEXP_RESET, 1);+} +#else +static inline void board_gpio_init(void) {} +#endif
+#if IS_ENABLED(CONFIG_FEC_MXC) +#include <miiphy.h>
+int board_phy_config(struct phy_device *phydev) +{
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);if (phydev->drv->config)phydev->drv->config(phydev);return 0;+} +#endif
+void build_info(void) +{
u32 sc_build = 0, sc_commit = 0;/* Get SCFW build and commit id */sc_misc_build_info(-1, &sc_build, &sc_commit);if (!sc_build) {printf("SCFW does not support build info\n");sc_commit = 0; /* Display 0 if build info notsupported */
}printf("Build: SCFW %x\n", sc_commit);+}
+int checkboard(void) +{
puts("Model: Toradex Colibri iMX8X\n");build_info();print_bootinfo();return 0;+}
+int board_init(void) +{
board_gpio_init();return 0;+}
+void detail_board_ddr_info(void) +{
puts("\nDDR ");+}
+/*
- Board specific reset that is system reset.
- */
+void reset_cpu(ulong addr) +{
/* TODO */+}
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{
return ft_common_board_setup(blob, bd);+} +#endif
+int board_mmc_get_env_dev(int devno) +{
return devno;+}
+int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +/* TODO move to common */
env_set("board_name", "Colibri iMX8QXP");env_set("board_rev", "v1.0");+#endif
return 0;+} diff --git a/board/toradex/colibri-imx8qxp/imximage.cfg b/board/toradex/colibri-imx8qxp/imximage.cfg new file mode 100644 index 0000000000..ce9e66c64d --- /dev/null +++ b/board/toradex/colibri-imx8qxp/imximage.cfg @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright 2019 Toradex
- Refer doc/README.imx8image for more details about how-to
configure
- and create imx8image boot image
- */
+#define __ASSEMBLY__
+/* Boot from SD, sector size 0x400 */ +BOOT_FROM EMMC_FASTBOOT 0x400 +/* SoC type IMX8QX */ +SOC_TYPE IMX8QX +/* Append seco container image */ +APPEND ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qx-colibri-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 bl31.bin 0x80000000 +/* Add U-Boot image with load attribute */ +DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/configs/colibri-imx8qxp_defconfig b/configs/colibri- imx8qxp_defconfig new file mode 100644 index 0000000000..d697546ed7 --- /dev/null +++ b/configs/colibri-imx8qxp_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_COLIBRI_IMX8QXP=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri- imx8qxp/imximage.cfg" +CONFIG_LOG=y +CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_UUID=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_DM_THERMAL=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/colibri-imx8qxp.h b/include/configs/colibri-imx8qxp.h new file mode 100644 index 0000000000..fe0da35cf5 --- /dev/null +++ b/include/configs/colibri-imx8qxp.h @@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright 2019 Toradex
- */
+#ifndef __COLIBRI_IMX8QXP_H +#define __COLIBRI_IMX8QXP_H
+#include <linux/sizes.h> +#include <asm/arch/imx-regs.h>
+#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_TEXT_BASE 0x0 +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x250 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot- spl.lds" +#define CONFIG_SPL_STACK 0x013E000 +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_MALLOC_F_ADDR 0x00120000
Why not to keep these all values in defconfig?
Again, that would rather be a question to be directed at NXP. However, as the whole use of SPL on i.MX 8X is anyway neither working well nor making any much sense I will just drop all of this in a v2.
+#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+#define CONFIG_OF_EMBED +#endif /* CONFIG_SPL_BUILD */
+#define CONFIG_REMAKE_ELF
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD
+#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define FEC_QUIRK_ENET_MAC
+#define CONFIG_IP_DEFRAG +#define CONFIG_TFTP_BLOCKSIZE 4096 +#define CONFIG_TFTP_TSIZE
+#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.10.1
+#define MEM_LAYOUT_ENV_SETTINGS \
"fdt_addr_r=0x84000000\0" \"kernel_addr_r=0x82000000\0" \"ramdisk_addr_r=0x84100000\0"+#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif
+/* Boot M4 */ +#define M4_BOOT_ENV \
"m4_0_image=m4_0.bin\0" \"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \
"${m4_0_image}\0" \"m4boot_0=run loadm4image_0; dcache flush; bootaux${loadaddr} 0\0" \
+#define MFG_NAND_PARTITION ""
+#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \func(MMC, mmc, 1) \func(DHCP, dhcp, na)+#include <config_distro_bootcmd.h> +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START ""
+#define CONFIG_MFG_ENV_SETTINGS \
"mfgtool_args=setenv bootargsconsole=${console},${baudrate} " \
"rdinit=/linuxrc g_mass_storage.stall=0 " \"g_mass_storage.removable=1g_mass_storage.idVendor=0x066F " \
"g_mass_storage.idProduct=0x37FF " \"g_mass_storage.iSerialNumber=\"\" "\MFG_NAND_PARTITION \"video=imxdpufb5:off video=imxdpufb6:offvideo=imxdpufb7:off " \
"clk_ignore_unused "\"\0" \"initrd_addr=0x83800000\0" \"initrd_high=0xffffffff\0" \"bootcmd_mfg=run mfgtool_args;booti ${loadaddr}${initrd_addr} " \
"${fdt_addr};\0" \+/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \
AHAB_ENV \BOOTENV \CONFIG_MFG_ENV_SETTINGS \M4_BOOT_ENV \MEM_LAYOUT_ENV_SETTINGS \"boot_fdt=try\0" \"bootscript=echo Running bootscript from mmc ...; source\0"\
"console=ttyLP3,115200earlycon=lpuart32,0x5a090000,115200\0" \
"fdt_addr=0x83000000\0" \"fdt_file=fsl-imx8qxp-colibri-eval-v3.dtb\0" \"fdt_high=0xffffffffffffffff\0" \"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \"image=Image\0" \"initrd_addr=0x83800000\0" \"initrd_high=0xffffffffffffffff\0" \"loadbootscript=fatload mmc ${mmcdev}:${mmcpart}${loadaddr} " \
"${script};\0" \"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr}${fdt_file}\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}${image}\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \"root=PARTUUID=${uuid} rootwait " \"mmcautodetect=yes\0" \"mmcboot=echo Booting from mmc ...; " \"run finduuid; run mmcargs; " \"if test ${boot_fdt} = yes || test ${boot_fdt} =try; then " \
"if run loadfdt; then " \"booti ${loadaddr} - ${fdt_addr}; "\
"else " \"echo WARN: Cannot load the DT; " \"fi; " \"else " \"echo wait for boot; " \"fi;\0" \"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \"netargs=setenv bootargs console=${console} root=/dev/nfsip=dhcp " \
"nfsroot=${serverip}:${nfsroot},v3,tcpvideo=imxdpufb5:off " \
"video=imxdpufb6:off video=imxdpufb7:off\0" \"netboot=echo Booting from net ...; " \"run netargs; " \"if test ${ip_dyn} = yes; then " \"setenv get_cmd dhcp; " \"else " \"setenv get_cmd tftp; " \"fi; " \"${get_cmd} ${loadaddr} ${image}; " \"if test ${boot_fdt} = yes || test ${boot_fdt} =try; then " \
"if ${get_cmd} ${fdt_addr} ${fdt_file};then " \
"booti ${loadaddr} - ${fdt_addr}; "\
"else " \"echo WARN: Cannot load the DT; " \"fi; " \"else " \"booti; " \"fi;\0" \"nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp${fdt_addr} " \
"colibri-imx8qxp/${fdt_file}; booti ${loadaddr} - "\
"${fdt_addr}\0" \"panel=NULL\0" \"script=boot.scr\0" \"video=imxdpufb5:off video=imxdpufb6:offvideo=imxdpufb7:off\0"
+#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \"if run loadbootscript; then " \"run bootscript; " \"else " \"if run loadimage; then " \"run mmcboot; " \"else run netboot; " \"fi; " \"fi; " \"else booti ${loadaddr} - ${fdt_addr}; fi"+/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
+#define CONFIG_SYS_MEMTEST_START 0x88000000 +#define CONFIG_SYS_MEMTEST_END 0x89000000
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */ +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
CONFIG_TDX_CFG_BLOCK_OFFSET) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 1
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+/* On Colibri iMX8 USDHC1 is eMMC, USDHC2 is 4-bit SD */ +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 eMMC */ +#define CONFIG_SYS_FSL_USDHC_NUM 2
+/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
+#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_NR_DRAM_BANKS 3 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
+/* Serial */ +#define CONFIG_BAUDRATE 115200
+/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) +
+/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */
+#define BOOTAUX_RESERVED_MEM_BASE 0x88000000 +#define BOOTAUX_RESERVED_MEM_SIZE 0x08000000 /* Reserve from second 128MB */
+#endif /* __COLIBRI_IMX8QXP_H */
2.20.1
Thanks, Igor.
Cheers
Marcel
participants (4)
-
Igor Opaniuk -
Marcel Ziswiler -
Marcel Ziswiler -
Peng Fan