[U-Boot] [PATCH] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM
Extend PHYTEC phyBOARD-i.MX6UL for phyCORE-i.MX6UL SoM (PCL063) with eMMC on SoM.
CPU: Freescale i.MX6ULL rev1.0 792 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 38C Reset cause: POR Model: Phytec phyBOARD-i.MX6ULL-Segin SBC Board: PHYTEC phyCORE-i.MX6ULL DRAM: 256 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial@02020000 Out: serial@02020000 Err: serial@02020000 Net: FEC0
Working: - Eth0 - i2C - MMC/SD - eMMC - UART (1 & 5) - USB (host & otg)
Signed-off-by: Parthiban Nallathambi parthitce@gmail.com --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx6ul-phycore-segin.dts | 3 +- arch/arm/dts/imx6ull-phycore-segin.dts | 81 ++++++++++++ ...{imx6ul-pcl063.dtsi => pcl063-common.dtsi} | 31 ++++- arch/arm/mach-imx/mx6/Kconfig | 12 ++ board/phytec/pcl063/Kconfig | 13 ++ board/phytec/pcl063/MAINTAINERS | 6 +- board/phytec/pcl063/pcl063.c | 5 +- board/phytec/pcl063/spl.c | 76 +++++++++++- configs/phycore_pcl063_ull_defconfig | 54 ++++++++ include/configs/pcl063_ull.h | 117 ++++++++++++++++++ 11 files changed, 388 insertions(+), 11 deletions(-) create mode 100644 arch/arm/dts/imx6ull-phycore-segin.dts rename arch/arm/dts/{imx6ul-pcl063.dtsi => pcl063-common.dtsi} (84%) create mode 100644 configs/phycore_pcl063_ull_defconfig create mode 100644 include/configs/pcl063_ull.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0e2ffdb87f..431afb915f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -539,6 +539,7 @@ dtb-$(CONFIG_MX6UL) += \ dtb-$(CONFIG_MX6ULL) += \ imx6ull-14x14-evk.dtb \ imx6ull-colibri.dtb \ + imx6ull-phycore-segin.dtb
dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ imx7d-sdb-qspi.dtb \ diff --git a/arch/arm/dts/imx6ul-phycore-segin.dts b/arch/arm/dts/imx6ul-phycore-segin.dts index a46012e2b4..9e6984e137 100644 --- a/arch/arm/dts/imx6ul-phycore-segin.dts +++ b/arch/arm/dts/imx6ul-phycore-segin.dts @@ -16,7 +16,8 @@
/dts-v1/;
-#include "imx6ul-pcl063.dtsi" +#include "imx6ul.dtsi" +#include "pcl063-common.dtsi"
/ { model = "Phytec phyBOARD-i.MX6UL-Segin SBC"; diff --git a/arch/arm/dts/imx6ull-phycore-segin.dts b/arch/arm/dts/imx6ull-phycore-segin.dts new file mode 100644 index 0000000000..c20a867c90 --- /dev/null +++ b/arch/arm/dts/imx6ull-phycore-segin.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Parthiban Nallathambi parthitce@gmail.com + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include "imx6ull.dtsi" +#include "pcl063-common.dtsi" + +/ { + model = "Phytec phyBOARD-i.MX6ULL-Segin SBC"; + compatible = "phytec,phyboard-imx6ull-segin", "phytec,imx6ull-pcl063", + "fsl,imx6ull"; +}; + +&gpmi { + status = "disabled"; +}; + +&i2c1 { + i2c_rtc: rtc@68 { + compatible = "microcrystal,rv4162"; + reg = <0x68>; + status = "okay"; + }; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc2 { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + +}; diff --git a/arch/arm/dts/imx6ul-pcl063.dtsi b/arch/arm/dts/pcl063-common.dtsi similarity index 84% rename from arch/arm/dts/imx6ul-pcl063.dtsi rename to arch/arm/dts/pcl063-common.dtsi index 24a6a47983..f505f62230 100644 --- a/arch/arm/dts/imx6ul-pcl063.dtsi +++ b/arch/arm/dts/pcl063-common.dtsi @@ -7,10 +7,6 @@ * Author: Christian Hemp c.hemp@phytec.de */
-/dts-v1/; - -#include "imx6ul.dtsi" - / { model = "Phytec phyCORE-i.MX6 Ultra Lite SOM"; compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul"; @@ -99,6 +95,18 @@ status = "okay"; };
+&usdhc2 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + status = "disabled"; +}; + &iomuxc { pinctrl-names = "default";
@@ -170,4 +178,19 @@
>; }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; }; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index e782859b1e..5e2f08e500 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -443,6 +443,18 @@ config TARGET_PCL063 select DM_THERMAL select SUPPORT_SPL
+config TARGET_PCL063_ULL + bool "PHYTEC PCL063 (phyCORE-i.MX6ULL)" + select MX6ULL + select DM + select DM_ETH + select DM_GPIO + select DM_I2C + select DM_MMC + select DM_SERIAL + select DM_THERMAL + select SUPPORT_SPL + config TARGET_SECOMX6 bool "secomx6 boards"
diff --git a/board/phytec/pcl063/Kconfig b/board/phytec/pcl063/Kconfig index 977db70f64..58f72f2791 100644 --- a/board/phytec/pcl063/Kconfig +++ b/board/phytec/pcl063/Kconfig @@ -10,3 +10,16 @@ config SYS_CONFIG_NAME default "pcl063"
endif + +if TARGET_PCL063_ULL + +config SYS_BOARD + default "pcl063" + +config SYS_VENDOR + default "phytec" + +config SYS_CONFIG_NAME + default "pcl063_ull" + +endif diff --git a/board/phytec/pcl063/MAINTAINERS b/board/phytec/pcl063/MAINTAINERS index c65a951f3d..70e03cfe71 100644 --- a/board/phytec/pcl063/MAINTAINERS +++ b/board/phytec/pcl063/MAINTAINERS @@ -1,8 +1,12 @@ PCL063 BOARD M: Martyn Welch martyn.welch@collabora.com +M: Parthiban Nallathambi parthitce@gmail.com S: Maintained -F: arch/arm/dts/imx6ul-pcl063.dtsi F: arch/arm/dts/imx6ul-phycore-segin.dts +F: arch/arm/dts/imx6ull-phycore-segin.dts +F: arch/arm/dts/pcl063-common.dtsi F: board/phytec/pcl063/ F: configs/phycore_pcl063_defconfig +F: configs/phycore_pcl063_ull_defconfig F: include/configs/pcl063.h +F: include/configs/pcl063_ull.h diff --git a/board/phytec/pcl063/pcl063.c b/board/phytec/pcl063/pcl063.c index 38b233d1b0..17012df037 100644 --- a/board/phytec/pcl063/pcl063.c +++ b/board/phytec/pcl063/pcl063.c @@ -200,7 +200,10 @@ int board_init(void)
int checkboard(void) { - puts("Board: PHYTEC phyCORE-i.MX6UL\n"); + u32 cpurev = get_cpu_rev(); + + printf("Board: PHYTEC phyCORE-i.MX%s\n", + get_imx_type((cpurev & 0xFF000) >> 12));
return 0; } diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c index b93cd493f2..73a774645d 100644 --- a/board/phytec/pcl063/spl.c +++ b/board/phytec/pcl063/spl.c @@ -13,6 +13,7 @@ #include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> #include <fsl_esdhc.h>
/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */ @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), };
+#ifndef CONFIG_NAND_MXS +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif + static struct fsl_esdhc_cfg usdhc_cfg[] = { { .esdhc_base = USDHC1_BASE_ADDR, .max_bus_width = 4, }, +#ifndef CONFIG_NAND_MXS + { + .esdhc_base = USDHC2_BASE_ADDR, + .max_bus_width = 8, + }, +#endif };
int board_mmc_getcd(struct mmc *mmc) @@ -131,12 +153,58 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis) { - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + int i, ret; + + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; +#ifndef CONFIG_NAND_MXS + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; +#endif + default: + printf("Warning - USDHC%d controller not supporting\n", + i + 1); + return 0; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; }
+void board_boot_order(u32 *spl_boot_list) +{ + u32 bmode = imx6_src_get_boot_mode(); + u8 boot_dev = BOOT_DEVICE_MMC1; + + switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) { + case IMX6_BMODE_SD: + case IMX6_BMODE_ESD: + boot_dev = BOOT_DEVICE_MMC1; + break; + case IMX6_BMODE_MMC: + case IMX6_BMODE_EMMC: + boot_dev = BOOT_DEVICE_MMC2; + break; + default: + /* Default - BOOT_DEVICE_MMC1 */ + printf("Wrong board boot order\n"); + break; + } + + spl_boot_list[0] = boot_dev; +} #endif /* CONFIG_FSL_ESDHC */
void board_init_f(ulong dummy) diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig new file mode 100644 index 0000000000..75408a8344 --- /dev/null +++ b/configs/phycore_pcl063_ull_defconfig @@ -0,0 +1,54 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_PCL063_ULL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +# CONFIG_CMD_DEKBLOB is not set +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=8 +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_CACHE=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-phycore-segin" +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_MXC=y +CONFIG_FSL_ESDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Phytec" +CONFIG_USB_GADGET_VENDOR_NUM=0x01b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_LZO=y diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h new file mode 100644 index 0000000000..0f1a010b4e --- /dev/null +++ b/include/configs/pcl063_ull.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Board configuration file for Phytec phyBOARD-i.MX6ULL-Segin SBC + * Copyright (C) 2019 Parthiban Nallathambi parthitce@gmail.com + * + * Based on include/configs/xpress.h: + * Copyright (C) 2015-2016 Stefan Roese sr@denx.de + */ +#ifndef __PCL063_ULL_H +#define __PCL063_ULL_H + +#include <linux/sizes.h> +#include "mx6_common.h" + +/* SPL options */ +#include "imx6_spl.h" + +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +/* Environment settings */ +#define CONFIG_ENV_SIZE (0x4000) +#define CONFIG_ENV_OFFSET (0x80000) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_OFFSET_REDUND \ + (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) + +/* Environment in SD */ +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 0 +#define MMC_ROOTFS_DEV 0 +#define MMC_ROOTFS_PART 2 + +/* Console configs */ +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +#define CONFIG_SUPPORT_EMMC_BOOT + +/* I2C configs */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_256M + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* NAND */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_IMX_THERMAL + +#define ENV_MMC \ + "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ + "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \ + "fitpart=1\0" \ + "bootdelay=3\0" \ + "silent=1\0" \ + "optargs=rw rootwait\0" \ + "mmcautodetect=yes\0" \ + "mmcrootfstype=ext4\0" \ + "mmcfit_name=fitImage\0" \ + "mmcloadfit=fatload mmc ${mmcdev}:${fitpart} ${fit_addr} " \ + "${mmcfit_name}\0" \ + "mmcargs=setenv bootargs " \ + "root=/dev/mmcblk${mmcdev}p${mmcpart} ${optargs} " \ + "console=${console} rootfstype=${mmcrootfstype}\0" \ + "mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm ${fit_addr}\0" \ + +/* Default environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0,115200n8\0" \ + "addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \ + "fit_addr=0x82000000\0" \ + ENV_MMC + +#define CONFIG_BOOTCOMMAND "run mmc_mmc_fit" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +#endif /* __PCL063_ULL_H */
On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote:
diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c index b93cd493f2..73a774645d 100644 --- a/board/phytec/pcl063/spl.c +++ b/board/phytec/pcl063/spl.c @@ -13,6 +13,7 @@ #include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> #include <fsl_esdhc.h>
/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */ @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), };
+#ifndef CONFIG_NAND_MXS +static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_NAND_RE_B__USDHC2_CLK |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_WE_B__USDHC2_CMD |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif
Umm, these pins are already used a few lines up for the NAND, via gpmi:
pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 >; };
static struct fsl_esdhc_cfg usdhc_cfg[] = { { .esdhc_base = USDHC1_BASE_ADDR, .max_bus_width = 4, }, +#ifndef CONFIG_NAND_MXS
- {
.esdhc_base = USDHC2_BASE_ADDR,.max_bus_width = 8,- },
+#endif };
int board_mmc_getcd(struct mmc *mmc) @@ -131,12 +153,58 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis) {
- imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
ARRAY_SIZE(usdhc1_pads));
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
- int i, ret;
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
This breaks for the existing phycore_pcl063_defconfig:
board/phytec/pcl063/spl.c: In function ‘board_mmc_init’: board/phytec/pcl063/spl.c:158:18: error: ‘CONFIG_SYS_FSL_USDHC_NUM’ undeclared (first use in this function); did you mean ‘CONFIG_SYS_FSL_ESDHC_ADDR’? for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { ^~~~~~~~~~~~~~~~~~~~~~~~
Martyn
Hello Martyn,
On 4/8/19 7:45 PM, Martyn Welch wrote:
On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote:
diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c index b93cd493f2..73a774645d 100644 --- a/board/phytec/pcl063/spl.c +++ b/board/phytec/pcl063/spl.c @@ -13,6 +13,7 @@ #include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> #include <fsl_esdhc.h>
/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */ @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), };
+#ifndef CONFIG_NAND_MXS +static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_NAND_RE_B__USDHC2_CLK |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_WE_B__USDHC2_CMD |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif
Umm, these pins are already used a few lines up for the NAND, via gpmi:
I understand. But pcl063 can't co-exit with NAND and eMMC together. I comes either with eMMC or NAND.
pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 >; };static struct fsl_esdhc_cfg usdhc_cfg[] = { { .esdhc_base = USDHC1_BASE_ADDR, .max_bus_width = 4, }, +#ifndef CONFIG_NAND_MXS
- {
.esdhc_base = USDHC2_BASE_ADDR,.max_bus_width = 8,- },
+#endif };
int board_mmc_getcd(struct mmc *mmc) @@ -131,12 +153,58 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis) {
- imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
ARRAY_SIZE(usdhc1_pads));
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
- int i, ret;
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
This breaks for the existing phycore_pcl063_defconfig:
Ah, I missed it. I will add CONFIG_SYS_FSL_USDHC_NUM to 1 in phycore_pcl063_defconfig.
Thanks, Parthiban N
board/phytec/pcl063/spl.c: In function ‘board_mmc_init’: board/phytec/pcl063/spl.c:158:18: error: ‘CONFIG_SYS_FSL_USDHC_NUM’ undeclared (first use in this function); did you mean ‘CONFIG_SYS_FSL_ESDHC_ADDR’? for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { ^~~~~~~~~~~~~~~~~~~~~~~~
Martyn
On Mon, 2019-04-08 at 20:04 +0200, Parthiban wrote:
Hello Martyn,
On 4/8/19 7:45 PM, Martyn Welch wrote:
On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote:
diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c index b93cd493f2..73a774645d 100644 --- a/board/phytec/pcl063/spl.c +++ b/board/phytec/pcl063/spl.c @@ -13,6 +13,7 @@ #include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> #include <fsl_esdhc.h>
/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */ @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), };
+#ifndef CONFIG_NAND_MXS +static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_NAND_RE_B__USDHC2_CLK |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_WE_B__USDHC2_CMD |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif
Umm, these pins are already used a few lines up for the NAND, via gpmi:
I understand. But pcl063 can't co-exit with NAND and eMMC together. I comes either with eMMC or NAND.
Opps, sorry, just realised that I added this comment in the wrong place. This is in relation to the following being added to pcl063-common.dtsi:
+ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + };
If there exists pcl063 modules that have eMMC and others that have NAND using the same pins, then this configuration is not common and therefore shouldn't be in pcl063-common.dtsi. Is it dependent on the flavour of i.MX used? If so I'd suggest the gpmi config needs to be pulled out into imx6ul-phycore-segin.dts and the usdhc2 config needs to be in imx6ull-phycore-segin.dts.
pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0 b0b1 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0 b0b1 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0 b0b1 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0 b0b1 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0 b0b1 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0 b0b1 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0 b0b1 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0 b0b1 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0 b0b1 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0 b0b1 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0 b0b1 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0 b0b1 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0 b0b1 >; };
static struct fsl_esdhc_cfg usdhc_cfg[] = { { .esdhc_base = USDHC1_BASE_ADDR, .max_bus_width = 4, }, +#ifndef CONFIG_NAND_MXS
- {
.esdhc_base = USDHC2_BASE_ADDR,.max_bus_width = 8,- },
+#endif };
int board_mmc_getcd(struct mmc *mmc) @@ -131,12 +153,58 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis) {
- imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
ARRAY_SIZE(usdhc1_pads));
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
- int i, ret;
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
This breaks for the existing phycore_pcl063_defconfig:
Ah, I missed it. I will add CONFIG_SYS_FSL_USDHC_NUM to 1 in phycore_pcl063_defconfig.
Thanks, Parthiban N
board/phytec/pcl063/spl.c: In function ‘board_mmc_init’: board/phytec/pcl063/spl.c:158:18: error: ‘CONFIG_SYS_FSL_USDHC_NUM’ undeclared (first use in this function); did you mean ‘CONFIG_SYS_FSL_ESDHC_ADDR’? for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { ^~~~~~~~~~~~~~~~~~~~~~~~
Martyn
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Hello Martyn,
On 4/9/19 10:49 AM, Martyn Welch wrote:
On Mon, 2019-04-08 at 20:04 +0200, Parthiban wrote:
Hello Martyn,
On 4/8/19 7:45 PM, Martyn Welch wrote:
On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote:
diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c index b93cd493f2..73a774645d 100644 --- a/board/phytec/pcl063/spl.c +++ b/board/phytec/pcl063/spl.c @@ -13,6 +13,7 @@ #include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> #include <fsl_esdhc.h>
/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */ @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), };
+#ifndef CONFIG_NAND_MXS +static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_NAND_RE_B__USDHC2_CLK |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_WE_B__USDHC2_CMD |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif
Umm, these pins are already used a few lines up for the NAND, via gpmi:
I understand. But pcl063 can't co-exit with NAND and eMMC together. I comes either with eMMC or NAND.
Opps, sorry, just realised that I added this comment in the wrong place. This is in relation to the following being added to pcl063-common.dtsi:
pinctrl_usdhc2: usdhc2grp {fsl,pins = <MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9>;};If there exists pcl063 modules that have eMMC and others that have NAND using the same pins, then this configuration is not common and therefore shouldn't be in pcl063-common.dtsi. Is it dependent on the flavour of i.MX used? If so I'd suggest the gpmi config needs to be pulled out into imx6ul-phycore-segin.dts and the usdhc2 config needs to be in imx6ull-phycore-segin.dts.
From phytec I understand that pcl063 SoM is a common platform for imx6UL and imx6ULL. This can either be shipped with eMMC or NAND, but not both.
So there exist a possibility that phytec can provide imx6UL with eMMC as well. IMO, both pinmux detailing for NAND and eMMC should still reside in common.dtsi.
Creating multiple common.dtsi based on these variants is not friendly. So I suggest to keep these changes in common.dtsi as such and decide in board dts whether to enable or disable usdhc1, usdhc2 explicitly.
pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0 b0b1 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0 b0b1 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0 b0b1 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0 b0b1 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0 b0b1 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0 b0b1 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0 b0b1 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0 b0b1 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0 b0b1 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0 b0b1 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0 b0b1 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0 b0b1 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0 b0b1 >; };
static struct fsl_esdhc_cfg usdhc_cfg[] = { { .esdhc_base = USDHC1_BASE_ADDR, .max_bus_width = 4, }, +#ifndef CONFIG_NAND_MXS
- {
.esdhc_base = USDHC2_BASE_ADDR,.max_bus_width = 8,- },
+#endif };
int board_mmc_getcd(struct mmc *mmc) @@ -131,12 +153,58 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis) {
- imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
ARRAY_SIZE(usdhc1_pads));
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
- int i, ret;
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
This breaks for the existing phycore_pcl063_defconfig:
Ah, I missed it. I will add CONFIG_SYS_FSL_USDHC_NUM to 1 in phycore_pcl063_defconfig.
Thanks, Parthiban N
board/phytec/pcl063/spl.c: In function ‘board_mmc_init’: board/phytec/pcl063/spl.c:158:18: error: ‘CONFIG_SYS_FSL_USDHC_NUM’ undeclared (first use in this function); did you mean ‘CONFIG_SYS_FSL_ESDHC_ADDR’? for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { ^~~~~~~~~~~~~~~~~~~~~~~~
Martyn
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
On Tue, 2019-04-09 at 11:30 +0200, Parthiban Nallathambi wrote:
Hello Martyn,
On 4/9/19 10:49 AM, Martyn Welch wrote:
On Mon, 2019-04-08 at 20:04 +0200, Parthiban wrote:
Hello Martyn,
On 4/8/19 7:45 PM, Martyn Welch wrote:
On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote:
diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c index b93cd493f2..73a774645d 100644 --- a/board/phytec/pcl063/spl.c +++ b/board/phytec/pcl063/spl.c @@ -13,6 +13,7 @@ #include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> #include <fsl_esdhc.h>
/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */ @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), };
+#ifndef CONFIG_NAND_MXS +static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_NAND_RE_B__USDHC2_CLK |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_WE_B__USDHC2_CMD |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif
Umm, these pins are already used a few lines up for the NAND, via gpmi:
I understand. But pcl063 can't co-exit with NAND and eMMC together. I comes either with eMMC or NAND.
Opps, sorry, just realised that I added this comment in the wrong place. This is in relation to the following being added to pcl063-common.dtsi:
pinctrl_usdhc2: usdhc2grp {fsl,pins = <MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
>;};If there exists pcl063 modules that have eMMC and others that have NAND using the same pins, then this configuration is not common and therefore shouldn't be in pcl063-common.dtsi. Is it dependent on the flavour of i.MX used? If so I'd suggest the gpmi config needs to be pulled out into imx6ul-phycore-segin.dts and the usdhc2 config needs to be in imx6ull-phycore-segin.dts.
From phytec I understand that pcl063 SoM is a common platform for imx6UL and imx6ULL. This can either be shipped with eMMC or NAND, but not both.
Looking a bit deeper, this seems a little odd as the product description suggests that NAND is provided onboard and 2 SD/SDIO/MMC connections are provided to the edge connector of the pcl063 for expansion.
The schematic suggests the only way they could achieve eMMC onboard would be with an eMMC that is pin compatible with the NAND they use.
Additionally, looking at the DTBs for this board in Phytec's own kernel tree, the only use of usdhc2 that I can see is for their WLAN expansion board[1] and I would have expected their tree to have supported such an option if it was available (they seem to have gone to some length to support a lot of configurations there).
Are you sure that the eMMC is provided on the pcl063 and not off board?
(CCing Wadim who might be able to shed some light on this)
So there exist a possibility that phytec can provide imx6UL with eMMC as well. IMO, both pinmux detailing for NAND and eMMC should still reside in common.dtsi.
Assuming Phytec do in fact sell a pcl0063 with eMMC on board, the DTB describes the hardware. You've said Phytec provide the board either with eMMC *or* NAND. The device tree, as used on a specific board, should show either the existence of NAND or eMMC.
I suspect having both options in the common file is going to lead to issues with the pinmuxing for one or the other option. The pins can't be muxed for both simultaneously, hence these need to be described in separate files.
Creating multiple common.dtsi based on these variants is not friendly. So I suggest to keep these changes in common.dtsi as such and decide in board dts whether to enable or disable usdhc1, usdhc2 explicitly.
This isn't about the selection of usdhc1 or usdhc2, it's whether gpmi or usdhc2 is using the pins of the SOC.
Martyn
[1] https://git.phytec.de/linux-mainline/tree/arch/arm/boot/dts/imx6ul-phytec-pe...
pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < MX6UL_PAD_NAND_CLE__RAWNAND_CLE0x0 b0b1 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0 b0b1 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0 b0b1 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_ B 0x0b000 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0 b0b1 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0 b0b1 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0 b0b1 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0 b0b1 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0 b0b1 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0 b0b1 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0 b0b1 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0 b0b1 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0 b0b1 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0 b0b1 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0 b0b1 >; };
Hello Martyn,
On 4/9/19 12:46 PM, Martyn Welch wrote:
On Tue, 2019-04-09 at 11:30 +0200, Parthiban Nallathambi wrote:
Hello Martyn,
On 4/9/19 10:49 AM, Martyn Welch wrote:
On Mon, 2019-04-08 at 20:04 +0200, Parthiban wrote:
Hello Martyn,
On 4/8/19 7:45 PM, Martyn Welch wrote:
On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote:
diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c index b93cd493f2..73a774645d 100644 --- a/board/phytec/pcl063/spl.c +++ b/board/phytec/pcl063/spl.c @@ -13,6 +13,7 @@ #include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> #include <fsl_esdhc.h>
/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */ @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), };
+#ifndef CONFIG_NAND_MXS +static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_NAND_RE_B__USDHC2_CLK |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_WE_B__USDHC2_CMD |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif
Umm, these pins are already used a few lines up for the NAND, via gpmi:
I understand. But pcl063 can't co-exit with NAND and eMMC together. I comes either with eMMC or NAND.
Opps, sorry, just realised that I added this comment in the wrong place. This is in relation to the following being added to pcl063-common.dtsi:
pinctrl_usdhc2: usdhc2grp {fsl,pins = <MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
>;};If there exists pcl063 modules that have eMMC and others that have NAND using the same pins, then this configuration is not common and therefore shouldn't be in pcl063-common.dtsi. Is it dependent on the flavour of i.MX used? If so I'd suggest the gpmi config needs to be pulled out into imx6ul-phycore-segin.dts and the usdhc2 config needs to be in imx6ull-phycore-segin.dts.
From phytec I understand that pcl063 SoM is a common platform for imx6UL and imx6ULL. This can either be shipped with eMMC or NAND, but not both.
Looking a bit deeper, this seems a little odd as the product description suggests that NAND is provided onboard and 2 SD/SDIO/MMC connections are provided to the edge connector of the pcl063 for expansion.
The schematic suggests the only way they could achieve eMMC onboard would be with an eMMC that is pin compatible with the NAND they use.
Additionally, looking at the DTBs for this board in Phytec's own kernel tree, the only use of usdhc2 that I can see is for their WLAN expansion board[1] and I would have expected their tree to have supported such an option if it was available (they seem to have gone to some length to support a lot of configurations there).
Are you sure that the eMMC is provided on the pcl063 and not off board?
Yes, I have this SoM with me and the changes are tested in it already. Pinmuxing details are based on phytec's barebox which is yet to be in mainline [1].
Phytec already published the booting from eMMC option and configurations which are needed in the hardware level here [2].
(CCing Wadim who might be able to shed some light on this)
So there exist a possibility that phytec can provide imx6UL with eMMC as well. IMO, both pinmux detailing for NAND and eMMC should still reside in common.dtsi.
Assuming Phytec do in fact sell a pcl0063 with eMMC on board, the DTB describes the hardware. You've said Phytec provide the board either with eMMC *or* NAND. The device tree, as used on a specific board, should show either the existence of NAND or eMMC.
I suspect having both options in the common file is going to lead to issues with the pinmuxing for one or the other option. The pins can't be muxed for both simultaneously, hence these need to be described in separate files.
I understand, does it makes sense to move the NAND to ul.dts and eMMC to ull.dts? But consider that there will be UL board with eMMC, which results in duplication of same pinmux details in all the board files.
pcl063-common should address the details about the SoM alone. So should we create another dtsi which can be included based on the SoM?
Creating multiple common.dtsi based on these variants is not friendly. So I suggest to keep these changes in common.dtsi as such and decide in board dts whether to enable or disable usdhc1, usdhc2 explicitly.
This isn't about the selection of usdhc1 or usdhc2, it's whether gpmi or usdhc2 is using the pins of the SOC.
Typo, selection between gpmi and usdhc2 is what I meant. So the board dts imx6ul-phycore-segin.dts with gpmi enabled + usdhc2 disabled and imx6ull-phycore-segin.dts with gpmi disabled + usdhc2 enabled.
Thanks, Parthiban N
[1] https://git.phytec.de/barebox/tree/arch/arm/dts/imx6ul-phytec-phycore-som.dt... [2] https://www.phytec.de/fileadmin/user_upload/images/content/1.Products/SOMs/p...
Martyn
[1] https://git.phytec.de/linux-mainline/tree/arch/arm/boot/dts/imx6ul-phytec-pe...
pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < MX6UL_PAD_NAND_CLE__RAWNAND_CLE0x0 b0b1 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0 b0b1 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0 b0b1 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_ B 0x0b000 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0 b0b1 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0 b0b1 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0 b0b1 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0 b0b1 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0 b0b1 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0 b0b1 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0 b0b1 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0 b0b1 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0 b0b1 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0 b0b1 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0 b0b1 >; };
Martyn,
On 09.04.19 12:46, Martyn Welch wrote:
On Tue, 2019-04-09 at 11:30 +0200, Parthiban Nallathambi wrote:
Hello Martyn,
On 4/9/19 10:49 AM, Martyn Welch wrote:
On Mon, 2019-04-08 at 20:04 +0200, Parthiban wrote:
Hello Martyn,
On 4/8/19 7:45 PM, Martyn Welch wrote:
On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote:
diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c index b93cd493f2..73a774645d 100644 --- a/board/phytec/pcl063/spl.c +++ b/board/phytec/pcl063/spl.c @@ -13,6 +13,7 @@ #include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> #include <fsl_esdhc.h>
/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */ @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), };
+#ifndef CONFIG_NAND_MXS +static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_NAND_RE_B__USDHC2_CLK |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_WE_B__USDHC2_CMD |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA00__USDHC2_DATA0 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA01__USDHC2_DATA1 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA02__USDHC2_DATA2 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA04__USDHC2_DATA4 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA05__USDHC2_DATA5 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA06__USDHC2_DATA6 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA07__USDHC2_DATA7 |
MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif
Umm, these pins are already used a few lines up for the NAND, via gpmi:
I understand. But pcl063 can't co-exit with NAND and eMMC together. I comes either with eMMC or NAND.
Opps, sorry, just realised that I added this comment in the wrong place. This is in relation to the following being added to pcl063-common.dtsi:
pinctrl_usdhc2: usdhc2grp {fsl,pins = <MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
>;};If there exists pcl063 modules that have eMMC and others that have NAND using the same pins, then this configuration is not common and therefore shouldn't be in pcl063-common.dtsi. Is it dependent on the flavour of i.MX used? If so I'd suggest the gpmi config needs to be pulled out into imx6ul-phycore-segin.dts and the usdhc2 config needs to be in imx6ull-phycore-segin.dts.
From phytec I understand that pcl063 SoM is a common platform for imx6UL and imx6ULL. This can either be shipped with eMMC or NAND, but not both.
This is correct. There are PCL-063 SOMs with eMMC or NAND. And each PCL-063 can be a 6UL or 6ULL.
Looking a bit deeper, this seems a little odd as the product description suggests that NAND is provided onboard and 2 SD/SDIO/MMC connections are provided to the edge connector of the pcl063 for expansion.
The schematic suggests the only way they could achieve eMMC onboard would be with an eMMC that is pin compatible with the NAND they use.
eMMC is connected via usdhc2. The usdhc2 pins conflict with the gpmi pins.
Additionally, looking at the DTBs for this board in Phytec's own kernel tree, the only use of usdhc2 that I can see is for their WLAN expansion board[1] and I would have expected their tree to have supported such an option if it was available (they seem to have gone to some length to support a lot of configurations there).
Are you sure that the eMMC is provided on the pcl063 and not off board?
eMMC is on the PCL-063 and not on a carrier board.
(CCing Wadim who might be able to shed some light on this)
So there exist a possibility that phytec can provide imx6UL with eMMC as well. IMO, both pinmux detailing for NAND and eMMC should still reside in common.dtsi.
Assuming Phytec do in fact sell a pcl0063 with eMMC on board, the DTB describes the hardware. You've said Phytec provide the board either with eMMC *or* NAND. The device tree, as used on a specific board, should show either the existence of NAND or eMMC.
AFAIK, the idea was to put the muxing for both flash devices in the pcl063-som.dtsi and keep them disabled. eMMC or NAND will be then enabled in a higher level carrier board dts file. The handling of the SOM variant is designed by the carrier board dts file name, e.g. imx6ul-phytec-segin-ff-rdk-nand.dts and in theory a imx6ul-phytec-segin-ff-rdk-emmc.dts (Right now there is no 6UL eMMC SOM variant, so you can not find it in our kernel repository).
I agree, that this does not describe the SOM hardware. This is just the way we handle the SOM variants.
It seems the upstream situation for kernel and u-boot differs to what we did quite a lot at the moment. I am just curious how you want to handle this now. Unfortunately, we did no had the time to bring our 6UL boards upstream and clarify the situation. But we can talk about it now and find out a way to handle the variants properly.
CC'ed Stefan who is maintaining the imx6 boards at Phytec.
I hope this helps :)
Regards, Wadim
I suspect having both options in the common file is going to lead to issues with the pinmuxing for one or the other option. The pins can't be muxed for both simultaneously, hence these need to be described in separate files.
Creating multiple common.dtsi based on these variants is not friendly. So I suggest to keep these changes in common.dtsi as such and decide in board dts whether to enable or disable usdhc1, usdhc2 explicitly.
This isn't about the selection of usdhc1 or usdhc2, it's whether gpmi or usdhc2 is using the pins of the SOC.
Martyn
[1] https://git.phytec.de/linux-mainline/tree/arch/arm/boot/dts/imx6ul-phytec-pe...
pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < MX6UL_PAD_NAND_CLE__RAWNAND_CLE0x0 b0b1 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0 b0b1 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0 b0b1 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_ B 0x0b000 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0 b0b1 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0 b0b1 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0 b0b1 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0 b0b1 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0 b0b1 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0 b0b1 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0 b0b1 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0 b0b1 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0 b0b1 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0 b0b1 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0 b0b1 >; };
Hello Wadim,
Thanks for sharing the details.
On 4/10/19 10:35 AM, Wadim Egorov wrote:
Martyn,
On 09.04.19 12:46, Martyn Welch wrote:
On Tue, 2019-04-09 at 11:30 +0200, Parthiban Nallathambi wrote:
Hello Martyn,
On 4/9/19 10:49 AM, Martyn Welch wrote:
On Mon, 2019-04-08 at 20:04 +0200, Parthiban wrote:
Hello Martyn,
On 4/8/19 7:45 PM, Martyn Welch wrote:
On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote: > diff --git a/board/phytec/pcl063/spl.c > b/board/phytec/pcl063/spl.c > index b93cd493f2..73a774645d 100644 > --- a/board/phytec/pcl063/spl.c > +++ b/board/phytec/pcl063/spl.c > @@ -13,6 +13,7 @@ > #include <asm/arch/mx6-ddr.h> > #include <asm/arch/mx6-pins.h> > #include <asm/arch/crm_regs.h> > +#include <asm/arch/sys_proto.h> > #include <fsl_esdhc.h> > > /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x > 16 x 8 > -> > 256MiB */ > @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const > usdhc1_pads[] = > { > MX6_PAD_UART1_RTS_B__USDHC1_CD_B | > MUX_PAD_CTRL(USDHC_PAD_CTRL), > }; > > +#ifndef CONFIG_NAND_MXS > +static iomux_v3_cfg_t const usdhc2_pads[] = { > + MX6_PAD_NAND_RE_B__USDHC2_CLK | > MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_WE_B__USDHC2_CMD | > MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | > MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | > MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | > MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | > MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | > MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | > MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | > MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | > MUX_PAD_CTRL(USDHC_PAD_CTRL), > +}; > +#endif > + Umm, these pins are already used a few lines up for the NAND, via gpmi:
I understand. But pcl063 can't co-exit with NAND and eMMC together. I comes either with eMMC or NAND.
Opps, sorry, just realised that I added this comment in the wrong place. This is in relation to the following being added to pcl063-common.dtsi:
pinctrl_usdhc2: usdhc2grp {fsl,pins = <MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
>;};If there exists pcl063 modules that have eMMC and others that have NAND using the same pins, then this configuration is not common and therefore shouldn't be in pcl063-common.dtsi. Is it dependent on the flavour of i.MX used? If so I'd suggest the gpmi config needs to be pulled out into imx6ul-phycore-segin.dts and the usdhc2 config needs to be in imx6ull-phycore-segin.dts.
From phytec I understand that pcl063 SoM is a common platform for imx6UL and imx6ULL. This can either be shipped with eMMC or NAND, but not both.
This is correct. There are PCL-063 SOMs with eMMC or NAND. And each PCL-063 can be a 6UL or 6ULL.
Looking a bit deeper, this seems a little odd as the product description suggests that NAND is provided onboard and 2 SD/SDIO/MMC connections are provided to the edge connector of the pcl063 for expansion.
The schematic suggests the only way they could achieve eMMC onboard would be with an eMMC that is pin compatible with the NAND they use.
eMMC is connected via usdhc2. The usdhc2 pins conflict with the gpmi pins.
Additionally, looking at the DTBs for this board in Phytec's own kernel tree, the only use of usdhc2 that I can see is for their WLAN expansion board[1] and I would have expected their tree to have supported such an option if it was available (they seem to have gone to some length to support a lot of configurations there).
Are you sure that the eMMC is provided on the pcl063 and not off board?
eMMC is on the PCL-063 and not on a carrier board.
(CCing Wadim who might be able to shed some light on this)
So there exist a possibility that phytec can provide imx6UL with eMMC as well. IMO, both pinmux detailing for NAND and eMMC should still reside in common.dtsi.
Assuming Phytec do in fact sell a pcl0063 with eMMC on board, the DTB describes the hardware. You've said Phytec provide the board either with eMMC *or* NAND. The device tree, as used on a specific board, should show either the existence of NAND or eMMC.
AFAIK, the idea was to put the muxing for both flash devices in the pcl063-som.dtsi and keep them disabled. eMMC or NAND will be then enabled in a higher level carrier board dts file. The handling of the SOM variant is designed by the carrier board dts file name, e.g. imx6ul-phytec-segin-ff-rdk-nand.dts and in theory a imx6ul-phytec-segin-ff-rdk-emmc.dts (Right now there is no 6UL eMMC SOM variant, so you can not find it in our kernel repository).
I agree to place both gpmi and eMMC pinmux details in common.dtsi with default "disabled" and enable them only in board dts.
@Martyn, please advise.
Thanks, Parthiban N
I agree, that this does not describe the SOM hardware. This is just the way we handle the SOM variants.
It seems the upstream situation for kernel and u-boot differs to what we did quite a lot at the moment. I am just curious how you want to handle this now. Unfortunately, we did no had the time to bring our 6UL boards upstream and clarify the situation. But we can talk about it now and find out a way to handle the variants properly.
CC'ed Stefan who is maintaining the imx6 boards at Phytec.
I hope this helps :)
Regards, Wadim
I suspect having both options in the common file is going to lead to issues with the pinmuxing for one or the other option. The pins can't be muxed for both simultaneously, hence these need to be described in separate files.
Creating multiple common.dtsi based on these variants is not friendly. So I suggest to keep these changes in common.dtsi as such and decide in board dts whether to enable or disable usdhc1, usdhc2 explicitly.
This isn't about the selection of usdhc1 or usdhc2, it's whether gpmi or usdhc2 is using the pins of the SOC.
Martyn
[1] https://git.phytec.de/linux-mainline/tree/arch/arm/boot/dts/imx6ul-phytec-pe...
pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < MX6UL_PAD_NAND_CLE__RAWNAND_CLE0x0 b0b1 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0 b0b1 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0 b0b1 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_ B 0x0b000 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0 b0b1 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0 b0b1 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0 b0b1 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0 b0b1 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0 b0b1 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0 b0b1 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0 b0b1 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0 b0b1 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0 b0b1 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0 b0b1 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0 b0b1 >; };
On Wed, 2019-04-10 at 15:23 +0200, Parthiban Nallathambi wrote:
Hello Wadim,
Thanks for sharing the details.
On 4/10/19 10:35 AM, Wadim Egorov wrote:
Martyn,
On 09.04.19 12:46, Martyn Welch wrote:
On Tue, 2019-04-09 at 11:30 +0200, Parthiban Nallathambi wrote:
Hello Martyn,
On 4/9/19 10:49 AM, Martyn Welch wrote:
On Mon, 2019-04-08 at 20:04 +0200, Parthiban wrote:
Hello Martyn,
On 4/8/19 7:45 PM, Martyn Welch wrote: > On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi > wrote: > > diff --git a/board/phytec/pcl063/spl.c > > b/board/phytec/pcl063/spl.c > > index b93cd493f2..73a774645d 100644 > > --- a/board/phytec/pcl063/spl.c > > +++ b/board/phytec/pcl063/spl.c > > @@ -13,6 +13,7 @@ > > #include <asm/arch/mx6-ddr.h> > > #include <asm/arch/mx6-pins.h> > > #include <asm/arch/crm_regs.h> > > +#include <asm/arch/sys_proto.h> > > #include <fsl_esdhc.h> > > > > /* Configuration for Micron MT41K256M16TW-107 IT:P, > > 32M x > > 16 x 8 > > -> > > 256MiB */ > > @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const > > usdhc1_pads[] = > > { > > MX6_PAD_UART1_RTS_B__USDHC1_CD_B | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > }; > > > > +#ifndef CONFIG_NAND_MXS > > +static iomux_v3_cfg_t const usdhc2_pads[] = { > > + MX6_PAD_NAND_RE_B__USDHC2_CLK | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > + MX6_PAD_NAND_WE_B__USDHC2_CMD | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > +}; > > +#endif > > + > Umm, these pins are already used a few lines up for the > NAND, > via > gpmi: I understand. But pcl063 can't co-exit with NAND and eMMC together. I comes either with eMMC or NAND.
Opps, sorry, just realised that I added this comment in the wrong place. This is in relation to the following being added to pcl063-common.dtsi:
pinctrl_usdhc2: usdhc2grp {fsl,pins = <MX6UL_PAD_NAND_WE_B__USDHC2_CMD70f9
MX6UL_PAD_NAND_RE_B__USDHC2_CLK00f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA070f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA270f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA370f9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA470f9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA570f9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA670f9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA770f9
>;};If there exists pcl063 modules that have eMMC and others that have NAND using the same pins, then this configuration is not common and therefore shouldn't be in pcl063-common.dtsi. Is it dependent on the flavour of i.MX used? If so I'd suggest the gpmi config needs to be pulled out into imx6ul-phycore-segin.dts and the usdhc2 config needs to be in imx6ull-phycore-segin.dts.
From phytec I understand that pcl063 SoM is a common platform for imx6UL and imx6ULL. This can either be shipped with eMMC or NAND, but not both.
This is correct. There are PCL-063 SOMs with eMMC or NAND. And each PCL-063 can be a 6UL or 6ULL.
Looking a bit deeper, this seems a little odd as the product description suggests that NAND is provided onboard and 2 SD/SDIO/MMC connections are provided to the edge connector of the pcl063 for expansion.
The schematic suggests the only way they could achieve eMMC onboard would be with an eMMC that is pin compatible with the NAND they use.
eMMC is connected via usdhc2. The usdhc2 pins conflict with the gpmi pins.
Additionally, looking at the DTBs for this board in Phytec's own kernel tree, the only use of usdhc2 that I can see is for their WLAN expansion board[1] and I would have expected their tree to have supported such an option if it was available (they seem to have gone to some length to support a lot of configurations there).
Are you sure that the eMMC is provided on the pcl063 and not off board?
eMMC is on the PCL-063 and not on a carrier board.
(CCing Wadim who might be able to shed some light on this)
So there exist a possibility that phytec can provide imx6UL with eMMC as well. IMO, both pinmux detailing for NAND and eMMC should still reside in common.dtsi.
Assuming Phytec do in fact sell a pcl0063 with eMMC on board, the DTB describes the hardware. You've said Phytec provide the board either with eMMC *or* NAND. The device tree, as used on a specific board, should show either the existence of NAND or eMMC.
AFAIK, the idea was to put the muxing for both flash devices in the pcl063-som.dtsi and keep them disabled. eMMC or NAND will be then enabled in a higher level carrier board dts file. The handling of the SOM variant is designed by the carrier board dts file name, e.g. imx6ul-phytec-segin-ff-rdk-nand.dts and in theory a imx6ul-phytec-segin-ff-rdk-emmc.dts (Right now there is no 6UL eMMC SOM variant, so you can not find it in our kernel repository).
I agree to place both gpmi and eMMC pinmux details in common.dtsi with default "disabled" and enable them only in board dts.
@Martyn, please advise.
Yes, that seems sensible.
Martyn
Thanks, Parthiban N
I agree, that this does not describe the SOM hardware. This is just the way we handle the SOM variants.
It seems the upstream situation for kernel and u-boot differs to what we did quite a lot at the moment. I am just curious how you want to handle this now. Unfortunately, we did no had the time to bring our 6UL boards upstream and clarify the situation. But we can talk about it now and find out a way to handle the variants properly.
CC'ed Stefan who is maintaining the imx6 boards at Phytec.
I hope this helps :)
Regards, Wadim
I suspect having both options in the common file is going to lead to issues with the pinmuxing for one or the other option. The pins can't be muxed for both simultaneously, hence these need to be described in separate files.
Creating multiple common.dtsi based on these variants is not friendly. So I suggest to keep these changes in common.dtsi as such and decide in board dts whether to enable or disable usdhc1, usdhc2 explicitly.
This isn't about the selection of usdhc1 or usdhc2, it's whether gpmi or usdhc2 is using the pins of the SOC.
Martyn
[1] https://git.phytec.de/linux-mainline/tree/arch/arm/boot/dts/imx6ul-phytec-pe...
> pinctrl_gpmi_nand: gpminandgrp { > fsl,pins = < > MX6UL_PAD_NAND_CLE__RAWNAND_CLE > 0x0 > b0b1 > MX6UL_PAD_NAND_ALE__RAWNAND_ALE > 0x0 > b0b1 > MX6UL_PAD_NAND_WP_B__RAWNAND_WP > _B > 0x0 > b0b1 > MX6UL_PAD_NAND_READY_B__RAWNAND > _READY_ > B > 0x0b000 > MX6UL_PAD_NAND_CE0_B__RAWNAND_C > E0_B > 0x0 > b0b1 > MX6UL_PAD_NAND_RE_B__RAWNAND_RE > _B > 0x0 > b0b1 > MX6UL_PAD_NAND_WE_B__RAWNAND_WE > _B > 0x0 > b0b1 > MX6UL_PAD_NAND_DATA00__RAWNAND_ > DATA00 > 0x0 > b0b1 > MX6UL_PAD_NAND_DATA01__RAWNAND_ > DATA01 > 0x0 > b0b1 > MX6UL_PAD_NAND_DATA02__RAWNAND_ > DATA02 > 0x0 > b0b1 > MX6UL_PAD_NAND_DATA03__RAWNAND_ > DATA03 > 0x0 > b0b1 > MX6UL_PAD_NAND_DATA04__RAWNAND_ > DATA04 > 0x0 > b0b1 > MX6UL_PAD_NAND_DATA05__RAWNAND_ > DATA05 > 0x0 > b0b1 > MX6UL_PAD_NAND_DATA06__RAWNAND_ > DATA06 > 0x0 > b0b1 > MX6UL_PAD_NAND_DATA07__RAWNAND_ > DATA07 > 0x0 > b0b1 > >; > }; >
participants (4)
-
Martyn Welch -
Parthiban -
Parthiban Nallathambi
-
Wadim Egorov