Hello all,

I'm having a couple of troubles on the MPC8540 on our board. It's derived from the MPC8540ADS board but we added a Spartan 3 FPGA with DDR memory on the local plus bus (with two chip selects for different memory windows in the fpga memory mapped driver) and we implemented a UPM (A) for 8 burst writes and reads on the bus. We're using U-Boot 1.2 and Linux 2.6.20.3. In debug, we can use Chipscope to view the local plus bus signals.

The problem is that every write burst that we issue generates an awful lot of read accesses to the same chip select / address range. We're clueless on what exactly is generating this. We've been thinking about caching issues, TLB setup, UPM misconfiguration, fishy driver code (memory mapped), or a fishy user application. Nothing of those seems wrong to us.

I was trying to get a write burst going to the FPGA from U-Boot but it seems that it only issues single word accesses on the bus. Is it actually possible to trigger the UPM burst sequencing at all from U-Boot?

If anyone had the same issues or something similar, I would like to know how you fixed it or how to debug it. I could give many more information or code snippets but I'll save that for later when someone has a good idea about what to check out.

To give a comparison about the bus access speeds to the local plus bus and the interface: our FPGA interface can give about 500Mpbs from FPGA DDR memory into the CPU's gigabit ethernet, but writing to the same memory is below 10Mbps due to the excessive reads.

I don't know if this list is actually the best option to get advice (maybe off topic), but I just don't know any better place to go.

Any help in this case is appreciated,

Regards, Gerrit Van de Velde