Move CONFIG_SYS_ARM_CACHE_WRITETHROUGH and CONFIG_SYS_ARM_CACHE_WRITEALLOC into Kconfig done by moveconfig.py.

Kconfig uses a choice between the 3 values supported in U-Boot, including the new configuration CONFIG_SYS_ARM_CACHE_WRITEBACK.

The patch also avoids to select simultaneously 2 configurations.

Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---

arch/arm/Kconfig | 27 +++++++++++++++++++++ arch/arm/include/asm/iproc-common/configs.h | 1 - configs/colibri_pxa270_defconfig | 1 + configs/grpeach_defconfig | 1 + include/configs/grpeach.h | 1 - include/configs/pxa-common.h | 2 -- scripts/config_whitelist.txt | 1 - 7 files changed, 29 insertions(+), 5 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index bbb1e2738b..4845a23993 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -340,6 +340,33 @@ config SYS_CACHELINE_SIZE default 64 if SYS_CACHE_SHIFT_6 default 32 if SYS_CACHE_SHIFT_5

+choice + prompt "Select the ARM data write cache policy" + default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || TARGET_BCMNSP + default SYS_ARM_CACHE_WRITEBACK + +config SYS_ARM_CACHE_WRITEBACK + bool "Write-back (WB)" + help + A write updates the cache only and marks the cache line as dirty. + External memory is updated only when the line is evicted or explicitly + cleaned. + +config SYS_ARM_CACHE_WRITETHROUGH + bool "Write-through (WT)" + help + A write updates both the cache and the external memory system. + This does not mark the cache line as dirty. + +config SYS_ARM_CACHE_WRITEALLOC + bool "Write allocation (WA)" + help + A cache line is allocated on a write miss. This means that executing a + store instruction on the processor might cause a burst read to occur. + There is a linefill to obtain the data for the cache line, before the + write is performed. +endchoice + config ARCH_CPU_INIT bool "Enable ARCH_CPU_INIT" help diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h index 96c4f54f4a..4733c0793c 100644 --- a/arch/arm/include/asm/iproc-common/configs.h +++ b/arch/arm/include/asm/iproc-common/configs.h @@ -10,7 +10,6 @@

/* Architecture, CPU, chip, etc */ #define CONFIG_IPROC -#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH

/* Memory Info */ #define CONFIG_SYS_SDRAM_BASE 0x61000000 diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig index 153ced707d..f18bda930b 100644 --- a/configs/colibri_pxa270_defconfig +++ b/configs/colibri_pxa270_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_SYS_ARM_CACHE_WRITETHROUGH=y CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_COLIBRI_PXA270=y CONFIG_SYS_TEXT_BASE=0x0 diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig index 99b656eb51..45cbb1619c 100644 --- a/configs/grpeach_defconfig +++ b/configs/grpeach_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_ARM_CACHE_WRITETHROUGH=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0x18000000 diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index b875f9b132..af5b92443e 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -16,7 +16,6 @@

/* Miscellaneous */ #define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH #define CONFIG_CMDLINE_TAG

/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ diff --git a/include/configs/pxa-common.h b/include/configs/pxa-common.h index e25800a095..2632d48cc9 100644 --- a/include/configs/pxa-common.h +++ b/include/configs/pxa-common.h @@ -8,8 +8,6 @@ #ifndef __CONFIG_PXA_COMMON_H__ #define __CONFIG_PXA_COMMON_H__

-#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH - /* * KGDB */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 6908431d03..0f747ac0a3 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1773,7 +1773,6 @@ CONFIG_SYS_AMASK4 CONFIG_SYS_AMASK5 CONFIG_SYS_AMASK6 CONFIG_SYS_AMASK7 -CONFIG_SYS_ARM_CACHE_WRITETHROUGH CONFIG_SYS_AT91_CPU_NAME CONFIG_SYS_AT91_MAIN_CLOCK CONFIG_SYS_AT91_PLLA