It is useful to be able to treat the different ranges of a regmap separately to be able to use distinct offset for them, but this is currently not implemented in the regmap API.

To preserve backwards compatibility, add regmap_read_range and regmap_write_range functions that take an additional parameter 'range_num' that identifies the range to operate on.

Reviewed-by: Anatolij Gustschin agust@denx.de Reviewed-by: Simon Glass sjg@chromium.org Signed-off-by: Mario Six mario.six@gdsys.cc

--- v10 -> v11: No changes

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v2 -> v3: * Renamed the functions to regmap_{write,read}_range * Added function comments * Fixed style violations * Improved error handling

v1 -> v2: New in v2 --- drivers/core/regmap.c | 49 ++++++++++++++++++++++++++++++++++++++----- include/regmap.h | 31 +++++++++++++++++++++++++++ 2 files changed, 75 insertions(+), 5 deletions(-)

diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index 916d9272ea..9b2e02af2e 100644 --- a/drivers/core/regmap.c +++ b/drivers/core/regmap.c @@ -188,11 +188,25 @@ int regmap_uninit(struct regmap *map) return 0; }

-int regmap_raw_read(struct regmap *map, uint offset, void *valp, size_t val_len) +int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset, + void *valp, size_t val_len) { + struct regmap_range *range; void *ptr;

- ptr = map_physmem(map->ranges[0].start + offset, val_len, MAP_NOCACHE); + if (range_num >= map->range_count) { + debug("%s: range index %d larger than range count\n", + __func__, range_num); + return -ERANGE; + } + range = &map->ranges[range_num]; + + ptr = map_physmem(range->start + offset, val_len, MAP_NOCACHE); + + if (offset + val_len > range->size) { + debug("%s: offset/size combination invalid\n", __func__); + return -ERANGE; + }

switch (val_len) { case REGMAP_SIZE_8: @@ -213,20 +227,39 @@ int regmap_raw_read(struct regmap *map, uint offset, void *valp, size_t val_len) debug("%s: regmap size %zu unknown\n", __func__, val_len); return -EINVAL; } + return 0; }

+int regmap_raw_read(struct regmap *map, uint offset, void *valp, size_t val_len) +{ + return regmap_raw_read_range(map, 0, offset, valp, val_len); +} + int regmap_read(struct regmap *map, uint offset, uint *valp) { return regmap_raw_read(map, offset, valp, REGMAP_SIZE_32); }

-int regmap_raw_write(struct regmap *map, uint offset, const void *val, - size_t val_len) +int regmap_raw_write_range(struct regmap *map, uint range_num, uint offset, + const void *val, size_t val_len) { + struct regmap_range *range; void *ptr;

- ptr = map_physmem(map->ranges[0].start + offset, val_len, MAP_NOCACHE); + if (range_num >= map->range_count) { + debug("%s: range index %d larger than range count\n", + __func__, range_num); + return -ERANGE; + } + range = &map->ranges[range_num]; + + ptr = map_physmem(range->start + offset, val_len, MAP_NOCACHE); + + if (offset + val_len > range->size) { + debug("%s: offset/size combination invalid\n", __func__); + return -ERANGE; + }

switch (val_len) { case REGMAP_SIZE_8: @@ -251,6 +284,12 @@ int regmap_raw_write(struct regmap *map, uint offset, const void *val, return 0; }

+int regmap_raw_write(struct regmap *map, uint offset, const void *val, + size_t val_len) +{ + return regmap_raw_write_range(map, 0, offset, val, val_len); +} + int regmap_write(struct regmap *map, uint offset, uint val) { return regmap_raw_write(map, offset, &val, REGMAP_SIZE_32); diff --git a/include/regmap.h b/include/regmap.h index f23664e8ba..eba300da29 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -115,6 +115,37 @@ int regmap_raw_write(struct regmap *map, uint offset, const void *val, int regmap_raw_read(struct regmap *map, uint offset, void *valp, size_t val_len);

+/** + * regmap_raw_write_range() - Write a value of specified length to a range of a + * regmap + * + * @map: Regmap to write to + * @range_num: Number of the range in the regmap to write to + * @offset: Offset in the regmap to write to + * @val: Value to write to the regmap at the specified offset + * @val_len: Length of the data to be written to the regmap + * + * Return: 0 if OK, -ve on error + */ +int regmap_raw_write_range(struct regmap *map, uint range_num, uint offset, + const void *val, size_t val_len); + +/** + * regmap_raw_read_range() - Read a value of specified length from a range of a + * regmap + * + * @map: Regmap to read from + * @range_num: Number of the range in the regmap to write to + * @offset: Offset in the regmap to read from + * @valp: Pointer to the buffer to receive the data read from the regmap + * at the specified offset + * @val_len: Length of the data to be read from the regmap + * + * Return: 0 if OK, -ve on error + */ +int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset, + void *valp, size_t val_len); + #define regmap_write32(map, ptr, member, val) \ regmap_write(map, (uint32_t *)(ptr)->member - (uint32_t *)(ptr), val)

-- 2.18.1

It would be convenient if one could use the regmap API in conjunction with register maps defined as structs (i.e. structs that directly mirror the memory layout of the registers in question). A similar approach was planned with the regmap_write32/regmap_read32 macros, but was never used.

Hence, implement regmap_set/regmap_range_set and regmap_get/regmap_range_get macros, which, given a register map, a struct describing the layout of the register map, and a member name automatically produce regmap_read/regmap_write calls that access the specified member in the register map.

Reviewed-by: Anatolij Gustschin agust@denx.de Reviewed-by: Simon Glass sjg@chromium.org Signed-off-by: Mario Six mario.six@gdsys.cc

--- v10 -> v11: No changes

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v2 -> v3: * Fixed style violations * Added documentation

v1 -> v2: New in v2 --- include/regmap.h | 54 ++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 50 insertions(+), 4 deletions(-)

diff --git a/include/regmap.h b/include/regmap.h index eba300da29..3b7eea5f49 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -146,11 +146,57 @@ int regmap_raw_write_range(struct regmap *map, uint range_num, uint offset, int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset, void *valp, size_t val_len);

-#define regmap_write32(map, ptr, member, val) \ - regmap_write(map, (uint32_t *)(ptr)->member - (uint32_t *)(ptr), val) +/** + * regmap_range_set() - Set a value in a regmap range described by a struct + * @map: Regmap in which a value should be set + * @range: Range of the regmap in which a value should be set + * @type: Structure type that describes the memory layout of the regmap range + * @member: Member of the describing structure that should be set in the regmap + * range + * @val: Value which should be written to the regmap range + */ +#define regmap_range_set(map, range, type, member, val) \ + do { \ + typeof(((type *)0)->member) __tmp = val; \ + regmap_raw_write_range(map, range, offsetof(type, member), \ + &__tmp, sizeof(((type *)0)->member)); \ + } while (0) + +/** + * regmap_set() - Set a value in a regmap described by a struct + * @map: Regmap in which a value should be set + * @type: Structure type that describes the memory layout of the regmap + * @member: Member of the describing structure that should be set in the regmap + * @val: Value which should be written to the regmap + */ +#define regmap_set(map, type, member, val) \ + regmap_range_set(map, 0, type, member, val)

-#define regmap_read32(map, ptr, member, valp) \ - regmap_read(map, (uint32_t *)(ptr)->member - (uint32_t *)(ptr), valp) +/** + * regmap_range_get() - Get a value from a regmap range described by a struct + * @map: Regmap from which a value should be read + * @range: Range of the regmap from which a value should be read + * @type: Structure type that describes the memory layout of the regmap + * range + * @member: Member of the describing structure that should be read in the + * regmap range + * @valp: Variable that receives the value read from the regmap range + */ +#define regmap_range_get(map, range, type, member, valp) \ + regmap_raw_read_range(map, range, offsetof(type, member), \ + (void *)valp, sizeof(((type *)0)->member)) + +/** + * regmap_get() - Get a value from a regmap described by a struct + * @map: Regmap from which a value should be read + * @type: Structure type that describes the memory layout of the regmap + * range + * @member: Member of the describing structure that should be read in the + * regmap + * @valp: Variable that receives the value read from the regmap + */ +#define regmap_get(map, type, member, valp) \ + regmap_range_get(map, 0, type, member, valp)

/** * regmap_update_bits() - Perform a read/modify/write using a mask -- 2.18.1

Add test for regmap_{set,get} functions.

Reviewed-by: Anatolij Gustschin agust@denx.de Reviewed-by: Simon Glass sjg@chromium.org Signed-off-by: Mario Six mario.six@gdsys.cc

--- v10 -> v11: No changes

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v2 -> v3: New in v3 --- test/dm/regmap.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)

diff --git a/test/dm/regmap.c b/test/dm/regmap.c index b28d6a6cd1..a8d7e6829e 100644 --- a/test/dm/regmap.c +++ b/test/dm/regmap.c @@ -116,3 +116,31 @@ static int dm_test_regmap_rw(struct unit_test_state *uts) }

DM_TEST(dm_test_regmap_rw, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Get/Set test */ +static int dm_test_regmap_getset(struct unit_test_state *uts) +{ + struct udevice *dev; + struct regmap *map; + uint reg; + struct layout { + u32 val0; + u32 val1; + u32 val2; + u32 val3; + }; + + ut_assertok(uclass_get_device(UCLASS_SYSCON, 0, &dev)); + map = syscon_get_regmap(dev); + ut_assertok_ptr(map); + + regmap_set(map, struct layout, val0, 0xcacafafa); + regmap_set(map, struct layout, val3, 0x55aa2211); + + ut_assertok(regmap_get(map, struct layout, val0, &reg)); + ut_assertok(regmap_get(map, struct layout, val3, &reg)); + + return 0; +} + +DM_TEST(dm_test_regmap_getset, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); -- 2.18.1

Add support for switching the endianness of regmap accesses via the "little-endian", "big-endian", and "native-endian" boolean properties in the device tree.

The default endianness is native endianness.

Signed-off-by: Mario Six mario.six@gdsys.cc Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com

--- v10 -> v11: * Added more #ifdef tests for 64-bit case to resolve compilation issues

v9 -> v10: * Switched to readb/writeb for 8-bit reads/writes

v8 -> v9: New in v9 --- drivers/core/regmap.c | 134 ++++++++++++++++++++++++++++++++++++++---- include/regmap.h | 14 +++++ 2 files changed, 138 insertions(+), 10 deletions(-)

diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index 9b2e02af2e..5ef0f71c8b 100644 --- a/drivers/core/regmap.c +++ b/drivers/core/regmap.c @@ -164,6 +164,15 @@ int regmap_init_mem(ofnode node, struct regmap **mapp) return ret; }

+ if (ofnode_read_bool(node, "little-endian")) + map->endianness = REGMAP_LITTLE_ENDIAN; + else if (ofnode_read_bool(node, "big-endian")) + map->endianness = REGMAP_BIG_ENDIAN; + else if (ofnode_read_bool(node, "native-endian")) + map->endianness = REGMAP_NATIVE_ENDIAN; + else /* Default: native endianness */ + map->endianness = REGMAP_NATIVE_ENDIAN; + *mapp = map;

return 0; @@ -188,6 +197,55 @@ int regmap_uninit(struct regmap *map) return 0; }

+static inline u8 __read_8(u8 *addr, enum regmap_endianness_t endianness) +{ + return readb(addr); +} + +static inline u16 __read_16(u16 *addr, enum regmap_endianness_t endianness) +{ + switch (endianness) { + case REGMAP_LITTLE_ENDIAN: + return in_le16(addr); + case REGMAP_BIG_ENDIAN: + return in_be16(addr); + case REGMAP_NATIVE_ENDIAN: + return readw(addr); + } + + return readw(addr); +} + +static inline u32 __read_32(u32 *addr, enum regmap_endianness_t endianness) +{ + switch (endianness) { + case REGMAP_LITTLE_ENDIAN: + return in_le32(addr); + case REGMAP_BIG_ENDIAN: + return in_be32(addr); + case REGMAP_NATIVE_ENDIAN: + return readl(addr); + } + + return readl(addr); +} + +#if defined(in_le64) && defined(in_be64) && defined(readq) +static inline u64 __read_64(u64 *addr, enum regmap_endianness_t endianness) +{ + switch (endianness) { + case REGMAP_LITTLE_ENDIAN: + return in_le64(addr); + case REGMAP_BIG_ENDIAN: + return in_be64(addr); + case REGMAP_NATIVE_ENDIAN: + return readq(addr); + } + + return readq(addr); +} +#endif + int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset, void *valp, size_t val_len) { @@ -210,17 +268,17 @@ int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset,

switch (val_len) { case REGMAP_SIZE_8: - *((u8 *)valp) = readb((u8 *)ptr); + *((u8 *)valp) = __read_8(ptr, map->endianness); break; case REGMAP_SIZE_16: - *((u16 *)valp) = readw((u16 *)ptr); + *((u16 *)valp) = __read_16(ptr, map->endianness); break; case REGMAP_SIZE_32: - *((u32 *)valp) = readl((u32 *)ptr); + *((u32 *)valp) = __read_32(ptr, map->endianness); break; -#if defined(readq) +#if defined(in_le64) && defined(in_be64) && defined(readq) case REGMAP_SIZE_64: - *((u64 *)valp) = readq((u64 *)ptr); + *((u64 *)valp) = __read_64(ptr, map->endianness); break; #endif default: @@ -241,6 +299,62 @@ int regmap_read(struct regmap *map, uint offset, uint *valp) return regmap_raw_read(map, offset, valp, REGMAP_SIZE_32); }

+static inline void __write_8(u8 *addr, const u8 *val, + enum regmap_endianness_t endianness) +{ + writeb(*val, addr); +} + +static inline void __write_16(u16 *addr, const u16 *val, + enum regmap_endianness_t endianness) +{ + switch (endianness) { + case REGMAP_NATIVE_ENDIAN: + writew(*val, addr); + break; + case REGMAP_LITTLE_ENDIAN: + out_le16(addr, *val); + break; + case REGMAP_BIG_ENDIAN: + out_be16(addr, *val); + break; + } +} + +static inline void __write_32(u32 *addr, const u32 *val, + enum regmap_endianness_t endianness) +{ + switch (endianness) { + case REGMAP_NATIVE_ENDIAN: + writel(*val, addr); + break; + case REGMAP_LITTLE_ENDIAN: + out_le32(addr, *val); + break; + case REGMAP_BIG_ENDIAN: + out_be32(addr, *val); + break; + } +} + +#if defined(out_le64) && defined(out_be64) && defined(writeq) +static inline void __write_64(u64 *addr, const u64 *val, + enum regmap_endianness_t endianness) +{ + switch (endianness) { + case REGMAP_NATIVE_ENDIAN: + writeq(*val, addr); + break; + case REGMAP_LITTLE_ENDIAN: + out_le64(addr, *val); + break; + case REGMAP_BIG_ENDIAN: + out_be64(addr, *val); + break; + } +} +#endif + int regmap_raw_write_range(struct regmap *map, uint range_num, uint offset, const void *val, size_t val_len) { @@ -263,17 +377,17 @@ int regmap_raw_write_range(struct regmap *map, uint range_num, uint offset,

switch (val_len) { case REGMAP_SIZE_8: - writeb(*((u8 *)val), (u8 *)ptr); + __write_8(ptr, val, map->endianness); break; case REGMAP_SIZE_16: - writew(*((u16 *)val), (u16 *)ptr); + __write_16(ptr, val, map->endianness); break; case REGMAP_SIZE_32: - writel(*((u32 *)val), (u32 *)ptr); + __write_32(ptr, val, map->endianness); break; -#if defined(writeq) +#if defined(out_le64) && defined(out_be64) && defined(writeq) case REGMAP_SIZE_64: - writeq(*((u64 *)val), (u64 *)ptr); + __write_64(ptr, val, map->endianness); break; #endif default: diff --git a/include/regmap.h b/include/regmap.h index 3b7eea5f49..98860c2732 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -22,6 +22,19 @@ enum regmap_size_t { REGMAP_SIZE_64 = 8, };

+/** + * enum regmap_endianness_t - Endianness for regmap reads and writes + * + * @REGMAP_NATIVE_ENDIAN: Native endian read/write accesses + * @REGMAP_LITTLE_ENDIAN: Little endian read/write accesses + * @REGMAP_BIG_ENDIAN: Big endian read/write accesses + */ +enum regmap_endianness_t { + REGMAP_NATIVE_ENDIAN, + REGMAP_LITTLE_ENDIAN, + REGMAP_BIG_ENDIAN, +}; + /** * struct regmap_range - a register map range * @@ -40,6 +53,7 @@ struct regmap_range { * @ranges: Array of ranges */ struct regmap { + enum regmap_endianness_t endianness; int range_count; struct regmap_range ranges[0]; }; -- 2.18.1

Add some overview documentation that explains the purpose and some of the features and limitations of the regmap interface.

Reviewed-by: Bin Meng bmeng.cn@gmail.com Signed-off-by: Mario Six mario.six@gdsys.cc

--- v10 -> v11: No changes

v9 -> v10: No changes

v8 -> v9: * Amended for inclusion of endianness setting via DT

v7 -> v8: New in v8 --- include/regmap.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)

diff --git a/include/regmap.h b/include/regmap.h index 98860c2732..b2b733fda6 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -7,6 +7,33 @@ #ifndef __REGMAP_H #define __REGMAP_H

+/** + * DOC: Overview + * + * Regmaps are an abstraction mechanism that allows device drivers to access + * register maps irrespective of the underlying bus architecture. This entails + * that for devices that support multiple busses (e.g. I2C and SPI for a GPIO + * expander chip) only one driver has to be written. This driver will + * instantiate a regmap with a backend depending on the bus the device is + * attached to, and use the regmap API to access the register map through that + * bus transparently. + * + * Read and write functions are supplied, which can read/write data of + * arbitrary length from/to the regmap. + * + * The endianness of regmap accesses is selectable for each map through device + * tree settings via the boolean "little-endian", "big-endian", and + * "native-endian" properties. + * + * Furthermore, the register map described by a regmap can be split into + * multiple disjoint areas called ranges. In this way, register maps with + * "holes", i.e. areas of addressable memory that are not part of the register + * map, can be accessed in a concise manner. + * + * Currently, only a bare "mem" backend for regmaps is supported, which + * accesses the register map as regular IO-mapped memory. + */ + /** * enum regmap_size_t - Access sizes for regmap reads and writes * -- 2.18.1

Makefile entries should be sorted.

Reviewed-by: Anatolij Gustschin agust@denx.de Reviewed-by: Simon Glass sjg@chromium.org Signed-off-by: Mario Six mario.six@gdsys.cc Signed-off-by: Anatolij Gustschin agust@denx.de

--- v10 -> v11: No changes

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v4 -> v5: Drop re-ordered entries that are not in mainline (e.g. CONFIG_GDSYS_IOEP, CONFIG_MPC83XX_SERDES, misc_sandbox.o)

v3 -> v4: No changes

v2 -> v3: New in v3 --- drivers/misc/Makefile | 58 +++++++++++++++++++++---------------------- 1 file changed, 29 insertions(+), 29 deletions(-)

diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index cf6587268e..aa5410ea15 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -4,11 +4,6 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de.

obj-$(CONFIG_MISC) += misc-uclass.o -obj-$(CONFIG_ALI152X) += ali512x.o -obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o -obj-$(CONFIG_ATSHA204A) += atsha204a-i2c.o -obj-$(CONFIG_DS4510) += ds4510.o -obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_CROS_EC) += cros_ec.o obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpc.o @@ -16,45 +11,50 @@ obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o endif -obj-$(CONFIG_FSL_IIM) += fsl_iim.o -obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o -obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o -obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o -obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o -obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o -obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o -obj-$(CONFIG_NS87308) += ns87308.o -obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o ifdef CONFIG_DM_I2C ifndef CONFIG_SPL_BUILD obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o endif endif -obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o -obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o -obj-$(CONFIG_LED_STATUS) += status_led.o -obj-$(CONFIG_SANDBOX) += swap_case.o ifdef CONFIG_SPL_OF_PLATDATA ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SANDBOX) += spltest_sandbox.o endif endif -obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o -obj-$(CONFIG_TEGRA_CAR) += tegra_car.o -obj-$(CONFIG_TEGRA186_BPMP) += tegra186_bpmp.o -obj-$(CONFIG_TWL4030_LED) += twl4030_led.o +obj-$(CONFIG_ALI152X) += ali512x.o +obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o +obj-$(CONFIG_ATSHA204A) += atsha204a-i2c.o +obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o +obj-$(CONFIG_DS4510) += ds4510.o +obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o obj-$(CONFIG_FSL_IFC) += fsl_ifc.o +obj-$(CONFIG_FSL_IIM) += fsl_iim.o +obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o +obj-$(CONFIG_FS_LOADER) += fs_loader.o +obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o +obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o +obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o +obj-$(CONFIG_LED_STATUS) += status_led.o +obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o +obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o +obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o +obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o +obj-$(CONFIG_NS87308) += ns87308.o +obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o obj-$(CONFIG_PCA9551_LED) += pca9551_led.o -obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o -obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o +obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o obj-$(CONFIG_QFW) += qfw.o obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o -obj-$(CONFIG_STM32_RCC) += stm32_rcc.o +obj-$(CONFIG_SANDBOX) += swap_case.o +obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o +obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o +obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o obj-$(CONFIG_STM32MP_FUSE) += stm32mp_fuse.o +obj-$(CONFIG_STM32_RCC) += stm32_rcc.o obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o -obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o -obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o +obj-$(CONFIG_TEGRA186_BPMP) += tegra186_bpmp.o +obj-$(CONFIG_TEGRA_CAR) += tegra_car.o +obj-$(CONFIG_TWL4030_LED) += twl4030_led.o obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o -obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o -obj-$(CONFIG_FS_LOADER) += fs_loader.o +obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o -- 2.18.1

This patch adds a driver for the bus associated with a IHS FPGA.

Reviewed-by: Simon Glass sjg@chromium.org Signed-off-by: Mario Six mario.six@gdsys.cc

--- v10 -> v11: No changes

v9 -> v10: No changes

v8 -> v9: No changes

v7 -> v8: No changes

v6 -> v7: No changes

v5 -> v6: No changes

v4 -> v5: No changes

v3 -> v4: No changes

v2 -> v3: * Fixed style violations * Added bindings file * Added more debug output in case of errors * Switched all printfs to debug * Documented the private data structure * Formatted documentation as proper kernel-doc * Expanded Kconfig description

v1 -> v2: * Switched to correct uclass for IHS FPGA driver (now in MISC uclass) --- .../devicetree/bindings/misc/gdsys,soc.txt | 16 ++++ drivers/misc/Kconfig | 8 ++ drivers/misc/Makefile | 1 + drivers/misc/gdsys_soc.c | 74 +++++++++++++++++++ drivers/misc/gdsys_soc.h | 23 ++++++ 5 files changed, 122 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/gdsys,soc.txt create mode 100644 drivers/misc/gdsys_soc.c create mode 100644 drivers/misc/gdsys_soc.h

diff --git a/Documentation/devicetree/bindings/misc/gdsys,soc.txt b/Documentation/devicetree/bindings/misc/gdsys,soc.txt new file mode 100644 index 0000000000..278e935b16 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/gdsys,soc.txt @@ -0,0 +1,16 @@ +gdsys soc bus driver + +This driver provides a simple interface for the busses associated with gdsys +IHS FPGAs. The bus itself contains devices whose register maps are contained +within the FPGA's register space. + +Required properties: +- fpga: A phandle to the controlling IHS FPGA + +Example: + +FPGA0BUS: fpga0bus { + compatible = "gdsys,soc"; + ranges = <0x0 0xe0600000 0x00004000>; + fpga = <&FPGA0>; +}; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index c5697011f2..d589f32a55 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -312,4 +312,12 @@ config FS_LOADER The consumer driver would then use this loader to program whatever, ie. the FPGA device.

+config GDSYS_SOC + bool "Enable gdsys SOC driver" + depends on MISC + help + Support for gdsys IHS SOC, a simple bus associated with each gdsys + IHS (Integrated Hardware Systems) FPGA, which holds all devices whose + register maps are contained within the FPGA's register map. + endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index aa5410ea15..ed5d7bb0c0 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o obj-$(CONFIG_FS_LOADER) += fs_loader.o obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o +obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o obj-$(CONFIG_LED_STATUS) += status_led.o obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o diff --git a/drivers/misc/gdsys_soc.c b/drivers/misc/gdsys_soc.c new file mode 100644 index 0000000000..94a21e08af --- /dev/null +++ b/drivers/misc/gdsys_soc.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +#include <common.h> +#include <dm.h> +#include <dm/lists.h> + +#include "gdsys_soc.h" + +/** + * struct gdsys_soc_priv - Private data for gdsys soc bus + * @fpga: The gdsys IHS FPGA this bus is associated with + */ +struct gdsys_soc_priv { + struct udevice *fpga; +}; + +static const struct udevice_id gdsys_soc_ids[] = { + { .compatible = "gdsys,soc" }, + { /* sentinel */ } +}; + +int gdsys_soc_get_fpga(struct udevice *child, struct udevice **fpga) +{ + struct gdsys_soc_priv *bus_priv; + + if (!child->parent) { + debug("%s: Invalid parent\n", child->name); + return -EINVAL; + } + + if (!device_is_compatible(child->parent, "gdsys,soc")) { + debug("%s: Not child of a gdsys soc\n", child->name); + return -EINVAL; + } + + bus_priv = dev_get_priv(child->parent); + + *fpga = bus_priv->fpga; + + return 0; +} + +static int gdsys_soc_probe(struct udevice *dev) +{ + struct gdsys_soc_priv *priv = dev_get_priv(dev); + struct udevice *fpga; + int res = uclass_get_device_by_phandle(UCLASS_MISC, dev, "fpga", + &fpga); + if (res == -ENOENT) { + debug("%s: Could not find 'fpga' phandle\n", dev->name); + return -EINVAL; + } + + if (res == -ENODEV) { + debug("%s: Could not get FPGA device\n", dev->name); + return -EINVAL; + } + + priv->fpga = fpga; + + return 0; +} + +U_BOOT_DRIVER(gdsys_soc_bus) = { + .name = "gdsys_soc_bus", + .id = UCLASS_SIMPLE_BUS, + .of_match = gdsys_soc_ids, + .probe = gdsys_soc_probe, + .priv_auto_alloc_size = sizeof(struct gdsys_soc_priv), +}; diff --git a/drivers/misc/gdsys_soc.h b/drivers/misc/gdsys_soc.h new file mode 100644 index 0000000000..088d3b6523 --- /dev/null +++ b/drivers/misc/gdsys_soc.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +#ifndef _GDSYS_SOC_H_ +#define _GDSYS_SOC_H_ + +/** + * gdsys_soc_get_fpga() - Retrieve pointer to parent bus' FPGA device + * @child: The child device on the FPGA bus needing access to the FPGA. + * @fpga: Pointer to the retrieved FPGA device. + * + * To access their register maps, devices on gdsys soc buses usually have + * facilitate the accessor function of the IHS FPGA their parent bus is + * attached to. To access the FPGA device from within the bus' children, this + * function returns a pointer to it. + * + * Return: 0 on success, -ve on failure + */ +int gdsys_soc_get_fpga(struct udevice *child, struct udevice **fpga); +#endif /* _GDSYS_SOC_H_ */ -- 2.18.1

Add a driver for gdsys IHS (Integrated Hardware Systems) FPGAs, which supports initialization of the FPGA, as well as information gathering.

Reviewed-by: Simon Glass sjg@chromium.org Signed-off-by: Mario Six mario.six@gdsys.cc

--- v10 -> v11: No changes

v9 -> v10: No changes

v8 -> v9: No changes

v7 -> v8: No changes

v6 -> v7: No changes

v5 -> v6: No changes

v4 -> v5: No changes

v3 -> v4: * Switched from 'res' as the name for return variables to 'ret'

v2 -> v3: * Fixed style violations * Added full documentation * Extracted some magic numbers to constants * Removed unnecessary includes * Extracted wait_for_fpga_done * Improved error handling and reporting * Added device-tree-binding files * Improved Kconfig entry

v1 -> v2: New in v2 --- .../bindings/misc/gdsys,iocon_fpga.txt | 19 + .../bindings/misc/gdsys,iocpu_fpga.txt | 19 + drivers/misc/Kconfig | 9 + drivers/misc/Makefile | 1 + drivers/misc/ihs_fpga.c | 867 ++++++++++++++++++ drivers/misc/ihs_fpga.h | 49 + 6 files changed, 964 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/gdsys,iocon_fpga.txt create mode 100644 Documentation/devicetree/bindings/misc/gdsys,iocpu_fpga.txt create mode 100644 drivers/misc/ihs_fpga.c create mode 100644 drivers/misc/ihs_fpga.h

diff --git a/Documentation/devicetree/bindings/misc/gdsys,iocon_fpga.txt b/Documentation/devicetree/bindings/misc/gdsys,iocon_fpga.txt new file mode 100644 index 0000000000..acd466fdc6 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/gdsys,iocon_fpga.txt @@ -0,0 +1,19 @@ +gdsys IHS FPGA for CON devices + +The gdsys IHS FPGA is the main FPGA on gdsys CON devices. This driver provides +support for enabling and starting the FPGA, as well as verifying working bus +communication. + +Required properties: +- compatible: must be "gdsys,iocon_fpga" +- reset-gpios: List of GPIOs controlling the FPGA's reset +- done-gpios: List of GPIOs notifying whether the FPGA's reconfiguration is + done + +Example: + +FPGA0 { + compatible = "gdsys,iocon_fpga"; + reset-gpios = <&PPCPCA 26 0>; + done-gpios = <&GPIO_VB0 19 0>; +}; diff --git a/Documentation/devicetree/bindings/misc/gdsys,iocpu_fpga.txt b/Documentation/devicetree/bindings/misc/gdsys,iocpu_fpga.txt new file mode 100644 index 0000000000..819db22bf7 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/gdsys,iocpu_fpga.txt @@ -0,0 +1,19 @@ +gdsys IHS FPGA for CPU devices + +The gdsys IHS FPGA is the main FPGA on gdsys CPU devices. This driver provides +support for enabling and starting the FPGA, as well as verifying working bus +communication. + +Required properties: +- compatible: must be "gdsys,iocpu_fpga" +- reset-gpios: List of GPIOs controlling the FPGA's reset +- done-gpios: List of GPIOs notifying whether the FPGA's reconfiguration is + done + +Example: + +FPGA0 { + compatible = "gdsys,iocpu_fpga"; + reset-gpios = <&PPCPCA 26 0>; + done-gpios = <&GPIO_VB0 19 0>; +}; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index d589f32a55..48febc47d2 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -320,4 +320,13 @@ config GDSYS_SOC IHS (Integrated Hardware Systems) FPGA, which holds all devices whose register maps are contained within the FPGA's register map.

+config IHS_FPGA + bool "Enable IHS FPGA driver" + depends on MISC + help + Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on + gdsys devices, which supply the majority of the functionality offered + by the devices. This driver supports both CON and CPU variants of the + devices, depending on the device tree entry. + endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index ed5d7bb0c0..ef4bacb718 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o +obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o obj-$(CONFIG_LED_STATUS) += status_led.o obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o diff --git a/drivers/misc/ihs_fpga.c b/drivers/misc/ihs_fpga.c new file mode 100644 index 0000000000..f9e4b27a27 --- /dev/null +++ b/drivers/misc/ihs_fpga.c @@ -0,0 +1,867 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + * + * based on the ioep-fpga driver, which is + * + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + */ + +#include <common.h> +#include <dm.h> +#include <regmap.h> +#include <asm/gpio.h> + +#include "ihs_fpga.h" + +/** + * struct ihs_fpga_priv - Private data structure for IHS FPGA driver + * @map: Register map for the FPGA's own register space + * @reset_gpio: GPIO to start FPGA reconfiguration + * @done_gpio: GPOI to read the 'ready' status of the FPGA + */ +struct ihs_fpga_priv { + struct regmap *map; + struct gpio_desc reset_gpio; + struct gpio_desc done_gpio; +}; + +/* Test pattern for reflection test */ +const u16 REFLECTION_TESTPATTERN = 0xdead; +/* Delay (in ms) for each round in the reflection test */ +const uint REFLECTION_TEST_DELAY = 100; +/* Maximum number of rounds in the reflection test */ +const uint REFLECTION_TEST_ROUNDS = 5; +/* Delay (in ms) for each round waiting for the FPGA's done GPIO */ +const uint FPGA_DONE_WAIT_DELAY = 100; +/* Maximum number of rounds for waiting for the FPGA's done GPIO */ +const uint FPGA_DONE_WAIT_ROUND = 5; + +/** + * enum pcb_video_type - Video type of the PCB + * @PCB_DVI_SL: Video type is DVI single-link + * @PCB_DP_165MPIX: Video type is DisplayPort (165Mpix) + * @PCB_DP_300MPIX: Video type is DisplayPort (300Mpix) + * @PCB_HDMI: Video type is HDMI + * @PCB_DP_1_2: Video type is DisplayPort 1.2 + * @PCB_HDMI_2_0: Video type is HDMI 2.0 + */ +enum pcb_video_type { + PCB_DVI_SL, + PCB_DP_165MPIX, + PCB_DP_300MPIX, + PCB_HDMI, + PCB_DP_1_2, + PCB_HDMI_2_0, +}; + +/** + * enum pcb_transmission_type - Transmission type of the PCB + * @PCB_CAT_1G: Transmission type is 1G Ethernet + * @PCB_FIBER_3G: Transmission type is 3G Fiber + * @PCB_CAT_10G: Transmission type is 10G Ethernet + * @PCB_FIBER_10G: Transmission type is 10G Fiber + */ +enum pcb_transmission_type { + PCB_CAT_1G, + PCB_FIBER_3G, + PCB_CAT_10G, + PCB_FIBER_10G, +}; + +/** + * enum carrier_speed - Speed of the FPGA's carrier + * @CARRIER_SPEED_1G: The carrier speed is 1G + * @CARRIER_SPEED_2_5G: The carrier speed is 2.5G + * @CARRIER_SPEED_3G: The carrier speed is 3G + * @CARRIER_SPEED_10G: The carrier speed is 10G + */ +enum carrier_speed { + CARRIER_SPEED_1G, + CARRIER_SPEED_3G, + CARRIER_SPEED_2_5G = CARRIER_SPEED_3G, + CARRIER_SPEED_10G, +}; + +/** + * enum ram_config - FPGA's RAM configuration + * @RAM_DDR2_32BIT_295MBPS: DDR2 32 bit at 295Mb/s + * @RAM_DDR3_32BIT_590MBPS: DDR3 32 bit at 590Mb/s + * @RAM_DDR3_48BIT_590MBPS: DDR3 48 bit at 590Mb/s + * @RAM_DDR3_64BIT_1800MBPS: DDR3 64 bit at 1800Mb/s + * @RAM_DDR3_48BIT_1800MBPS: DDR3 48 bit at 1800Mb/s + */ +enum ram_config { + RAM_DDR2_32BIT_295MBPS, + RAM_DDR3_32BIT_590MBPS, + RAM_DDR3_48BIT_590MBPS, + RAM_DDR3_64BIT_1800MBPS, + RAM_DDR3_48BIT_1800MBPS, +}; + +/** + * enum sysclock - Speed of the FPGA's system clock + * @SYSCLK_147456: System clock is 147.456 MHz + */ +enum sysclock { + SYSCLK_147456, +}; + +/** + * struct fpga_versions - Data read from the versions register + * @video_channel: Is the FPGA for a video channel (true) or main + * channel (false) device? + * @con_side: Is the FPGA for a CON (true) or a CPU (false) device? + * @pcb_video_type: Defines for whch video type the FPGA is configured + * @pcb_transmission_type: Defines for which transmission type the FPGA is + * configured + * @hw_version: Hardware version of the FPGA + */ +struct fpga_versions { + bool video_channel; + bool con_side; + enum pcb_video_type pcb_video_type; + enum pcb_transmission_type pcb_transmission_type; + unsigned int hw_version; +}; + +/** + * struct fpga_features - Data read from the features register + * @video_channels: Number of video channels supported + * @carriers: Number of carrier channels supported + * @carrier_speed: Speed of carriers + * @ram_config: RAM configuration of FPGA + * @sysclock: System clock speed of FPGA + * @pcm_tx: Support for PCM transmission + * @pcm_rx: Support for PCM reception + * @spdif_tx: Support for SPDIF audio transmission + * @spdif_rx: Support for SPDIF audio reception + * @usb2: Support for transparent USB2.0 + * @rs232: Support for bidirectional RS232 + * @compression_type1: Support for compression type 1 + * @compression_type2: Support for compression type 2 + * @compression_type3: Support for compression type 3 + * @interlace: Support for interlace image formats + * @osd: Support for a OSD + * @compression_pipes: Number of compression pipes supported + */ +struct fpga_features { + u8 video_channels; + u8 carriers; + enum carrier_speed carrier_speed; + enum ram_config ram_config; + enum sysclock sysclock; + bool pcm_tx; + bool pcm_rx; + bool spdif_tx; + bool spdif_rx; + bool usb2; + bool rs232; + bool compression_type1; + bool compression_type2; + bool compression_type3; + bool interlace; + bool osd; + bool compression_pipes; +}; + +#ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM + +/** + * get_versions() - Fill structure with info from version register. + * @dev: FPGA device to be queried for information + * @versions: Pointer to the structure to fill with information from the + * versions register + * Return: 0 + */ +static int get_versions(struct udevice *dev, struct fpga_versions *versions) +{ + struct ihs_fpga_priv *priv = dev_get_priv(dev); + enum { + VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12), + VERSIONS_FPGA_CON_SIDE = BIT(13), + VERSIONS_FPGA_SC = BIT(14), + VERSIONS_PCB_CON = BIT(9), + VERSIONS_PCB_SC = BIT(8), + VERSIONS_PCB_VIDEO_MASK = 0x3 << 6, + VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6, + VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6, + VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4, + VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4, + VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4, + VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4, + VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4, + VERSIONS_HW_VER_MASK = 0xf << 0, + }; + u16 raw_versions; + + memset(versions, 0, sizeof(struct fpga_versions)); + + ihs_fpga_get(priv->map, versions, &raw_versions); + + versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL; + versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE; + + switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) { + case VERSIONS_PCB_VIDEO_DP_1_2: + versions->pcb_video_type = PCB_DP_1_2; + break; + + case VERSIONS_PCB_VIDEO_HDMI_2_0: + versions->pcb_video_type = PCB_HDMI_2_0; + break; + } + + switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) { + case VERSIONS_PCB_TRANSMISSION_FIBER_10G: + versions->pcb_transmission_type = PCB_FIBER_10G; + break; + + case VERSIONS_PCB_TRANSMISSION_CAT_10G: + versions->pcb_transmission_type = PCB_CAT_10G; + break; + + case VERSIONS_PCB_TRANSMISSION_FIBER_3G: + versions->pcb_transmission_type = PCB_FIBER_3G; + break; + + case VERSIONS_PCB_TRANSMISSION_CAT_1G: + versions->pcb_transmission_type = PCB_CAT_1G; + break; + } + + versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK; + + return 0; +} + +/** + * get_features() - Fill structure with info from features register. + * @dev: FPGA device to be queried for information + * @features: Pointer to the structure to fill with information from the + * features register + * Return: 0 + */ +static int get_features(struct udevice *dev, struct fpga_features *features) +{ + struct ihs_fpga_priv *priv = dev_get_priv(dev); + enum { + FEATURE_SPDIF_RX = BIT(15), + FEATURE_SPDIF_TX = BIT(14), + FEATURE_PCM_RX = BIT(13), + FEATURE_PCM_TX = BIT(12), + FEATURE_RAM_MASK = GENMASK(11, 8), + FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8, + FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8, + FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8, + FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8, + FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8, + FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6), + FEATURE_CARRIER_SPEED_1G = 0x0 << 6, + FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6, + FEATURE_CARRIER_SPEED_10G = 0x2 << 6, + FEATURE_CARRIERS_MASK = GENMASK(5, 4), + FEATURE_CARRIERS_0 = 0x0 << 4, + FEATURE_CARRIERS_1 = 0x1 << 4, + FEATURE_CARRIERS_2 = 0x2 << 4, + FEATURE_CARRIERS_4 = 0x3 << 4, + FEATURE_USB2 = BIT(3), + FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0), + FEATURE_VIDEOCHANNELS_0 = 0x0 << 0, + FEATURE_VIDEOCHANNELS_1 = 0x1 << 0, + FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0, + FEATURE_VIDEOCHANNELS_2 = 0x3 << 0, + }; + + enum { + EXT_FEATURE_OSD = BIT(15), + EXT_FEATURE_ETHERNET = BIT(9), + EXT_FEATURE_INTERLACE = BIT(8), + EXT_FEATURE_RS232 = BIT(7), + EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4), + EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4, + EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4, + EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4, + EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0), + EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1), + EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2), + }; + + u16 raw_features; + u16 raw_extended_features; + + memset(features, 0, sizeof(struct fpga_features)); + + ihs_fpga_get(priv->map, features, &raw_features); + ihs_fpga_get(priv->map, extended_features, &raw_extended_features); + + switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) { + case FEATURE_VIDEOCHANNELS_0: + features->video_channels = 0; + break; + + case FEATURE_VIDEOCHANNELS_1: + features->video_channels = 1; + break; + + case FEATURE_VIDEOCHANNELS_1_1: + case FEATURE_VIDEOCHANNELS_2: + features->video_channels = 2; + break; + }; + + switch (raw_features & FEATURE_CARRIERS_MASK) { + case FEATURE_CARRIERS_0: + features->carriers = 0; + break; + + case FEATURE_CARRIERS_1: + features->carriers = 1; + break; + + case FEATURE_CARRIERS_2: + features->carriers = 2; + break; + + case FEATURE_CARRIERS_4: + features->carriers = 4; + break; + } + + switch (raw_features & FEATURE_CARRIER_SPEED_MASK) { + case FEATURE_CARRIER_SPEED_1G: + features->carrier_speed = CARRIER_SPEED_1G; + break; + case FEATURE_CARRIER_SPEED_2_5G: + features->carrier_speed = CARRIER_SPEED_2_5G; + break; + case FEATURE_CARRIER_SPEED_10G: + features->carrier_speed = CARRIER_SPEED_10G; + break; + } + + switch (raw_features & FEATURE_RAM_MASK) { + case FEATURE_RAM_DDR2_32BIT_295MBPS: + features->ram_config = RAM_DDR2_32BIT_295MBPS; + break; + + case FEATURE_RAM_DDR3_32BIT_590MBPS: + features->ram_config = RAM_DDR3_32BIT_590MBPS; + break; + + case FEATURE_RAM_DDR3_48BIT_590MBPS: + features->ram_config = RAM_DDR3_48BIT_590MBPS; + break; + + case FEATURE_RAM_DDR3_64BIT_1800MBPS: + features->ram_config = RAM_DDR3_64BIT_1800MBPS; + break; + + case FEATURE_RAM_DDR3_48BIT_1800MBPS: + features->ram_config = RAM_DDR3_48BIT_1800MBPS; + break; + } + + features->pcm_tx = raw_features & FEATURE_PCM_TX; + features->pcm_rx = raw_features & FEATURE_PCM_RX; + features->spdif_tx = raw_features & FEATURE_SPDIF_TX; + features->spdif_rx = raw_features & FEATURE_SPDIF_RX; + features->usb2 = raw_features & FEATURE_USB2; + features->rs232 = raw_extended_features & EXT_FEATURE_RS232; + features->compression_type1 = raw_extended_features & + EXT_FEATURE_COMPRESSION_TYPE1; + features->compression_type2 = raw_extended_features & + EXT_FEATURE_COMPRESSION_TYPE2; + features->compression_type3 = raw_extended_features & + EXT_FEATURE_COMPRESSION_TYPE3; + features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE; + features->osd = raw_extended_features & EXT_FEATURE_OSD; + features->compression_pipes = raw_extended_features & + EXT_FEATURE_COMPRESSION_PERF_MASK; + + return 0; +} + +#else + +/** + * get_versions() - Fill structure with info from version register. + * @fpga: Identifier of the FPGA device to be queried for information + * @versions: Pointer to the structure to fill with information from the + * versions register + * + * This is the legacy version and should be considered deprecated for new + * devices. + * + * Return: 0 + */ +static int get_versions(unsigned int fpga, struct fpga_versions *versions) +{ + enum { + /* HW version encoding is a mess, leave it for the moment */ + VERSIONS_HW_VER_MASK = 0xf << 0, + VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4), + VERSIONS_SFP = BIT(5), + VERSIONS_VIDEO_MASK = 0x7 << 6, + VERSIONS_VIDEO_DVI = 0x0 << 6, + VERSIONS_VIDEO_DP_165 = 0x1 << 6, + VERSIONS_VIDEO_DP_300 = 0x2 << 6, + VERSIONS_VIDEO_HDMI = 0x3 << 6, + VERSIONS_UT_MASK = 0xf << 12, + VERSIONS_UT_MAIN_SERVER = 0x0 << 12, + VERSIONS_UT_MAIN_USER = 0x1 << 12, + VERSIONS_UT_VIDEO_SERVER = 0x2 << 12, + VERSIONS_UT_VIDEO_USER = 0x3 << 12, + }; + u16 raw_versions; + + memset(versions, 0, sizeof(struct fpga_versions)); + + FPGA_GET_REG(fpga, versions, &raw_versions); + + switch (raw_versions & VERSIONS_UT_MASK) { + case VERSIONS_UT_MAIN_SERVER: + versions->video_channel = false; + versions->con_side = false; + break; + + case VERSIONS_UT_MAIN_USER: + versions->video_channel = false; + versions->con_side = true; + break; + + case VERSIONS_UT_VIDEO_SERVER: + versions->video_channel = true; + versions->con_side = false; + break; + + case VERSIONS_UT_VIDEO_USER: + versions->video_channel = true; + versions->con_side = true; + break; + } + + switch (raw_versions & VERSIONS_VIDEO_MASK) { + case VERSIONS_VIDEO_DVI: + versions->pcb_video_type = PCB_DVI_SL; + break; + + case VERSIONS_VIDEO_DP_165: + versions->pcb_video_type = PCB_DP_165MPIX; + break; + + case VERSIONS_VIDEO_DP_300: + versions->pcb_video_type = PCB_DP_300MPIX; + break; + + case VERSIONS_VIDEO_HDMI: + versions->pcb_video_type = PCB_HDMI; + break; + } + + versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK; + + if (raw_versions & VERSIONS_SFP) + versions->pcb_transmission_type = PCB_FIBER_3G; + else + versions->pcb_transmission_type = PCB_CAT_1G; + + return 0; +} + +/** + * get_features() - Fill structure with info from features register. + * @fpga: Identifier of the FPGA device to be queried for information + * @features: Pointer to the structure to fill with information from the + * features register + * + * This is the legacy version and should be considered deprecated for new + * devices. + * + * Return: 0 + */ +static int get_features(unsigned int fpga, struct fpga_features *features) +{ + enum { + FEATURE_CARRIER_SPEED_2_5 = BIT(4), + FEATURE_RAM_MASK = 0x7 << 5, + FEATURE_RAM_DDR2_32BIT = 0x0 << 5, + FEATURE_RAM_DDR3_32BIT = 0x1 << 5, + FEATURE_RAM_DDR3_48BIT = 0x2 << 5, + FEATURE_PCM_AUDIO_TX = BIT(9), + FEATURE_PCM_AUDIO_RX = BIT(10), + FEATURE_OSD = BIT(11), + FEATURE_USB20 = BIT(12), + FEATURE_COMPRESSION_MASK = 7 << 13, + FEATURE_COMPRESSION_TYPE1 = 0x1 << 13, + FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13, + FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13, + }; + + enum { + EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0), + EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1), + EXTENDED_FEATURE_RS232 = BIT(2), + EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3), + EXTENDED_FEATURE_INTERLACE = BIT(4), + }; + + u16 raw_features; + u16 raw_extended_features; + + memset(features, 0, sizeof(struct fpga_features)); + + FPGA_GET_REG(fpga, fpga_features, &raw_features); + FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features); + + features->video_channels = raw_features & 0x3; + features->carriers = (raw_features >> 2) & 0x3; + + features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5) + ? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G; + + switch (raw_features & FEATURE_RAM_MASK) { + case FEATURE_RAM_DDR2_32BIT: + features->ram_config = RAM_DDR2_32BIT_295MBPS; + break; + + case FEATURE_RAM_DDR3_32BIT: + features->ram_config = RAM_DDR3_32BIT_590MBPS; + break; + + case FEATURE_RAM_DDR3_48BIT: + features->ram_config = RAM_DDR3_48BIT_590MBPS; + break; + } + + features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX; + features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX; + features->spdif_tx = raw_extended_features & + EXTENDED_FEATURE_SPDIF_AUDIO_TX; + features->spdif_rx = raw_extended_features & + EXTENDED_FEATURE_SPDIF_AUDIO_RX; + + features->usb2 = raw_features & FEATURE_USB20; + features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232; + + features->compression_type1 = false; + features->compression_type2 = false; + features->compression_type3 = false; + switch (raw_features & FEATURE_COMPRESSION_MASK) { + case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3: + features->compression_type3 = true; + /* fall-through */ + case FEATURE_COMPRESSION_TYPE1_TYPE2: + features->compression_type2 = true; + /* fall-through */ + case FEATURE_COMPRESSION_TYPE1: + features->compression_type1 = true; + break; + } + + features->interlace = raw_extended_features & + EXTENDED_FEATURE_INTERLACE; + features->osd = raw_features & FEATURE_OSD; + features->compression_pipes = raw_extended_features & + EXTENDED_FEATURE_COMPRESSION_PIPES; + + return 0; +} + +#endif + +/** + * fpga_print_info() - Print information about FPGA device + * @dev: FPGA device to print information about + */ +static void fpga_print_info(struct udevice *dev) +{ + struct ihs_fpga_priv *priv = dev_get_priv(dev); + u16 fpga_version; + struct fpga_versions versions; + struct fpga_features features; + + ihs_fpga_get(priv->map, fpga_version, &fpga_version); + get_versions(dev, &versions); + get_features(dev, &features); + + if (versions.video_channel) + printf("Videochannel"); + else + printf("Mainchannel"); + + if (versions.con_side) + printf(" User"); + else + printf(" Server"); + + switch (versions.pcb_transmission_type) { + case PCB_CAT_1G: + case PCB_CAT_10G: + printf(" CAT"); + break; + case PCB_FIBER_3G: + case PCB_FIBER_10G: + printf(" Fiber"); + break; + }; + + switch (versions.pcb_video_type) { + case PCB_DVI_SL: + printf(" DVI,"); + break; + case PCB_DP_165MPIX: + printf(" DP 165MPix/s,"); + break; + case PCB_DP_300MPIX: + printf(" DP 300MPix/s,"); + break; + case PCB_HDMI: + printf(" HDMI,"); + break; + case PCB_DP_1_2: + printf(" DP 1.2,"); + break; + case PCB_HDMI_2_0: + printf(" HDMI 2.0,"); + break; + } + + printf(" FPGA V %d.%02d\n features: ", + fpga_version / 100, fpga_version % 100); + + if (!features.compression_type1 && + !features.compression_type2 && + !features.compression_type3) + printf("no compression, "); + + if (features.compression_type1) + printf("type1, "); + + if (features.compression_type2) + printf("type2, "); + + if (features.compression_type3) + printf("type3, "); + + printf("%sosd", features.osd ? "" : "no "); + + if (features.pcm_rx && features.pcm_tx) + printf(", pcm rx+tx"); + else if (features.pcm_rx) + printf(", pcm rx"); + else if (features.pcm_tx) + printf(", pcm tx"); + + if (features.spdif_rx && features.spdif_tx) + printf(", spdif rx+tx"); + else if (features.spdif_rx) + printf(", spdif rx"); + else if (features.spdif_tx) + printf(", spdif tx"); + + puts(",\n "); + + switch (features.sysclock) { + case SYSCLK_147456: + printf("clock 147.456 MHz"); + break; + } + + switch (features.ram_config) { + case RAM_DDR2_32BIT_295MBPS: + printf(", RAM 32 bit DDR2"); + break; + case RAM_DDR3_32BIT_590MBPS: + printf(", RAM 32 bit DDR3"); + break; + case RAM_DDR3_48BIT_590MBPS: + case RAM_DDR3_48BIT_1800MBPS: + printf(", RAM 48 bit DDR3"); + break; + case RAM_DDR3_64BIT_1800MBPS: + printf(", RAM 64 bit DDR3"); + break; + } + + printf(", %d carrier(s)", features.carriers); + + switch (features.carrier_speed) { + case CARRIER_SPEED_1G: + printf(", 1Gbit/s"); + break; + case CARRIER_SPEED_3G: + printf(", 3Gbit/s"); + break; + case CARRIER_SPEED_10G: + printf(", 10Gbit/s"); + break; + } + + printf(", %d video channel(s)\n", features.video_channels); +} + +/** + * do_reflection_test() - Run reflection test on a FPGA device + * @dev: FPGA device to run reflection test on + * + * Return: 0 if reflection test succeeded, -ve on error + */ +static int do_reflection_test(struct udevice *dev) +{ + struct ihs_fpga_priv *priv = dev_get_priv(dev); + int ctr = 0; + + while (1) { + u16 val; + + ihs_fpga_set(priv->map, reflection_low, REFLECTION_TESTPATTERN); + + ihs_fpga_get(priv->map, reflection_low, &val); + if (val == (~REFLECTION_TESTPATTERN & 0xffff)) + return -EIO; + + mdelay(REFLECTION_TEST_DELAY); + if (ctr++ > REFLECTION_TEST_ROUNDS) + return 0; + } +} + +/** + * wait_for_fpga_done() - Wait until 'done'-flag is set for FPGA device + * @dev: FPGA device whose done flag to wait for + * + * This function waits until it detects that the done-GPIO's value was changed + * to 1 by the FPGA, which indicates that the device is configured and ready to + * use. + * + * Return: 0 if done flag was detected, -ve on error + */ +static int wait_for_fpga_done(struct udevice *dev) +{ + struct ihs_fpga_priv *priv = dev_get_priv(dev); + int ctr = 0; + int done_val; + + while (1) { + done_val = dm_gpio_get_value(&priv->done_gpio); + if (done_val < 0) { + debug("%s: Error while reading done-GPIO (err = %d)\n", + dev->name, done_val); + return done_val; + } + + if (done_val) + return 0; + + mdelay(FPGA_DONE_WAIT_DELAY); + if (ctr++ > FPGA_DONE_WAIT_ROUND) { + debug("%s: FPGA init failed (done not detected)\n", + dev->name); + return -EIO; + } + } +} + +static int ihs_fpga_probe(struct udevice *dev) +{ + struct ihs_fpga_priv *priv = dev_get_priv(dev); + int ret; + + /* TODO(mario.six@gdsys.cc): Case of FPGA attached to MCLink bus */ + + ret = regmap_init_mem(dev_ofnode(dev), &priv->map); + if (ret) { + debug("%s: Could not initialize regmap (err = %d)", + dev->name, ret); + return ret; + } + + ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio, + GPIOD_IS_OUT); + if (ret) { + debug("%s: Could not get reset-GPIO (err = %d)\n", + dev->name, ret); + return ret; + } + + if (!priv->reset_gpio.dev) { + debug("%s: Could not get reset-GPIO\n", dev->name); + return -ENOENT; + } + + ret = gpio_request_by_name(dev, "done-gpios", 0, &priv->done_gpio, + GPIOD_IS_IN); + if (ret) { + debug("%s: Could not get done-GPIO (err = %d)\n", + dev->name, ret); + return ret; + } + + if (!priv->done_gpio.dev) { + debug("%s: Could not get done-GPIO\n", dev->name); + return -ENOENT; + } + + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) { + debug("%s: Error while setting reset-GPIO (err = %d)\n", + dev->name, ret); + return ret; + } + + /* If FPGA already runs, don't initialize again */ + if (do_reflection_test(dev)) + goto reflection_ok; + + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) { + debug("%s: Error while setting reset-GPIO (err = %d)\n", + dev->name, ret); + return ret; + } + + ret = wait_for_fpga_done(dev); + if (ret) { + debug("%s: Error while waiting for FPGA done (err = %d)\n", + dev->name, ret); + return ret; + } + + udelay(10); + + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) { + debug("%s: Error while setting reset-GPIO (err = %d)\n", + dev->name, ret); + return ret; + } + + if (!do_reflection_test(dev)) { + debug("%s: Reflection test FAILED\n", dev->name); + return -EIO; + } + +reflection_ok: + printf("%s: Reflection test passed.\n", dev->name); + + fpga_print_info(dev); + + return 0; +} + +static const struct udevice_id ihs_fpga_ids[] = { + { .compatible = "gdsys,iocon_fpga" }, + { .compatible = "gdsys,iocpu_fpga" }, + { } +}; + +U_BOOT_DRIVER(ihs_fpga_bus) = { + .name = "ihs_fpga_bus", + .id = UCLASS_MISC, + .of_match = ihs_fpga_ids, + .probe = ihs_fpga_probe, + .priv_auto_alloc_size = sizeof(struct ihs_fpga_priv), +}; diff --git a/drivers/misc/ihs_fpga.h b/drivers/misc/ihs_fpga.h new file mode 100644 index 0000000000..efb5dabb9c --- /dev/null +++ b/drivers/misc/ihs_fpga.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +/** + * struct ihs_fpga_regs - IHS FPGA register map structure + * @reflection_low: Lower reflection register + * @versions: PCB versions register + * @fpga_version: FPGA versions register + * @features: FPGA features register + * @extended_features: FPGA extended features register + * @top_interrupt: Top interrupt register + * @top_interrupt_enable: Top interrupt enable register + * @status: FPGA status register + * @control: FPGA control register + * @extended_control: FPGA extended control register + */ +struct ihs_fpga_regs { + u16 reflection_low; + u16 versions; + u16 fpga_version; + u16 features; + u16 extended_features; + u16 top_interrupt; + u16 top_interrupt_enable; + u16 status; + u16 control; + u16 extended_control; +}; + +/** + * ihs_fpga_set() - Convenience macro to set values in FPGA register map + * @map: Register map to set a value in + * @member: Name of member (described by ihs_fpga_regs) to set + * @val: Value to set the member to + */ +#define ihs_fpga_set(map, member, val) \ + regmap_set(map, struct ihs_fpga_regs, member, val) + +/** + * ihs_fpga_get() - Convenience macro to get values from FPGA register map + * @map: Register map to read value from + * @member: Name of member (described by ihs_fpga_regs) to get + * @valp: Pointe to variable to receive the value read + */ +#define ihs_fpga_get(map, member, valp) \ + regmap_get(map, struct ihs_fpga_regs, member, valp) -- 2.18.1