--- include/configs/devkit8000.h | 133 ++++++++++++------------------------------- 1 file changed, 36 insertions(+), 97 deletions(-)

diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 930b08e..182a137 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -16,11 +16,8 @@ #define __CONFIG_H

/* High Level Configuration Options */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 -#define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON

/* * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM @@ -30,11 +27,28 @@ */ #define CONFIG_SYS_TEXT_BASE 0x80100000

-#define CONFIG_SDRC /* The chip has SDRC controller */ +#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */

#include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h>

+#define CONFIG_SDRC /* The chip has SDRC controller */ +#define CONFIG_NAND +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand at */ + /* CS0 */ + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +#include <configs/ti_armv7_common.h> + /* Display CPU and Board information */ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 @@ -45,16 +59,12 @@

#define CONFIG_MISC_INIT_R

-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1

-#define CONFIG_OF_LIBFDT 1 - /* Size of malloc() pool */ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ +#undef CONFIG_SYS_MALLOC_LEN #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))

/* Hardware drivers */ @@ -78,20 +88,15 @@ #define CONFIG_CONS_INDEX 3 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 #define CONFIG_SERIAL3 3 -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200}

-/* MMC */ -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 +/* SPI */ +#undef CONFIG_SPI +#undef CONFIG_OMAP3_SPI

/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#undef CONFIG_SYS_I2C_OMAP24XX #define CONFIG_SYS_I2C_OMAP34XX

/* TWL4030 */ @@ -99,8 +104,6 @@ #define CONFIG_TWL4030_LED 1

/* Board NAND Info */ -#define CONFIG_SYS_NO_FLASH /* no NOR flash */ -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define MTDIDS_DEFAULT "nand0=nand" #define MTDPARTS_DEFAULT "mtdparts=nand:" \ "512k(x-loader)," \ @@ -109,14 +112,8 @@ "4m(kernel)," \ "-(fs)"

-#define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - /* devices */ #define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ #define CONFIG_JFFS2_DEV "nand0" @@ -126,20 +123,20 @@ /* partition */

/* commands to include */ -#include <config_cmd_default.h> - #define CONFIG_CMD_DHCP /* DHCP support */ -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_I2C /* I2C serial bus support */ #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ -#define CONFIG_CMD_NAND /* NAND support */ #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */

#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ #undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_SPI +#undef CONFIG_CMD_GPIO +#undef CONFIG_CMD_ASKENV +#undef CONFIG_CMD_BOOTZ +#undef CONFIG_SUPPORT_RAW_INITRD +#undef CONFIG_FAT_WRITE +#undef CONFIG_CMD_EXT4 +#undef CONFIG_CMD_FS_GENERIC

/* BOOTP/DHCP options */ #define CONFIG_BOOTP_SUBNETMASK @@ -156,10 +153,6 @@ #undef CONFIG_BOOTP_VENDOREX

/* Environment information */ -#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ - -#define CONFIG_BOOTDELAY 3 - #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyO2,115200n8\0" \ @@ -227,38 +220,17 @@

#define CONFIG_BOOTCOMMAND "run autoboot"

-/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # " -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 128 /* max number of command args */ - /* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 0x01000000) /* 16MB */

-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) - /* * OMAP3 has 12 GP timers, they can be driven by the system clock * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). * This rate is divided by a local divisor. */ #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1

/* NAND and environment organization */ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ @@ -268,47 +240,22 @@

#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET

-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - /* SRAM config */ #define CONFIG_SYS_SRAM_START 0x40200000 #define CONFIG_SYS_SRAM_SIZE 0x10000

/* Defines for SPL */ -#define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_NAND_SIMPLE

-#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_POWER_SUPPORT -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#undef CONFIG_SPL_MTD_SUPPORT

#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ +#undef CONFIG_SPL_STACK #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK

-#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - /* NAND boot config */ #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE @@ -324,26 +271,18 @@ #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW

-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE - #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000

-#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ - /* SPL OS boot options */ -#define CONFIG_SPL_OS_BOOT - -#define CONFIG_CMD_SPL #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */ #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\ 0x400000) #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000

-#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" - +#undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR +#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR +#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */ #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */ #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */

Signed-off-by: Anthoine Bourgeois anthoine.bourgeois@gmail.com --- board/timll/devkit8000/devkit8000.c | 13 +++++++++++ include/configs/devkit8000.h | 45 +++---------------------------------- 2 files changed, 16 insertions(+), 42 deletions(-)

diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index b978044..4d07313 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -17,6 +17,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <dm.h> +#include <ns16550.h> #include <twl4030.h> #include <asm/io.h> #include <asm/arch/mmc_host_def.h> @@ -43,6 +45,17 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = { 0 };

+static const struct ns16550_platdata devkit8000_serial = { + OMAP34XX_UART3, + 2, + V_NS16550_CLK +}; + +U_BOOT_DEVICE(devkit8000_uart) = { + "serial_omap", + &devkit8000_serial +}; + /* * Routine: board_init * Description: Early hardware init. diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 182a137..1c69551 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -33,30 +33,17 @@ #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */

-#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> - -#define CONFIG_SDRC /* The chip has SDRC controller */ #define CONFIG_NAND -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */

/* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1

-#include <configs/ti_armv7_common.h> +#include <configs/ti_omap3_common.h>

/* Display CPU and Board information */ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1

-/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - #define CONFIG_MISC_INIT_R

#define CONFIG_REVISION_TAG 1 @@ -78,19 +65,6 @@ #define CONFIG_DM9000_NO_SROM 1 #undef CONFIG_DM9000_DEBUG

-/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -/* select serial console configuration */ -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - /* SPI */ #undef CONFIG_SPI #undef CONFIG_OMAP3_SPI @@ -100,7 +74,6 @@ #define CONFIG_SYS_I2C_OMAP34XX

/* TWL4030 */ -#define CONFIG_TWL4030_POWER 1 #define CONFIG_TWL4030_LED 1

/* Board NAND Info */ @@ -225,16 +198,7 @@ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 0x01000000) /* 16MB */

-/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) - /* NAND and environment organization */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */

@@ -245,14 +209,10 @@ #define CONFIG_SYS_SRAM_SIZE 0x10000

/* Defines for SPL */ -#define CONFIG_SPL_NAND_SIMPLE - -#define CONFIG_SPL_POWER_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" #undef CONFIG_SPL_MTD_SUPPORT

+#undef CONFIG_SPL_TEXT_BASE #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ -#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ #undef CONFIG_SPL_STACK #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK

@@ -287,6 +247,7 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */ #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */

+#undef CONFIG_SYS_SPL_ARGS_ADDR #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)

#endif /* __CONFIG_H */