This driver is a simplified version of linux/drivers/spi/spi-bcm63xx-hsspi.c

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- v2: Introduce changes suggested by Simon Glass: - Split bcm63xx_hsspi_xfer() into smaller functions. - Check possible clock errors. - Check possible reset errors. - Switch to devfdt_get_addr_size_index(). - Use setbits32_be() for clock gate.

drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/bcm63xx_hsspi.c | 413 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 422 insertions(+) create mode 100644 drivers/spi/bcm63xx_hsspi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 0b408db..e49ec36 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -40,6 +40,14 @@ config ATMEL_SPI many AT32 (AVR32) and AT91 (ARM) chips. This driver can be used to access the SPI Flash, such as AT25DF321.

+config BCM6328_HSSPI + bool "BCM6328 HSSPI driver" + depends on ARCH_BMIPS + help + Enable the BCM6328 HSSPI driver. This driver can be used to + access the SPI NOR flash on platforms embedding this Broadcom + SPI core. + choice prompt "BCM63xx SPI driver" depends on ARCH_BMIPS diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 2795a34..7ad0da1 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o +obj-$(CONFIG_BCM6328_HSSPI) += bcm63xx_hsspi.o obj-$(CONFIG_BCM6348_SPI)$(CONFIG_BCM6358_SPI) += bcm63xx_spi.o obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o obj-$(CONFIG_CF_SPI) += cf_spi.o diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c new file mode 100644 index 0000000..538c4ec --- /dev/null +++ b/drivers/spi/bcm63xx_hsspi.c @@ -0,0 +1,413 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com + * + * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c: + * Copyright (C) 2000-2010 Broadcom Corporation + * Copyright (C) 2012-2013 Jonas Gorski jogo@openwrt.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <spi.h> +#include <reset.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define SPI_PP_SEL 0 + +#define SPI_MAX_SYNC_CLOCK 30000000 + +/* SPI Control register */ +#define SPI_CTL_REG 0x000 +#define SPI_CTL_CS_POL_SHIFT 0 +#define SPI_CTL_CS_POL_MASK (0xff << SPI_CTL_CS_POL_SHIFT) +#define SPI_CTL_CLK_GATE_SHIFT 16 +#define SPI_CTL_CLK_GATE_MASK (1 << SPI_CTL_CLK_GATE_SHIFT) +#define SPI_CTL_CLK_POL_SHIFT 17 +#define SPI_CTL_CLK_POL_MASK (1 << SPI_CTL_CLK_POL_SHIFT) + +/* SPI Interrupts registers */ +#define SPI_IR_STAT_REG 0x008 +#define SPI_IR_ST_MASK_REG 0x00c +#define SPI_IR_MASK_REG 0x010 + +#define SPI_IR_CLEAR_ALL 0xff001f1f + +/* SPI Ping-Pong Command registers */ +#define SPI_PP_CMD_REG (0x080 + (0x40 * (SPI_PP_SEL)) + 0x00) +#define SPI_PP_CMD_OP_SHIFT 0 +#define SPI_PP_CMD_OP_START (0x1 << SPI_PP_CMD_OP_SHIFT) +#define SPI_PP_CMD_PFL_SHIFT 8 +#define SPI_PP_CMD_PFL_MASK (0x7 << SPI_PP_CMD_PFL_SHIFT) +#define SPI_PP_CMD_SLAVE_SHIFT 12 +#define SPI_PP_CMD_SLAVE_MASK (0x7 << SPI_PP_CMD_SLAVE_SHIFT) + +/* SPI Ping-Pong Status registers */ +#define SPI_PP_STAT_REG (0x080 + (0x40 * (SPI_PP_SEL)) + 0x04) +#define SPI_PP_STAT_SRCBUSY_SHIFT 1 +#define SPI_PP_STAT_SRCBUSY_MASK (1 << SPI_PP_STAT_SRCBUSY_SHIFT) + +/* SPI Profile Clock registers */ +#define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00) +#define SPI_PFL_CLK_FREQ_SHIFT 0 +#define SPI_PFL_CLK_FREQ_MASK (0x3fff << SPI_PFL_CLK_FREQ_SHIFT) +#define SPI_PFL_CLK_RSTLOOP_SHIFT 15 +#define SPI_PFL_CLK_RSTLOOP_MASK (1 << SPI_PFL_CLK_RSTLOOP_SHIFT) + +/* SPI Profile Signal registers */ +#define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04) +#define SPI_PFL_SIG_LATCHRIS_SHIFT 12 +#define SPI_PFL_SIG_LATCHRIS_MASK (1 << SPI_PFL_SIG_LATCHRIS_SHIFT) +#define SPI_PFL_SIG_LAUNCHRIS_SHIFT 13 +#define SPI_PFL_SIG_LAUNCHRIS_MASK (1 << SPI_PFL_SIG_LAUNCHRIS_SHIFT) +#define SPI_PFL_SIG_ASYNCIN_SHIFT 16 +#define SPI_PFL_SIG_ASYNCIN_MASK (1 << SPI_PFL_SIG_ASYNCIN_SHIFT) + +/* SPI Profile Mode registers */ +#define SPI_PFL_MODE_REG(x) (0x100 + (0x20 * (x)) + 0x08) +#define SPI_PFL_MODE_FILL_SHIFT 0 +#define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT) +#define SPI_PFL_MODE_MDRDSZ_SHIFT 16 +#define SPI_PFL_MODE_MDRDSZ_MASK (1 << SPI_PFL_MODE_MDRDSZ_SHIFT) +#define SPI_PFL_MODE_MDWRSZ_SHIFT 18 +#define SPI_PFL_MODE_MDWRSZ_MASK (1 << SPI_PFL_MODE_MDWRSZ_SHIFT) +#define SPI_PFL_MODE_3WIRE_SHIFT 20 +#define SPI_PFL_MODE_3WIRE_MASK (1 << SPI_PFL_MODE_3WIRE_SHIFT) + +/* SPI Ping-Pong FIFO registers */ +#define SPI_PP_FIFO_SIZE 0x200 +#define SPI_PP_FIFO_BASE (0x200 + \ + (SPI_PP_FIFO_SIZE * SPI_PP_SEL)) + +/* SPI Ping-Pong FIFO OP register */ +#define SPI_PP_FIFO_OP_SIZE 0x2 +#define SPI_PP_FIFO_OP_REG (SPI_PP_FIFO_BASE + 0x00) +#define SPI_PP_FIFO_OP_BYTES_SHIFT 0 +#define SPI_PP_FIFO_OP_BYTES_MASK (0x3ff << SPI_PP_FIFO_OP_BYTES_SHIFT) +#define SPI_PP_FIFO_OP_MBIT_SHIFT 11 +#define SPI_PP_FIFO_OP_MBIT_MASK (1 << SPI_PP_FIFO_OP_MBIT_SHIFT) +#define SPI_PP_FIFO_OP_CODE_SHIFT 13 +#define SPI_PP_FIFO_OP_CODE_RW (1 << SPI_PP_FIFO_OP_CODE_SHIFT) +#define SPI_PP_FIFO_OP_CODE_W (2 << SPI_PP_FIFO_OP_CODE_SHIFT) +#define SPI_PP_FIFO_OP_CODE_R (3 << SPI_PP_FIFO_OP_CODE_SHIFT) + +struct bcm63xx_hsspi_priv { + void __iomem *regs; + ulong clk_rate; + uint8_t num_cs; + uint8_t cs_pols; + uint speed; +}; + +static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs, + struct spi_cs_info *info) +{ + struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus); + + if (cs >= priv->num_cs) { + error("no cs %u\n", cs); + return -ENODEV; + } + + return 0; +} + +static int bcm63xx_hsspi_set_mode(struct udevice *bus, uint mode) +{ + struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus); + + /* clock polarity */ + if (mode & SPI_CPOL) + setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); + else + clrbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); + + return 0; +} + +static int bcm63xx_hsspi_set_speed(struct udevice *bus, uint speed) +{ + struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus); + + priv->speed = speed; + + return 0; +} + +static void bcm63xx_hsspi_claim_cs(struct bcm63xx_hsspi_priv *priv, + struct dm_spi_slave_platdata *plat) +{ + uint32_t clr, set; + + /* profile clock */ + set = DIV_ROUND_UP(priv->clk_rate, priv->speed); + set = DIV_ROUND_UP(2048, set); + set &= SPI_PFL_CLK_FREQ_MASK; + set |= SPI_PFL_CLK_RSTLOOP_MASK; + writel_be(set, priv->regs + SPI_PFL_CLK_REG(plat->cs)); + + /* profile signal */ + set = 0; + clr = SPI_PFL_SIG_LAUNCHRIS_MASK | + SPI_PFL_SIG_LATCHRIS_MASK | + SPI_PFL_SIG_ASYNCIN_MASK; + + /* latch/launch config */ + if (plat->mode & SPI_CPHA) + set |= SPI_PFL_SIG_LAUNCHRIS_MASK; + else + set |= SPI_PFL_SIG_LATCHRIS_MASK; + + /* async clk */ + if (priv->speed > SPI_MAX_SYNC_CLOCK) + set |= SPI_PFL_SIG_ASYNCIN_MASK; + + clrsetbits_be32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set); + + /* global control */ + set = 0; + clr = 0; + + /* invert cs polarity */ + if (priv->cs_pols & BIT(plat->cs)) + clr |= BIT(plat->cs); + else + set |= BIT(plat->cs); + + /* invert dummy cs polarity */ + if (priv->cs_pols & BIT(!plat->cs)) + clr |= BIT(!plat->cs); + else + set |= BIT(!plat->cs); + + clrsetbits_be32(priv->regs + SPI_CTL_REG, clr, set); +} + +static void bcm63xx_hsspi_release_cs(struct bcm63xx_hsspi_priv *priv) +{ + /* restore cs polarities */ + clrsetbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK, + priv->cs_pols); +} + +/* + * BCM63xx HSSPI driver doesn't allow keeping CS active between transfers + * because they are controlled by HW. + * However, it provides a mechanism to prepend write transfers prior to read + * transfers (with a maximum prepend of 15 bytes), which is usually enough for + * SPI-connected flashes since reading requires prepending a write transfer of + * 5 bytes. On the other hand it also provides a way to invert each CS + * polarity, not only between transfers like the older BCM63xx SPI driver, but + * also the rest of the time. + * + * Instead of using the prepend mechanism, this implementation inverts the + * polarity of both the desired CS and another dummy CS when the bus is + * claimed. This way, the dummy CS is restored to its inactive value when + * transfers are issued and the desired CS is preserved in its active value + * all the time. This hack is also used in the upstream linux driver and + * allows keeping CS active between trasnfers even if the HW doesn't give + * this possibility. + */ +static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent); + struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev); + size_t data_bytes = bitlen / 8; + size_t step_size = SPI_PP_FIFO_SIZE; + uint16_t opcode = 0; + uint32_t val; + const uint8_t *tx = dout; + uint8_t *rx = din; + + if (flags & SPI_XFER_BEGIN) + bcm63xx_hsspi_claim_cs(priv, plat); + + /* fifo operation */ + if (tx && rx) + opcode = SPI_PP_FIFO_OP_CODE_RW; + else if (rx) + opcode = SPI_PP_FIFO_OP_CODE_R; + else if (tx) + opcode = SPI_PP_FIFO_OP_CODE_W; + + if (opcode != SPI_PP_FIFO_OP_CODE_R) + step_size -= SPI_PP_FIFO_OP_SIZE; + + /* dual mode */ + if ((opcode == SPI_PP_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) || + (opcode == SPI_PP_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL)) + opcode |= SPI_PP_FIFO_OP_MBIT_MASK; + + /* profile mode */ + val = SPI_PFL_MODE_FILL_MASK | + SPI_PFL_MODE_MDRDSZ_MASK | + SPI_PFL_MODE_MDWRSZ_MASK; + if (plat->mode & SPI_3WIRE) + val |= SPI_PFL_MODE_3WIRE_MASK; + writel_be(val, priv->regs + SPI_PFL_MODE_REG(plat->cs)); + + /* transfer loop */ + while (data_bytes > 0) { + size_t curr_step = min(step_size, data_bytes); + + /* copy tx data */ + if (tx) { + memcpy_toio(priv->regs + SPI_PP_FIFO_BASE + + SPI_PP_FIFO_OP_SIZE, tx, curr_step); + tx += curr_step; + } + + /* set fifo operation */ + writew_be(opcode | (curr_step & SPI_PP_FIFO_OP_BYTES_MASK), + priv->regs + SPI_PP_FIFO_OP_REG); + + /* issue the transfer */ + val = SPI_PP_CMD_OP_START; + val |= (plat->cs << SPI_PP_CMD_PFL_SHIFT) & + SPI_PP_CMD_PFL_MASK; + val |= (!plat->cs << SPI_PP_CMD_SLAVE_SHIFT) & + SPI_PP_CMD_SLAVE_MASK; + writel_be(val, priv->regs + SPI_PP_CMD_REG); + + /* wait for completion */ + do { + /* check ping-pong status */ + val = readl_be(priv->regs + SPI_PP_STAT_REG); + + /* transfer completed */ + if (!(val & SPI_PP_STAT_SRCBUSY_MASK)) + break; + } while (1); + + /* copy rx data */ + if (rx) { + memcpy_fromio(rx, priv->regs + SPI_PP_FIFO_BASE, + curr_step); + rx += curr_step; + } + + data_bytes -= curr_step; + } + + if (flags & SPI_XFER_END) + bcm63xx_hsspi_release_cs(priv); + + return 0; +} + +static const struct dm_spi_ops bcm63xx_hsspi_ops = { + .cs_info = bcm63xx_hsspi_cs_info, + .set_mode = bcm63xx_hsspi_set_mode, + .set_speed = bcm63xx_hsspi_set_speed, + .xfer = bcm63xx_hsspi_xfer, +}; + +static const struct udevice_id bcm63xx_hsspi_ids[] = { + { .compatible = "brcm,bcm6328-hsspi", }, + { /* sentinel */ } +}; + +static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev) +{ + struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent); + struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev); + + /* check cs */ + if (plat->cs >= priv->num_cs) { + error("no cs %u\n", plat->cs); + return -ENODEV; + } + + /* cs polarity */ + if (plat->mode & SPI_CS_HIGH) + priv->cs_pols |= BIT(plat->cs); + else + priv->cs_pols &= ~BIT(plat->cs); + + return 0; +} + +static int bcm63xx_hsspi_probe(struct udevice *dev) +{ + struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev); + struct reset_ctl rst_ctl; + struct clk clk; + fdt_addr_t addr; + fdt_size_t size; + int ret; + + addr = devfdt_get_addr_size_index(dev, 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = ioremap(addr, size); + priv->num_cs = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), + "num-cs", 8); + + /* enable clock */ + ret = clk_get_by_name(dev, "hsspi", &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + if (ret < 0) + return ret; + + ret = clk_free(&clk); + if (ret < 0) + return ret; + + /* get clock rate */ + ret = clk_get_by_name(dev, "pll", &clk); + if (ret < 0) + return ret; + + priv->clk_rate = clk_get_rate(&clk); + + ret = clk_free(&clk); + if (ret < 0) + return ret; + + /* perform reset */ + ret = reset_get_by_index(dev, 0, &rst_ctl); + if (ret < 0) + return ret; + + ret = reset_deassert(&rst_ctl); + if (ret < 0) + return ret; + + ret = reset_free(&rst_ctl); + if (ret < 0) + return ret; + + /* initialize hardware */ + writel_be(0, priv->regs + SPI_IR_MASK_REG); + + /* clear pending interrupts */ + writel_be(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG); + + /* enable clk gate */ + setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK); + + /* read default cs polarities */ + priv->cs_pols = readl_be(priv->regs + SPI_CTL_REG) & + SPI_CTL_CS_POL_MASK; + + return 0; +} + +U_BOOT_DRIVER(bcm63xx_hsspi) = { + .name = "bcm63xx_hsspi", + .id = UCLASS_SPI, + .of_match = bcm63xx_hsspi_ids, + .ops = &bcm63xx_hsspi_ops, + .priv_auto_alloc_size = sizeof(struct bcm63xx_hsspi_priv), + .child_pre_probe = bcm63xx_hsspi_child_pre_probe, + .probe = bcm63xx_hsspi_probe, +};

This driver manages the high speed SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- v2: no changes

arch/mips/dts/brcm,bcm63268.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)

diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index 6e3d9c3..4d4e36c 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -15,6 +15,7 @@

aliases { spi0 = &lsspi; + spi1 = &hsspi; };

cpus { @@ -44,6 +45,12 @@ #size-cells = <1>; u-boot,dm-pre-reloc;

+ hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + periph_osc: periph-osc { compatible = "fixed-clock"; #clock-cells = <0>; @@ -153,6 +160,20 @@ status = "disabled"; };

+ hsspi: spi@10001000 { + compatible = "brcm,bcm6328-hsspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10001000 0x600>; + clocks = <&periph_clk BCM63268_CLK_HSSPI>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + resets = <&periph_rst BCM63268_RST_SPI>; + spi-max-frequency = <50000000>; + num-cs = <8>; + + status = "disabled"; + }; + leds: led-controller@10001900 { compatible = "brcm,bcm6328-leds"; reg = <0x10001900 0x24>;

This driver manages the SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com --- v3: no changes v2: no changes

arch/mips/dts/brcm,bcm6328.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)

diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi index a996075..67d9278 100644 --- a/arch/mips/dts/brcm,bcm6328.dtsi +++ b/arch/mips/dts/brcm,bcm6328.dtsi @@ -13,6 +13,10 @@ / { compatible = "brcm,bcm6328";

+ aliases { + spi0 = &spi; + }; + cpus { reg = <0x10000000 0x4>; #address-cells = <1>; @@ -40,6 +44,12 @@ #size-cells = <1>; u-boot,dm-pre-reloc;

+ hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133333333>; + }; + periph_osc: periph-osc { compatible = "fixed-clock"; #clock-cells = <0>; @@ -123,6 +133,20 @@ status = "disabled"; };

+ spi: spi@10001000 { + compatible = "brcm,bcm6328-hsspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10001000 0x600>; + clocks = <&periph_clk BCM6328_CLK_HSSPI>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + resets = <&periph_rst BCM6328_RST_SPI>; + spi-max-frequency = <33333334>; + num-cs = <3>; + + status = "disabled"; + }; + periph_pwr: power-controller@10001848 { compatible = "brcm,bcm6328-power-domain"; reg = <0x10001848 0x4>;

It's a Macronix (mx25l12805d) 16 MB SPI flash.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com --- v3: switch to CONFIG_BCM63XX_HSSPI v2: no changes

arch/mips/dts/comtrend,ar-5387un.dts | 12 ++++++++++++ configs/comtrend_ar5387un_ram_defconfig | 8 ++++++++ 2 files changed, 20 insertions(+)

diff --git a/arch/mips/dts/comtrend,ar-5387un.dts b/arch/mips/dts/comtrend,ar-5387un.dts index 73f2b49..6067881 100644 --- a/arch/mips/dts/comtrend,ar-5387un.dts +++ b/arch/mips/dts/comtrend,ar-5387un.dts @@ -51,6 +51,18 @@ }; };

+&spi { + status = "okay"; + + spi-flash@0 { + compatible = "spi-flash"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <33333334>; + }; +}; + &uart0 { u-boot,dm-pre-reloc; status = "okay"; diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig index 5b05fd2..b5433bd 100644 --- a/configs/comtrend_ar5387un_ram_defconfig +++ b/configs/comtrend_ar5387un_ram_defconfig @@ -3,6 +3,7 @@ CONFIG_BAUDRATE=115200 CONFIG_BCM6328_POWER_DOMAIN=y CONFIG_BCM6345_CLK=y CONFIG_BCM6345_SERIAL=y +CONFIG_BCM63XX_HSSPI=y CONFIG_BMIPS_BOOT_RAM=y CONFIG_BOARD_COMTREND_AR5387UN=y # CONFIG_CMD_BOOTD is not set @@ -27,6 +28,8 @@ CONFIG_CMD_MEMINFO=y # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set # CONFIG_CMD_SAVEENV is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y # CONFIG_CMD_XIMG is not set CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5387un" CONFIG_DISPLAY_CPUINFO=y @@ -34,6 +37,8 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DM_GPIO=y CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_HUSH_PARSER=y CONFIG_LED=y CONFIG_LED_BCM6328=y @@ -47,6 +52,9 @@ CONFIG_POWER_DOMAIN=y CONFIG_RESET=y CONFIG_RESET_BCM6345=y CONFIG_SOC_BMIPS_BCM6328=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_SPI_FLASH_MACRONIX=y # CONFIG_SPL_SERIAL_PRESENT is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SYS_NO_FLASH=y

This driver is a simplified version of linux/drivers/spi/spi-bcm63xx-hsspi.c

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com --- v4: no changes. v3: Switch to CONFIG_BCM63XX_HSSPI and rebase on top of SPI v4. v2: Introduce changes suggested by Simon Glass: - Split bcm63xx_hsspi_xfer() into smaller functions. - Check possible clock errors. - Check possible reset errors. - Switch to devfdt_get_addr_size_index(). - Use setbits32_be() for clock gate.

drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/bcm63xx_hsspi.c | 413 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 422 insertions(+) create mode 100644 drivers/spi/bcm63xx_hsspi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 511643607b..97c3cb6103 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -40,6 +40,14 @@ config ATMEL_SPI many AT91 (ARM) chips. This driver can be used to access the SPI Flash, such as AT25DF321.

+config BCM63XX_HSSPI + bool "BCM63XX HSSPI driver" + depends on ARCH_BMIPS + help + Enable the BCM6328 HSSPI driver. This driver can be used to + access the SPI NOR flash on platforms embedding this Broadcom + SPI core. + config BCM63XX_SPI bool "BCM6348 SPI driver" depends on ARCH_BMIPS diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index d9802dd8c3..fefafbe333 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o +obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o obj-$(CONFIG_CF_SPI) += cf_spi.o diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c new file mode 100644 index 0000000000..538c4ec4fe --- /dev/null +++ b/drivers/spi/bcm63xx_hsspi.c @@ -0,0 +1,413 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com + * + * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c: + * Copyright (C) 2000-2010 Broadcom Corporation + * Copyright (C) 2012-2013 Jonas Gorski jogo@openwrt.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <spi.h> +#include <reset.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define SPI_PP_SEL 0 + +#define SPI_MAX_SYNC_CLOCK 30000000 + +/* SPI Control register */ +#define SPI_CTL_REG 0x000 +#define SPI_CTL_CS_POL_SHIFT 0 +#define SPI_CTL_CS_POL_MASK (0xff << SPI_CTL_CS_POL_SHIFT) +#define SPI_CTL_CLK_GATE_SHIFT 16 +#define SPI_CTL_CLK_GATE_MASK (1 << SPI_CTL_CLK_GATE_SHIFT) +#define SPI_CTL_CLK_POL_SHIFT 17 +#define SPI_CTL_CLK_POL_MASK (1 << SPI_CTL_CLK_POL_SHIFT) + +/* SPI Interrupts registers */ +#define SPI_IR_STAT_REG 0x008 +#define SPI_IR_ST_MASK_REG 0x00c +#define SPI_IR_MASK_REG 0x010 + +#define SPI_IR_CLEAR_ALL 0xff001f1f + +/* SPI Ping-Pong Command registers */ +#define SPI_PP_CMD_REG (0x080 + (0x40 * (SPI_PP_SEL)) + 0x00) +#define SPI_PP_CMD_OP_SHIFT 0 +#define SPI_PP_CMD_OP_START (0x1 << SPI_PP_CMD_OP_SHIFT) +#define SPI_PP_CMD_PFL_SHIFT 8 +#define SPI_PP_CMD_PFL_MASK (0x7 << SPI_PP_CMD_PFL_SHIFT) +#define SPI_PP_CMD_SLAVE_SHIFT 12 +#define SPI_PP_CMD_SLAVE_MASK (0x7 << SPI_PP_CMD_SLAVE_SHIFT) + +/* SPI Ping-Pong Status registers */ +#define SPI_PP_STAT_REG (0x080 + (0x40 * (SPI_PP_SEL)) + 0x04) +#define SPI_PP_STAT_SRCBUSY_SHIFT 1 +#define SPI_PP_STAT_SRCBUSY_MASK (1 << SPI_PP_STAT_SRCBUSY_SHIFT) + +/* SPI Profile Clock registers */ +#define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00) +#define SPI_PFL_CLK_FREQ_SHIFT 0 +#define SPI_PFL_CLK_FREQ_MASK (0x3fff << SPI_PFL_CLK_FREQ_SHIFT) +#define SPI_PFL_CLK_RSTLOOP_SHIFT 15 +#define SPI_PFL_CLK_RSTLOOP_MASK (1 << SPI_PFL_CLK_RSTLOOP_SHIFT) + +/* SPI Profile Signal registers */ +#define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04) +#define SPI_PFL_SIG_LATCHRIS_SHIFT 12 +#define SPI_PFL_SIG_LATCHRIS_MASK (1 << SPI_PFL_SIG_LATCHRIS_SHIFT) +#define SPI_PFL_SIG_LAUNCHRIS_SHIFT 13 +#define SPI_PFL_SIG_LAUNCHRIS_MASK (1 << SPI_PFL_SIG_LAUNCHRIS_SHIFT) +#define SPI_PFL_SIG_ASYNCIN_SHIFT 16 +#define SPI_PFL_SIG_ASYNCIN_MASK (1 << SPI_PFL_SIG_ASYNCIN_SHIFT) + +/* SPI Profile Mode registers */ +#define SPI_PFL_MODE_REG(x) (0x100 + (0x20 * (x)) + 0x08) +#define SPI_PFL_MODE_FILL_SHIFT 0 +#define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT) +#define SPI_PFL_MODE_MDRDSZ_SHIFT 16 +#define SPI_PFL_MODE_MDRDSZ_MASK (1 << SPI_PFL_MODE_MDRDSZ_SHIFT) +#define SPI_PFL_MODE_MDWRSZ_SHIFT 18 +#define SPI_PFL_MODE_MDWRSZ_MASK (1 << SPI_PFL_MODE_MDWRSZ_SHIFT) +#define SPI_PFL_MODE_3WIRE_SHIFT 20 +#define SPI_PFL_MODE_3WIRE_MASK (1 << SPI_PFL_MODE_3WIRE_SHIFT) + +/* SPI Ping-Pong FIFO registers */ +#define SPI_PP_FIFO_SIZE 0x200 +#define SPI_PP_FIFO_BASE (0x200 + \ + (SPI_PP_FIFO_SIZE * SPI_PP_SEL)) + +/* SPI Ping-Pong FIFO OP register */ +#define SPI_PP_FIFO_OP_SIZE 0x2 +#define SPI_PP_FIFO_OP_REG (SPI_PP_FIFO_BASE + 0x00) +#define SPI_PP_FIFO_OP_BYTES_SHIFT 0 +#define SPI_PP_FIFO_OP_BYTES_MASK (0x3ff << SPI_PP_FIFO_OP_BYTES_SHIFT) +#define SPI_PP_FIFO_OP_MBIT_SHIFT 11 +#define SPI_PP_FIFO_OP_MBIT_MASK (1 << SPI_PP_FIFO_OP_MBIT_SHIFT) +#define SPI_PP_FIFO_OP_CODE_SHIFT 13 +#define SPI_PP_FIFO_OP_CODE_RW (1 << SPI_PP_FIFO_OP_CODE_SHIFT) +#define SPI_PP_FIFO_OP_CODE_W (2 << SPI_PP_FIFO_OP_CODE_SHIFT) +#define SPI_PP_FIFO_OP_CODE_R (3 << SPI_PP_FIFO_OP_CODE_SHIFT) + +struct bcm63xx_hsspi_priv { + void __iomem *regs; + ulong clk_rate; + uint8_t num_cs; + uint8_t cs_pols; + uint speed; +}; + +static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs, + struct spi_cs_info *info) +{ + struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus); + + if (cs >= priv->num_cs) { + error("no cs %u\n", cs); + return -ENODEV; + } + + return 0; +} + +static int bcm63xx_hsspi_set_mode(struct udevice *bus, uint mode) +{ + struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus); + + /* clock polarity */ + if (mode & SPI_CPOL) + setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); + else + clrbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); + + return 0; +} + +static int bcm63xx_hsspi_set_speed(struct udevice *bus, uint speed) +{ + struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus); + + priv->speed = speed; + + return 0; +} + +static void bcm63xx_hsspi_claim_cs(struct bcm63xx_hsspi_priv *priv, + struct dm_spi_slave_platdata *plat) +{ + uint32_t clr, set; + + /* profile clock */ + set = DIV_ROUND_UP(priv->clk_rate, priv->speed); + set = DIV_ROUND_UP(2048, set); + set &= SPI_PFL_CLK_FREQ_MASK; + set |= SPI_PFL_CLK_RSTLOOP_MASK; + writel_be(set, priv->regs + SPI_PFL_CLK_REG(plat->cs)); + + /* profile signal */ + set = 0; + clr = SPI_PFL_SIG_LAUNCHRIS_MASK | + SPI_PFL_SIG_LATCHRIS_MASK | + SPI_PFL_SIG_ASYNCIN_MASK; + + /* latch/launch config */ + if (plat->mode & SPI_CPHA) + set |= SPI_PFL_SIG_LAUNCHRIS_MASK; + else + set |= SPI_PFL_SIG_LATCHRIS_MASK; + + /* async clk */ + if (priv->speed > SPI_MAX_SYNC_CLOCK) + set |= SPI_PFL_SIG_ASYNCIN_MASK; + + clrsetbits_be32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set); + + /* global control */ + set = 0; + clr = 0; + + /* invert cs polarity */ + if (priv->cs_pols & BIT(plat->cs)) + clr |= BIT(plat->cs); + else + set |= BIT(plat->cs); + + /* invert dummy cs polarity */ + if (priv->cs_pols & BIT(!plat->cs)) + clr |= BIT(!plat->cs); + else + set |= BIT(!plat->cs); + + clrsetbits_be32(priv->regs + SPI_CTL_REG, clr, set); +} + +static void bcm63xx_hsspi_release_cs(struct bcm63xx_hsspi_priv *priv) +{ + /* restore cs polarities */ + clrsetbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK, + priv->cs_pols); +} + +/* + * BCM63xx HSSPI driver doesn't allow keeping CS active between transfers + * because they are controlled by HW. + * However, it provides a mechanism to prepend write transfers prior to read + * transfers (with a maximum prepend of 15 bytes), which is usually enough for + * SPI-connected flashes since reading requires prepending a write transfer of + * 5 bytes. On the other hand it also provides a way to invert each CS + * polarity, not only between transfers like the older BCM63xx SPI driver, but + * also the rest of the time. + * + * Instead of using the prepend mechanism, this implementation inverts the + * polarity of both the desired CS and another dummy CS when the bus is + * claimed. This way, the dummy CS is restored to its inactive value when + * transfers are issued and the desired CS is preserved in its active value + * all the time. This hack is also used in the upstream linux driver and + * allows keeping CS active between trasnfers even if the HW doesn't give + * this possibility. + */ +static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent); + struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev); + size_t data_bytes = bitlen / 8; + size_t step_size = SPI_PP_FIFO_SIZE; + uint16_t opcode = 0; + uint32_t val; + const uint8_t *tx = dout; + uint8_t *rx = din; + + if (flags & SPI_XFER_BEGIN) + bcm63xx_hsspi_claim_cs(priv, plat); + + /* fifo operation */ + if (tx && rx) + opcode = SPI_PP_FIFO_OP_CODE_RW; + else if (rx) + opcode = SPI_PP_FIFO_OP_CODE_R; + else if (tx) + opcode = SPI_PP_FIFO_OP_CODE_W; + + if (opcode != SPI_PP_FIFO_OP_CODE_R) + step_size -= SPI_PP_FIFO_OP_SIZE; + + /* dual mode */ + if ((opcode == SPI_PP_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) || + (opcode == SPI_PP_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL)) + opcode |= SPI_PP_FIFO_OP_MBIT_MASK; + + /* profile mode */ + val = SPI_PFL_MODE_FILL_MASK | + SPI_PFL_MODE_MDRDSZ_MASK | + SPI_PFL_MODE_MDWRSZ_MASK; + if (plat->mode & SPI_3WIRE) + val |= SPI_PFL_MODE_3WIRE_MASK; + writel_be(val, priv->regs + SPI_PFL_MODE_REG(plat->cs)); + + /* transfer loop */ + while (data_bytes > 0) { + size_t curr_step = min(step_size, data_bytes); + + /* copy tx data */ + if (tx) { + memcpy_toio(priv->regs + SPI_PP_FIFO_BASE + + SPI_PP_FIFO_OP_SIZE, tx, curr_step); + tx += curr_step; + } + + /* set fifo operation */ + writew_be(opcode | (curr_step & SPI_PP_FIFO_OP_BYTES_MASK), + priv->regs + SPI_PP_FIFO_OP_REG); + + /* issue the transfer */ + val = SPI_PP_CMD_OP_START; + val |= (plat->cs << SPI_PP_CMD_PFL_SHIFT) & + SPI_PP_CMD_PFL_MASK; + val |= (!plat->cs << SPI_PP_CMD_SLAVE_SHIFT) & + SPI_PP_CMD_SLAVE_MASK; + writel_be(val, priv->regs + SPI_PP_CMD_REG); + + /* wait for completion */ + do { + /* check ping-pong status */ + val = readl_be(priv->regs + SPI_PP_STAT_REG); + + /* transfer completed */ + if (!(val & SPI_PP_STAT_SRCBUSY_MASK)) + break; + } while (1); + + /* copy rx data */ + if (rx) { + memcpy_fromio(rx, priv->regs + SPI_PP_FIFO_BASE, + curr_step); + rx += curr_step; + } + + data_bytes -= curr_step; + } + + if (flags & SPI_XFER_END) + bcm63xx_hsspi_release_cs(priv); + + return 0; +} + +static const struct dm_spi_ops bcm63xx_hsspi_ops = { + .cs_info = bcm63xx_hsspi_cs_info, + .set_mode = bcm63xx_hsspi_set_mode, + .set_speed = bcm63xx_hsspi_set_speed, + .xfer = bcm63xx_hsspi_xfer, +}; + +static const struct udevice_id bcm63xx_hsspi_ids[] = { + { .compatible = "brcm,bcm6328-hsspi", }, + { /* sentinel */ } +}; + +static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev) +{ + struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent); + struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev); + + /* check cs */ + if (plat->cs >= priv->num_cs) { + error("no cs %u\n", plat->cs); + return -ENODEV; + } + + /* cs polarity */ + if (plat->mode & SPI_CS_HIGH) + priv->cs_pols |= BIT(plat->cs); + else + priv->cs_pols &= ~BIT(plat->cs); + + return 0; +} + +static int bcm63xx_hsspi_probe(struct udevice *dev) +{ + struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev); + struct reset_ctl rst_ctl; + struct clk clk; + fdt_addr_t addr; + fdt_size_t size; + int ret; + + addr = devfdt_get_addr_size_index(dev, 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = ioremap(addr, size); + priv->num_cs = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), + "num-cs", 8); + + /* enable clock */ + ret = clk_get_by_name(dev, "hsspi", &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + if (ret < 0) + return ret; + + ret = clk_free(&clk); + if (ret < 0) + return ret; + + /* get clock rate */ + ret = clk_get_by_name(dev, "pll", &clk); + if (ret < 0) + return ret; + + priv->clk_rate = clk_get_rate(&clk); + + ret = clk_free(&clk); + if (ret < 0) + return ret; + + /* perform reset */ + ret = reset_get_by_index(dev, 0, &rst_ctl); + if (ret < 0) + return ret; + + ret = reset_deassert(&rst_ctl); + if (ret < 0) + return ret; + + ret = reset_free(&rst_ctl); + if (ret < 0) + return ret; + + /* initialize hardware */ + writel_be(0, priv->regs + SPI_IR_MASK_REG); + + /* clear pending interrupts */ + writel_be(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG); + + /* enable clk gate */ + setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK); + + /* read default cs polarities */ + priv->cs_pols = readl_be(priv->regs + SPI_CTL_REG) & + SPI_CTL_CS_POL_MASK; + + return 0; +} + +U_BOOT_DRIVER(bcm63xx_hsspi) = { + .name = "bcm63xx_hsspi", + .id = UCLASS_SPI, + .of_match = bcm63xx_hsspi_ids, + .ops = &bcm63xx_hsspi_ops, + .priv_auto_alloc_size = sizeof(struct bcm63xx_hsspi_priv), + .child_pre_probe = bcm63xx_hsspi_child_pre_probe, + .probe = bcm63xx_hsspi_probe, +};

Hi Jagan,

El 11/08/2017 a las 11:42, Jagan Teki escribió:

On Sun, Jul 30, 2017 at 5:44 PM, Álvaro Fernández Rojas noltari@gmail.com wrote:

...

This driver is a simplified version of linux/drivers/spi/spi-bcm63xx-hsspi.c

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com

---

v4: no changes. v3: Switch to CONFIG_BCM63XX_HSSPI and rebase on top of SPI v4. v2: Introduce changes suggested by Simon Glass:

• Split bcm63xx_hsspi_xfer() into smaller functions.
• Check possible clock errors.
• Check possible reset errors.
• Switch to devfdt_get_addr_size_index().
• Use setbits32_be() for clock gate.

drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/bcm63xx_hsspi.c | 413 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 422 insertions(+) create mode 100644 drivers/spi/bcm63xx_hsspi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 511643607b..97c3cb6103 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -40,6 +40,14 @@ config ATMEL_SPI many AT91 (ARM) chips. This driver can be used to access the SPI Flash, such as AT25DF321.

+config BCM63XX_HSSPI

•   bool "BCM63XX HSSPI driver"
  

•   depends on ARCH_BMIPS
  

•   help
  

•     Enable the BCM6328 HSSPI driver. This driver can be used to
  

•     access the SPI NOR flash on platforms embedding this Broadcom
  

•     SPI core.
  

• config BCM63XX_SPI bool "BCM6348 SPI driver" depends on ARCH_BMIPS

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index d9802dd8c3..fefafbe333 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o +obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o obj-$(CONFIG_CF_SPI) += cf_spi.o diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c new file mode 100644 index 0000000000..538c4ec4fe --- /dev/null +++ b/drivers/spi/bcm63xx_hsspi.c @@ -0,0 +1,413 @@ +/*

• • Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com
• • Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:

• • Copyright (C) 2000-2010 Broadcom Corporation
    

• • Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org>
    

• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <clk.h> +#include <dm.h> +#include <spi.h> +#include <reset.h> +#include <asm/io.h>

+DECLARE_GLOBAL_DATA_PTR;

+#define SPI_PP_SEL 0

+#define SPI_MAX_SYNC_CLOCK 30000000

+/* SPI Control register */ +#define SPI_CTL_REG 0x000 +#define SPI_CTL_CS_POL_SHIFT 0 +#define SPI_CTL_CS_POL_MASK (0xff << SPI_CTL_CS_POL_SHIFT) +#define SPI_CTL_CLK_GATE_SHIFT 16 +#define SPI_CTL_CLK_GATE_MASK (1 << SPI_CTL_CLK_GATE_SHIFT) +#define SPI_CTL_CLK_POL_SHIFT 17 +#define SPI_CTL_CLK_POL_MASK (1 << SPI_CTL_CLK_POL_SHIFT)

+/* SPI Interrupts registers */ +#define SPI_IR_STAT_REG 0x008 +#define SPI_IR_ST_MASK_REG 0x00c +#define SPI_IR_MASK_REG 0x010

+#define SPI_IR_CLEAR_ALL 0xff001f1f

+/* SPI Ping-Pong Command registers */ +#define SPI_PP_CMD_REG (0x080 + (0x40 * (SPI_PP_SEL)) + 0x00) +#define SPI_PP_CMD_OP_SHIFT 0 +#define SPI_PP_CMD_OP_START (0x1 << SPI_PP_CMD_OP_SHIFT) +#define SPI_PP_CMD_PFL_SHIFT 8 +#define SPI_PP_CMD_PFL_MASK (0x7 << SPI_PP_CMD_PFL_SHIFT) +#define SPI_PP_CMD_SLAVE_SHIFT 12 +#define SPI_PP_CMD_SLAVE_MASK (0x7 << SPI_PP_CMD_SLAVE_SHIFT)

+/* SPI Ping-Pong Status registers */ +#define SPI_PP_STAT_REG (0x080 + (0x40 * (SPI_PP_SEL)) + 0x04) +#define SPI_PP_STAT_SRCBUSY_SHIFT 1 +#define SPI_PP_STAT_SRCBUSY_MASK (1 << SPI_PP_STAT_SRCBUSY_SHIFT)

+/* SPI Profile Clock registers */ +#define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00) +#define SPI_PFL_CLK_FREQ_SHIFT 0 +#define SPI_PFL_CLK_FREQ_MASK (0x3fff << SPI_PFL_CLK_FREQ_SHIFT) +#define SPI_PFL_CLK_RSTLOOP_SHIFT 15 +#define SPI_PFL_CLK_RSTLOOP_MASK (1 << SPI_PFL_CLK_RSTLOOP_SHIFT)

+/* SPI Profile Signal registers */ +#define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04) +#define SPI_PFL_SIG_LATCHRIS_SHIFT 12 +#define SPI_PFL_SIG_LATCHRIS_MASK (1 << SPI_PFL_SIG_LATCHRIS_SHIFT) +#define SPI_PFL_SIG_LAUNCHRIS_SHIFT 13 +#define SPI_PFL_SIG_LAUNCHRIS_MASK (1 << SPI_PFL_SIG_LAUNCHRIS_SHIFT) +#define SPI_PFL_SIG_ASYNCIN_SHIFT 16 +#define SPI_PFL_SIG_ASYNCIN_MASK (1 << SPI_PFL_SIG_ASYNCIN_SHIFT)

+/* SPI Profile Mode registers */ +#define SPI_PFL_MODE_REG(x) (0x100 + (0x20 * (x)) + 0x08) +#define SPI_PFL_MODE_FILL_SHIFT 0 +#define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT) +#define SPI_PFL_MODE_MDRDSZ_SHIFT 16 +#define SPI_PFL_MODE_MDRDSZ_MASK (1 << SPI_PFL_MODE_MDRDSZ_SHIFT) +#define SPI_PFL_MODE_MDWRSZ_SHIFT 18 +#define SPI_PFL_MODE_MDWRSZ_MASK (1 << SPI_PFL_MODE_MDWRSZ_SHIFT) +#define SPI_PFL_MODE_3WIRE_SHIFT 20 +#define SPI_PFL_MODE_3WIRE_MASK (1 << SPI_PFL_MODE_3WIRE_SHIFT)

+/* SPI Ping-Pong FIFO registers */ +#define SPI_PP_FIFO_SIZE 0x200 +#define SPI_PP_FIFO_BASE (0x200 + \

•                                    (SPI_PP_FIFO_SIZE * SPI_PP_SEL))
  

+/* SPI Ping-Pong FIFO OP register */ +#define SPI_PP_FIFO_OP_SIZE 0x2 +#define SPI_PP_FIFO_OP_REG (SPI_PP_FIFO_BASE + 0x00) +#define SPI_PP_FIFO_OP_BYTES_SHIFT 0 +#define SPI_PP_FIFO_OP_BYTES_MASK (0x3ff << SPI_PP_FIFO_OP_BYTES_SHIFT) +#define SPI_PP_FIFO_OP_MBIT_SHIFT 11 +#define SPI_PP_FIFO_OP_MBIT_MASK (1 << SPI_PP_FIFO_OP_MBIT_SHIFT) +#define SPI_PP_FIFO_OP_CODE_SHIFT 13 +#define SPI_PP_FIFO_OP_CODE_RW (1 << SPI_PP_FIFO_OP_CODE_SHIFT) +#define SPI_PP_FIFO_OP_CODE_W (2 << SPI_PP_FIFO_OP_CODE_SHIFT) +#define SPI_PP_FIFO_OP_CODE_R (3 << SPI_PP_FIFO_OP_CODE_SHIFT)

+struct bcm63xx_hsspi_priv {

•   void __iomem *regs;
  

•   ulong clk_rate;
  

•   uint8_t num_cs;
  

•   uint8_t cs_pols;
  

•   uint speed;
  

+};

+static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs,

•                      struct spi_cs_info *info)
  

+{

•   struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
  

•   if (cs >= priv->num_cs) {
  

•           error("no cs %u\n", cs);
  

•           return -ENODEV;
  

•   }
  

•   return 0;
  

+}

+static int bcm63xx_hsspi_set_mode(struct udevice *bus, uint mode) +{

•   struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
  

•   /* clock polarity */
  

•   if (mode & SPI_CPOL)
  

•           setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
  

•   else
  

•           clrbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
  

•   return 0;
  

+}

+static int bcm63xx_hsspi_set_speed(struct udevice *bus, uint speed) +{

•   struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
  

•   priv->speed = speed;
  

•   return 0;
  

+}

+static void bcm63xx_hsspi_claim_cs(struct bcm63xx_hsspi_priv *priv,

•                              struct dm_spi_slave_platdata *plat)
  

+{

•   uint32_t clr, set;
  

•   /* profile clock */
  

•   set = DIV_ROUND_UP(priv->clk_rate, priv->speed);
  

•   set = DIV_ROUND_UP(2048, set);
  

•   set &= SPI_PFL_CLK_FREQ_MASK;
  

•   set |= SPI_PFL_CLK_RSTLOOP_MASK;
  

•   writel_be(set, priv->regs + SPI_PFL_CLK_REG(plat->cs));
  

•   /* profile signal */
  

•   set = 0;
  

•   clr = SPI_PFL_SIG_LAUNCHRIS_MASK |
  

•         SPI_PFL_SIG_LATCHRIS_MASK |
  

•         SPI_PFL_SIG_ASYNCIN_MASK;
  

•   /* latch/launch config */
  

•   if (plat->mode & SPI_CPHA)
  

•           set |= SPI_PFL_SIG_LAUNCHRIS_MASK;
  

•   else
  

•           set |= SPI_PFL_SIG_LATCHRIS_MASK;
  

•   /* async clk */
  

•   if (priv->speed > SPI_MAX_SYNC_CLOCK)
  

•           set |= SPI_PFL_SIG_ASYNCIN_MASK;
  

•   clrsetbits_be32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set);
  

This code should be one-time processed gather them as mode and speed and move them into .set_mode and .set_speed. activate chipselect should have SPI_CTL_REG reg update.

I'm afraid I can't do that since both registers depend on the CS.

...

•   /* global control */
  

•   set = 0;
  

•   clr = 0;
  

•   /* invert cs polarity */
  

•   if (priv->cs_pols & BIT(plat->cs))
  

•           clr |= BIT(plat->cs);
  

•   else
  

•           set |= BIT(plat->cs);
  

•   /* invert dummy cs polarity */
  

•   if (priv->cs_pols & BIT(!plat->cs))
  

•           clr |= BIT(!plat->cs);
  

•   else
  

•           set |= BIT(!plat->cs);
  

•   clrsetbits_be32(priv->regs + SPI_CTL_REG, clr, set);
  

+}

+static void bcm63xx_hsspi_release_cs(struct bcm63xx_hsspi_priv *priv) +{

•   /* restore cs polarities */
  

•   clrsetbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK,
  

•                   priv->cs_pols);
  

+}

I think we can have single function for activate and deactivate cs like set_cs, try to group the same.

bcm63xx_hsspi_claim_cs needs to set more registers, so there's no point in grouping under a single set_cs function.

...

+/*

• • BCM63xx HSSPI driver doesn't allow keeping CS active between transfers
• • because they are controlled by HW.
• • However, it provides a mechanism to prepend write transfers prior to read
• • transfers (with a maximum prepend of 15 bytes), which is usually enough for
• • SPI-connected flashes since reading requires prepending a write transfer of
• • 5 bytes. On the other hand it also provides a way to invert each CS
• • polarity, not only between transfers like the older BCM63xx SPI driver, but
• • also the rest of the time.
• • Instead of using the prepend mechanism, this implementation inverts the
• • polarity of both the desired CS and another dummy CS when the bus is
• • claimed. This way, the dummy CS is restored to its inactive value when
• • transfers are issued and the desired CS is preserved in its active value
• • all the time. This hack is also used in the upstream linux driver and
• • allows keeping CS active between trasnfers even if the HW doesn't give
• • this possibility.
• */

+static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen,

•           const void *dout, void *din, unsigned long flags)
  

+{

•   struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
  

•   struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
  

•   size_t data_bytes = bitlen / 8;
  

•   size_t step_size = SPI_PP_FIFO_SIZE;
  

Rename this macro which should resembles local driver name.

OK.

...

•   uint16_t opcode = 0;
  

•   uint32_t val;
  

•   const uint8_t *tx = dout;
  

•   uint8_t *rx = din;
  

•   if (flags & SPI_XFER_BEGIN)
  

•           bcm63xx_hsspi_claim_cs(priv, plat);
  

_cs_activate better name than _claim_cs which usually preferred in other drivers too.

OK.

...

•   /* fifo operation */
  

•   if (tx && rx)
  

•           opcode = SPI_PP_FIFO_OP_CODE_RW;
  

these are not exactly SPI specific stuff, so drop SPI on macros something like HSSPI_OP_READ_WRITE and similar to below macros as well.

OK.

...

•   else if (rx)
  

•           opcode = SPI_PP_FIFO_OP_CODE_R;
  

•   else if (tx)
  

•           opcode = SPI_PP_FIFO_OP_CODE_W;
  

•   if (opcode != SPI_PP_FIFO_OP_CODE_R)
  

•           step_size -= SPI_PP_FIFO_OP_SIZE;
  

•   /* dual mode */
  

•   if ((opcode == SPI_PP_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) ||
  

•       (opcode == SPI_PP_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL))
  

•           opcode |= SPI_PP_FIFO_OP_MBIT_MASK;
  

•   /* profile mode */
  

•   val = SPI_PFL_MODE_FILL_MASK |
  

•         SPI_PFL_MODE_MDRDSZ_MASK |
  

•         SPI_PFL_MODE_MDWRSZ_MASK;
  

•   if (plat->mode & SPI_3WIRE)
  

•           val |= SPI_PFL_MODE_3WIRE_MASK;
  

•   writel_be(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
  

•   /* transfer loop */
  

•   while (data_bytes > 0) {
  

•           size_t curr_step = min(step_size, data_bytes);
  

•           /* copy tx data */
  

•           if (tx) {
  

•                   memcpy_toio(priv->regs + SPI_PP_FIFO_BASE +
  

•                               SPI_PP_FIFO_OP_SIZE, tx, curr_step);
  

•                   tx += curr_step;
  

•           }
  

•           /* set fifo operation */
  

•           writew_be(opcode | (curr_step & SPI_PP_FIFO_OP_BYTES_MASK),
  

•                     priv->regs + SPI_PP_FIFO_OP_REG);
  

•           /* issue the transfer */
  

•           val = SPI_PP_CMD_OP_START;
  

•           val |= (plat->cs << SPI_PP_CMD_PFL_SHIFT) &
  

•                  SPI_PP_CMD_PFL_MASK;
  

•           val |= (!plat->cs << SPI_PP_CMD_SLAVE_SHIFT) &
  

•                  SPI_PP_CMD_SLAVE_MASK;
  

•           writel_be(val, priv->regs + SPI_PP_CMD_REG);
  

•           /* wait for completion */
  

•           do {
  

•                   /* check ping-pong status */
  

•                   val = readl_be(priv->regs + SPI_PP_STAT_REG);
  

•                   /* transfer completed */
  

•                   if (!(val & SPI_PP_STAT_SRCBUSY_MASK))
  

•                           break;
  

•           } while (1);
  

try to use wait_for_bit

wait_for_bit_be? https://gist.github.com/Noltari/8ab369cae5f8577255c81e16402b358e

...

•           /* copy rx data */
  

•           if (rx) {
  

•                   memcpy_fromio(rx, priv->regs + SPI_PP_FIFO_BASE,
  

•                                 curr_step);
  

•                   rx += curr_step;
  

•           }
  

•           data_bytes -= curr_step;
  

•   }
  

•   if (flags & SPI_XFER_END)
  

•           bcm63xx_hsspi_release_cs(priv);
  

_deactivate_cs better name than _claim_cs which usually preferred in other drivers too.

OK.

...

•   return 0;
  

+}

+static const struct dm_spi_ops bcm63xx_hsspi_ops = {

•   .cs_info = bcm63xx_hsspi_cs_info,
  

•   .set_mode = bcm63xx_hsspi_set_mode,
  

•   .set_speed = bcm63xx_hsspi_set_speed,
  

•   .xfer = bcm63xx_hsspi_xfer,
  

+};

+static const struct udevice_id bcm63xx_hsspi_ids[] = {

•   { .compatible = "brcm,bcm6328-hsspi", },
  

•   { /* sentinel */ }
  

+};

+static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev) +{

•   struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
  

•   struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
  

•   /* check cs */
  

•   if (plat->cs >= priv->num_cs) {
  

•           error("no cs %u\n", plat->cs);
  

•           return -ENODEV;
  

•   }
  

•   /* cs polarity */
  

•   if (plat->mode & SPI_CS_HIGH)
  

•           priv->cs_pols |= BIT(plat->cs);
  

•   else
  

•           priv->cs_pols &= ~BIT(plat->cs);
  

•   return 0;
  

+}.cs

Why we need to child_probe here? becuase cs polarity mode check we can do it on .set_mode and check cs we can do it on .cs_info

Because we need to know in advance if any of the existing SPI slaves require changing CS polarity to high. This is due to the prepend workaround:

/* * BCM63xx HSSPI driver doesn't allow keeping CS active between transfers * because they are controlled by HW. * However, it provides a mechanism to prepend write transfers prior to read * transfers (with a maximum prepend of 15 bytes), which is usually enough for * SPI-connected flashes since reading requires prepending a write transfer of * 5 bytes. On the other hand it also provides a way to invert each CS * polarity, not only between transfers like the older BCM63xx SPI driver, but * also the rest of the time. * * Instead of using the prepend mechanism, this implementation inverts the * polarity of both the desired CS and another dummy CS when the bus is * claimed. This way, the dummy CS is restored to its inactive value when * transfers are issued and the desired CS is preserved in its active value * all the time. This hack is also used in the upstream linux driver and * allows keeping CS active between trasnfers even if the HW doesn't give * this possibility. */

...

+static int bcm63xx_hsspi_probe(struct udevice *dev) +{

•   struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev);
  

•   struct reset_ctl rst_ctl;
  

•   struct clk clk;
  

•   fdt_addr_t addr;
  

•   fdt_size_t size;
  

•   int ret;
  

•   addr = devfdt_get_addr_size_index(dev, 0, &size);
  

•   if (addr == FDT_ADDR_T_NONE)
  

•           return -EINVAL;
  

•   priv->regs = ioremap(addr, size);
  

•   priv->num_cs = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
  

•                                  "num-cs", 8);
  

•   /* enable clock */
  

•   ret = clk_get_by_name(dev, "hsspi", &clk);
  

•   if (ret < 0)
  

•           return ret;
  

•   ret = clk_enable(&clk);
  

•   if (ret < 0)
  

•           return ret;
  

•   ret = clk_free(&clk);
  

•   if (ret < 0)
  

•           return ret;
  

•   /* get clock rate */
  

•   ret = clk_get_by_name(dev, "pll", &clk);
  

•   if (ret < 0)
  

•           return ret;
  

•   priv->clk_rate = clk_get_rate(&clk);
  

•   ret = clk_free(&clk);
  

•   if (ret < 0)
  

•           return ret;
  

•   /* perform reset */
  

•   ret = reset_get_by_index(dev, 0, &rst_ctl);
  

•   if (ret < 0)
  

•           return ret;
  

•   ret = reset_deassert(&rst_ctl);
  

•   if (ret < 0)
  

•           return ret;
  

•   ret = reset_free(&rst_ctl);
  

•   if (ret < 0)
  

•           return ret;
  

•   /* initialize hardware */
  

•   writel_be(0, priv->regs + SPI_IR_MASK_REG);
  

•   /* clear pending interrupts */
  

•   writel_be(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG);
  

•   /* enable clk gate */
  

•   setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK);
  

•   /* read default cs polarities */
  

•   priv->cs_pols = readl_be(priv->regs + SPI_CTL_REG) &
  

•                   SPI_CTL_CS_POL_MASK;
  

•   return 0;
  

+}

+U_BOOT_DRIVER(bcm63xx_hsspi) = {

•   .name = "bcm63xx_hsspi",
  

•   .id = UCLASS_SPI,
  

•   .of_match = bcm63xx_hsspi_ids,
  

•   .ops = &bcm63xx_hsspi_ops,
  

•   .priv_auto_alloc_size = sizeof(struct bcm63xx_hsspi_priv),
  

•   .child_pre_probe = bcm63xx_hsspi_child_pre_probe,
  

•   .probe = bcm63xx_hsspi_probe,
  

+};

2.11.0

thanks!

This driver manages the high speed SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com --- v4: no changes v3: no changes v2: no changes

arch/mips/dts/brcm,bcm63268.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)

diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index 6e3d9c3820..4d4e36cccc 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -15,6 +15,7 @@

aliases { spi0 = &lsspi; + spi1 = &hsspi; };

cpus { @@ -44,6 +45,12 @@ #size-cells = <1>; u-boot,dm-pre-reloc;

+ hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + periph_osc: periph-osc { compatible = "fixed-clock"; #clock-cells = <0>; @@ -153,6 +160,20 @@ status = "disabled"; };

+ hsspi: spi@10001000 { + compatible = "brcm,bcm6328-hsspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10001000 0x600>; + clocks = <&periph_clk BCM63268_CLK_HSSPI>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + resets = <&periph_rst BCM63268_RST_SPI>; + spi-max-frequency = <50000000>; + num-cs = <8>; + + status = "disabled"; + }; + leds: led-controller@10001900 { compatible = "brcm,bcm6328-leds"; reg = <0x10001900 0x24>;

This driver manages the SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com --- v5: no changes v4: no changes v3: no changes v2: no changes

arch/mips/dts/brcm,bcm6328.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)

diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi index a996075743..67d9278be4 100644 --- a/arch/mips/dts/brcm,bcm6328.dtsi +++ b/arch/mips/dts/brcm,bcm6328.dtsi @@ -13,6 +13,10 @@ / { compatible = "brcm,bcm6328";

+ aliases { + spi0 = &spi; + }; + cpus { reg = <0x10000000 0x4>; #address-cells = <1>; @@ -40,6 +44,12 @@ #size-cells = <1>; u-boot,dm-pre-reloc;

+ hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133333333>; + }; + periph_osc: periph-osc { compatible = "fixed-clock"; #clock-cells = <0>; @@ -123,6 +133,20 @@ status = "disabled"; };

+ spi: spi@10001000 { + compatible = "brcm,bcm6328-hsspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10001000 0x600>; + clocks = <&periph_clk BCM6328_CLK_HSSPI>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + resets = <&periph_rst BCM6328_RST_SPI>; + spi-max-frequency = <33333334>; + num-cs = <3>; + + status = "disabled"; + }; + periph_pwr: power-controller@10001848 { compatible = "brcm,bcm6328-power-domain"; reg = <0x10001848 0x4>;

It's a Macronix (mx25l12805d) 16 MB SPI flash.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com --- v5: no changes v4: Sync with master. v3: switch to CONFIG_BCM63XX_HSSPI v2: no changes

arch/mips/dts/comtrend,ar-5387un.dts | 12 ++++++++++++ configs/comtrend_ar5387un_ram_defconfig | 8 ++++++++ 2 files changed, 20 insertions(+)

diff --git a/arch/mips/dts/comtrend,ar-5387un.dts b/arch/mips/dts/comtrend,ar-5387un.dts index 73f2b49b76..6067881a78 100644 --- a/arch/mips/dts/comtrend,ar-5387un.dts +++ b/arch/mips/dts/comtrend,ar-5387un.dts @@ -51,6 +51,18 @@ }; };

+&spi { + status = "okay"; + + spi-flash@0 { + compatible = "spi-flash"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <33333334>; + }; +}; + &uart0 { u-boot,dm-pre-reloc; status = "okay"; diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig index b64018ae71..59ec86b253 100644 --- a/configs/comtrend_ar5387un_ram_defconfig +++ b/configs/comtrend_ar5387un_ram_defconfig @@ -41,3 +41,11 @@ CONFIG_RESET_BCM6345=y # CONFIG_SPL_SERIAL_PRESENT is not set CONFIG_DM_SERIAL=y CONFIG_BCM6345_SERIAL=y +CONFIG_BCM63XX_HSSPI=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_SPI_FLASH_MACRONIX=y

This driver is a simplified version of linux/drivers/spi/spi-bcm63xx-hsspi.c

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com --- v6: no changes v5: Introduce changes suggested by Jagan Teki: - Rename SPI_PP_ macros. - cs_activate instead of claim_cs. - deactivate_cs instead of release_cs. - Use wait_for_bit_be32 instead of infinite loop. v4: no changes. v3: Switch to CONFIG_BCM63XX_HSSPI and rebase on top of SPI v4. v2: Introduce changes suggested by Simon Glass: - Split bcm63xx_hsspi_xfer() into smaller functions. - Check possible clock errors. - Check possible reset errors. - Switch to devfdt_get_addr_size_index(). - Use setbits32_be() for clock gate.

drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/bcm63xx_hsspi.c | 414 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 423 insertions(+) create mode 100644 drivers/spi/bcm63xx_hsspi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index ebc71c2e42..28ddcf85a3 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -40,6 +40,14 @@ config ATMEL_SPI many AT91 (ARM) chips. This driver can be used to access the SPI Flash, such as AT25DF321.

+config BCM63XX_HSSPI + bool "BCM63XX HSSPI driver" + depends on ARCH_BMIPS + help + Enable the BCM6328 HSSPI driver. This driver can be used to + access the SPI NOR flash on platforms embedding this Broadcom + SPI core. + config BCM63XX_SPI bool "BCM6348 SPI driver" depends on ARCH_BMIPS diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 5770b3f7cc..4b6000fd9a 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -18,6 +18,7 @@ endif obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o +obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o obj-$(CONFIG_CF_SPI) += cf_spi.o diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c new file mode 100644 index 0000000000..3393166a1e --- /dev/null +++ b/drivers/spi/bcm63xx_hsspi.c @@ -0,0 +1,414 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com + * + * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c: + * Copyright (C) 2000-2010 Broadcom Corporation + * Copyright (C) 2012-2013 Jonas Gorski jogo@openwrt.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <spi.h> +#include <reset.h> +#include <wait_bit.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define HSSPI_PP 0 + +#define SPI_MAX_SYNC_CLOCK 30000000 + +/* SPI Control register */ +#define SPI_CTL_REG 0x000 +#define SPI_CTL_CS_POL_SHIFT 0 +#define SPI_CTL_CS_POL_MASK (0xff << SPI_CTL_CS_POL_SHIFT) +#define SPI_CTL_CLK_GATE_SHIFT 16 +#define SPI_CTL_CLK_GATE_MASK (1 << SPI_CTL_CLK_GATE_SHIFT) +#define SPI_CTL_CLK_POL_SHIFT 17 +#define SPI_CTL_CLK_POL_MASK (1 << SPI_CTL_CLK_POL_SHIFT) + +/* SPI Interrupts registers */ +#define SPI_IR_STAT_REG 0x008 +#define SPI_IR_ST_MASK_REG 0x00c +#define SPI_IR_MASK_REG 0x010 + +#define SPI_IR_CLEAR_ALL 0xff001f1f + +/* SPI Ping-Pong Command registers */ +#define SPI_CMD_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x00) +#define SPI_CMD_OP_SHIFT 0 +#define SPI_CMD_OP_START (0x1 << SPI_CMD_OP_SHIFT) +#define SPI_CMD_PFL_SHIFT 8 +#define SPI_CMD_PFL_MASK (0x7 << SPI_CMD_PFL_SHIFT) +#define SPI_CMD_SLAVE_SHIFT 12 +#define SPI_CMD_SLAVE_MASK (0x7 << SPI_CMD_SLAVE_SHIFT) + +/* SPI Ping-Pong Status registers */ +#define SPI_STAT_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x04) +#define SPI_STAT_SRCBUSY_SHIFT 1 +#define SPI_STAT_SRCBUSY_MASK (1 << SPI_STAT_SRCBUSY_SHIFT) + +/* SPI Profile Clock registers */ +#define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00) +#define SPI_PFL_CLK_FREQ_SHIFT 0 +#define SPI_PFL_CLK_FREQ_MASK (0x3fff << SPI_PFL_CLK_FREQ_SHIFT) +#define SPI_PFL_CLK_RSTLOOP_SHIFT 15 +#define SPI_PFL_CLK_RSTLOOP_MASK (1 << SPI_PFL_CLK_RSTLOOP_SHIFT) + +/* SPI Profile Signal registers */ +#define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04) +#define SPI_PFL_SIG_LATCHRIS_SHIFT 12 +#define SPI_PFL_SIG_LATCHRIS_MASK (1 << SPI_PFL_SIG_LATCHRIS_SHIFT) +#define SPI_PFL_SIG_LAUNCHRIS_SHIFT 13 +#define SPI_PFL_SIG_LAUNCHRIS_MASK (1 << SPI_PFL_SIG_LAUNCHRIS_SHIFT) +#define SPI_PFL_SIG_ASYNCIN_SHIFT 16 +#define SPI_PFL_SIG_ASYNCIN_MASK (1 << SPI_PFL_SIG_ASYNCIN_SHIFT) + +/* SPI Profile Mode registers */ +#define SPI_PFL_MODE_REG(x) (0x100 + (0x20 * (x)) + 0x08) +#define SPI_PFL_MODE_FILL_SHIFT 0 +#define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT) +#define SPI_PFL_MODE_MDRDSZ_SHIFT 16 +#define SPI_PFL_MODE_MDRDSZ_MASK (1 << SPI_PFL_MODE_MDRDSZ_SHIFT) +#define SPI_PFL_MODE_MDWRSZ_SHIFT 18 +#define SPI_PFL_MODE_MDWRSZ_MASK (1 << SPI_PFL_MODE_MDWRSZ_SHIFT) +#define SPI_PFL_MODE_3WIRE_SHIFT 20 +#define SPI_PFL_MODE_3WIRE_MASK (1 << SPI_PFL_MODE_3WIRE_SHIFT) + +/* SPI Ping-Pong FIFO registers */ +#define HSSPI_FIFO_SIZE 0x200 +#define HSSPI_FIFO_BASE (0x200 + \ + (HSSPI_FIFO_SIZE * HSSPI_PP)) + +/* SPI Ping-Pong FIFO OP register */ +#define HSSPI_FIFO_OP_SIZE 0x2 +#define HSSPI_FIFO_OP_REG (HSSPI_FIFO_BASE + 0x00) +#define HSSPI_FIFO_OP_BYTES_SHIFT 0 +#define HSSPI_FIFO_OP_BYTES_MASK (0x3ff << HSSPI_FIFO_OP_BYTES_SHIFT) +#define HSSPI_FIFO_OP_MBIT_SHIFT 11 +#define HSSPI_FIFO_OP_MBIT_MASK (1 << HSSPI_FIFO_OP_MBIT_SHIFT) +#define HSSPI_FIFO_OP_CODE_SHIFT 13 +#define HSSPI_FIFO_OP_READ_WRITE (1 << HSSPI_FIFO_OP_CODE_SHIFT) +#define HSSPI_FIFO_OP_CODE_W (2 << HSSPI_FIFO_OP_CODE_SHIFT) +#define HSSPI_FIFO_OP_CODE_R (3 << HSSPI_FIFO_OP_CODE_SHIFT) + +struct bcm63xx_hsspi_priv { + void __iomem *regs; + ulong clk_rate; + uint8_t num_cs; + uint8_t cs_pols; + uint speed; +}; + +static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs, + struct spi_cs_info *info) +{ + struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus); + + if (cs >= priv->num_cs) { + printf("no cs %u\n", cs); + return -ENODEV; + } + + return 0; +} + +static int bcm63xx_hsspi_set_mode(struct udevice *bus, uint mode) +{ + struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus); + + /* clock polarity */ + if (mode & SPI_CPOL) + setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); + else + clrbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); + + return 0; +} + +static int bcm63xx_hsspi_set_speed(struct udevice *bus, uint speed) +{ + struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus); + + priv->speed = speed; + + return 0; +} + +static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv, + struct dm_spi_slave_platdata *plat) +{ + uint32_t clr, set; + + /* profile clock */ + set = DIV_ROUND_UP(priv->clk_rate, priv->speed); + set = DIV_ROUND_UP(2048, set); + set &= SPI_PFL_CLK_FREQ_MASK; + set |= SPI_PFL_CLK_RSTLOOP_MASK; + writel_be(set, priv->regs + SPI_PFL_CLK_REG(plat->cs)); + + /* profile signal */ + set = 0; + clr = SPI_PFL_SIG_LAUNCHRIS_MASK | + SPI_PFL_SIG_LATCHRIS_MASK | + SPI_PFL_SIG_ASYNCIN_MASK; + + /* latch/launch config */ + if (plat->mode & SPI_CPHA) + set |= SPI_PFL_SIG_LAUNCHRIS_MASK; + else + set |= SPI_PFL_SIG_LATCHRIS_MASK; + + /* async clk */ + if (priv->speed > SPI_MAX_SYNC_CLOCK) + set |= SPI_PFL_SIG_ASYNCIN_MASK; + + clrsetbits_be32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set); + + /* global control */ + set = 0; + clr = 0; + + /* invert cs polarity */ + if (priv->cs_pols & BIT(plat->cs)) + clr |= BIT(plat->cs); + else + set |= BIT(plat->cs); + + /* invert dummy cs polarity */ + if (priv->cs_pols & BIT(!plat->cs)) + clr |= BIT(!plat->cs); + else + set |= BIT(!plat->cs); + + clrsetbits_be32(priv->regs + SPI_CTL_REG, clr, set); +} + +static void bcm63xx_hsspi_deactivate_cs(struct bcm63xx_hsspi_priv *priv) +{ + /* restore cs polarities */ + clrsetbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK, + priv->cs_pols); +} + +/* + * BCM63xx HSSPI driver doesn't allow keeping CS active between transfers + * because they are controlled by HW. + * However, it provides a mechanism to prepend write transfers prior to read + * transfers (with a maximum prepend of 15 bytes), which is usually enough for + * SPI-connected flashes since reading requires prepending a write transfer of + * 5 bytes. On the other hand it also provides a way to invert each CS + * polarity, not only between transfers like the older BCM63xx SPI driver, but + * also the rest of the time. + * + * Instead of using the prepend mechanism, this implementation inverts the + * polarity of both the desired CS and another dummy CS when the bus is + * claimed. This way, the dummy CS is restored to its inactive value when + * transfers are issued and the desired CS is preserved in its active value + * all the time. This hack is also used in the upstream linux driver and + * allows keeping CS active between trasnfers even if the HW doesn't give + * this possibility. + */ +static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent); + struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev); + size_t data_bytes = bitlen / 8; + size_t step_size = HSSPI_FIFO_SIZE; + uint16_t opcode = 0; + uint32_t val; + const uint8_t *tx = dout; + uint8_t *rx = din; + + if (flags & SPI_XFER_BEGIN) + bcm63xx_hsspi_activate_cs(priv, plat); + + /* fifo operation */ + if (tx && rx) + opcode = HSSPI_FIFO_OP_READ_WRITE; + else if (rx) + opcode = HSSPI_FIFO_OP_CODE_R; + else if (tx) + opcode = HSSPI_FIFO_OP_CODE_W; + + if (opcode != HSSPI_FIFO_OP_CODE_R) + step_size -= HSSPI_FIFO_OP_SIZE; + + /* dual mode */ + if ((opcode == HSSPI_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) || + (opcode == HSSPI_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL)) + opcode |= HSSPI_FIFO_OP_MBIT_MASK; + + /* profile mode */ + val = SPI_PFL_MODE_FILL_MASK | + SPI_PFL_MODE_MDRDSZ_MASK | + SPI_PFL_MODE_MDWRSZ_MASK; + if (plat->mode & SPI_3WIRE) + val |= SPI_PFL_MODE_3WIRE_MASK; + writel_be(val, priv->regs + SPI_PFL_MODE_REG(plat->cs)); + + /* transfer loop */ + while (data_bytes > 0) { + size_t curr_step = min(step_size, data_bytes); + int ret; + + /* copy tx data */ + if (tx) { + memcpy_toio(priv->regs + HSSPI_FIFO_BASE + + HSSPI_FIFO_OP_SIZE, tx, curr_step); + tx += curr_step; + } + + /* set fifo operation */ + writew_be(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK), + priv->regs + HSSPI_FIFO_OP_REG); + + /* issue the transfer */ + val = SPI_CMD_OP_START; + val |= (plat->cs << SPI_CMD_PFL_SHIFT) & + SPI_CMD_PFL_MASK; + val |= (!plat->cs << SPI_CMD_SLAVE_SHIFT) & + SPI_CMD_SLAVE_MASK; + writel_be(val, priv->regs + SPI_CMD_REG); + + /* wait for completion */ + ret = wait_for_bit_be32(priv->regs + SPI_STAT_REG, + SPI_STAT_SRCBUSY_MASK, false, + 1000, false); + if (ret) { + printf("interrupt timeout\n"); + return ret; + } + + /* copy rx data */ + if (rx) { + memcpy_fromio(rx, priv->regs + HSSPI_FIFO_BASE, + curr_step); + rx += curr_step; + } + + data_bytes -= curr_step; + } + + if (flags & SPI_XFER_END) + bcm63xx_hsspi_deactivate_cs(priv); + + return 0; +} + +static const struct dm_spi_ops bcm63xx_hsspi_ops = { + .cs_info = bcm63xx_hsspi_cs_info, + .set_mode = bcm63xx_hsspi_set_mode, + .set_speed = bcm63xx_hsspi_set_speed, + .xfer = bcm63xx_hsspi_xfer, +}; + +static const struct udevice_id bcm63xx_hsspi_ids[] = { + { .compatible = "brcm,bcm6328-hsspi", }, + { /* sentinel */ } +}; + +static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev) +{ + struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent); + struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev); + + /* check cs */ + if (plat->cs >= priv->num_cs) { + printf("no cs %u\n", plat->cs); + return -ENODEV; + } + + /* cs polarity */ + if (plat->mode & SPI_CS_HIGH) + priv->cs_pols |= BIT(plat->cs); + else + priv->cs_pols &= ~BIT(plat->cs); + + return 0; +} + +static int bcm63xx_hsspi_probe(struct udevice *dev) +{ + struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev); + struct reset_ctl rst_ctl; + struct clk clk; + fdt_addr_t addr; + fdt_size_t size; + int ret; + + addr = devfdt_get_addr_size_index(dev, 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = ioremap(addr, size); + priv->num_cs = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), + "num-cs", 8); + + /* enable clock */ + ret = clk_get_by_name(dev, "hsspi", &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + if (ret < 0) + return ret; + + ret = clk_free(&clk); + if (ret < 0) + return ret; + + /* get clock rate */ + ret = clk_get_by_name(dev, "pll", &clk); + if (ret < 0) + return ret; + + priv->clk_rate = clk_get_rate(&clk); + + ret = clk_free(&clk); + if (ret < 0) + return ret; + + /* perform reset */ + ret = reset_get_by_index(dev, 0, &rst_ctl); + if (ret < 0) + return ret; + + ret = reset_deassert(&rst_ctl); + if (ret < 0) + return ret; + + ret = reset_free(&rst_ctl); + if (ret < 0) + return ret; + + /* initialize hardware */ + writel_be(0, priv->regs + SPI_IR_MASK_REG); + + /* clear pending interrupts */ + writel_be(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG); + + /* enable clk gate */ + setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK); + + /* read default cs polarities */ + priv->cs_pols = readl_be(priv->regs + SPI_CTL_REG) & + SPI_CTL_CS_POL_MASK; + + return 0; +} + +U_BOOT_DRIVER(bcm63xx_hsspi) = { + .name = "bcm63xx_hsspi", + .id = UCLASS_SPI, + .of_match = bcm63xx_hsspi_ids, + .ops = &bcm63xx_hsspi_ops, + .priv_auto_alloc_size = sizeof(struct bcm63xx_hsspi_priv), + .child_pre_probe = bcm63xx_hsspi_child_pre_probe, + .probe = bcm63xx_hsspi_probe, +};

This driver manages the high speed SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com --- v6: no changes v5: no changes v4: no changes v3: no changes v2: no changes

arch/mips/dts/brcm,bcm63268.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)

diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index 6e3d9c3820..4d4e36cccc 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -15,6 +15,7 @@

aliases { spi0 = &lsspi; + spi1 = &hsspi; };

cpus { @@ -44,6 +45,12 @@ #size-cells = <1>; u-boot,dm-pre-reloc;

+ hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + periph_osc: periph-osc { compatible = "fixed-clock"; #clock-cells = <0>; @@ -153,6 +160,20 @@ status = "disabled"; };

+ hsspi: spi@10001000 { + compatible = "brcm,bcm6328-hsspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10001000 0x600>; + clocks = <&periph_clk BCM63268_CLK_HSSPI>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + resets = <&periph_rst BCM63268_RST_SPI>; + spi-max-frequency = <50000000>; + num-cs = <8>; + + status = "disabled"; + }; + leds: led-controller@10001900 { compatible = "brcm,bcm6328-leds"; reg = <0x10001900 0x24>;