Start documentation section for Enclustra. Cover Enclustra Intel SoMs and related carrier board setups.

- Mercury AA1 (Arria10)

Signed-off-by: Lothar Rubusch l.rubusch@gmail.com --- doc/board/enclustra/index.rst | 9 ++ doc/board/enclustra/mercury-aa1.rst | 209 ++++++++++++++++++++++++++++ doc/board/index.rst | 1 + 3 files changed, 219 insertions(+) create mode 100644 doc/board/enclustra/index.rst create mode 100644 doc/board/enclustra/mercury-aa1.rst

diff --git a/doc/board/enclustra/index.rst b/doc/board/enclustra/index.rst new file mode 100644 index 0000000000..00727d0861 --- /dev/null +++ b/doc/board/enclustra/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Enclustra +========= + +.. toctree:: + :maxdepth: 2 + + mercury-aa1 diff --git a/doc/board/enclustra/mercury-aa1.rst b/doc/board/enclustra/mercury-aa1.rst new file mode 100644 index 0000000000..0331756045 --- /dev/null +++ b/doc/board/enclustra/mercury-aa1.rst @@ -0,0 +1,209 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later +.. sectionauthor:: Lothar Rubusch l.rubusch@gmail.com + +Mercury AA1 Module (Arria1 10) +============================== + +- SoM: https://www.enclustra.com/en/products/system-on-chip-modules/mercury-aa1/ +- Carrier board Mercury+ ST1: https://www.enclustra.com/en/products/base-boards/mercury-st1/ +- Carrier board Mercury+ PE1: https://www.enclustra.com/en/products/base-boards/mercury-pe1-200-300-400/ +- Carrier board Mercury+ PE3: https://www.enclustra.com/en/products/base-boards/mercury-pe3/ + +There are slightly different variants of the AA1 SoM, going by the identifier. + +- Me-aa1-270-2i2-d11e-nfx3 +- Me-aa1-270-3e4-d11e-nfx3 +- Me-aa1-480-2i3-d12e-nfx3 + +The u-boot setup is specific to a quartus design. Generate handoff files from +the design. Pass them to a python script to produce a handoff.h file. This is +needed as input for building the device-tree for u-boot. Eventually, building +the final u-boot depends on the particular Quartus design, the particular +carrier board, the selected boot media and boot mode. + +Enclustra provides reference design examples which can be built with yocto +using their meta-layer. + +- Reference Design AA1 on ST1: https://github.com/enclustra/Mercury_AA1_ST1_Reference_Design +- Reference Design AA1 on PE1: https://github.com/enclustra/Mercury_AA1_PE1_Reference_Design +- Reference Design AA1 on PE3: https://github.com/enclustra/Mercury_AA1_PE3_Reference_Design +- Yocto meta-layer: https://github.com/enclustra/meta-enclustra-socfpga + +Quick Start +----------- + +- Setup and build a Quartus design project +- Obtain the hps.xml file from the Quartus design project +- Generate the handoff.h file for u-boot +- Adjust the device-tree file according to your setup +- Build u-boot +- Flash u-boot + +Build U-Boot +------------ + +The Quartus design produces a design specific ``hps.xml``, an ``emif.xml`` and +a corresponding ``id`` file contained in a folder ``handoff``. + +Generate the handoff.h file for u-boot, from a provided ``hps.xml`` using the +script provided in u-boot. + +.. code-block:: bash + + $ arch/arm/mach-socfpga/qts-filter-a10.sh <where you saved it>/hps.xml arch/arm/dts/socfpga_arria10_mercury_aa1_handoff.h + +Adjust the device-tree file according to your setup. Follow the comments in the +file. + +.. code-block:: bash + + $ vi ./arch/arm/dts/enclustra-aa1.dts + +Build u-boot. Source your favorite toolchain for ARM first. + +.. code-block:: bash + + $ make socfpga_enclustra_mercury_aa1_defconfig + $ make -j8 + +Setup and compile a boot script as needed. Depending on the boot-mode select +``sd-aa1.cmd`` for SD/eMMC, or ``qspi-aa1.cmd`` for QSPI flash. Also, +optionally prepare an environment file. Examples of boot command files and +environment files are provided. + +.. code-block:: bash + + $ ./tools/mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "Uboot mmc startscript" -d board/enclustra/bootscripts/sd-aa1.cmd boot.scr + $ ./tools/mkenvimage -s 0x80000 -o uboot.env board/enclustra/mercury_aa1/mercury_aa1.env + +Device-Tree setup +----------------- + +The basic u-boot device-tree fragments are provided here. The handoff tools +will generate further u-boot device-tree fragments. The various .dtsi files +then need to be included in a top-level .dts file. + +Flash the U-Boot Binary to a Micro SD Card +------------------------------------------ + +The following example describes the full approach. Prepare a micro SD card with +three partitions as follows: + +* ``type=c, start=2048, size=409600`` +* ``type=a2, start=411648, size=14336`` +* ``type=83, start=425984, size=1619968`` + +.. code-block:: bash + + $ sudo fdisk /dev/sda + n,p,1,2048,+20M + t,1,c + n,p,2,409600,+1M + t,2,a2 + n,p,3,425984,<REST> + t,3,83 + w + +Note: The ``bitstream.itb`` is needed to start the bootloader. A kernel +``devicetree.dtb`` is needed to boot into the system. Both are not part of +u-boot, but are be provided through yocto using Enclustra's meta-layer. + +Generally the bitstream files depend on the logic design, but the meta-layer +provides a demo design. Copy the ``bitstream.periph.rbf`` and +``bitstream.core.rbf`` from your design or yocto's deploy folder. The +``bitstream.its`` in board/enclustra then is used to bundle them. + + .. code-block:: bash + + $ cp bitstream.periph.rbf ./board/enclustra/mercury_aa1/ + $ cp bitstream.core.rbf ./board/enclustra/mercury_aa1/ + $ ./tools/mkimage -E -f ./board/enclustra/mercury_aa1/bitstream.its bitstream.itb + +Format the SD card, and copy the following artifacts to the mounted boot +partition, e.g. on /dev/sda (check before). + + .. code-block:: bash + + $ mkfs.vfat -n boot /dev/sda1 + $ mount /dev/sda1 /media/boot + $ cp ./{boot.scr,u-boot.img,uboot.env,bitstream.itb,Image,devicetree.dtb} /media/boot/ + $ umount /dev/sda1 + +Flash the SPL directly. + + .. code-block:: bash + + $ dd if=./spl/u-boot-splx4.sfp of=/dev/sda2 conv=fdatasync bs=4k status=progress + +Format and flash a rootfs from image or files to the third partition. + + .. code-block:: bash + + $ mkfs.ext4 -L rootfs /dev/sda3 + $ mount /dev/sda3 /media/rootfs + $ tar xf ./rootfs.tar -C /media/rootfs + $ umount /dev/sda3 + +Boot Media +---------- + +Alternative boot media are possible as officially documented by Enclustra. + +* Micro-SD card +* eMMC +* QSPI + +NB: eMMC and QSPI can be flashed from off the u-boot shell. Usually after +flashing, the coorect boot mode needs to be set by a BSEL switch. Approaches +are described consistently in the offical Enclustra documentation according to +their releases mentioned as links. + +Before turning on the setup, make sure to have the correct voltage configured +at the carrier board, using the jumpers on the voltage pin header. Also make +sure to have switched to the correct boot media using typically some dip +switches to be found on the carrier board. + +Boot Log +-------- + +The demo shows booting a AA1 + ST1 setup and stopping at the u-boot shell. + +Here is the console output:: + + U-Boot SPL 2024.10-rc4-00416-gf0b9c383e6c3 (Sep 08 2024 - 14:03:59 +0000) + FPGA: Checking FPGA configuration setting ... + FPGA: Start to program peripheral/full bitstream ... + FPGA: Early Release Succeeded. + FPGA: Checking FPGA configuration setting ... + FPGA: Start to program peripheral/full bitstream ... + FPGA: Early Release Succeeded. + + U-Boot SPL 2024.10-rc4-00416-gf0b9c383e6c3 (Sep 08 2024 - 14:03:59 +0000) + DDRCAL: Success + DDRCAL: Scrubbing ECC RAM (2048 MiB). + DDRCAL: Scrubbing ECC RAM done. + FPGA: Checking FPGA configuration setting ... + FPGA: Start to program core bitstream ... + Full Configuration Succeeded. + FPGA: Enter user mode. + Trying to boot from MMC1 + + + U-Boot 2024.10-rc4-00416-gf0b9c383e6c3 (Sep 08 2024 - 14:03:59 +0000)socfpga_arria10 + + CPU: Altera SoCFPGA Arria 10 + BOOT: SD/MMC External Transceiver (1.8V) + Model: Enclustra Mercury+ AA1 + DRAM: 2 GiB + Core: 80 devices, 20 uclasses, devicetree: separate + MMC: dwmmc0@ff808000: 0 + Loading Environment from FAT... OK + In: serial + Out: serial + Err: serial + Model: Enclustra Mercury+ AA1 + ethaddr set to 20:B0:F7:06:0D:BE + eth1addr set to 20:B0:F7:06:0D:BF + Net: eth0: ethernet@ff800000 + => + diff --git a/doc/board/index.rst b/doc/board/index.rst index 417c128c7a..42244a689b 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -24,6 +24,7 @@ Board-specific doc congatec/index coreboot/index emulation/index + enclustra/index gateworks/index google/index highbank/index

Introduce initial support for the Enclustra SoMs:

- Mercury AA1

Cover general board files for SD/MMC and QSPI boot modes. Integrate the boards to kconfig. All build variants will depend on Quartus handoff files, thus they depend on the particular Quartus design. The approach is covered in the according documentation part.

Additionally add configuration for SD/MMC boot and QSPI bootmodes. Register additional targets in kconfig.

Signed-off-by: Andreas Buerkler andreas.buerkler@enclustra.com Signed-off-by: Lothar Rubusch l.rubusch@gmail.com --- arch/arm/mach-socfpga/Kconfig | 9 + board/enclustra/common/Kconfig | 1 + board/enclustra/common/Makefile | 4 + board/enclustra/mercury_aa1/Kconfig | 15 ++ board/enclustra/mercury_aa1/MAINTAINERS | 10 + board/enclustra/mercury_aa1/Makefile | 4 + board/enclustra/mercury_aa1/bitstream.its | 32 +++ board/enclustra/mercury_aa1/mercury_aa1.c | 185 ++++++++++++++++++ .../socfpga_enclustra_mercury_aa1_defconfig | 78 ++++++++ include/configs/socfpga_mercury_aa1.h | 33 ++++ 10 files changed, 371 insertions(+) create mode 100644 board/enclustra/common/Kconfig create mode 100644 board/enclustra/common/Makefile create mode 100644 board/enclustra/mercury_aa1/Kconfig create mode 100644 board/enclustra/mercury_aa1/MAINTAINERS create mode 100644 board/enclustra/mercury_aa1/Makefile create mode 100644 board/enclustra/mercury_aa1/bitstream.its create mode 100644 board/enclustra/mercury_aa1/mercury_aa1.c create mode 100644 configs/socfpga_enclustra_mercury_aa1_defconfig create mode 100644 include/configs/socfpga_mercury_aa1.h

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 6b6a162f56..d42e7817be 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -221,6 +221,10 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT bool "Terasic SoCkit (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5

+config TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1 + bool "Enclustra Mercury+ AA1" + select TARGET_SOCFPGA_ARRIA10 + endchoice

config SYS_BOARD @@ -244,6 +248,7 @@ config SYS_BOARD default "sr1500" if TARGET_SOCFPGA_SR1500 default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA + default "mercury_aa1" if TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1

config SYS_VENDOR default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK @@ -264,6 +269,7 @@ config SYS_VENDOR default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT + default "enclustra" if TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1

config SYS_SOC default "socfpga" @@ -289,5 +295,8 @@ config SYS_CONFIG_NAME default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA + default "socfpga_mercury_aa1" if TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1 + +source "board/enclustra/common/Kconfig"

endif diff --git a/board/enclustra/common/Kconfig b/board/enclustra/common/Kconfig new file mode 100644 index 0000000000..51169bada3 --- /dev/null +++ b/board/enclustra/common/Kconfig @@ -0,0 +1 @@ +source "board/enclustra/mercury_aa1/Kconfig" diff --git a/board/enclustra/common/Makefile b/board/enclustra/common/Makefile new file mode 100644 index 0000000000..16c8531d74 --- /dev/null +++ b/board/enclustra/common/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (c) 2024 Enclustra GmbH + +# Common for several Enclustra modules diff --git a/board/enclustra/mercury_aa1/Kconfig b/board/enclustra/mercury_aa1/Kconfig new file mode 100644 index 0000000000..40c7cb2687 --- /dev/null +++ b/board/enclustra/mercury_aa1/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1 + +config SYS_CPU + default "armv7" + +config SYS_BOARD + default "mercury_aa1" + +config SYS_VENDOR + default "enclustra" + +config SYS_CONFIG_NAME + default "socfpga_mercury_aa1" + +endif diff --git a/board/enclustra/mercury_aa1/MAINTAINERS b/board/enclustra/mercury_aa1/MAINTAINERS new file mode 100644 index 0000000000..11b7058d61 --- /dev/null +++ b/board/enclustra/mercury_aa1/MAINTAINERS @@ -0,0 +1,10 @@ +Enclustra Mercury+ AA1 +M: Lothar Rubusch l.rubusch@gmail.com +S: Maintained +F: board/enclustra/mercury_aa1/ +F: board/enclustra/common/ +F: include/configs/socfpga_mercury_aa1.h +F: configs/socfpga_enclustra_mercury_aa1_defconfig +F: arch/arm/dts/socfpga_enclustra_mercury_aa1.dtsi +F: arch/arm/dts/socfpga_enclustra_mercury_aa1_emmc_boot.dtsi +F: arch/arm/dts/socfpga_enclustra_mercury_aa1_qspi_boot.dtsi diff --git a/board/enclustra/mercury_aa1/Makefile b/board/enclustra/mercury_aa1/Makefile new file mode 100644 index 0000000000..d830170dea --- /dev/null +++ b/board/enclustra/mercury_aa1/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (c) 2024 Enclustra GmbH + +obj-y += mercury_aa1.o diff --git a/board/enclustra/mercury_aa1/bitstream.its b/board/enclustra/mercury_aa1/bitstream.its new file mode 100644 index 0000000000..d16e4598de --- /dev/null +++ b/board/enclustra/mercury_aa1/bitstream.its @@ -0,0 +1,32 @@ +/dts-v1/; + +/ { + description = "FIT image with FPGA bistream"; + #address-cells = <1>; + + images { + fpga-periph-1 { + description = "FPGA peripheral bitstream"; + data = /incbin/("bitstream.periph.rbf"); + type = "fpga"; + arch = "arm"; + compression = "none"; + }; + + fpga-core-1 { + description = "FPGA core bitstream"; + data = /incbin/("bitstream.core.rbf"); + type = "fpga"; + arch = "arm"; + compression = "none"; + }; + }; + + configurations { + default = "config-1"; + config-1 { + description = "Boot with FPGA early IO release config"; + fpga = "fpga-periph-1", "fpga-core-1"; + }; + }; +}; diff --git a/board/enclustra/mercury_aa1/mercury_aa1.c b/board/enclustra/mercury_aa1/mercury_aa1.c new file mode 100644 index 0000000000..7de9b287d9 --- /dev/null +++ b/board/enclustra/mercury_aa1/mercury_aa1.c @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Enclustra GmbH + * info@enclustra.com + */ + +#include <command.h> +#include <env.h> +#include <init.h> +#include <dm/uclass.h> +#include <asm-generic/gpio.h> +#include <asm/io.h> + +/* Pin muxing */ +#if !defined(CONFIG_SPL_BUILD) + +#define ALTERA_NONE 0 +#define ALTERA_MMC 1 +#define ALTERA_QSPI 2 +#define ALTERA_EMMC 3 +#define MMC_CLK_DIV 0x9 +#define QSPI_CLK_DIV 0x384 +#define ALTERA_PINMUX_OFFS 0xffd07200 +#define ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE 0xFFD04078 + +static int altera_current_storage = ALTERA_NONE; + +#endif + +#if !defined(CONFIG_SPL_BUILD) + +static void set_mux_mmc(void) +{ + u32 pinmux_arr[] = {0x0c, 0x8, // IO4 connected to SDMMC + 0x10, 0x8, // IO5 + 0x14, 0x8, // IO6 + 0x18, 0x8, // IO7 + 0x1c, 0x8, // IO8 + 0x20, 0x8, // IO9 + 0x24, 0xf, // IO10 connected to GPIO + 0x28, 0xf, // IO11 + 0x2c, 0xf, // IO12 + 0x30, 0xf, // IO13 + 0x34, 0xf, // IO14 + 0x38, 0xf}; // IO15 + u32 len, i, offset, value; + + len = sizeof(pinmux_arr) / sizeof(u32); + for (i = 0; i < len; i += 2) { + offset = pinmux_arr[i]; + value = pinmux_arr[i + 1]; + writel(value, ALTERA_PINMUX_OFFS + offset); + } +} + +static void set_mux_emmc(void) +{ + u32 pinmux_arr[] = {0x0c, 0x8, // IO4 + 0x10, 0x8, // IO5 + 0x14, 0x8, // IO6 + 0x18, 0x8, // IO7 + 0x1c, 0x8, // IO8 + 0x20, 0x8, // IO9 + 0x24, 0xf, // IO10 + 0x28, 0xf, // IO11 + 0x2c, 0x8, // IO12 + 0x30, 0x8, // IO13 + 0x34, 0x8, // IO14 + 0x38, 0x8}; // IO15 + u32 len, i, offset, value; + + len = sizeof(pinmux_arr) / sizeof(u32); + for (i = 0; i < len; i += 2) { + offset = pinmux_arr[i]; + value = pinmux_arr[i + 1]; + writel(value, ALTERA_PINMUX_OFFS + offset); + } +} + +static void set_mux_qspi(void) +{ + u32 pinmux_arr[] = {0x0c, 0x4, // IO4 connected to QSPI + 0x10, 0x4, // IO5 + 0x14, 0x4, // IO6 + 0x18, 0x4, // IO7 + 0x1c, 0x4, // IO8 + 0x20, 0x4, // IO9 + 0x24, 0xf, // IO10 + 0x28, 0xf, // IO11 + 0x2c, 0xf, // IO12 + 0x30, 0xf, // IO13 + 0x34, 0xf, // IO14 + 0x38, 0xf}; // IO15 + u32 len, i, offset, value; + + len = sizeof(pinmux_arr) / sizeof(u32); + for (i = 0; i < len; i += 2) { + offset = pinmux_arr[i]; + value = pinmux_arr[i + 1]; + writel(value, ALTERA_PINMUX_OFFS + offset); + } +} + +void altera_set_storage(int store) +{ + unsigned int gpio_flash_sel; + unsigned int gpio_flash_oe; + + if (store == altera_current_storage) + return; + + if (gpio_lookup_name("portb5", NULL, NULL, &gpio_flash_oe)) { + printf("ERROR: GPIO not found\n"); + return; + } + + if (gpio_request(gpio_flash_oe, "flash_oe")) { + printf("ERROR: GPIO request failed\n"); + return; + } + + if (gpio_lookup_name("portc6", NULL, NULL, &gpio_flash_sel)) { + printf("ERROR: GPIO not found\n"); + return; + } + + if (gpio_request(gpio_flash_sel, "flash_sel")) { + printf("ERROR: GPIO request failed\n"); + return; + } + + switch (store) { + case ALTERA_MMC: + set_mux_mmc(); + gpio_direction_output(gpio_flash_sel, 0); + gpio_direction_output(gpio_flash_oe, 0); + altera_current_storage = ALTERA_MMC; + writel(MMC_CLK_DIV, ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE); + break; + case ALTERA_EMMC: + set_mux_emmc(); + gpio_direction_output(gpio_flash_sel, 1); + gpio_direction_output(gpio_flash_oe, 1); + altera_current_storage = ALTERA_EMMC; + writel(MMC_CLK_DIV, ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE); + break; + case ALTERA_QSPI: + set_mux_qspi(); + gpio_direction_output(gpio_flash_sel, 1); + gpio_direction_output(gpio_flash_oe, 0); + altera_current_storage = ALTERA_QSPI; + writel(QSPI_CLK_DIV, ALTERA_CLKMGR_MAINPLL_CNTR6CLK_BASE); + break; + default: + altera_current_storage = ALTERA_NONE; + break; + } + + gpio_free(gpio_flash_sel); + gpio_free(gpio_flash_oe); +} + +int altera_set_storage_cmd(struct cmd_tbl *cmdtp, int flag, + int argc, char * const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + + if (!strcmp(argv[1], "MMC")) + altera_set_storage(ALTERA_MMC); + else if (!strcmp(argv[1], "QSPI")) + altera_set_storage(ALTERA_QSPI); + else if (!strcmp(argv[1], "EMMC")) + altera_set_storage(ALTERA_EMMC); + else + return CMD_RET_USAGE; + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD(altera_set_storage, 2, 0, altera_set_storage_cmd, + "Set non volatile memory access", + "<MMC|QSPI|EMMC> - Set access for the selected memory device"); + +#endif diff --git a/configs/socfpga_enclustra_mercury_aa1_defconfig b/configs/socfpga_enclustra_mercury_aa1_defconfig new file mode 100644 index 0000000000..b475bd916d --- /dev/null +++ b/configs/socfpga_enclustra_mercury_aa1_defconfig @@ -0,0 +1,78 @@ +CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_MALLOC_LEN=0x4000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffe2b000 +CONFIG_SF_DEFAULT_SPEED=10000000 +CONFIG_ENV_SIZE=0x80000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="enclustra-aa1" +CONFIG_SPL_TEXT_BASE=0xFFE00000 +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0xffe2b000 +CONFIG_TARGET_SOCFPGA_ENCLUSTRA_MERCURY_AA1=y +CONFIG_IDENT_STRING="socfpga_arria10" +CONFIG_SPL_FS_FAT=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200" +CONFIG_DEFAULT_FDT_FILE="system.dtb" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CLOCKS=y +CONFIG_SPL_PAD_TO=0x40000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xffe2b000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x15000 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" +CONFIG_SPL_FPGA=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_VERSION_VARIABLE=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DWAPB_GPIO=y +CONFIG_SYS_I2C_DW=y +CONFIG_MISC=y +CONFIG_FS_LOADER=y +CONFIG_SPL_FS_LOADER=y +CONFIG_MMC_DW=y +CONFIG_SPI_FLASH_SPANSION=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_DESIGNWARE_APB_TIMER=y +CONFIG_USB=y +CONFIG_USB_DWC2=y diff --git a/include/configs/socfpga_mercury_aa1.h b/include/configs/socfpga_mercury_aa1.h new file mode 100644 index 0000000000..a5b63336e8 --- /dev/null +++ b/include/configs/socfpga_mercury_aa1.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2024 Enclustra GmbH + * info@enclustra.com + */ + +#ifndef __CONFIG_SOCFGPA_MERCURY_AA1_H__ +#define __CONFIG_SOCFGPA_MERCURY_AA1_H__ + +#include <asm/arch/base_addr_a10.h> + +/* + * U-Boot general configurations + */ + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x80000000 + +/* + * Serial / UART configurations + */ +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} + +/* + * L4 OSC1 Timer 0 + */ +/* reload value when timer count to zero */ +#define TIMER_LOAD_VAL 0xFFFFFFFF + +/* The rest of the configuration is shared */ +#include <configs/socfpga_common.h> + +#endif /* __CONFIG_SOCFGPA_MERCURY_AA1_H__ */

Add command files for boot scripts and initial boot environment.

Signed-off-by: Andreas Buerkler andreas.buerkler@enclustra.com Signed-off-by: Lothar Rubusch l.rubusch@gmail.com --- include/configs/socfpga_mercury_aa1.h | 35 +++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)

diff --git a/include/configs/socfpga_mercury_aa1.h b/include/configs/socfpga_mercury_aa1.h index a5b63336e8..4b047e11a7 100644 --- a/include/configs/socfpga_mercury_aa1.h +++ b/include/configs/socfpga_mercury_aa1.h @@ -21,6 +21,41 @@ */ #define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}

+/* U-Boot environment */ +#define CFG_EXTRA_ENV_SETTINGS \ + "bitstream_size=0xD00000\0" \ + "bootargs=earlycon console=ttyS0,115200 rw rootwait root=/dev/mmcblk0p3\0" \ + "bootargs_qspi=earlycon console=ttyS0,115200 rw root=/dev/ram0\0" \ + "bootm_size=0x0a000000\0" \ + "env_size=0x80000\0" \ + "fdt_addr_r=0x10000000\0" \ + "fdtfile=system.dtb\0" \ + "fdtload=load ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} ${bootdir}/${fdtfile}; load ${devtype} ${devnum}:${distro_bootpart} ${fdto_addr_r} ${bootdir}/${fdtofile}; fdt addr $fdt_addr_r; fdt resize 8192; fdt apply $fdto_addr_r\0" \ + "fdtload_qspi=sf probe; sf read ${fdt_addr_r} ${qspi_offset_addr_devicetree} ${fdt_size}; sf read ${fdto_addr_r} ${qspi_offset_addr_dtoverlay} ${fdto_size}; fdt addr ${fdt_addr_r}; fdt resize 8192; fdt apply ${fdto_addr_r}\0" \ + "fdto_addr_r=0x100c0000\0" \ + "fdtofile=socfpga_enclustra_mercury_XXX_overlay.dtbo\0" \ + "fdto_size=0x40000\0" \ + "fdt_size=0x40000\0" \ + "kernel_addr_r=0x11000000\0" \ + "kernel_size=0x1000000\0" \ + "qspiboot=source ${scriptaddr}\0" \ + "qspiload=setenv bootargs ${bootargs_qspi}; sf probe; sf read ${scriptaddr} ${qspi_offset_addr_boot_script} ${scriptsize}\0" \ + "qspi_offset_addr_bitstream=0x300000\0" \ + "qspi_offset_addr_boot_script=0x200000\0" \ + "qspi_offset_addr_devicetree=0x280000\0" \ + "qspi_offset_addr_dtoverlay=0x2c0000\0" \ + "qspi_offset_addr_kernel=0x1000000\0" \ + "qspi_offset_addr_rootfs=0x2000000\0" \ + "qspi_offset_addr_spl=0x0\0" \ + "qspi_offset_addr_uboot=0x100000\0" \ + "qspi_offset_addr_uboot_env=0x180000\0" \ + "rootfs_addr_r=0x12000000\0" \ + "rootfs_size=0x2000000\0" \ + "scriptaddr=0x10800000\0" \ + "scriptsize=0x80000\0" \ + "spl_size=0x100000\0" \ + "uboot_size=0x80000\0" + /* * L4 OSC1 Timer 0 */

Add support to boot Enclustra SoMs from MMC, SD or QSPI flash.

Signed-off-by: Lothar Rubusch l.rubusch@gmail.com --- board/enclustra/bootscripts/qspi-aa1.cmd | 12 ++++++++++++ board/enclustra/bootscripts/sd-aa1.cmd | 10 ++++++++++ 2 files changed, 22 insertions(+) create mode 100644 board/enclustra/bootscripts/qspi-aa1.cmd create mode 100644 board/enclustra/bootscripts/sd-aa1.cmd

diff --git a/board/enclustra/bootscripts/qspi-aa1.cmd b/board/enclustra/bootscripts/qspi-aa1.cmd new file mode 100644 index 0000000000..42d02cfce1 --- /dev/null +++ b/board/enclustra/bootscripts/qspi-aa1.cmd @@ -0,0 +1,12 @@ +# This is an example input file for boot.scr generation. +# Generate boot.scr +# ./tools/mkimage -A arm -O linux -T script -C none -a 0 -e 0 -d board/enclustra/bootscripts/qspi-aa1.cmd boot.scr +# +# NB: The needed variables need to be set in the environment. +bridge enable +sf probe +sf read $kernel_addr_r $qspi_offset_addr_kernel $kernel_size +sf read $fdt_addr_r $qspi_offset_addr_devicetree $fdt_size +sf read $rootfs_addr_r $qspi_offset_addr_rootfs $rootfs_size +run fdtload_qspi +bootm $kernel_addr_r $rootfs_addr_r $fdt_addr_r diff --git a/board/enclustra/bootscripts/sd-aa1.cmd b/board/enclustra/bootscripts/sd-aa1.cmd new file mode 100644 index 0000000000..4beefc7e13 --- /dev/null +++ b/board/enclustra/bootscripts/sd-aa1.cmd @@ -0,0 +1,10 @@ +# This is an example input file for boot.scr generation. +# Generate boot.scr +# ./tools/mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "U-boot mmc start script" -d board/enclustra/bootscripts/sd-aa1.cmd boot.scr +# +# NB: The needed variables need to be set in the environment. +bridge enable +fatload mmc $devnum:$distro_bootpart $kernel_addr_r Image +fatload mmc $devnum:$distro_bootpart $fdt_addr_r $fdtfile +run fdtload +bootm $kernel_addr_r - $fdt_addr_r

The si5338 clock generator is needed on some Enclustra Socfpga SoMs. Introduce minimal support of this device.

Signed-off-by: Lothar Rubusch l.rubusch@gmail.com --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/skyworks/Kconfig | 10 + drivers/clk/skyworks/Makefile | 3 + drivers/clk/skyworks/Si5338-RevB-Registers.h | 441 +++++++++++++++++++ drivers/clk/skyworks/si5338_clkgen.c | 177 ++++++++ drivers/clk/skyworks/si5338_clkgen.h | 18 + 7 files changed, 651 insertions(+) create mode 100644 drivers/clk/skyworks/Kconfig create mode 100644 drivers/clk/skyworks/Makefile create mode 100644 drivers/clk/skyworks/Si5338-RevB-Registers.h create mode 100644 drivers/clk/skyworks/si5338_clkgen.c create mode 100644 drivers/clk/skyworks/si5338_clkgen.h

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 9acbc47fe8..5d2053623c 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -259,6 +259,7 @@ source "drivers/clk/qcom/Kconfig" source "drivers/clk/renesas/Kconfig" source "drivers/clk/sunxi/Kconfig" source "drivers/clk/sifive/Kconfig" +source "drivers/clk/skyworks/Kconfig" source "drivers/clk/starfive/Kconfig" source "drivers/clk/stm32/Kconfig" source "drivers/clk/tegra/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 847b9b2911..daa70112ac 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_CLK_QCOM) += qcom/ obj-$(CONFIG_CLK_RENESAS) += renesas/ obj-$(CONFIG_$(SPL_TPL_)CLK_SCMI) += clk_scmi.o obj-$(CONFIG_CLK_SIFIVE) += sifive/ +obj-$(CONFIG_CLK_SKYWORKS_SI5338) += skyworks/ obj-$(CONFIG_CLK_SUNXI) += sunxi/ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o diff --git a/drivers/clk/skyworks/Kconfig b/drivers/clk/skyworks/Kconfig new file mode 100644 index 0000000000..dd041f603a --- /dev/null +++ b/drivers/clk/skyworks/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 + +config CLK_SKYWORKS_SI5338 + bool "Skyworks SI5338 clock generator" + depends on CLK + depends on DM_I2C + depends on SPL_I2C + help + Configure the SI5338 clock generator device. The SI5338 is needed on + some Enclustra Socfpga SoMs. diff --git a/drivers/clk/skyworks/Makefile b/drivers/clk/skyworks/Makefile new file mode 100644 index 0000000000..c676b6ef94 --- /dev/null +++ b/drivers/clk/skyworks/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_CLK_SKYWORKS_SI5338) += si5338_clkgen.o diff --git a/drivers/clk/skyworks/Si5338-RevB-Registers.h b/drivers/clk/skyworks/Si5338-RevB-Registers.h new file mode 100644 index 0000000000..e1754cd807 --- /dev/null +++ b/drivers/clk/skyworks/Si5338-RevB-Registers.h @@ -0,0 +1,441 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2024 Enclustra GmbH + * info@enclustra.com + */ + +#ifndef __SI5338_REVB_REGISTERS_H +#define __SI5338_REVB_REGISTERS_H + +#include "si5338_clkgen.h" + +/* + * Register map for use with AN428 (JumpStart) + * http://www.skyworksinc.com/timing + * #BEGIN_HEADER + * Date = Friday, June 09, 2023 5:03 PM + * File version = 3 + * Software Name = ClockBuilder Pro + * Software version = 4.9.0.0 + * Software date = 4 24, 2023 + * Chip = Si533x + * Part Number = Si533x + * #END_HEADER + * Input Frequency (MHz) = 24.000000000 + * Input Type = CMOS_SSTL_HSTL + * P1 = 1 + * Input Mux = RefClk + * FDBK Input Frequency (MHz) = 24.000000000 + * FDBK Input Type = OFF + * P2 = 1 + * FDBK Mux = NoClk + * PFD Input Frequency (MHz) = 24.000000000 + * VCO Frequency (GHz) = 2.500000 + * N = 104 1/6 (104.1667) + * Internal feedback enabled + * Output Clock 0 + * Output Frequency (MHz) = 125.000000000 + * Mux Selection = IDn + * MultiSynth = 20 (20.0000) + * R = 1 + * Output Clock 1 + * Output is off + * Output Clock 2 + * Output is off + * Output Clock 3 + * Output Frequency (MHz) = 100.000000000 + * Mux Selection = IDn + * MultiSynth = 25 (25.0000) + * R = 1 + * Driver 0 + * Enabled + * Powered on + * Output voltage = 3.30 + * Output type = 3.3V LVDS + * Output state when disabled = Tristate + * Driver 1 + * Disabled + * Powered off + * Output voltage = 3.30 + * Output type = 3.3V LVDS + * Output state when disabled = StopLow + * Driver 2 + * Disabled + * Powered off + * Output voltage = 3.30 + * Output type = 3.3V LVDS + * Output state when disabled = StopLow + * Driver 3 + * Enabled + * Powered on + * Output voltage = 3.30 + * Output type = 3.3V CMOS on A + * Output state when disabled = Tristate + * Clock 0 phase inc/dec step size (ns) = 0.000 + * Clock 1 phase inc/dec step size (ns) = 0.000 + * Clock 2 phase inc/dec step size (ns) = 0.000 + * Clock 3 phase inc/dec step size (ns) = 0.000 + * Phase increment and decrement pin control is off + * Frequency increment and decrement pin control is off + * Frequency increment and decrement is disabled + * Initial phase offset 0 (ns) = 0.000 + * Initial phase offset 1 (ns) = 0.000 + * Initial phase offset 2 (ns) = 0.000 + * Initial phase offset 3 (ns) = 0.000 + * SSC is disabled + */ + +#define NUM_REGS_MAX 350 + +struct reg_data const reg_store[NUM_REGS_MAX] = { + { 0, 0x00, 0x00}, + { 1, 0x00, 0x00}, + { 2, 0x00, 0x00}, + { 3, 0x00, 0x00}, + { 4, 0x00, 0x00}, + { 5, 0x00, 0x00}, + { 6, 0x08, 0x1D}, + { 7, 0x00, 0x00}, + { 8, 0x70, 0x00}, + { 9, 0x0F, 0x00}, + { 10, 0x00, 0x00}, + { 11, 0x00, 0x00}, + { 12, 0x00, 0x00}, + { 13, 0x00, 0x00}, + { 14, 0x00, 0x00}, + { 15, 0x00, 0x00}, + { 16, 0x00, 0x00}, + { 17, 0x00, 0x00}, + { 18, 0x00, 0x00}, + { 19, 0x00, 0x00}, + { 20, 0x00, 0x00}, + { 21, 0x00, 0x00}, + { 22, 0x00, 0x00}, + { 23, 0x00, 0x00}, + { 24, 0x00, 0x00}, + { 25, 0x00, 0x00}, + { 26, 0x00, 0x00}, + { 27, 0x70, 0x80}, + { 28, 0x0B, 0xFF}, + { 29, 0x08, 0xFF}, + { 30, 0xB0, 0xFF}, + { 31, 0xC0, 0xFF}, + { 32, 0xE3, 0xFF}, + { 33, 0xE3, 0xFF}, + { 34, 0xC0, 0xFF}, + { 35, 0x00, 0xFF}, + { 36, 0x06, 0x1F}, + { 37, 0x00, 0x1F}, + { 38, 0x00, 0x1F}, + { 39, 0x01, 0x1F}, + { 40, 0x63, 0xFF}, + { 41, 0x0C, 0x7F}, + { 42, 0x37, 0x3F}, + { 43, 0x00, 0x00}, + { 44, 0x00, 0x00}, + { 45, 0x00, 0xFF}, + { 46, 0x00, 0xFF}, + { 47, 0x14, 0x3F}, + { 48, 0x3C, 0xFF}, + { 49, 0x00, 0xFF}, + { 50, 0xC4, 0xFF}, + { 51, 0x07, 0xFF}, + { 52, 0x10, 0xFF}, + { 53, 0x00, 0xFF}, + { 54, 0x08, 0xFF}, + { 55, 0x00, 0xFF}, + { 56, 0x00, 0xFF}, + { 57, 0x00, 0xFF}, + { 58, 0x00, 0xFF}, + { 59, 0x01, 0xFF}, + { 60, 0x00, 0xFF}, + { 61, 0x00, 0xFF}, + { 62, 0x00, 0x3F}, + { 63, 0x10, 0xFF}, + { 64, 0x00, 0xFF}, + { 65, 0x00, 0xFF}, + { 66, 0x00, 0xFF}, + { 67, 0x00, 0xFF}, + { 68, 0x00, 0xFF}, + { 69, 0x00, 0xFF}, + { 70, 0x00, 0xFF}, + { 71, 0x00, 0xFF}, + { 72, 0x00, 0xFF}, + { 73, 0x00, 0x3F}, + { 74, 0x10, 0xFF}, + { 75, 0x00, 0xFF}, + { 76, 0x00, 0xFF}, + { 77, 0x00, 0xFF}, + { 78, 0x00, 0xFF}, + { 79, 0x00, 0xFF}, + { 80, 0x00, 0xFF}, + { 81, 0x00, 0xFF}, + { 82, 0x00, 0xFF}, + { 83, 0x00, 0xFF}, + { 84, 0x00, 0x3F}, + { 85, 0x10, 0xFF}, + { 86, 0x80, 0xFF}, + { 87, 0x0A, 0xFF}, + { 88, 0x00, 0xFF}, + { 89, 0x00, 0xFF}, + { 90, 0x00, 0xFF}, + { 91, 0x00, 0xFF}, + { 92, 0x01, 0xFF}, + { 93, 0x00, 0xFF}, + { 94, 0x00, 0xFF}, + { 95, 0x00, 0x3F}, + { 96, 0x10, 0x00}, + { 97, 0x15, 0xFF}, + { 98, 0x32, 0xFF}, + { 99, 0x08, 0xFF}, + {100, 0x00, 0xFF}, + {101, 0x00, 0xFF}, + {102, 0x00, 0xFF}, + {103, 0x06, 0xFF}, + {104, 0x00, 0xFF}, + {105, 0x00, 0xFF}, + {106, 0x80, 0xBF}, + {107, 0x00, 0xFF}, + {108, 0x00, 0xFF}, + {109, 0x00, 0xFF}, + {110, 0x00, 0xFF}, + {111, 0x00, 0xFF}, + {112, 0x00, 0xFF}, + {113, 0x00, 0xFF}, + {114, 0x40, 0xFF}, + {115, 0x00, 0xFF}, + {116, 0x80, 0xFF}, + {117, 0x00, 0xFF}, + {118, 0x40, 0xFF}, + {119, 0x00, 0xFF}, + {120, 0x00, 0xFF}, + {121, 0x00, 0xFF}, + {122, 0x00, 0xFF}, + {123, 0x00, 0xFF}, + {124, 0x00, 0xFF}, + {125, 0x00, 0xFF}, + {126, 0x00, 0xFF}, + {127, 0x00, 0xFF}, + {128, 0x00, 0xFF}, + {129, 0x00, 0x0F}, + {130, 0x00, 0x0F}, + {131, 0x00, 0xFF}, + {132, 0x00, 0xFF}, + {133, 0x00, 0xFF}, + {134, 0x00, 0xFF}, + {135, 0x00, 0xFF}, + {136, 0x00, 0xFF}, + {137, 0x00, 0xFF}, + {138, 0x00, 0xFF}, + {139, 0x00, 0xFF}, + {140, 0x00, 0xFF}, + {141, 0x00, 0xFF}, + {142, 0x00, 0xFF}, + {143, 0x00, 0xFF}, + {144, 0x00, 0xFF}, + {145, 0x00, 0x00}, + {146, 0xFF, 0x00}, + {147, 0x00, 0x00}, + {148, 0x00, 0x00}, + {149, 0x00, 0x00}, + {150, 0x00, 0x00}, + {151, 0x00, 0x00}, + {152, 0x00, 0xFF}, + {153, 0x00, 0xFF}, + {154, 0x00, 0xFF}, + {155, 0x00, 0xFF}, + {156, 0x00, 0xFF}, + {157, 0x00, 0xFF}, + {158, 0x00, 0x0F}, + {159, 0x00, 0x0F}, + {160, 0x00, 0xFF}, + {161, 0x00, 0xFF}, + {162, 0x00, 0xFF}, + {163, 0x00, 0xFF}, + {164, 0x00, 0xFF}, + {165, 0x00, 0xFF}, + {166, 0x00, 0xFF}, + {167, 0x00, 0xFF}, + {168, 0x00, 0xFF}, + {169, 0x00, 0xFF}, + {170, 0x00, 0xFF}, + {171, 0x00, 0xFF}, + {172, 0x00, 0xFF}, + {173, 0x00, 0xFF}, + {174, 0x00, 0xFF}, + {175, 0x00, 0xFF}, + {176, 0x00, 0xFF}, + {177, 0x00, 0xFF}, + {178, 0x00, 0xFF}, + {179, 0x00, 0xFF}, + {180, 0x00, 0xFF}, + {181, 0x00, 0x0F}, + {182, 0x00, 0xFF}, + {183, 0x00, 0xFF}, + {184, 0x00, 0xFF}, + {185, 0x00, 0xFF}, + {186, 0x00, 0xFF}, + {187, 0x00, 0xFF}, + {188, 0x00, 0xFF}, + {189, 0x00, 0xFF}, + {190, 0x00, 0xFF}, + {191, 0x00, 0xFF}, + {192, 0x00, 0xFF}, + {193, 0x00, 0xFF}, + {194, 0x00, 0xFF}, + {195, 0x00, 0xFF}, + {196, 0x00, 0xFF}, + {197, 0x00, 0xFF}, + {198, 0x00, 0xFF}, + {199, 0x00, 0xFF}, + {200, 0x00, 0xFF}, + {201, 0x00, 0xFF}, + {202, 0x00, 0xFF}, + {203, 0x00, 0x0F}, + {204, 0x00, 0xFF}, + {205, 0x00, 0xFF}, + {206, 0x00, 0xFF}, + {207, 0x00, 0xFF}, + {208, 0x00, 0xFF}, + {209, 0x00, 0xFF}, + {210, 0x00, 0xFF}, + {211, 0x00, 0xFF}, + {212, 0x00, 0xFF}, + {213, 0x00, 0xFF}, + {214, 0x00, 0xFF}, + {215, 0x00, 0xFF}, + {216, 0x00, 0xFF}, + {217, 0x00, 0xFF}, + {218, 0x00, 0x00}, + {219, 0x00, 0x00}, + {220, 0x00, 0x00}, + {221, 0x0D, 0x00}, + {222, 0x00, 0x00}, + {223, 0x00, 0x00}, + {224, 0xF4, 0x00}, + {225, 0xF0, 0x00}, + {226, 0x00, 0x00}, + {227, 0x00, 0x00}, + {228, 0x00, 0x00}, + {229, 0x00, 0x00}, + {231, 0x00, 0x00}, + {232, 0x00, 0x00}, + {233, 0x00, 0x00}, + {234, 0x00, 0x00}, + {235, 0x00, 0x00}, + {236, 0x00, 0x00}, + {237, 0x00, 0x00}, + {238, 0x14, 0x00}, + {239, 0x00, 0x00}, + {240, 0x00, 0x00}, + {242, 0x02, 0x02}, + {243, 0xF0, 0x00}, + {244, 0x00, 0x00}, + {245, 0x00, 0x00}, + {247, 0x00, 0x00}, + {248, 0x00, 0x00}, + {249, 0xA8, 0x00}, + {250, 0x00, 0x00}, + {251, 0x84, 0x00}, + {252, 0x00, 0x00}, + {253, 0x00, 0x00}, + {254, 0x00, 0x00}, + {255, 1, 0xFF}, // set page bit to 1 + { 0, 0x00, 0x00}, + { 1, 0x00, 0x00}, + { 2, 0x00, 0x00}, + { 3, 0x00, 0x00}, + { 4, 0x00, 0x00}, + { 5, 0x00, 0x00}, + { 6, 0x00, 0x00}, + { 7, 0x00, 0x00}, + { 8, 0x00, 0x00}, + { 9, 0x00, 0x00}, + { 10, 0x00, 0x00}, + { 11, 0x00, 0x00}, + { 12, 0x00, 0x00}, + { 13, 0x00, 0x00}, + { 14, 0x00, 0x00}, + { 15, 0x00, 0x00}, + { 16, 0x00, 0x00}, + { 17, 0x01, 0x00}, + { 18, 0x00, 0x00}, + { 19, 0x00, 0x00}, + { 20, 0x90, 0x00}, + { 21, 0x31, 0x00}, + { 22, 0x00, 0x00}, + { 23, 0x00, 0x00}, + { 24, 0x01, 0x00}, + { 25, 0x00, 0x00}, + { 26, 0x00, 0x00}, + { 27, 0x00, 0x00}, + { 28, 0x00, 0x00}, + { 29, 0x00, 0x00}, + { 30, 0x00, 0x00}, + { 31, 0x00, 0xFF}, + { 32, 0x00, 0xFF}, + { 33, 0x01, 0xFF}, + { 34, 0x00, 0xFF}, + { 35, 0x00, 0xFF}, + { 36, 0x90, 0xFF}, + { 37, 0x31, 0xFF}, + { 38, 0x00, 0xFF}, + { 39, 0x00, 0xFF}, + { 40, 0x01, 0xFF}, + { 41, 0x00, 0xFF}, + { 42, 0x00, 0xFF}, + { 43, 0x00, 0x0F}, + { 44, 0x00, 0x00}, + { 45, 0x00, 0x00}, + { 46, 0x00, 0x00}, + { 47, 0x00, 0xFF}, + { 48, 0x00, 0xFF}, + { 49, 0x01, 0xFF}, + { 50, 0x00, 0xFF}, + { 51, 0x00, 0xFF}, + { 52, 0x90, 0xFF}, + { 53, 0x31, 0xFF}, + { 54, 0x00, 0xFF}, + { 55, 0x00, 0xFF}, + { 56, 0x01, 0xFF}, + { 57, 0x00, 0xFF}, + { 58, 0x00, 0xFF}, + { 59, 0x00, 0x0F}, + { 60, 0x00, 0x00}, + { 61, 0x00, 0x00}, + { 62, 0x00, 0x00}, + { 63, 0x00, 0xFF}, + { 64, 0x00, 0xFF}, + { 65, 0x01, 0xFF}, + { 66, 0x00, 0xFF}, + { 67, 0x00, 0xFF}, + { 68, 0x90, 0xFF}, + { 69, 0x31, 0xFF}, + { 70, 0x00, 0xFF}, + { 71, 0x00, 0xFF}, + { 72, 0x01, 0xFF}, + { 73, 0x00, 0xFF}, + { 74, 0x00, 0xFF}, + { 75, 0x00, 0x0F}, + { 76, 0x00, 0x00}, + { 77, 0x00, 0x00}, + { 78, 0x00, 0x00}, + { 79, 0x00, 0xFF}, + { 80, 0x00, 0xFF}, + { 81, 0x00, 0xFF}, + { 82, 0x00, 0xFF}, + { 83, 0x00, 0xFF}, + { 84, 0x90, 0xFF}, + { 85, 0x31, 0xFF}, + { 86, 0x00, 0xFF}, + { 87, 0x00, 0xFF}, + { 88, 0x01, 0xFF}, + { 89, 0x00, 0xFF}, + { 90, 0x00, 0xFF}, + { 91, 0x00, 0x0F}, + { 92, 0x00, 0x00}, + { 93, 0x00, 0x00}, + { 94, 0x00, 0x00}, + {255, 0, 0xFF} }; // set page bit to 0 + +#endif /* __SI5338_REVB_REGISTERS_H */ diff --git a/drivers/clk/skyworks/si5338_clkgen.c b/drivers/clk/skyworks/si5338_clkgen.c new file mode 100644 index 0000000000..903dd05d5d --- /dev/null +++ b/drivers/clk/skyworks/si5338_clkgen.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Enclustra GmbH + * + * SI5338 - A I2C programmable any-frequency, any-output quad clock generator. + */ + +#include <linux/compat.h> +#include <i2c.h> +#include <linux/delay.h> +#include <clk.h> +#include <clk-uclass.h> +#include <dm.h> + +#include "si5338_clkgen.h" + +#include "Si5338-RevB-Registers.h" + +int i2c_write_simple(struct udevice *dev, u8 addr, u8 data) +{ + unsigned char buf[1]; + + buf[0] = data; + if (dm_i2c_write(dev, addr, buf, 1) != 0) { + printf("SI5338 I2C write failed: %02x, %02x\n", addr, data); + return -1; + } + return 0; +} + +int i2c_write_masked(struct udevice *dev, u8 addr, u8 data, u8 mask) +{ + unsigned char buf[1]; + + if (mask == 0x00) + return 0; + + if (mask == 0xff) + return i2c_write_simple(dev, addr, data); + + if (dm_i2c_read(dev, addr, buf, 1) != 0) { + printf("SI5338 I2C read failed\n"); + return -1; + } + buf[0] &= ~mask; + buf[0] |= data & mask; + if (dm_i2c_write(dev, addr, buf, 1) != 0) { + printf("SI5338 I2C write failed: %02x, %02x, %02x\n", + addr, data, mask); + return -1; + } + return 0; +} + +int si5338_init(void) +{ + unsigned char buf[1]; + struct udevice *dev; + int try = 0; + int i; + int ret; + + ret = i2c_get_chip_for_busnum(0, 0x70, 1, &dev); + if (ret) { + printf("SI5338 I2C init failed\n"); + return -ENODEV; + } + + /* Set page to 0 */ + if (i2c_write_simple(dev, 255, 0x00)) + return -EFAULT; + + /* Disable outputs */ + if (i2c_write_masked(dev, 230, 0x10, 0x10)) + return -EFAULT; + + /* Pause */ + if (i2c_write_masked(dev, 241, 0x80, 0x80)) + return -EFAULT; + + /* Write new configuration */ + for (i = 0; i < NUM_REGS_MAX; i++) { + if (i2c_write_masked(dev, reg_store[i].reg_addr, + reg_store[i].reg_val, + reg_store[i].reg_mask)) { + return -EFAULT; + } + } + + /* Validate input clock status */ + do { + if (dm_i2c_read(dev, 218, buf, 1) != 0) { + printf("SI5338 I2C read failed\n"); + return -EFAULT; + } + } while ((buf[0] & 0x04) != 0); + + /* Configure PLL for locking */ + if (i2c_write_masked(dev, 49, 0, 0x80)) + return -EFAULT; + + /* Initiate locking of PLL */ + if (i2c_write_simple(dev, 246, 0x02)) + return -EFAULT; + + /* Wait 25ms (100ms to be on the safe side) */ + mdelay(100); + + /* Restart */ + if (i2c_write_masked(dev, 241, 0x65, 0xff)) + return -EFAULT; + + /* Confirm PLL lock status */ + do { + if (dm_i2c_read(dev, 218, buf, 1) != 0) { + printf("SI5338 I2C read failed\n"); + return -EFAULT; + } + mdelay(100); + try++; + if (try > 10) { + printf("SI5338 PLL is not locking\n"); + return -EFAULT; + } + } while ((buf[0] & 0x15) != 0); + + /* Copy fcal values to active registers */ + if (dm_i2c_read(dev, 237, buf, 1) != 0) { + printf("SI5338 I2C failed\n"); + return -EFAULT; + } + + if (i2c_write_masked(dev, 47, buf[0], 0x03)) + return -EFAULT; + + if (dm_i2c_read(dev, 236, buf, 1) != 0) { + printf("SI5338 I2C failed\n"); + return -EFAULT; + } + + if (i2c_write_masked(dev, 46, buf[0], 0xFF)) + return -EFAULT; + + if (dm_i2c_read(dev, 235, buf, 1) != 0) { + printf("SI5338 I2C failed\n"); + return -EFAULT; + } + + if (i2c_write_simple(dev, 45, buf[0])) + return -EFAULT; + + if (i2c_write_masked(dev, 47, 0x14, 0xFC)) + return -EFAULT; + + /* Set PLL to use FCAL values */ + if (i2c_write_masked(dev, 49, 0x80, 0x80)) + return -EFAULT; + + /* Enable outputs */ + if (i2c_write_simple(dev, 230, 0x00)) + return -EFAULT; + + printf("SI5338 init successful\n"); + + return 0; +} + +static int si5338_clk_probe(struct udevice *dev) +{ + return si5338_init(); +} + +U_BOOT_DRIVER(si5338_clkgen) = { + .name = "si5338_clkgen", + .id = UCLASS_CLK, + .probe = si5338_clk_probe, +}; diff --git a/drivers/clk/skyworks/si5338_clkgen.h b/drivers/clk/skyworks/si5338_clkgen.h new file mode 100644 index 0000000000..98c6ff1960 --- /dev/null +++ b/drivers/clk/skyworks/si5338_clkgen.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2024 Enclustra GmbH + * info@enclustra.com + */ + +#ifndef __SI5338_CLKGEN_H +#define __SI5338_CLKGEN_H + +int si5338_init(void); + +struct reg_data { + unsigned char reg_addr; + unsigned char reg_val; + unsigned char reg_mask; +}; + +#endif /* __SI5338_CLKGEN_H */