The ALE mask used by DaVinci SOCs is wrong. The patch changes the mask value from '0xa' to '0x8'. This is the mask we use for all TI releases.

Signed-off-by: Sandeep Paulraj s-paulraj@ti.com --- include/asm-arm/arch-davinci/nand_defs.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/include/asm-arm/arch-davinci/nand_defs.h b/include/asm-arm/arch-davinci/nand_defs.h index 70094e7..ba75cd6 100644 --- a/include/asm-arm/arch-davinci/nand_defs.h +++ b/include/asm-arm/arch-davinci/nand_defs.h @@ -29,7 +29,7 @@ #include <asm/arch/hardware.h>

#define MASK_CLE 0x10 -#define MASK_ALE 0x0a +#define MASK_ALE 0x08

#define NAND_READ_START 0x00 #define NAND_READ_END 0x30