From: Ye Li ye.li@nxp.com To support HDMI display on EVK board, the LCDIF pix clock must be 25.2Mhz. Since the its PCC divider range is from 1-8, the max rate of LCDIF PCC source clock is 201.6Mhz. This limits the source clock must from NIC1 bus clock or NIC1 clock, other sources from APLL PFDs are higher than this max rate. The NIC1 bus clock and NIC1 clock are from DDRCLK whose parent source is APLL PFD0, so we must change the APLL PFD0 and have impact to DDRCLK, NIC1 and NIC1 bus. Eventually, this requests to set the APLL PFD0 frequency to 302.4Mhz (25.2 * 12), with settings: PFD0 FRAC: 32 APLL MULT: 22 APLL NUM: 2 APLL DENOM: 5 Signed-off-by: Ye Li ye.li@nxp.com Tested-by: Fancy Fang chen.fang@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com

Applied to u-boot-imx, master, thanks !

Best regards, Stefano Babic