[U-Boot] [RESEND PATCH v3 1/3] Don't enable CONFIG_SPL_DM_USB for non-DM SPL
When CONFIG_SPL_DM_USB was added, it was added defaulted on without protection to ensure it didn't get set for non-DM SPL builds.
This leads to unexpected and confusing failures when building a DM based U-Boot but with a non-DM SPL, as the defconfig is unlikely to have CONFIG_SPL_DM_USB actively disabled.
Tweak the Kconfig to not enable this setting unless CONFIG_SPL_DM is set.
Signed-off-by: Martyn Welch martyn.welch@collabora.com
---
Changes in v3: - New in v3
Changes in v2: None
drivers/usb/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index d456beb43f..3c978d43aa 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -49,7 +49,7 @@ config DM_USB
config SPL_DM_USB bool "Enable driver model for USB in SPL" - depends on DM_USB + depends on SPL_DM && DM_USB default y
source "drivers/usb/host/Kconfig"
Currently if we have more than one phy on the MDIO bus, we do not have a good mechanism for determining which should be used at runtime. Enable the FEC driver to determine the address for the PHY from the device tree.
Signed-off-by: Martyn Welch martyn.welch@collabora.com Reviewed-by: Lukasz Majewski lukma@denx.de
---
Changes in v3: - No changes in v3
Changes in v2: - New in v2
drivers/net/fec_mxc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 99c5c649a0..425f6197cb 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1264,11 +1264,32 @@ static const struct eth_ops fecmxc_ops = { .read_rom_hwaddr = fecmxc_read_rom_hwaddr, };
+static int device_get_phy_addr(struct udevice *dev) +{ + struct ofnode_phandle_args phandle_args; + int reg; + + if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, + &phandle_args)) { + debug("Failed to find phy-handle"); + return -ENODEV; + } + + reg = ofnode_read_u32_default(phandle_args.node, "reg", 0); + + return reg; +} + static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) { struct phy_device *phydev; + int addr; int mask = 0xffffffff;
+ addr = device_get_phy_addr(dev); + if (addr >= 0) + mask = 1 << addr; + #ifdef CONFIG_FEC_MXC_PHYADDR mask = 1 << CONFIG_FEC_MXC_PHYADDR; #endif
Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on the PHYTEC phyCORE-i.MX6UL SOM (PCL063).
CPU: Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 44C Reset cause: POR Board: PHYTEC phyCORE-i.MX6UL I2C: ready DRAM: 256 MiB NAND: 512 MiB MMC: FSL_SDHC: 0 In: serial Out: serial Err: serial Net: FEC0
Working: - Eth0 - i2C - MMC/SD - NAND - UART (1 & 5) - USB (host & otg)
Signed-off-by: Martyn Welch martyn.welch@collabora.com
---
Changes in v3: - Correct spelling of Phytec - Remove unneeded license information - Correct image name in documentation - Correct whitespacing - Enable SPL to boot from MMC - Simplify defconfig, remove non-SPL build
Changes in v2: - Switch to driver model
arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx6ul-pcl063.dtsi | 173 +++++++++++++++++++++ arch/arm/dts/imx6ul-phycore-segin.dts | 76 ++++++++++ arch/arm/mach-imx/mx6/Kconfig | 13 ++ board/phytec/pcl063/Kconfig | 12 ++ board/phytec/pcl063/MAINTAINERS | 8 + board/phytec/pcl063/Makefile | 7 + board/phytec/pcl063/README | 26 ++++ board/phytec/pcl063/pcl063.c | 206 ++++++++++++++++++++++++++ board/phytec/pcl063/spl.c | 160 ++++++++++++++++++++ configs/phycore_pcl063_defconfig | 61 ++++++++ include/configs/pcl063.h | 100 +++++++++++++ 12 files changed, 844 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx6ul-pcl063.dtsi create mode 100644 arch/arm/dts/imx6ul-phycore-segin.dts create mode 100644 board/phytec/pcl063/Kconfig create mode 100644 board/phytec/pcl063/MAINTAINERS create mode 100644 board/phytec/pcl063/Makefile create mode 100644 board/phytec/pcl063/README create mode 100644 board/phytec/pcl063/pcl063.c create mode 100644 board/phytec/pcl063/spl.c create mode 100644 configs/phycore_pcl063_defconfig create mode 100644 include/configs/pcl063.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 949ee472fc..68411623e5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -453,7 +453,8 @@ dtb-$(CONFIG_MX6UL) += \ imx6ul-isiot-nand.dtb \ imx6ul-opos6uldev.dtb \ imx6ul-14x14-evk.dtb \ - imx6ul-9x9-evk.dtb + imx6ul-9x9-evk.dtb \ + imx6ul-phycore-segin.dtb
dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb
diff --git a/arch/arm/dts/imx6ul-pcl063.dtsi b/arch/arm/dts/imx6ul-pcl063.dtsi new file mode 100644 index 0000000000..24a6a47983 --- /dev/null +++ b/arch/arm/dts/imx6ul-pcl063.dtsi @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Collabora Ltd. + * + * Based on dts[i] from Phytec barebox port: + * Copyright (C) 2016 PHYTEC Messtechnik GmbH + * Author: Christian Hemp c.hemp@phytec.de + */ + +/dts-v1/; + +#include "imx6ul.dtsi" + +/ { + model = "Phytec phyCORE-i.MX6 Ultra Lite SOM"; + compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul"; + + memory { + reg = <0x80000000 0x20000000>; + }; + + chosen { + stdout-path = &uart1; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + reg = <1>; + micrel,led-mode = <1>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + fsl,no-blockmark-swap; + status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x400000>; + }; + + partition@400000 { + label = "uboot-env"; + reg = <0x400000 0x100000>; + }; + + partition@500000 { + label = "root"; + reg = <0x500000 0x0>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + status = "okay"; + + eeprom@52 { + compatible = "cat,24c32"; + reg = <0x52>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + bus-width = <0x4>; + pinctrl-0 = <&pinctrl_usdhc1>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0X1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_i2c1: i2cgrp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + + >; + }; +}; diff --git a/arch/arm/dts/imx6ul-phycore-segin.dts b/arch/arm/dts/imx6ul-phycore-segin.dts new file mode 100644 index 0000000000..a46012e2b4 --- /dev/null +++ b/arch/arm/dts/imx6ul-phycore-segin.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Collabora Ltd. + * + * Based on dts[i] from Phytec barebox port: + * Copyright (C) 2016 PHYTEC Messtechnik GmbH + * Author: Christian Hemp c.hemp@phytec.de + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include "imx6ul-pcl063.dtsi" + +/ { + model = "Phytec phyBOARD-i.MX6UL-Segin SBC"; + compatible = "phytec,phyboard-imx6ul-segin", "phytec,imx6ul-pcl063", + "fsl,imx6ul"; +}; + +&i2c1 { + i2c_rtc: rtc@68 { + compatible = "microcrystal,rv4162"; + reg = <0x68>; + status = "okay"; + }; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 06c25bae36..e253f495c5 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -428,6 +428,18 @@ config TARGET_PFLA02 select MX6QDL select SUPPORT_SPL
+config TARGET_PCL063 + bool "PHYTEC PCL063 (phyCORE-i.MX6UL)" + select MX6UL + select DM + select DM_ETH + select DM_GPIO + select DM_I2C + select DM_MMC + select DM_SERIAL + select DM_THERMAL + select SUPPORT_SPL + config TARGET_SECOMX6 bool "secomx6 boards"
@@ -550,6 +562,7 @@ source "board/freescale/mx6ullevk/Kconfig" source "board/grinn/liteboard/Kconfig" source "board/phytec/pcm058/Kconfig" source "board/phytec/pfla02/Kconfig" +source "board/phytec/pcl063/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/kosagi/novena/Kconfig" source "board/samtec/vining_2000/Kconfig" diff --git a/board/phytec/pcl063/Kconfig b/board/phytec/pcl063/Kconfig new file mode 100644 index 0000000000..977db70f64 --- /dev/null +++ b/board/phytec/pcl063/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PCL063 + +config SYS_BOARD + default "pcl063" + +config SYS_VENDOR + default "phytec" + +config SYS_CONFIG_NAME + default "pcl063" + +endif diff --git a/board/phytec/pcl063/MAINTAINERS b/board/phytec/pcl063/MAINTAINERS new file mode 100644 index 0000000000..c65a951f3d --- /dev/null +++ b/board/phytec/pcl063/MAINTAINERS @@ -0,0 +1,8 @@ +PCL063 BOARD +M: Martyn Welch martyn.welch@collabora.com +S: Maintained +F: arch/arm/dts/imx6ul-pcl063.dtsi +F: arch/arm/dts/imx6ul-phycore-segin.dts +F: board/phytec/pcl063/ +F: configs/phycore_pcl063_defconfig +F: include/configs/pcl063.h diff --git a/board/phytec/pcl063/Makefile b/board/phytec/pcl063/Makefile new file mode 100644 index 0000000000..53c73c9b08 --- /dev/null +++ b/board/phytec/pcl063/Makefile @@ -0,0 +1,7 @@ +# Copyright (C) 2018 Collabora Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := pcl063.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/phytec/pcl063/README b/board/phytec/pcl063/README new file mode 100644 index 0000000000..be83bdb0d8 --- /dev/null +++ b/board/phytec/pcl063/README @@ -0,0 +1,26 @@ +How to use U-Boot on PHYTEC phyBOARD-i.MX6UL-Segin +-------------------------------------------------- + +- Configure and build U-Boot for phyCORE-i.MX6UL: + + $ make mrproper + $ make phycore_pcl063_defconfig + $ make + + This will generate SPL and u-boot-dtb.img images. + +- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card: + + $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync + $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync + +- Jumper settings: + + JP1: Open: Boot from NAND + Closed: Boot from SD/MMC1 + +- Connect the Serial cable to UART0 and the PC for the console. + +- Insert the micro SD card in the board and power it up. + +- U-Boot messages should come up. diff --git a/board/phytec/pcl063/pcl063.c b/board/phytec/pcl063/pcl063.c new file mode 100644 index 0000000000..38b233d1b0 --- /dev/null +++ b/board/phytec/pcl063/pcl063.c @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Collabora Ltd. + * + * Based on board/ccv/xpress/xpress.c: + * Copyright (C) 2015-2016 Stefan Roese sr@denx.de + */ + +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <fsl_esdhc.h> +#include <linux/bitops.h> +#include <miiphy.h> +#include <netdev.h> +#include <usb.h> +#include <usb/ehci-ci.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart5_pads[] = { + MX6_PAD_UART5_TX_DATA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART5_RX_DATA__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); +} + +#ifdef CONFIG_NAND_MXS + +#define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP) + +#define NANDREADYPC MUX_PAD_CTRL(NAND_PAD_READY0_CTRL) + +static iomux_v3_cfg_t const gpmi_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | NANDREADYPC, +}; + +static void setup_gpmi_nand(void) +{ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + + setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); +} + +#endif /* CONFIG_NAND_MXS */ + +#ifdef CONFIG_FEC_MXC + +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \ + PAD_CTL_SRE_FAST) + +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_ODE) + +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); + imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); +} + +static int setup_fec(void) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + + ret = enable_fec_anatop_clock(0, ENET_50MHZ); + if (ret) + return ret; + + /* + * Use 50M anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + + ret = enable_fec_anatop_clock(1, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + /* + * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select + * 50 MHz RMII clock mode. + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif /* CONFIG_FEC_MXC */ + +int board_early_init_f(void) +{ + setup_iomux_uart(); + setup_iomux_fec(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + return 0; +} + +int checkboard(void) +{ + puts("Board: PHYTEC phyCORE-i.MX6UL\n"); + + return 0; +} diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c new file mode 100644 index 0000000000..d071e16576 --- /dev/null +++ b/board/phytec/pcl063/spl.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Collabora Ltd. + * + * Based on board/ccv/xpress/spl.c: + * Copyright (C) 2015-2016 Stefan Roese sr@denx.de + */ + +#include <common.h> +#include <spl.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/crm_regs.h> +#include <fsl_esdhc.h> + +/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */ + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x000c0000, +}; + +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000030, + .dram_odt1 = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpdgctrl0 = 0x41480148, + .p0_mprddlctl = 0x40403E42, + .p0_mpwrdlctl = 0x40405852, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, /* Bus size = 16bit */ + .cs_density = 18, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1, + .rtt_nom = 1, + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .pd_fast_exit = 1, + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 933, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 1, + .trcd = 1391, + .trcmin = 4791, + .trasmin = 3400, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); +} + +static void spl_dram_init(void) +{ + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +#ifdef CONFIG_FSL_ESDHC + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[] = { + { + .esdhc_base = USDHC1_BASE_ADDR, + .max_bus_width = 4, + }, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + +#endif /* CONFIG_FSL_ESDHC */ + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* Setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* Setup iomux and i2c */ + board_early_init_f(); + + /* Setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); +} diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig new file mode 100644 index 0000000000..bc6ebe68c8 --- /dev/null +++ b/configs/phycore_pcl063_defconfig @@ -0,0 +1,61 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_PCL063=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=8 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_CACHE=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_DEFAULT="gpmi-nand:4m(uboot),1m(env),-(root)" +CONFIG_CMD_UBI=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-phycore-segin" +CONFIG_DM_I2C_GPIO=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Phytec" +CONFIG_USB_GADGET_VENDOR_NUM=0x01b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h new file mode 100644 index 0000000000..d8856b3e5d --- /dev/null +++ b/include/configs/pcl063.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Collabora Ltd. + * + * Based on include/configs/xpress.h: + * Copyright (C) 2015-2016 Stefan Roese sr@denx.de + */ +#ifndef __PCL063_H +#define __PCL063_H + +#include <linux/sizes.h> +#include "mx6_common.h" + +/* SPL options */ +#include "imx6_spl.h" + +/* + * There is a bug in some i.MX6UL processors that results in the initial + * portion of OCRAM being unavailable when booting from (at least) an SD + * card. + * + * Tweak the SPL text base address to avoid this. + */ +#undef CONFIG_SPL_TEXT_BASE +#define CONFIG_SPL_TEXT_BASE 0x00909000 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +/* Console configs */ +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR + +/* I2C configs */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_256M + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_SIZE (16 << 10) +#define CONFIG_ENV_OFFSET (512 << 10) + +/* NAND */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_IMX_THERMAL + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200n8\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "fdt_addr_r=0x82000000\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x87100000\0" \ + "ramdisk_addr_r=0x82100000\0" \ + "scriptaddr=0x87000000\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(UBIFS, ubifs, 0) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +#endif /* __PCL063_H */
Hi Martyn,
Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on the PHYTEC phyCORE-i.MX6UL SOM (PCL063).
CPU: Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 44C Reset cause: POR Board: PHYTEC phyCORE-i.MX6UL I2C: ready DRAM: 256 MiB NAND: 512 MiB MMC: FSL_SDHC: 0 In: serial Out: serial Err: serial Net: FEC0
Working:
- Eth0
- i2C
I've noticed that you are using non DM I2C driver for IMX6Q. Was there any reason not to use it?
- MMC/SD
- NAND
- UART (1 & 5)
- USB (host & otg)
Signed-off-by: Martyn Welch martyn.welch@collabora.com
Changes in v3:
- Correct spelling of Phytec
- Remove unneeded license information
- Correct image name in documentation
- Correct whitespacing
- Enable SPL to boot from MMC
- Simplify defconfig, remove non-SPL build
Changes in v2:
- Switch to driver model
arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx6ul-pcl063.dtsi | 173 +++++++++++++++++++++ arch/arm/dts/imx6ul-phycore-segin.dts | 76 ++++++++++ arch/arm/mach-imx/mx6/Kconfig | 13 ++ board/phytec/pcl063/Kconfig | 12 ++ board/phytec/pcl063/MAINTAINERS | 8 + board/phytec/pcl063/Makefile | 7 + board/phytec/pcl063/README | 26 ++++ board/phytec/pcl063/pcl063.c | 206 ++++++++++++++++++++++++++ board/phytec/pcl063/spl.c | 160 ++++++++++++++++++++ configs/phycore_pcl063_defconfig | 61 ++++++++ include/configs/pcl063.h | 100 +++++++++++++ 12 files changed, 844 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx6ul-pcl063.dtsi create mode 100644 arch/arm/dts/imx6ul-phycore-segin.dts create mode 100644 board/phytec/pcl063/Kconfig create mode 100644 board/phytec/pcl063/MAINTAINERS create mode 100644 board/phytec/pcl063/Makefile create mode 100644 board/phytec/pcl063/README create mode 100644 board/phytec/pcl063/pcl063.c create mode 100644 board/phytec/pcl063/spl.c create mode 100644 configs/phycore_pcl063_defconfig create mode 100644 include/configs/pcl063.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 949ee472fc..68411623e5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -453,7 +453,8 @@ dtb-$(CONFIG_MX6UL) += \ imx6ul-isiot-nand.dtb \ imx6ul-opos6uldev.dtb \ imx6ul-14x14-evk.dtb \
- imx6ul-9x9-evk.dtb
- imx6ul-9x9-evk.dtb \
- imx6ul-phycore-segin.dtb
dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb
diff --git a/arch/arm/dts/imx6ul-pcl063.dtsi b/arch/arm/dts/imx6ul-pcl063.dtsi new file mode 100644 index 0000000000..24a6a47983 --- /dev/null +++ b/arch/arm/dts/imx6ul-pcl063.dtsi @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2018 Collabora Ltd.
- Based on dts[i] from Phytec barebox port:
- Copyright (C) 2016 PHYTEC Messtechnik GmbH
- Author: Christian Hemp c.hemp@phytec.de
- */
+/dts-v1/;
+#include "imx6ul.dtsi"
+/ {
- model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
- compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
- memory {
reg = <0x80000000 0x20000000>;- };
- chosen {
stdout-path = &uart1;- };
+};
+&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet1>;
- phy-mode = "rmii";
- phy-handle = <ðphy0>;
- status = "okay";
- mdio: mdio {
#address-cells = <1>;#size-cells = <0>;ethphy0: ethernet-phy@1 {reg = <1>;micrel,led-mode = <1>;};- };
+};
+&gpmi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpmi_nand>;
- nand-on-flash-bbt;
- fsl,no-blockmark-swap;
- status = "okay";
- #address-cells = <1>;
- #size-cells = <1>;
- partition@0 {
label = "uboot";reg = <0x0 0x400000>;- };
- partition@400000 {
label = "uboot-env";reg = <0x400000 0x100000>;- };
- partition@500000 {
label = "root";reg = <0x500000 0x0>;- };
+};
+&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
- sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
- status = "okay";
- eeprom@52 {
compatible = "cat,24c32";reg = <0x52>;- };
+};
+&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
+};
+&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
- bus-width = <0x4>;
- pinctrl-0 = <&pinctrl_usdhc1>;
- no-1-8-v;
- status = "okay";
+};
+&iomuxc {
- pinctrl-names = "default";
- pinctrl_enet1: enet1grp {
fsl,pins = <MX6UL_PAD_GPIO1_IO06__ENET1_MDIO0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0X1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>;- };
- pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B0x0b0b1
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B0x0b0b1
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B0x0b0b1
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B0x0b0b1
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA000x0b0b1
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA010x0b0b1
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA020x0b0b1
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA030x0b0b1
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA040x0b0b1
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA050x0b0b1
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA060x0b0b1
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA070x0b0b1
>;- };
- pinctrl_i2c1: i2cgrp {
fsl,pins = <MX6UL_PAD_UART4_TX_DATA__I2C1_SCL0x4001b8b0
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA0x4001b8b0
>;- };
- pinctrl_i2c1_gpio: i2c1grp_gpio {
fsl,pins = <MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0>;- };
- pinctrl_uart1: uart1grp {
fsl,pins = <MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX0x1b0b1
>;- };
- pinctrl_usdhc1: usdhc1grp {
fsl,pins = <MX6UL_PAD_SD1_CMD__USDHC1_CMD0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA00x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA10x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA20x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA30x17059
MX6UL_PAD_UART1_RTS_B__GPIO1_IO190x17059 +
>;- };
+}; diff --git a/arch/arm/dts/imx6ul-phycore-segin.dts b/arch/arm/dts/imx6ul-phycore-segin.dts new file mode 100644 index 0000000000..a46012e2b4 --- /dev/null +++ b/arch/arm/dts/imx6ul-phycore-segin.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2018 Collabora Ltd.
- Based on dts[i] from Phytec barebox port:
- Copyright (C) 2016 PHYTEC Messtechnik GmbH
- Author: Christian Hemp c.hemp@phytec.de
- The code contained herein is licensed under the GNU General Public
- License. You may obtain a copy of the GNU General Public License
- Version 2 or later at the following locations:
- */
+/dts-v1/;
+#include "imx6ul-pcl063.dtsi"
+/ {
- model = "Phytec phyBOARD-i.MX6UL-Segin SBC";
- compatible = "phytec,phyboard-imx6ul-segin",
"phytec,imx6ul-pcl063",
"fsl,imx6ul";+};
+&i2c1 {
- i2c_rtc: rtc@68 {
compatible = "microcrystal,rv4162";reg = <0x68>;status = "okay";- };
+};
+&uart5 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart5>;
- uart-has-rtscts;
- status = "okay";
+};
+&usbotg1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb_otg1_id>;
- dr_mode = "otg";
- srp-disable;
- hnp-disable;
- adp-disable;
- status = "okay";
+};
+&usbotg2 {
- dr_mode = "host";
- disable-over-current;
- status = "okay";
+};
+&iomuxc {
- pinctrl-names = "default";
- pinctrl_uart5: uart5grp {
fsl,pins = <MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX0x1b0b1
MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX0x1b0b1
MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS0x1b0b1
MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS0x1b0b1
>;- };
- pinctrl_usb_otg1_id: usbotg1idgrp {
fsl,pins = <MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID0x17059
>;- };
+}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 06c25bae36..e253f495c5 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -428,6 +428,18 @@ config TARGET_PFLA02 select MX6QDL select SUPPORT_SPL
+config TARGET_PCL063
- bool "PHYTEC PCL063 (phyCORE-i.MX6UL)"
- select MX6UL
- select DM
- select DM_ETH
- select DM_GPIO
- select DM_I2C
- select DM_MMC
- select DM_SERIAL
- select DM_THERMAL
- select SUPPORT_SPL
config TARGET_SECOMX6 bool "secomx6 boards"
@@ -550,6 +562,7 @@ source "board/freescale/mx6ullevk/Kconfig" source "board/grinn/liteboard/Kconfig" source "board/phytec/pcm058/Kconfig" source "board/phytec/pfla02/Kconfig" +source "board/phytec/pcl063/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/kosagi/novena/Kconfig" source "board/samtec/vining_2000/Kconfig" diff --git a/board/phytec/pcl063/Kconfig b/board/phytec/pcl063/Kconfig new file mode 100644 index 0000000000..977db70f64 --- /dev/null +++ b/board/phytec/pcl063/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PCL063
+config SYS_BOARD
- default "pcl063"
+config SYS_VENDOR
- default "phytec"
+config SYS_CONFIG_NAME
- default "pcl063"
+endif diff --git a/board/phytec/pcl063/MAINTAINERS b/board/phytec/pcl063/MAINTAINERS new file mode 100644 index 0000000000..c65a951f3d --- /dev/null +++ b/board/phytec/pcl063/MAINTAINERS @@ -0,0 +1,8 @@ +PCL063 BOARD +M: Martyn Welch martyn.welch@collabora.com +S: Maintained +F: arch/arm/dts/imx6ul-pcl063.dtsi +F: arch/arm/dts/imx6ul-phycore-segin.dts +F: board/phytec/pcl063/ +F: configs/phycore_pcl063_defconfig +F: include/configs/pcl063.h diff --git a/board/phytec/pcl063/Makefile b/board/phytec/pcl063/Makefile new file mode 100644 index 0000000000..53c73c9b08 --- /dev/null +++ b/board/phytec/pcl063/Makefile @@ -0,0 +1,7 @@ +# Copyright (C) 2018 Collabora Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := pcl063.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/phytec/pcl063/README b/board/phytec/pcl063/README new file mode 100644 index 0000000000..be83bdb0d8 --- /dev/null +++ b/board/phytec/pcl063/README @@ -0,0 +1,26 @@ +How to use U-Boot on PHYTEC phyBOARD-i.MX6UL-Segin +--------------------------------------------------
+- Configure and build U-Boot for phyCORE-i.MX6UL:
- $ make mrproper
- $ make phycore_pcl063_defconfig
- $ make
- This will generate SPL and u-boot-dtb.img images.
+- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card: +
- $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
- $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+- Jumper settings:
- JP1: Open: Boot from NAND
Closed: Boot from SD/MMC1+- Connect the Serial cable to UART0 and the PC for the console.
+- Insert the micro SD card in the board and power it up.
+- U-Boot messages should come up. diff --git a/board/phytec/pcl063/pcl063.c b/board/phytec/pcl063/pcl063.c new file mode 100644 index 0000000000..38b233d1b0 --- /dev/null +++ b/board/phytec/pcl063/pcl063.c @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2018 Collabora Ltd.
- Based on board/ccv/xpress/xpress.c:
- Copyright (C) 2015-2016 Stefan Roese sr@denx.de
- */
+#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <fsl_esdhc.h> +#include <linux/bitops.h> +#include <miiphy.h> +#include <netdev.h> +#include <usb.h> +#include <usb/ehci-ci.h>
+DECLARE_GLOBAL_DATA_PTR;
+int dram_init(void) +{
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
PHYS_SDRAM_SIZE); +
- return 0;
+}
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \PAD_CTL_HYS)+static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_UART1_TX_DATA__UART1_DCE_TX |
MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_UART1_RX_DATA__UART1_DCE_RX |
MUX_PAD_CTRL(UART_PAD_CTRL), +};
+static iomux_v3_cfg_t const uart5_pads[] = {
- MX6_PAD_UART5_TX_DATA__UART5_DCE_TX |
MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_UART5_RX_DATA__UART5_DCE_RX |
MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_GPIO1_IO09__UART5_DCE_CTS |
MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_GPIO1_IO08__UART5_DCE_RTS |
MUX_PAD_CTRL(UART_PAD_CTRL), +};
+static void setup_iomux_uart(void) +{
- imx_iomux_v3_setup_multiple_pads(uart1_pads,
ARRAY_SIZE(uart1_pads));
- imx_iomux_v3_setup_multiple_pads(uart5_pads,
ARRAY_SIZE(uart5_pads)); +}
+#ifdef CONFIG_NAND_MXS
+#define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP)
+#define NANDREADYPC MUX_PAD_CTRL(NAND_PAD_READY0_CTRL)
+static iomux_v3_cfg_t const gpmi_pads[] = {
- MX6_PAD_NAND_DATA00__RAWNAND_DATA00 |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_DATA01__RAWNAND_DATA01 |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_DATA02__RAWNAND_DATA02 |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_DATA03__RAWNAND_DATA03 |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_DATA04__RAWNAND_DATA04 |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_DATA05__RAWNAND_DATA05 |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_DATA06__RAWNAND_DATA06 |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_DATA07__RAWNAND_DATA07 |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_CLE__RAWNAND_CLE |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_ALE__RAWNAND_ALE |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_RE_B__RAWNAND_RE_B |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_WE_B__RAWNAND_WE_B |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_READY_B__RAWNAND_READY_B | NANDREADYPC,
+};
+static void setup_gpmi_nand(void) +{
- imx_iomux_v3_setup_multiple_pads(gpmi_pads,
ARRAY_SIZE(gpmi_pads)); +
- setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));+}
+#endif /* CONFIG_NAND_MXS */
+#ifdef CONFIG_FEC_MXC
+#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm |\
PAD_CTL_SRE_FAST)+#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | \PAD_CTL_ODE)+static iomux_v3_cfg_t const fec1_pads[] = {
- MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
- MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_EN__ENET1_TX_EN |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 |
MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
- MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_RX_ER__ENET1_RX_ER |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_RX_EN__ENET1_RX_EN |
MUX_PAD_CTRL(ENET_PAD_CTRL), +};
+static iomux_v3_cfg_t const fec2_pads[] = {
- MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET2_TX_EN__ENET2_TX_EN |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 |
MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
- MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET2_RX_ER__ENET2_RX_ER |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET2_RX_EN__ENET2_RX_EN |
MUX_PAD_CTRL(ENET_PAD_CTRL), +};
+static void setup_iomux_fec(void) +{
- imx_iomux_v3_setup_multiple_pads(fec1_pads,
ARRAY_SIZE(fec1_pads));
- imx_iomux_v3_setup_multiple_pads(fec2_pads,
ARRAY_SIZE(fec2_pads)); +}
+static int setup_fec(void) +{
- struct iomuxc *const iomuxc_regs = (struct iomuxc
*)IOMUXC_BASE_ADDR;
- int ret;
- /*
* Use 50M anatop loopback REF_CLK1 for ENET1,* clear gpr1[13], set gpr1[17].*/- clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);- ret = enable_fec_anatop_clock(0, ENET_50MHZ);
- if (ret)
return ret;- /*
* Use 50M anatop loopback REF_CLK2 for ENET2,* clear gpr1[14], set gpr1[18].*/- clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);- ret = enable_fec_anatop_clock(1, ENET_50MHZ);
- if (ret)
return ret;- enable_enet_clk(1);
- return 0;
+}
+int board_phy_config(struct phy_device *phydev) +{
- /*
* Defaults + Enable status LEDs (LED1: Activity, LED0:Link) & select
* 50 MHz RMII clock mode.*/- phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
- if (phydev->drv->config)
phydev->drv->config(phydev);- return 0;
+} +#endif /* CONFIG_FEC_MXC */
+int board_early_init_f(void) +{
- setup_iomux_uart();
- setup_iomux_fec();
- return 0;
+}
+int board_init(void) +{
- /* Address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+#ifdef CONFIG_NAND_MXS
- setup_gpmi_nand();
+#endif
+#ifdef CONFIG_FEC_MXC
- setup_fec();
+#endif
- return 0;
+}
+int checkboard(void) +{
- puts("Board: PHYTEC phyCORE-i.MX6UL\n");
- return 0;
+} diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c new file mode 100644 index 0000000000..d071e16576 --- /dev/null +++ b/board/phytec/pcl063/spl.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2018 Collabora Ltd.
- Based on board/ccv/xpress/spl.c:
- Copyright (C) 2015-2016 Stefan Roese sr@denx.de
- */
+#include <common.h> +#include <spl.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/crm_regs.h> +#include <fsl_esdhc.h>
+/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */ + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
- .grp_addds = 0x00000030,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_b0ds = 0x00000030,
- .grp_ctlds = 0x00000030,
- .grp_b1ds = 0x00000030,
- .grp_ddrpke = 0x00000000,
- .grp_ddrmode = 0x00020000,
- .grp_ddr_type = 0x000c0000,
+};
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
- .dram_dqm0 = 0x00000030,
- .dram_dqm1 = 0x00000030,
- .dram_ras = 0x00000030,
- .dram_cas = 0x00000030,
- .dram_odt0 = 0x00000030,
- .dram_odt1 = 0x00000030,
- .dram_sdba2 = 0x00000000,
- .dram_sdclk_0 = 0x00000030,
- .dram_sdqs0 = 0x00000030,
- .dram_sdqs1 = 0x00000030,
- .dram_reset = 0x00000030,
+};
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
- .p0_mpwldectrl0 = 0x00000000,
- .p0_mpdgctrl0 = 0x41480148,
- .p0_mprddlctl = 0x40403E42,
- .p0_mpwrdlctl = 0x40405852,
+};
+struct mx6_ddr_sysinfo ddr_sysinfo = {
- .dsize = 0, /* Bus size = 16bit */
- .cs_density = 18,
- .ncs = 1,
- .cs1_mirror = 0,
- .rtt_wr = 1,
- .rtt_nom = 1,
- .walat = 1, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working
mode */
- .bi_on = 1, /* Bank interleaving enabled */
- .pd_fast_exit = 1,
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC
default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC
default) */
- .ddr_type = DDR_TYPE_DDR3,
- .refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 7, /* 8 refresh commands per refresh
cycle */ +};
+static struct mx6_ddr3_cfg mem_ddr = {
- .mem_speed = 933,
- .density = 4,
- .width = 16,
- .banks = 8,
- .rowaddr = 14,
- .coladdr = 10,
- .pagesz = 1,
- .trcd = 1391,
- .trcmin = 4791,
- .trasmin = 3400,
+};
+static void ccgr_init(void) +{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg
*)CCM_BASE_ADDR; +
- writel(0xFFFFFFFF, &ccm->CCGR0);
- writel(0xFFFFFFFF, &ccm->CCGR1);
- writel(0xFFFFFFFF, &ccm->CCGR2);
- writel(0xFFFFFFFF, &ccm->CCGR3);
- writel(0xFFFFFFFF, &ccm->CCGR4);
- writel(0xFFFFFFFF, &ccm->CCGR5);
- writel(0xFFFFFFFF, &ccm->CCGR6);
+}
+static void spl_dram_init(void) +{
- mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs,
&mx6_grp_ioregs);
- mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+#ifdef CONFIG_FSL_ESDHC
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \PAD_CTL_HYS)+static iomux_v3_cfg_t const usdhc1_pads[] = {
- MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA0__USDHC1_DATA0 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA1__USDHC1_DATA1 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA2__USDHC1_DATA2 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA3__USDHC1_DATA3 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_UART1_RTS_B__USDHC1_CD_B |
MUX_PAD_CTRL(USDHC_PAD_CTRL), +};
+static struct fsl_esdhc_cfg usdhc_cfg[] = {
- {
.esdhc_base = USDHC1_BASE_ADDR,.max_bus_width = 4,- },
+};
+int board_mmc_getcd(struct mmc *mmc) +{
- return 1;
+}
+int board_mmc_init(bd_t *bis) +{
- imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
ARRAY_SIZE(usdhc1_pads));
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif /* CONFIG_FSL_ESDHC */
+void board_init_f(ulong dummy) +{
- ccgr_init();
- /* Setup AIPS and disable watchdog */
- arch_cpu_init();
- /* Setup iomux and i2c */
- board_early_init_f();
- /* Setup GP timer */
- timer_init();
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
- /* DDR initialization */
- spl_dram_init();
+} diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig new file mode 100644 index 0000000000..bc6ebe68c8 --- /dev/null +++ b/configs/phycore_pcl063_defconfig @@ -0,0 +1,61 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_PCL063=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=8 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_CACHE=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_DEFAULT="gpmi-nand:4m(uboot),1m(env),-(root)" +CONFIG_CMD_UBI=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-phycore-segin" +CONFIG_DM_I2C_GPIO=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Phytec" +CONFIG_USB_GADGET_VENDOR_NUM=0x01b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h new file mode 100644 index 0000000000..d8856b3e5d --- /dev/null +++ b/include/configs/pcl063.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2018 Collabora Ltd.
- Based on include/configs/xpress.h:
- Copyright (C) 2015-2016 Stefan Roese sr@denx.de
- */
+#ifndef __PCL063_H +#define __PCL063_H
+#include <linux/sizes.h> +#include "mx6_common.h"
+/* SPL options */ +#include "imx6_spl.h"
+/*
- There is a bug in some i.MX6UL processors that results in the
initial
- portion of OCRAM being unavailable when booting from (at least)
an SD
- card.
- Tweak the SPL text base address to avoid this.
- */
+#undef CONFIG_SPL_TEXT_BASE +#define CONFIG_SPL_TEXT_BASE 0x00909000
+/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
+/* Console configs */ +#define CONFIG_MXC_UART_BASE UART1_BASE
+/* MMC Configs */ +#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+/* I2C configs */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif
+/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000
+/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_256M
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+#define CONFIG_ENV_SIZE (16 << 10) +#define CONFIG_ENV_OFFSET (512 << 10)
+/* NAND */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000
+/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_IMX_THERMAL
+#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=ttymxc0,115200n8\0" \
- "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- "fdt_addr_r=0x82000000\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "kernel_addr_r=0x81000000\0" \
- "pxefile_addr_r=0x87100000\0" \
- "ramdisk_addr_r=0x82100000\0" \
- "scriptaddr=0x87000000\0" \
- BOOTENV
+#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(UBIFS, ubifs, 0) \
- func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#endif /* __PCL063_H */
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
On Mon, 2018-12-10 at 12:49 +0100, Lukasz Majewski wrote:
Hi Martyn,
Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on the PHYTEC phyCORE-i.MX6UL SOM (PCL063).
CPU: Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 44C Reset cause: POR Board: PHYTEC phyCORE-i.MX6UL I2C: ready DRAM: 256 MiB NAND: 512 MiB MMC: FSL_SDHC: 0 In: serial Out: serial Err: serial Net: FEC0
Working:
- Eth0
- i2C
I've noticed that you are using non DM I2C driver for IMX6Q. Was there any reason not to use it?
I didn't think I was, though now that you mention it I can see I've left the defines in the board header. I'll remove them.
Martyn
- MMC/SD
- NAND
- UART (1 & 5)
- USB (host & otg)
Signed-off-by: Martyn Welch martyn.welch@collabora.com
Changes in v3:
- Correct spelling of Phytec
- Remove unneeded license information
- Correct image name in documentation
- Correct whitespacing
- Enable SPL to boot from MMC
- Simplify defconfig, remove non-SPL build
Changes in v2:
- Switch to driver model
arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx6ul-pcl063.dtsi | 173 +++++++++++++++++++++ arch/arm/dts/imx6ul-phycore-segin.dts | 76 ++++++++++ arch/arm/mach-imx/mx6/Kconfig | 13 ++ board/phytec/pcl063/Kconfig | 12 ++ board/phytec/pcl063/MAINTAINERS | 8 + board/phytec/pcl063/Makefile | 7 + board/phytec/pcl063/README | 26 ++++ board/phytec/pcl063/pcl063.c | 206 ++++++++++++++++++++++++++ board/phytec/pcl063/spl.c | 160 ++++++++++++++++++++ configs/phycore_pcl063_defconfig | 61 ++++++++ include/configs/pcl063.h | 100 +++++++++++++ 12 files changed, 844 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx6ul-pcl063.dtsi create mode 100644 arch/arm/dts/imx6ul-phycore-segin.dts create mode 100644 board/phytec/pcl063/Kconfig create mode 100644 board/phytec/pcl063/MAINTAINERS create mode 100644 board/phytec/pcl063/Makefile create mode 100644 board/phytec/pcl063/README create mode 100644 board/phytec/pcl063/pcl063.c create mode 100644 board/phytec/pcl063/spl.c create mode 100644 configs/phycore_pcl063_defconfig create mode 100644 include/configs/pcl063.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 949ee472fc..68411623e5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -453,7 +453,8 @@ dtb-$(CONFIG_MX6UL) += \ imx6ul-isiot-nand.dtb \ imx6ul-opos6uldev.dtb \ imx6ul-14x14-evk.dtb \
- imx6ul-9x9-evk.dtb
- imx6ul-9x9-evk.dtb \
- imx6ul-phycore-segin.dtb
dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb
diff --git a/arch/arm/dts/imx6ul-pcl063.dtsi b/arch/arm/dts/imx6ul-pcl063.dtsi new file mode 100644 index 0000000000..24a6a47983 --- /dev/null +++ b/arch/arm/dts/imx6ul-pcl063.dtsi @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2018 Collabora Ltd.
- Based on dts[i] from Phytec barebox port:
- Copyright (C) 2016 PHYTEC Messtechnik GmbH
- Author: Christian Hemp c.hemp@phytec.de
- */
+/dts-v1/;
+#include "imx6ul.dtsi"
+/ {
- model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
- compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
- memory {
reg = <0x80000000 0x20000000>;- };
- chosen {
stdout-path = &uart1;- };
+};
+&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet1>;
- phy-mode = "rmii";
- phy-handle = <ðphy0>;
- status = "okay";
- mdio: mdio {
#address-cells = <1>;#size-cells = <0>;ethphy0: ethernet-phy@1 {reg = <1>;micrel,led-mode = <1>;};- };
+};
+&gpmi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpmi_nand>;
- nand-on-flash-bbt;
- fsl,no-blockmark-swap;
- status = "okay";
- #address-cells = <1>;
- #size-cells = <1>;
- partition@0 {
label = "uboot";reg = <0x0 0x400000>;- };
- partition@400000 {
label = "uboot-env";reg = <0x400000 0x100000>;- };
- partition@500000 {
label = "root";reg = <0x500000 0x0>;- };
+};
+&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
- sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
- status = "okay";
- eeprom@52 {
compatible = "cat,24c32";reg = <0x52>;- };
+};
+&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
+};
+&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
- bus-width = <0x4>;
- pinctrl-0 = <&pinctrl_usdhc1>;
- no-1-8-v;
- status = "okay";
+};
+&iomuxc {
- pinctrl-names = "default";
- pinctrl_enet1: enet1grp {
fsl,pins = <MX6UL_PAD_GPIO1_IO06__ENET1_MDIO0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0X1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>;- };
- pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B0x0b0b1
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B0x0b0b1
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B0x0b0b1
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B0x0b0b1
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA000x0b0b1
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA010x0b0b1
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA020x0b0b1
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA030x0b0b1
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA040x0b0b1
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA050x0b0b1
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA060x0b0b1
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA070x0b0b1
>;- };
- pinctrl_i2c1: i2cgrp {
fsl,pins = <MX6UL_PAD_UART4_TX_DATA__I2C1_SCL0x4001b8b0
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA0x4001b8b0
>;- };
- pinctrl_i2c1_gpio: i2c1grp_gpio {
fsl,pins = <MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0>;- };
- pinctrl_uart1: uart1grp {
fsl,pins = <MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX0x1b0b1
>;- };
- pinctrl_usdhc1: usdhc1grp {
fsl,pins = <MX6UL_PAD_SD1_CMD__USDHC1_CMD0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA00x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA10x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA20x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA30x17059
MX6UL_PAD_UART1_RTS_B__GPIO1_IO190x17059 +
>;- };
+}; diff --git a/arch/arm/dts/imx6ul-phycore-segin.dts b/arch/arm/dts/imx6ul-phycore-segin.dts new file mode 100644 index 0000000000..a46012e2b4 --- /dev/null +++ b/arch/arm/dts/imx6ul-phycore-segin.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2018 Collabora Ltd.
- Based on dts[i] from Phytec barebox port:
- Copyright (C) 2016 PHYTEC Messtechnik GmbH
- Author: Christian Hemp c.hemp@phytec.de
- The code contained herein is licensed under the GNU General
Public
- License. You may obtain a copy of the GNU General Public
License
- Version 2 or later at the following locations:
- */
+/dts-v1/;
+#include "imx6ul-pcl063.dtsi"
+/ {
- model = "Phytec phyBOARD-i.MX6UL-Segin SBC";
- compatible = "phytec,phyboard-imx6ul-segin",
"phytec,imx6ul-pcl063",
"fsl,imx6ul";+};
+&i2c1 {
- i2c_rtc: rtc@68 {
compatible = "microcrystal,rv4162";reg = <0x68>;status = "okay";- };
+};
+&uart5 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart5>;
- uart-has-rtscts;
- status = "okay";
+};
+&usbotg1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb_otg1_id>;
- dr_mode = "otg";
- srp-disable;
- hnp-disable;
- adp-disable;
- status = "okay";
+};
+&usbotg2 {
- dr_mode = "host";
- disable-over-current;
- status = "okay";
+};
+&iomuxc {
- pinctrl-names = "default";
- pinctrl_uart5: uart5grp {
fsl,pins = <MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX0x1b0b1
MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX0x1b0b1
MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS0x1b0b1
MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS0x1b0b1
>;- };
- pinctrl_usb_otg1_id: usbotg1idgrp {
fsl,pins = <MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID0x17059
>;- };
+}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 06c25bae36..e253f495c5 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -428,6 +428,18 @@ config TARGET_PFLA02 select MX6QDL select SUPPORT_SPL
+config TARGET_PCL063
- bool "PHYTEC PCL063 (phyCORE-i.MX6UL)"
- select MX6UL
- select DM
- select DM_ETH
- select DM_GPIO
- select DM_I2C
- select DM_MMC
- select DM_SERIAL
- select DM_THERMAL
- select SUPPORT_SPL
config TARGET_SECOMX6 bool "secomx6 boards"
@@ -550,6 +562,7 @@ source "board/freescale/mx6ullevk/Kconfig" source "board/grinn/liteboard/Kconfig" source "board/phytec/pcm058/Kconfig" source "board/phytec/pfla02/Kconfig" +source "board/phytec/pcl063/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/kosagi/novena/Kconfig" source "board/samtec/vining_2000/Kconfig" diff --git a/board/phytec/pcl063/Kconfig b/board/phytec/pcl063/Kconfig new file mode 100644 index 0000000000..977db70f64 --- /dev/null +++ b/board/phytec/pcl063/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PCL063
+config SYS_BOARD
- default "pcl063"
+config SYS_VENDOR
- default "phytec"
+config SYS_CONFIG_NAME
- default "pcl063"
+endif diff --git a/board/phytec/pcl063/MAINTAINERS b/board/phytec/pcl063/MAINTAINERS new file mode 100644 index 0000000000..c65a951f3d --- /dev/null +++ b/board/phytec/pcl063/MAINTAINERS @@ -0,0 +1,8 @@ +PCL063 BOARD +M: Martyn Welch martyn.welch@collabora.com +S: Maintained +F: arch/arm/dts/imx6ul-pcl063.dtsi +F: arch/arm/dts/imx6ul-phycore-segin.dts +F: board/phytec/pcl063/ +F: configs/phycore_pcl063_defconfig +F: include/configs/pcl063.h diff --git a/board/phytec/pcl063/Makefile b/board/phytec/pcl063/Makefile new file mode 100644 index 0000000000..53c73c9b08 --- /dev/null +++ b/board/phytec/pcl063/Makefile @@ -0,0 +1,7 @@ +# Copyright (C) 2018 Collabora Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := pcl063.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/phytec/pcl063/README b/board/phytec/pcl063/README new file mode 100644 index 0000000000..be83bdb0d8 --- /dev/null +++ b/board/phytec/pcl063/README @@ -0,0 +1,26 @@ +How to use U-Boot on PHYTEC phyBOARD-i.MX6UL-Segin +--------------------------------------------------
+- Configure and build U-Boot for phyCORE-i.MX6UL:
- $ make mrproper
- $ make phycore_pcl063_defconfig
- $ make
- This will generate SPL and u-boot-dtb.img images.
+- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card: +
- $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
- $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69;
sync
+- Jumper settings:
- JP1: Open: Boot from NAND
Closed: Boot from SD/MMC1+- Connect the Serial cable to UART0 and the PC for the console.
+- Insert the micro SD card in the board and power it up.
+- U-Boot messages should come up. diff --git a/board/phytec/pcl063/pcl063.c b/board/phytec/pcl063/pcl063.c new file mode 100644 index 0000000000..38b233d1b0 --- /dev/null +++ b/board/phytec/pcl063/pcl063.c @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2018 Collabora Ltd.
- Based on board/ccv/xpress/xpress.c:
- Copyright (C) 2015-2016 Stefan Roese sr@denx.de
- */
+#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <fsl_esdhc.h> +#include <linux/bitops.h> +#include <miiphy.h> +#include <netdev.h> +#include <usb.h> +#include <usb/ehci-ci.h>
+DECLARE_GLOBAL_DATA_PTR;
+int dram_init(void) +{
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
PHYS_SDRAM_SIZE); +
- return 0;
+}
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \PAD_CTL_HYS)+static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_UART1_TX_DATA__UART1_DCE_TX |
MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_UART1_RX_DATA__UART1_DCE_RX |
MUX_PAD_CTRL(UART_PAD_CTRL), +};
+static iomux_v3_cfg_t const uart5_pads[] = {
- MX6_PAD_UART5_TX_DATA__UART5_DCE_TX |
MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_UART5_RX_DATA__UART5_DCE_RX |
MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_GPIO1_IO09__UART5_DCE_CTS |
MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_GPIO1_IO08__UART5_DCE_RTS |
MUX_PAD_CTRL(UART_PAD_CTRL), +};
+static void setup_iomux_uart(void) +{
- imx_iomux_v3_setup_multiple_pads(uart1_pads,
ARRAY_SIZE(uart1_pads));
- imx_iomux_v3_setup_multiple_pads(uart5_pads,
ARRAY_SIZE(uart5_pads)); +}
+#ifdef CONFIG_NAND_MXS
+#define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP)
+#define NANDREADYPC MUX_PAD_CTRL(NAND_PAD_READY0_CTRL)
+static iomux_v3_cfg_t const gpmi_pads[] = {
- MX6_PAD_NAND_DATA00__RAWNAND_DATA00 |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_DATA01__RAWNAND_DATA01 |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_DATA02__RAWNAND_DATA02 |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_DATA03__RAWNAND_DATA03 |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_DATA04__RAWNAND_DATA04 |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_DATA05__RAWNAND_DATA05 |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_DATA06__RAWNAND_DATA06 |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_DATA07__RAWNAND_DATA07 |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_CLE__RAWNAND_CLE |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_ALE__RAWNAND_ALE |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_RE_B__RAWNAND_RE_B |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_WE_B__RAWNAND_WE_B |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B |
MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_READY_B__RAWNAND_READY_B | NANDREADYPC,
+};
+static void setup_gpmi_nand(void) +{
- imx_iomux_v3_setup_multiple_pads(gpmi_pads,
ARRAY_SIZE(gpmi_pads)); +
- setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));+}
+#endif /* CONFIG_NAND_MXS */
+#ifdef CONFIG_FEC_MXC
+#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm |\
PAD_CTL_SRE_FAST)+#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | \PAD_CTL_ODE)+static iomux_v3_cfg_t const fec1_pads[] = {
- MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
- MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_EN__ENET1_TX_EN |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 |
MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
- MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_RX_ER__ENET1_RX_ER |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_RX_EN__ENET1_RX_EN |
MUX_PAD_CTRL(ENET_PAD_CTRL), +};
+static iomux_v3_cfg_t const fec2_pads[] = {
- MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET2_TX_EN__ENET2_TX_EN |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 |
MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
- MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET2_RX_ER__ENET2_RX_ER |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET2_RX_EN__ENET2_RX_EN |
MUX_PAD_CTRL(ENET_PAD_CTRL), +};
+static void setup_iomux_fec(void) +{
- imx_iomux_v3_setup_multiple_pads(fec1_pads,
ARRAY_SIZE(fec1_pads));
- imx_iomux_v3_setup_multiple_pads(fec2_pads,
ARRAY_SIZE(fec2_pads)); +}
+static int setup_fec(void) +{
- struct iomuxc *const iomuxc_regs = (struct iomuxc
*)IOMUXC_BASE_ADDR;
- int ret;
- /*
* Use 50M anatop loopback REF_CLK1 for ENET1,* clear gpr1[13], set gpr1[17].*/- clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);- ret = enable_fec_anatop_clock(0, ENET_50MHZ);
- if (ret)
return ret;- /*
* Use 50M anatop loopback REF_CLK2 for ENET2,* clear gpr1[14], set gpr1[18].*/- clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);- ret = enable_fec_anatop_clock(1, ENET_50MHZ);
- if (ret)
return ret;- enable_enet_clk(1);
- return 0;
+}
+int board_phy_config(struct phy_device *phydev) +{
- /*
* Defaults + Enable status LEDs (LED1: Activity, LED0:Link) & select
* 50 MHz RMII clock mode.*/- phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
- if (phydev->drv->config)
phydev->drv->config(phydev);- return 0;
+} +#endif /* CONFIG_FEC_MXC */
+int board_early_init_f(void) +{
- setup_iomux_uart();
- setup_iomux_fec();
- return 0;
+}
+int board_init(void) +{
- /* Address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+#ifdef CONFIG_NAND_MXS
- setup_gpmi_nand();
+#endif
+#ifdef CONFIG_FEC_MXC
- setup_fec();
+#endif
- return 0;
+}
+int checkboard(void) +{
- puts("Board: PHYTEC phyCORE-i.MX6UL\n");
- return 0;
+} diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c new file mode 100644 index 0000000000..d071e16576 --- /dev/null +++ b/board/phytec/pcl063/spl.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2018 Collabora Ltd.
- Based on board/ccv/xpress/spl.c:
- Copyright (C) 2015-2016 Stefan Roese sr@denx.de
- */
+#include <common.h> +#include <spl.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/crm_regs.h> +#include <fsl_esdhc.h>
+/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */ + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
- .grp_addds = 0x00000030,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_b0ds = 0x00000030,
- .grp_ctlds = 0x00000030,
- .grp_b1ds = 0x00000030,
- .grp_ddrpke = 0x00000000,
- .grp_ddrmode = 0x00020000,
- .grp_ddr_type = 0x000c0000,
+};
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
- .dram_dqm0 = 0x00000030,
- .dram_dqm1 = 0x00000030,
- .dram_ras = 0x00000030,
- .dram_cas = 0x00000030,
- .dram_odt0 = 0x00000030,
- .dram_odt1 = 0x00000030,
- .dram_sdba2 = 0x00000000,
- .dram_sdclk_0 = 0x00000030,
- .dram_sdqs0 = 0x00000030,
- .dram_sdqs1 = 0x00000030,
- .dram_reset = 0x00000030,
+};
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
- .p0_mpwldectrl0 = 0x00000000,
- .p0_mpdgctrl0 = 0x41480148,
- .p0_mprddlctl = 0x40403E42,
- .p0_mpwrdlctl = 0x40405852,
+};
+struct mx6_ddr_sysinfo ddr_sysinfo = {
- .dsize = 0, /* Bus size = 16bit */
- .cs_density = 18,
- .ncs = 1,
- .cs1_mirror = 0,
- .rtt_wr = 1,
- .rtt_nom = 1,
- .walat = 1, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working
mode */
- .bi_on = 1, /* Bank interleaving enabled */
- .pd_fast_exit = 1,
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC
default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC
default) */
- .ddr_type = DDR_TYPE_DDR3,
- .refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 7, /* 8 refresh commands per refresh
cycle */ +};
+static struct mx6_ddr3_cfg mem_ddr = {
- .mem_speed = 933,
- .density = 4,
- .width = 16,
- .banks = 8,
- .rowaddr = 14,
- .coladdr = 10,
- .pagesz = 1,
- .trcd = 1391,
- .trcmin = 4791,
- .trasmin = 3400,
+};
+static void ccgr_init(void) +{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg
*)CCM_BASE_ADDR; +
- writel(0xFFFFFFFF, &ccm->CCGR0);
- writel(0xFFFFFFFF, &ccm->CCGR1);
- writel(0xFFFFFFFF, &ccm->CCGR2);
- writel(0xFFFFFFFF, &ccm->CCGR3);
- writel(0xFFFFFFFF, &ccm->CCGR4);
- writel(0xFFFFFFFF, &ccm->CCGR5);
- writel(0xFFFFFFFF, &ccm->CCGR6);
+}
+static void spl_dram_init(void) +{
- mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs,
&mx6_grp_ioregs);
- mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+#ifdef CONFIG_FSL_ESDHC
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \PAD_CTL_HYS)+static iomux_v3_cfg_t const usdhc1_pads[] = {
- MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA0__USDHC1_DATA0 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA1__USDHC1_DATA1 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA2__USDHC1_DATA2 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA3__USDHC1_DATA3 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_UART1_RTS_B__USDHC1_CD_B |
MUX_PAD_CTRL(USDHC_PAD_CTRL), +};
+static struct fsl_esdhc_cfg usdhc_cfg[] = {
- {
.esdhc_base = USDHC1_BASE_ADDR,.max_bus_width = 4,- },
+};
+int board_mmc_getcd(struct mmc *mmc) +{
- return 1;
+}
+int board_mmc_init(bd_t *bis) +{
- imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
ARRAY_SIZE(usdhc1_pads));
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif /* CONFIG_FSL_ESDHC */
+void board_init_f(ulong dummy) +{
- ccgr_init();
- /* Setup AIPS and disable watchdog */
- arch_cpu_init();
- /* Setup iomux and i2c */
- board_early_init_f();
- /* Setup GP timer */
- timer_init();
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
- /* DDR initialization */
- spl_dram_init();
+} diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig new file mode 100644 index 0000000000..bc6ebe68c8 --- /dev/null +++ b/configs/phycore_pcl063_defconfig @@ -0,0 +1,61 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_PCL063=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=8 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_CACHE=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_DEFAULT="gpmi-nand:4m(uboot),1m(env),-(root)" +CONFIG_CMD_UBI=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-phycore-segin" +CONFIG_DM_I2C_GPIO=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Phytec" +CONFIG_USB_GADGET_VENDOR_NUM=0x01b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h new file mode 100644 index 0000000000..d8856b3e5d --- /dev/null +++ b/include/configs/pcl063.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2018 Collabora Ltd.
- Based on include/configs/xpress.h:
- Copyright (C) 2015-2016 Stefan Roese sr@denx.de
- */
+#ifndef __PCL063_H +#define __PCL063_H
+#include <linux/sizes.h> +#include "mx6_common.h"
+/* SPL options */ +#include "imx6_spl.h"
+/*
- There is a bug in some i.MX6UL processors that results in the
initial
- portion of OCRAM being unavailable when booting from (at least)
an SD
- card.
- Tweak the SPL text base address to avoid this.
- */
+#undef CONFIG_SPL_TEXT_BASE +#define CONFIG_SPL_TEXT_BASE 0x00909000
+/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
+/* Console configs */ +#define CONFIG_MXC_UART_BASE UART1_BASE
+/* MMC Configs */ +#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+/* I2C configs */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif
+/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000
+/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_256M
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+#define CONFIG_ENV_SIZE (16 << 10) +#define CONFIG_ENV_OFFSET (512 << 10)
+/* NAND */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000
+/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_IMX_THERMAL
+#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=ttymxc0,115200n8\0" \
- "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- "fdt_addr_r=0x82000000\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "kernel_addr_r=0x81000000\0" \
- "pxefile_addr_r=0x87100000\0" \
- "ramdisk_addr_r=0x82100000\0" \
- "scriptaddr=0x87000000\0" \
- BOOTENV
+#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(UBIFS, ubifs, 0) \
- func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#endif /* __PCL063_H */
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
On 10/12/2018 12:05, Martyn Welch wrote:
When CONFIG_SPL_DM_USB was added, it was added defaulted on without protection to ensure it didn't get set for non-DM SPL builds.
This leads to unexpected and confusing failures when building a DM based U-Boot but with a non-DM SPL, as the defconfig is unlikely to have CONFIG_SPL_DM_USB actively disabled.
Tweak the Kconfig to not enable this setting unless CONFIG_SPL_DM is set.
Signed-off-by: Martyn Welch martyn.welch@collabora.com
Changes in v3:
- New in v3
Changes in v2: None
drivers/usb/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index d456beb43f..3c978d43aa 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -49,7 +49,7 @@ config DM_USB
config SPL_DM_USB bool "Enable driver model for USB in SPL"
- depends on DM_USB
depends on SPL_DM && DM_USB default y
source "drivers/usb/host/Kconfig"
Reviewed-by: Jean-Jacques Hiblot jjhiblot@ti.com
On 12/10/2018 12:05 PM, Martyn Welch wrote:
When CONFIG_SPL_DM_USB was added, it was added defaulted on without protection to ensure it didn't get set for non-DM SPL builds.
This leads to unexpected and confusing failures when building a DM based U-Boot but with a non-DM SPL, as the defconfig is unlikely to have CONFIG_SPL_DM_USB actively disabled.
Tweak the Kconfig to not enable this setting unless CONFIG_SPL_DM is set.
Signed-off-by: Martyn Welch martyn.welch@collabora.com
Ah, I didn't realize the other patches weren't USB too. Applied, thanks.
On Mon, 2018-12-10 at 13:07 +0100, Marek Vasut wrote:
On 12/10/2018 12:05 PM, Martyn Welch wrote:
When CONFIG_SPL_DM_USB was added, it was added defaulted on without protection to ensure it didn't get set for non-DM SPL builds.
This leads to unexpected and confusing failures when building a DM based U-Boot but with a non-DM SPL, as the defconfig is unlikely to have CONFIG_SPL_DM_USB actively disabled.
Tweak the Kconfig to not enable this setting unless CONFIG_SPL_DM is set.
Signed-off-by: Martyn Welch martyn.welch@collabora.com
Ah, I didn't realize the other patches weren't USB too. Applied, thanks.
Thanks.
I assume this is juat patch 1/3 that you've applied?
Martyn
On 12/10/2018 02:53 PM, Martyn Welch wrote:
On Mon, 2018-12-10 at 13:07 +0100, Marek Vasut wrote:
On 12/10/2018 12:05 PM, Martyn Welch wrote:
When CONFIG_SPL_DM_USB was added, it was added defaulted on without protection to ensure it didn't get set for non-DM SPL builds.
This leads to unexpected and confusing failures when building a DM based U-Boot but with a non-DM SPL, as the defconfig is unlikely to have CONFIG_SPL_DM_USB actively disabled.
Tweak the Kconfig to not enable this setting unless CONFIG_SPL_DM is set.
Signed-off-by: Martyn Welch martyn.welch@collabora.com
Ah, I didn't realize the other patches weren't USB too. Applied, thanks.
Thanks.
I assume this is juat patch 1/3 that you've applied?
Yes
participants (5)
-
Jean-Jacques Hiblot -
Lukasz Majewski -
Marek Vasut -
Martyn Welch -
Martyn Welch