Bootscripts for some distro's such as Android can benefit from knowing what boot media its script was loaded from.

Signed-off-by: Tim Harvey tharvey@gateworks.com --- include/configs/gw_ventana.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 684f347..48919e8 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -359,7 +359,7 @@ "mmc_boot=" \ "setenv fsload 'ext2load mmc 0:1'; " \ "mmc dev 0 && mmc rescan && " \ - "run loadscript; " \ + "setenv dtype mmc; run loadscript; " \ "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ "setenv bootargs console=${console},${baudrate} " \ "root=/dev/mmcblk0p1 rootfstype=ext4 " \ @@ -373,7 +373,7 @@ \ "sata_boot=" \ "setenv fsload 'ext2load sata 0:1'; sata init && " \ - "run loadscript; " \ + "setenv dtype sata; run loadscript; " \ "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ "setenv bootargs console=${console},${baudrate} " \ "root=/dev/sda1 rootfstype=ext4 " \ @@ -386,7 +386,7 @@ "fi\0" \ "usb_boot=" \ "setenv fsload 'ext2load usb 0:1'; usb start && usb dev 0 && " \ - "run loadscript; " \ + "setenv dtype usb; run loadscript; " \ "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ "setenv bootargs console=${console},${baudrate} " \ "root=/dev/sda1 rootfstype=ext4 " \ @@ -450,7 +450,7 @@ "setenv root ubi0:rootfs ubi.mtd=2 " \ "rootfstype=ubifs; " \ "fi; " \ - "run loadscript; " \ + "setenv dtype nand; run loadscript; " \ "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ "setenv bootargs console=${console},${baudrate} " \ "root=${root} ${video} ${extra}; " \

Signed-off-by: Tim Harvey tharvey@gateworks.com --- include/configs/gw_ventana.h | 1 + 1 file changed, 1 insertion(+)

diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index dfe818e..db0cf51 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -47,6 +47,7 @@

/* GPIO */ #define CONFIG_MXC_GPIO +#define CONFIG_CMD_GPIO

/* Serial */ #define CONFIG_MXC_UART

Prior to using a gpio a call to gpio_request() should be called to register it with the gpio subsystem.

Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 77 ++++++++++++++++++++++++--------- 1 file changed, 57 insertions(+), 20 deletions(-)

diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 1e54912..8818be4 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -268,14 +268,15 @@ static void setup_gpmi_nand(void) } #endif

-static void setup_iomux_enet(void) +static void setup_iomux_enet(int gpio) { SETUP_IOMUX_PADS(enet_pads);

/* toggle PHY_RST# */ - gpio_direction_output(GP_PHY_RST, 0); + gpio_request(gpio, "phy_rst#"); + gpio_direction_output(gpio, 0); mdelay(2); - gpio_set_value(GP_PHY_RST, 1); + gpio_set_value(gpio, 1); }

static void setup_iomux_uart(void) @@ -295,6 +296,7 @@ static iomux_v3_cfg_t const usb_pads[] = { int board_ehci_hcd_init(int port) { struct ventana_board_info *info = &ventana_info; + int gpio;

SETUP_IOMUX_PADS(usb_pads);

@@ -303,18 +305,22 @@ int board_ehci_hcd_init(int port) case '3': /* GW53xx */ case '5': /* GW552x */ SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG); - gpio_direction_output(IMX_GPIO_NR(1, 9), 0); - mdelay(2); - gpio_set_value(IMX_GPIO_NR(1, 9), 1); + gpio = (IMX_GPIO_NR(1, 9)); break; case '4': /* GW54xx */ SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG); - gpio_direction_output(IMX_GPIO_NR(1, 16), 0); - mdelay(2); - gpio_set_value(IMX_GPIO_NR(1, 16), 1); + gpio = (IMX_GPIO_NR(1, 16)); break; + default: + return 0; }

+ /* request and toggle hub rst */ + gpio_request(gpio, "usb_hub_rst#"); + gpio_direction_output(gpio, 0); + mdelay(2); + gpio_set_value(gpio, 1); + return 0; }

@@ -322,6 +328,7 @@ int board_ehci_power(int port, int on) { if (port) return 0; + gpio_request(GP_USB_OTG_PWR, "usb_otg_pwr"); gpio_set_value(GP_USB_OTG_PWR, on); return 0; } @@ -333,6 +340,7 @@ static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; int board_mmc_getcd(struct mmc *mmc) { /* Card Detect */ + gpio_request(GP_SD3_CD, "sd_cd"); gpio_direction_input(GP_SD3_CD); return !gpio_get_value(GP_SD3_CD); } @@ -364,6 +372,7 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)

static void setup_spi(void) { + gpio_request(IMX_GPIO_NR(3, 19), "spi_cs"); gpio_direction_output(IMX_GPIO_NR(3, 19), 1); SETUP_IOMUX_PADS(ecspi1_pads); } @@ -399,7 +408,7 @@ int board_eth_init(bd_t *bis) { #ifdef CONFIG_FEC_MXC if (board_type != GW551x && board_type != GW552x) { - setup_iomux_enet(); + setup_iomux_enet(GP_PHY_RST); cpu_eth_init(bis); } #endif @@ -449,6 +458,7 @@ static void enable_lvds(struct display_info_t const *dev) writel(reg, &iomux->gpr[2]);

/* Enable Backlight */ + gpio_request(IMX_GPIO_NR(1, 18), "bklt_en"); SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG); gpio_direction_output(IMX_GPIO_NR(1, 18), 1); } @@ -588,6 +598,7 @@ static void setup_display(void) writel(reg, &iomux->gpr[3]);

/* Backlight CABEN on LVDS connector */ + gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio"); SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG); gpio_direction_output(IMX_GPIO_NR(1, 10), 0); } @@ -1158,9 +1169,11 @@ static void setup_board_gpio(int board) return;

/* RS232_EN# */ + gpio_request(GP_RS232_EN, "rs232_en"); gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);

/* MSATA Enable */ + gpio_request(GP_MSATA_SEL, "msata_en"); if (is_cpu_type(MXC_CPU_MX6Q) && test_bit(EECONFIG_SATA, info->config)) { gpio_direction_output(GP_MSATA_SEL, @@ -1175,50 +1188,71 @@ static void setup_board_gpio(int board) gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23);

/* assert PCI_RST# (released by OS when clock is valid) */ + gpio_request(gpio_cfg[board].pcie_rst, "pci_rst#"); gpio_direction_output(gpio_cfg[board].pcie_rst, 0); #endif

/* turn off (active-high) user LED's */ for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) { - if (gpio_cfg[board].leds[i]) + if (gpio_cfg[board].leds[i]) { + gpio_requestf(gpio_cfg[board].leds[i], "led_user%d", i); gpio_direction_output(gpio_cfg[board].leds[i], 1); + } }

/* Expansion Mezzanine IO */ - if (gpio_cfg[board].mezz_pwren) + if (gpio_cfg[board].mezz_pwren) { + gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr"); gpio_direction_output(gpio_cfg[board].mezz_pwren, 0); - if (gpio_cfg[board].mezz_irq) + } + if (gpio_cfg[board].mezz_irq) { + gpio_request(gpio_cfg[board].mezz_irq, "mezz_irq#"); gpio_direction_input(gpio_cfg[board].mezz_irq); + }

/* RS485 Transmit Enable */ - if (gpio_cfg[board].rs485en) + if (gpio_cfg[board].rs485en) { + gpio_request(gpio_cfg[board].rs485en, "rs485_en"); gpio_direction_output(gpio_cfg[board].rs485en, 0); + }

/* GPS_SHDN */ - if (gpio_cfg[board].gps_shdn) + if (gpio_cfg[board].gps_shdn) { + gpio_request(gpio_cfg[board].gps_shdn, "gps_shdn"); gpio_direction_output(gpio_cfg[board].gps_shdn, 1); + }

/* Analog video codec power enable */ - if (gpio_cfg[board].vidin_en) + if (gpio_cfg[board].vidin_en) { + gpio_request(gpio_cfg[board].vidin_en, "anavidin_en"); gpio_direction_output(gpio_cfg[board].vidin_en, 1); + }

/* DIOI2C_DIS# */ - if (gpio_cfg[board].dioi2c_en) + if (gpio_cfg[board].dioi2c_en) { + gpio_request(gpio_cfg[board].dioi2c_en, "dioi2c_dis#"); gpio_direction_output(gpio_cfg[board].dioi2c_en, 0); + }

/* PCICK_SSON: disable spread-spectrum clock */ - if (gpio_cfg[board].pcie_sson) + if (gpio_cfg[board].pcie_sson) { + gpio_request(gpio_cfg[board].pcie_sson, "pci_sson"); gpio_direction_output(gpio_cfg[board].pcie_sson, 0); + }

/* USBOTG Select (PCISKT or FrontPanel) */ - if (gpio_cfg[board].usb_sel) + if (gpio_cfg[board].usb_sel) { + gpio_request(gpio_cfg[board].usb_sel, "usb_pcisel"); gpio_direction_output(gpio_cfg[board].usb_sel, (hwconfig("usb_pcisel")) ? 1 : 0); + }

/* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */ - if (gpio_cfg[board].wdis) + if (gpio_cfg[board].wdis) { + gpio_request(gpio_cfg[board].wdis, "wlan_dis"); gpio_direction_output(gpio_cfg[board].wdis, 1); + }

/* * Configure DIO pinmux/padctl registers @@ -1248,6 +1282,7 @@ static void setup_board_gpio(int board) } imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] | ctrl); + gpio_requestf(cfg->gpio_param, "dio%d", i); gpio_direction_input(cfg->gpio_param); } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") && cfg->pwm_padmux) { @@ -1274,6 +1309,7 @@ int imx6_pcie_toggle_reset(void) { if (board_type < GW_UNKNOWN) { uint pin = gpio_cfg[board_type].pcie_rst; + gpio_request(pin, "pci_rst#"); gpio_direction_output(pin, 0); mdelay(50); gpio_direction_output(pin, 1); @@ -1343,6 +1379,7 @@ void get_board_serial(struct tag_serialnr *serialnr) int board_early_init_f(void) { setup_iomux_uart(); + gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */

#if defined(CONFIG_VIDEO_IPUV3)

Signed-off-by: Tim Harvey tharvey@gateworks.com --- include/configs/gw_ventana.h | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index ea1848a..63af20c 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -50,6 +50,7 @@ #define CONFIG_DM #define CONFIG_DM_GPIO #define CONFIG_DM_SERIAL +#define CONFIG_DM_THERMAL #define CONFIG_CMD_DM #endif

@@ -57,6 +58,9 @@ #define CONFIG_MXC_GPIO #define CONFIG_CMD_GPIO

+/* Thermal */ +#define CONFIG_IMX6_THERMAL + /* Serial */ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART2_BASE

The re-assignment of pcie_rst gpio for GW522x needs to occur earlier, before the PCI subsystem calls the toggle funciton.

Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 554cd84..8cfc1f2 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1184,10 +1184,6 @@ static void setup_board_gpio(int board) }

#if !defined(CONFIG_CMD_PCI) - /* GW522x Uses GPIO3_IO23 for PCIE_RST# */ - if (board_type == GW52xx && info->model[4] == '2') - gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23); - /* assert PCI_RST# (released by OS when clock is valid) */ gpio_request(gpio_cfg[board].pcie_rst, "pci_rst#"); gpio_direction_output(gpio_cfg[board].pcie_rst, 0); @@ -1435,6 +1431,10 @@ int board_init(void) int count = gpio_cfg[board_type].num_pads;

imx_iomux_v3_setup_multiple_pads(p, count); + + /* GW522x Uses GPIO3_IO23 for PCIE_RST# */ + if (board_type == GW52xx && ventana_info.model[4] == '2') + gpio_cfg[board_type].pcie_rst = IMX_GPIO_NR(3, 23); }

return 0;

Move shared functions used by both SPL and U-Boot to common.c: - setup_iomux_uart() and uart pad config - gpio pad config

In the process also moved the following to common.c in preparation for calling it from the SPL: - split i2c setup into a shared function - move pmic init to setup_pmic() function to call directly from power_init_board() - split gpio setup into early (iomux and default pin config) and late (output configuration based on env)

Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/Makefile | 2 +- board/gateworks/gw_ventana/common.c | 823 ++++++++++++++++++++++++++++++ board/gateworks/gw_ventana/common.h | 98 ++++ board/gateworks/gw_ventana/gw_ventana.c | 874 +------------------------------- 4 files changed, 933 insertions(+), 864 deletions(-) create mode 100644 board/gateworks/gw_ventana/common.c create mode 100644 board/gateworks/gw_ventana/common.h

diff --git a/board/gateworks/gw_ventana/Makefile b/board/gateworks/gw_ventana/Makefile index 33a1788..8fa691a 100644 --- a/board/gateworks/gw_ventana/Makefile +++ b/board/gateworks/gw_ventana/Makefile @@ -6,6 +6,6 @@ # SPDX-License-Identifier: GPL-2.0+ #

-obj-y := gw_ventana.o gsc.o eeprom.o +obj-y := gw_ventana.o gsc.o eeprom.o common.o obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o

diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c new file mode 100644 index 0000000..45c5b4c --- /dev/null +++ b/board/gateworks/gw_ventana/common.c @@ -0,0 +1,823 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * Author: Tim Harvey tharvey@gateworks.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/mxc_i2c.h> +#include <hwconfig.h> +#include <power/pmic.h> +#include <power/ltc3676_pmic.h> +#include <power/pfuze100_pmic.h> + +#include "common.h" + +/* UART1: Function varies per baseboard */ +static iomux_v3_cfg_t const uart1_pads[] = { + IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +/* UART2: Serial Console */ +static iomux_v3_cfg_t const uart2_pads[] = { + IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); + SETUP_IOMUX_PADS(uart2_pads); +} + +/* I2C1: GSC */ +static struct i2c_pads_info mx6q_i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC, + .gp = IMX_GPIO_NR(3, 21) + }, + .sda = { + .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC, + .gp = IMX_GPIO_NR(3, 28) + } +}; +static struct i2c_pads_info mx6dl_i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC, + .gp = IMX_GPIO_NR(3, 21) + }, + .sda = { + .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC, + .gp = IMX_GPIO_NR(3, 28) + } +}; + +/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */ +static struct i2c_pads_info mx6q_i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; +static struct i2c_pads_info mx6dl_i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +/* I2C3: Misc/Expansion */ +static struct i2c_pads_info mx6q_i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC, + .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC, + .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC, + .gp = IMX_GPIO_NR(1, 6) + } +}; +static struct i2c_pads_info mx6dl_i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC, + .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC, + .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC, + .gp = IMX_GPIO_NR(1, 6) + } +}; + +void setup_ventana_i2c(void) +{ + if (is_cpu_type(MXC_CPU_MX6Q)) { + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2); + } else { + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2); + } +} + +/* + * Baseboard specific GPIO + */ + +/* common to add baseboards */ +static iomux_v3_cfg_t const gw_gpio_pads[] = { + /* MSATA_EN */ + IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), + /* RS232_EN# */ + IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), +}; + +/* prototype */ +static iomux_v3_cfg_t const gwproto_gpio_pads[] = { + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* LOCLED# */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* RS485_EN */ + IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), + /* IOEXP_PWREN# */ + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), + /* IOEXP_IRQ# */ + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + /* VID_EN */ + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), + /* DIOI2C_DIS# */ + IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), + /* PCICK_SSON */ + IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), +}; + +static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* IOEXP_PWREN# */ + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), + /* IOEXP_IRQ# */ + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + + /* GPS_SHDN */ + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), + /* VID_PWR */ + IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), +}; + +static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* IOEXP_PWREN# */ + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), + /* IOEXP_IRQ# */ + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + + /* MX6_LOCLED# */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* GPS_SHDN */ + IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), + /* USBOTG_SEL */ + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), + /* VID_PWR */ + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), + /* PCI_RST# (GW522x) */ + IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), +}; + +static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* MX6_LOCLED# */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* IOEXP_PWREN# */ + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), + /* IOEXP_IRQ# */ + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + /* DIOI2C_DIS# */ + IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), + /* GPS_SHDN */ + IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), + /* VID_EN */ + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), +}; + +static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG), + /* MX6_LOCLED# */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* MIPI_DIO */ + IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG), + /* RS485_EN */ + IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG), + /* IOEXP_PWREN# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* IOEXP_IRQ# */ + IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + /* DIOI2C_DIS# */ + IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), + /* VID_EN */ + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), +}; + +static iomux_v3_cfg_t const gw551x_gpio_pads[] = { + /* PANLED# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), +}; + +static iomux_v3_cfg_t const gw552x_gpio_pads[] = { + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* MX6_LOCLED# */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), + /* MX6_DIO[4:9] */ + IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG), + IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), + IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG), + IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG), + IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG), + IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG), + /* PCIEGBE1_OFF# */ + IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG), + /* PCIEGBE2_OFF# */ + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), +}; + + +/* + * Board Specific GPIO + */ +struct ventana gpio_cfg[GW_UNKNOWN] = { + /* GW5400proto */ + { + .gpio_pads = gw54xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, + IMX_GPIO_NR(1, 9), + { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, + 1 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, + IMX_GPIO_NR(2, 9), + { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, + IMX_GPIO_NR(2, 10), + { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, + 4 + }, + }, + .num_gpios = 4, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 10), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .mezz_pwren = IMX_GPIO_NR(4, 7), + .mezz_irq = IMX_GPIO_NR(4, 9), + .rs485en = IMX_GPIO_NR(3, 24), + .dioi2c_en = IMX_GPIO_NR(4, 5), + .pcie_sson = IMX_GPIO_NR(1, 20), + }, + + /* GW51xx */ + { + .gpio_pads = gw51xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, + IMX_GPIO_NR(1, 18), + { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, + 4 + }, + }, + .num_gpios = 4, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 10), + }, + .pcie_rst = IMX_GPIO_NR(1, 0), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .gps_shdn = IMX_GPIO_NR(1, 2), + .vidin_en = IMX_GPIO_NR(5, 20), + .wdis = IMX_GPIO_NR(7, 12), + }, + + /* GW52xx */ + { + .gpio_pads = gw52xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, + IMX_GPIO_NR(1, 20), + { 0, 0 }, + 0 + }, + }, + .num_gpios = 4, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 7), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .gps_shdn = IMX_GPIO_NR(1, 27), + .vidin_en = IMX_GPIO_NR(3, 31), + .usb_sel = IMX_GPIO_NR(1, 2), + .wdis = IMX_GPIO_NR(7, 12), + }, + + /* GW53xx */ + { + .gpio_pads = gw53xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, + IMX_GPIO_NR(1, 20), + { 0, 0 }, + 0 + }, + }, + .num_gpios = 4, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 7), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .gps_shdn = IMX_GPIO_NR(1, 27), + .vidin_en = IMX_GPIO_NR(3, 31), + .wdis = IMX_GPIO_NR(7, 12), + }, + + /* GW54xx */ + { + .gpio_pads = gw54xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, + IMX_GPIO_NR(1, 9), + { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, + 1 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, + IMX_GPIO_NR(2, 9), + { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, + IMX_GPIO_NR(2, 10), + { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, + 4 + }, + }, + .num_gpios = 4, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 7), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .rs485en = IMX_GPIO_NR(7, 1), + .vidin_en = IMX_GPIO_NR(3, 31), + .dioi2c_en = IMX_GPIO_NR(4, 5), + .pcie_sson = IMX_GPIO_NR(1, 20), + .wdis = IMX_GPIO_NR(5, 17), + }, + + /* GW551x */ + { + .gpio_pads = gw551x_gpio_pads, + .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, + IMX_GPIO_NR(1, 18), + { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, + 4 + }, + }, + .num_gpios = 2, + .leds = { + IMX_GPIO_NR(4, 7), + }, + .pcie_rst = IMX_GPIO_NR(1, 0), + .wdis = IMX_GPIO_NR(7, 12), + }, + + /* GW552x */ + { + .gpio_pads = gw552x_gpio_pads, + .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + }, + .num_gpios = 4, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 7), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .wdis = IMX_GPIO_NR(7, 12), + }, +}; + +void setup_iomux_gpio(int board, struct ventana_board_info *info) +{ + int i; + + /* iomux common to all Ventana boards */ + SETUP_IOMUX_PADS(gw_gpio_pads); + + /* OTG power off */ + gpio_request(GP_USB_OTG_PWR, "usbotg_pwr"); + gpio_direction_output(GP_USB_OTG_PWR, 0); + + /* MSATA Enable - default to PCI */ + gpio_request(GP_MSATA_SEL, "msata_en"); + gpio_direction_output(GP_MSATA_SEL, 0); + + /* RS232_EN# */ + gpio_request(GP_RS232_EN, "rs232_en"); + gpio_direction_output(GP_RS232_EN, 0); + + if (board >= GW_UNKNOWN) + return; + + /* board specific iomux */ + imx_iomux_v3_setup_multiple_pads(gpio_cfg[board].gpio_pads, + gpio_cfg[board].num_pads); + + /* GW522x Uses GPIO3_IO23 for PCIE_RST# */ + if (board == GW52xx && info->model[4] == '2') + gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23); + + /* assert PCI_RST# */ + gpio_request(gpio_cfg[board].pcie_rst, "pci_rst#"); + gpio_direction_output(gpio_cfg[board].pcie_rst, 0); + + /* turn off (active-high) user LED's */ + for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) { + char name[16]; + if (gpio_cfg[board].leds[i]) { + sprintf(name, "led_user%d", i); + gpio_request(gpio_cfg[board].leds[i], name); + gpio_direction_output(gpio_cfg[board].leds[i], 1); + } + } + + /* Expansion Mezzanine IO */ + if (gpio_cfg[board].mezz_pwren) { + gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr"); + gpio_direction_output(gpio_cfg[board].mezz_pwren, 0); + } + if (gpio_cfg[board].mezz_irq) { + gpio_request(gpio_cfg[board].mezz_irq, "mezz_irq#"); + gpio_direction_input(gpio_cfg[board].mezz_irq); + } + + /* RS485 Transmit Enable */ + if (gpio_cfg[board].rs485en) { + gpio_request(gpio_cfg[board].rs485en, "rs485_en"); + gpio_direction_output(gpio_cfg[board].rs485en, 0); + } + + /* GPS_SHDN */ + if (gpio_cfg[board].gps_shdn) { + gpio_request(gpio_cfg[board].gps_shdn, "gps_shdn"); + gpio_direction_output(gpio_cfg[board].gps_shdn, 1); + } + + /* Analog video codec power enable */ + if (gpio_cfg[board].vidin_en) { + gpio_request(gpio_cfg[board].vidin_en, "anavidin_en"); + gpio_direction_output(gpio_cfg[board].vidin_en, 1); + } + + /* DIOI2C_DIS# */ + if (gpio_cfg[board].dioi2c_en) { + gpio_request(gpio_cfg[board].dioi2c_en, "dioi2c_dis#"); + gpio_direction_output(gpio_cfg[board].dioi2c_en, 0); + } + + /* PCICK_SSON: disable spread-spectrum clock */ + if (gpio_cfg[board].pcie_sson) { + gpio_request(gpio_cfg[board].pcie_sson, "pci_sson"); + gpio_direction_output(gpio_cfg[board].pcie_sson, 0); + } + + /* USBOTG mux routing */ + if (gpio_cfg[board].usb_sel) { + gpio_request(gpio_cfg[board].usb_sel, "usb_pcisel"); + gpio_direction_output(gpio_cfg[board].usb_sel, 0); + } + + /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */ + if (gpio_cfg[board].wdis) { + gpio_request(gpio_cfg[board].wdis, "wlan_dis"); + gpio_direction_output(gpio_cfg[board].wdis, 1); + } +} + +/* setup GPIO pinmux and default configuration per baseboard and env */ +void setup_board_gpio(int board, struct ventana_board_info *info) +{ + const char *s; + char arg[10]; + size_t len; + int i; + int quiet = simple_strtol(getenv("quiet"), NULL, 10); + + if (board >= GW_UNKNOWN) + return; + + /* RS232_EN# */ + gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1); + + /* MSATA Enable */ + if (is_cpu_type(MXC_CPU_MX6Q) && + test_bit(EECONFIG_SATA, info->config)) { + gpio_direction_output(GP_MSATA_SEL, + (hwconfig("msata")) ? 1 : 0); + } + + /* USBOTG Select (PCISKT or FrontPanel) */ + if (gpio_cfg[board].usb_sel) { + gpio_direction_output(gpio_cfg[board].usb_sel, + (hwconfig("usb_pcisel")) ? 1 : 0); + } + + /* + * Configure DIO pinmux/padctl registers + * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions + */ + for (i = 0; i < 4; i++) { + struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; + iomux_v3_cfg_t ctrl = DIO_PAD_CFG; + unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1; + + if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1]) + continue; + sprintf(arg, "dio%d", i); + if (!hwconfig(arg)) + continue; + s = hwconfig_subarg(arg, "padctrl", &len); + if (s) { + ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16) + & 0x1ffff) | MUX_MODE_SION; + } + if (hwconfig_subarg_cmp(arg, "mode", "gpio")) { + if (!quiet) { + printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i, + (cfg->gpio_param/32)+1, + cfg->gpio_param%32, + cfg->gpio_param); + } + imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] | + ctrl); + gpio_requestf(cfg->gpio_param, "dio%d", i); + gpio_direction_input(cfg->gpio_param); + } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") && + cfg->pwm_padmux) { + if (!quiet) + printf("DIO%d: pwm%d\n", i, cfg->pwm_param); + imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] | + MUX_PAD_CTRL(ctrl)); + } + } + + if (!quiet) { + if (is_cpu_type(MXC_CPU_MX6Q) && + (test_bit(EECONFIG_SATA, info->config))) { + printf("MSATA: %s\n", (hwconfig("msata") ? + "enabled" : "disabled")); + } + printf("RS232: %s\n", (hwconfig("rs232")) ? + "enabled" : "disabled"); + } +} + +/* setup board specific PMIC */ +void setup_pmic(int board) +{ + struct pmic *p; + u32 reg; + + /* configure PFUZE100 PMIC */ + if (board == GW54xx || board == GW54proto) { + power_pfuze100_init(CONFIG_I2C_PMIC); + p = pmic_get("PFUZE100"); + if (p && !pmic_probe(p)) { + pmic_reg_read(p, PFUZE100_DEVICEID, &reg); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + /* Set VGEN1 to 1.5V and enable */ + pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg); + reg &= ~(LDO_VOL_MASK); + reg |= (LDOA_1_50V | LDO_EN); + pmic_reg_write(p, PFUZE100_VGEN1VOL, reg); + + /* Set SWBST to 5.0V and enable */ + pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg); + reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK); + reg |= (SWBST_5_00V | SWBST_MODE_AUTO); + pmic_reg_write(p, PFUZE100_SWBSTCON1, reg); + } + } + + /* configure LTC3676 PMIC */ + else { + power_ltc3676_init(CONFIG_I2C_PMIC); + p = pmic_get("LTC3676_PMIC"); + if (p && !pmic_probe(p)) { + puts("PMIC: LTC3676\n"); + /* + * set board-specific scalar for max CPU frequency + * per CPU based on the LDO enabled Operating Ranges + * defined in the respective IMX6DQ and IMX6SDL + * datasheets. The voltage resulting from the R1/R2 + * feedback inputs on Ventana is 1308mV. Note that this + * is a bit shy of the Vmin of 1350mV in the datasheet + * for LDO enabled mode but is as high as we can go. + * + * We will rely on an OS kernel driver to properly + * regulate these per CPU operating point and use LDO + * bypass mode when using the higher frequency + * operating points to compensate as LDO bypass mode + * allows the rails be 125mV lower. + */ + /* mask PGOOD during SW1 transition */ + pmic_reg_write(p, LTC3676_DVB1B, + 0x1f | LTC3676_PGOOD_MASK); + /* set SW1 (VDD_SOC) */ + pmic_reg_write(p, LTC3676_DVB1A, 0x1f); + + /* mask PGOOD during SW3 transition */ + pmic_reg_write(p, LTC3676_DVB3B, + 0x1f | LTC3676_PGOOD_MASK); + /* set SW3 (VDD_ARM) */ + pmic_reg_write(p, LTC3676_DVB3A, 0x1f); + } + } +} diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h new file mode 100644 index 0000000..a303b55 --- /dev/null +++ b/board/gateworks/gw_ventana/common.h @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * Author: Tim Harvey tharvey@gateworks.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _GWVENTANA_COMMON_H_ +#define _GWVENTANA_COMMON_H_ + +#include "ventana_eeprom.h" + +/* GPIO's common to all baseboards */ +#define GP_PHY_RST IMX_GPIO_NR(1, 30) +#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) +#define GP_SD3_CD IMX_GPIO_NR(7, 0) +#define GP_RS232_EN IMX_GPIO_NR(2, 11) +#define GP_MSATA_SEL IMX_GPIO_NR(2, 8) + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) + +#define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION) + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +/* + * each baseboard has 4 user configurable Digital IO lines which can + * be pinmuxed as a GPIO or in some cases a PWM + */ +struct dio_cfg { + iomux_v3_cfg_t gpio_padmux[2]; + unsigned gpio_param; + iomux_v3_cfg_t pwm_padmux[2]; + unsigned pwm_param; +}; + +struct ventana { + /* pinmux */ + iomux_v3_cfg_t const *gpio_pads; + int num_pads; + /* DIO pinmux/val */ + struct dio_cfg dio_cfg[4]; + int num_gpios; + /* various gpios (0 if non-existent) */ + int leds[3]; + int pcie_rst; + int mezz_pwren; + int mezz_irq; + int rs485en; + int gps_shdn; + int vidin_en; + int dioi2c_en; + int pcie_sson; + int usb_sel; + int wdis; +}; + +extern struct ventana gpio_cfg[GW_UNKNOWN]; + +/* configure i2c iomux */ +void setup_ventana_i2c(void); +/* configure uart iomux */ +void setup_iomux_uart(void); +/* conifgure PMIC */ +void setup_pmic(int board); +/* configure gpio iomux/defaults */ +void setup_iomux_gpio(int board, struct ventana_board_info *); +/* late setup of GPIO (configuration per baseboard and env) */ +void setup_board_gpio(int board, struct ventana_board_info *); + +#endif /* #ifndef _GWVENTANA_COMMON_H_ */ diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index cf866ca..8163d38 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -7,30 +7,26 @@ */

#include <common.h> -#include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> #include <asm/arch/iomux.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/mxc_hdmi.h> -#include <asm/arch/crm_regs.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> -#include <asm/imx-common/iomux-v3.h> -#include <asm/imx-common/mxc_i2c.h> #include <asm/imx-common/boot_mode.h> #include <asm/imx-common/sata.h> #include <asm/imx-common/spi.h> #include <asm/imx-common/video.h> +#include <asm/io.h> +#include <dm.h> #include <dm/platform_data/serial_mxc.h> -#include <jffs2/load_kernel.h> -#include <hwconfig.h> #include <i2c.h> -#include <linux/ctype.h> #include <fdt_support.h> #include <fsl_esdhc.h> +#include <jffs2/load_kernel.h> +#include <linux/ctype.h> #include <miiphy.h> -#include <mmc.h> #include <mtd_node.h> #include <netdev.h> #include <pci.h> @@ -42,47 +38,10 @@ #include <spi_flash.h>

#include "gsc.h" -#include "ventana_eeprom.h" +#include "common.h"

DECLARE_GLOBAL_DATA_PTR;

-/* GPIO's common to all baseboards */ -#define GP_PHY_RST IMX_GPIO_NR(1, 30) -#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) -#define GP_SD3_CD IMX_GPIO_NR(7, 0) -#define GP_RS232_EN IMX_GPIO_NR(2, 11) -#define GP_MSATA_SEL IMX_GPIO_NR(2, 8) - -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define SPI_PAD_CTRL (PAD_CTL_HYS | \ - PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) - -#define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION) -

/* * EEPROM board info struct populated by read_eeprom so that we only have to @@ -92,98 +51,6 @@ struct ventana_board_info ventana_info;

static int board_type;

-/* UART1: Function varies per baseboard */ -static iomux_v3_cfg_t const uart1_pads[] = { - IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), -}; - -/* UART2: Serial Console */ -static iomux_v3_cfg_t const uart2_pads[] = { - IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), -}; - -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) - -/* I2C1: GSC */ -static struct i2c_pads_info mx6q_i2c_pad_info0 = { - .scl = { - .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, - .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC, - .gp = IMX_GPIO_NR(3, 21) - }, - .sda = { - .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, - .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC, - .gp = IMX_GPIO_NR(3, 28) - } -}; -static struct i2c_pads_info mx6dl_i2c_pad_info0 = { - .scl = { - .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC, - .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC, - .gp = IMX_GPIO_NR(3, 21) - }, - .sda = { - .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC, - .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC, - .gp = IMX_GPIO_NR(3, 28) - } -}; - -/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */ -static struct i2c_pads_info mx6q_i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, - .gp = IMX_GPIO_NR(4, 13) - } -}; -static struct i2c_pads_info mx6dl_i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -/* I2C3: Misc/Expansion */ -static struct i2c_pads_info mx6q_i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC, - .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC, - .gp = IMX_GPIO_NR(1, 6) - } -}; -static struct i2c_pads_info mx6dl_i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC, - .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC, - .gp = IMX_GPIO_NR(1, 6) - } -}; - /* MMC */ static iomux_v3_cfg_t const usdhc3_pads[] = { IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), @@ -280,12 +147,6 @@ static void setup_iomux_enet(int gpio) gpio_set_value(gpio, 1); }

-static void setup_iomux_uart(void) -{ - SETUP_IOMUX_PADS(uart1_pads); - SETUP_IOMUX_PADS(uart2_pads); -} - #ifdef CONFIG_USB_EHCI_MX6 static iomux_v3_cfg_t const usb_pads[] = { IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG), @@ -329,7 +190,6 @@ int board_ehci_power(int port, int on) { if (port) return 0; - gpio_request(GP_USB_OTG_PWR, "usb_otg_pwr"); gpio_set_value(GP_USB_OTG_PWR, on); return 0; } @@ -605,699 +465,13 @@ static void setup_display(void) } #endif /* CONFIG_VIDEO_IPUV3 */

-/* - * Baseboard specific GPIO - */ - -/* common to add baseboards */ -static iomux_v3_cfg_t const gw_gpio_pads[] = { - /* MSATA_EN */ - IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), - /* RS232_EN# */ - IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), -}; - -/* prototype */ -static iomux_v3_cfg_t const gwproto_gpio_pads[] = { - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* RS485_EN */ - IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), - /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), - /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - /* VID_EN */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), - /* DIOI2C_DIS# */ - IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), - /* PCICK_SSON */ - IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), - /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - - /* GPS_SHDN */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), - /* VID_PWR */ - IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), - /* PCIESKT_WDIS# */ - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), - /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* GPS_SHDN */ - IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), - /* USBOTG_SEL */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), - /* VID_PWR */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), - /* PCI_RST# (GW522x) */ - IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG), - /* PCIESKT_WDIS# */ - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), - /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - /* DIOI2C_DIS# */ - IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), - /* GPS_SHDN */ - IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), - /* VID_EN */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), - /* PCIESKT_WDIS# */ - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* MIPI_DIO */ - IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG), - /* RS485_EN */ - IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG), - /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - /* DIOI2C_DIS# */ - IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), - /* VID_EN */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), - /* PCIESKT_WDIS# */ - IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw551x_gpio_pads[] = { - /* PANLED# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), - /* PCIESKT_WDIS# */ - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), -}; - -static iomux_v3_cfg_t const gw552x_gpio_pads[] = { - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), - /* MX6_DIO[4:9] */ - IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG), - IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), - IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG), - IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG), - IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG), - IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG), - /* PCIEGBE1_OFF# */ - IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG), - /* PCIEGBE2_OFF# */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), - /* PCIESKT_WDIS# */ - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), -}; - -/* - * each baseboard has 4 user configurable Digital IO lines which can - * be pinmuxed as a GPIO or in some cases a PWM - */ -struct dio_cfg { - iomux_v3_cfg_t gpio_padmux[2]; - unsigned gpio_param; - iomux_v3_cfg_t pwm_padmux[2]; - unsigned pwm_param; -}; - -struct ventana { - /* pinmux */ - iomux_v3_cfg_t const *gpio_pads; - int num_pads; - /* DIO pinmux/val */ - struct dio_cfg dio_cfg[4]; - int num_gpios; - /* various gpios (0 if non-existent) */ - int leds[3]; - int pcie_rst; - int mezz_pwren; - int mezz_irq; - int rs485en; - int gps_shdn; - int vidin_en; - int dioi2c_en; - int pcie_sson; - int usb_sel; - int wdis; -}; - -static struct ventana gpio_cfg[] = { - /* GW5400proto */ - { - .gpio_pads = gw54xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, - IMX_GPIO_NR(1, 9), - { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, - 1 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, - IMX_GPIO_NR(2, 9), - { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, - 3 - }, - { - { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, - IMX_GPIO_NR(2, 10), - { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, - 4 - }, - }, - .num_gpios = 4, - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 10), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), - .mezz_pwren = IMX_GPIO_NR(4, 7), - .mezz_irq = IMX_GPIO_NR(4, 9), - .rs485en = IMX_GPIO_NR(3, 24), - .dioi2c_en = IMX_GPIO_NR(4, 5), - .pcie_sson = IMX_GPIO_NR(1, 20), - }, - - /* GW51xx */ - { - .gpio_pads = gw51xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - { - { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, - IMX_GPIO_NR(1, 18), - { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, - 4 - }, - }, - .num_gpios = 4, - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 10), - }, - .pcie_rst = IMX_GPIO_NR(1, 0), - .mezz_pwren = IMX_GPIO_NR(2, 19), - .mezz_irq = IMX_GPIO_NR(2, 18), - .gps_shdn = IMX_GPIO_NR(1, 2), - .vidin_en = IMX_GPIO_NR(5, 20), - .wdis = IMX_GPIO_NR(7, 12), - }, - - /* GW52xx */ - { - .gpio_pads = gw52xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - { - { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, - IMX_GPIO_NR(1, 20), - { 0, 0 }, - 0 - }, - }, - .num_gpios = 4, - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), - .mezz_pwren = IMX_GPIO_NR(2, 19), - .mezz_irq = IMX_GPIO_NR(2, 18), - .gps_shdn = IMX_GPIO_NR(1, 27), - .vidin_en = IMX_GPIO_NR(3, 31), - .usb_sel = IMX_GPIO_NR(1, 2), - .wdis = IMX_GPIO_NR(7, 12), - }, - - /* GW53xx */ - { - .gpio_pads = gw53xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - { - {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, - IMX_GPIO_NR(1, 20), - { 0, 0 }, - 0 - }, - }, - .num_gpios = 4, - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), - .mezz_pwren = IMX_GPIO_NR(2, 19), - .mezz_irq = IMX_GPIO_NR(2, 18), - .gps_shdn = IMX_GPIO_NR(1, 27), - .vidin_en = IMX_GPIO_NR(3, 31), - .wdis = IMX_GPIO_NR(7, 12), - }, - - /* GW54xx */ - { - .gpio_pads = gw54xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, - IMX_GPIO_NR(1, 9), - { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, - 1 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, - IMX_GPIO_NR(2, 9), - { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, - 3 - }, - { - { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, - IMX_GPIO_NR(2, 10), - { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, - 4 - }, - }, - .num_gpios = 4, - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), - .mezz_pwren = IMX_GPIO_NR(2, 19), - .mezz_irq = IMX_GPIO_NR(2, 18), - .rs485en = IMX_GPIO_NR(7, 1), - .vidin_en = IMX_GPIO_NR(3, 31), - .dioi2c_en = IMX_GPIO_NR(4, 5), - .pcie_sson = IMX_GPIO_NR(1, 20), - .wdis = IMX_GPIO_NR(5, 17), - }, - - /* GW551x */ - { - .gpio_pads = gw551x_gpio_pads, - .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - { - { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, - IMX_GPIO_NR(1, 18), - { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, - 4 - }, - }, - .num_gpios = 2, - .leds = { - IMX_GPIO_NR(4, 7), - }, - .pcie_rst = IMX_GPIO_NR(1, 0), - .wdis = IMX_GPIO_NR(7, 12), - }, - - /* GW552x */ - { - .gpio_pads = gw552x_gpio_pads, - .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - }, - .num_gpios = 4, - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), - .wdis = IMX_GPIO_NR(7, 12), - }, -}; - /* setup board specific PMIC */ int power_init_board(void) { - struct pmic *p; - u32 reg; - - /* configure PFUZE100 PMIC */ - if (board_type == GW54xx || board_type == GW54proto) { - power_pfuze100_init(CONFIG_I2C_PMIC); - p = pmic_get("PFUZE100"); - if (p && !pmic_probe(p)) { - pmic_reg_read(p, PFUZE100_DEVICEID, &reg); - printf("PMIC: PFUZE100 ID=0x%02x\n", reg); - - /* Set VGEN1 to 1.5V and enable */ - pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg); - reg &= ~(LDO_VOL_MASK); - reg |= (LDOA_1_50V | LDO_EN); - pmic_reg_write(p, PFUZE100_VGEN1VOL, reg); - - /* Set SWBST to 5.0V and enable */ - pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg); - reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK); - reg |= (SWBST_5_00V | SWBST_MODE_AUTO); - pmic_reg_write(p, PFUZE100_SWBSTCON1, reg); - } - } - - /* configure LTC3676 PMIC */ - else { - power_ltc3676_init(CONFIG_I2C_PMIC); - p = pmic_get("LTC3676_PMIC"); - if (p && !pmic_probe(p)) { - puts("PMIC: LTC3676\n"); - /* - * set board-specific scalar for max CPU frequency - * per CPU based on the LDO enabled Operating Ranges - * defined in the respective IMX6DQ and IMX6SDL - * datasheets. The voltage resulting from the R1/R2 - * feedback inputs on Ventana is 1308mV. Note that this - * is a bit shy of the Vmin of 1350mV in the datasheet - * for LDO enabled mode but is as high as we can go. - * - * We will rely on an OS kernel driver to properly - * regulate these per CPU operating point and use LDO - * bypass mode when using the higher frequency - * operating points to compensate as LDO bypass mode - * allows the rails be 125mV lower. - */ - /* mask PGOOD during SW1 transition */ - pmic_reg_write(p, LTC3676_DVB1B, - 0x1f | LTC3676_PGOOD_MASK); - /* set SW1 (VDD_SOC) */ - pmic_reg_write(p, LTC3676_DVB1A, 0x1f); - - /* mask PGOOD during SW3 transition */ - pmic_reg_write(p, LTC3676_DVB3B, - 0x1f | LTC3676_PGOOD_MASK); - /* set SW3 (VDD_ARM) */ - pmic_reg_write(p, LTC3676_DVB3A, 0x1f); - } - } - + setup_pmic(board_type); return 0; }

-/* setup GPIO pinmux and default configuration per baseboard */ -static void setup_board_gpio(int board) -{ - struct ventana_board_info *info = &ventana_info; - const char *s; - char arg[10]; - size_t len; - int i; - int quiet = simple_strtol(getenv("quiet"), NULL, 10); - - if (board >= GW_UNKNOWN) - return; - - /* RS232_EN# */ - gpio_request(GP_RS232_EN, "rs232_en"); - gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1); - - /* MSATA Enable */ - if (is_cpu_type(MXC_CPU_MX6Q) && - test_bit(EECONFIG_SATA, info->config)) { - gpio_direction_output(GP_MSATA_SEL, - (hwconfig("msata")) ? 1 : 0); - } - -#if !defined(CONFIG_CMD_PCI) - /* assert PCI_RST# (released by OS when clock is valid) */ - gpio_request(gpio_cfg[board].pcie_rst, "pci_rst#"); - gpio_direction_output(gpio_cfg[board].pcie_rst, 0); -#endif - - /* turn off (active-high) user LED's */ - for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) { - if (gpio_cfg[board].leds[i]) { - gpio_requestf(gpio_cfg[board].leds[i], "led_user%d", i); - gpio_direction_output(gpio_cfg[board].leds[i], 1); - } - } - - /* Expansion Mezzanine IO */ - if (gpio_cfg[board].mezz_pwren) { - gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr"); - gpio_direction_output(gpio_cfg[board].mezz_pwren, 0); - } - if (gpio_cfg[board].mezz_irq) { - gpio_request(gpio_cfg[board].mezz_irq, "mezz_irq#"); - gpio_direction_input(gpio_cfg[board].mezz_irq); - } - - /* RS485 Transmit Enable */ - if (gpio_cfg[board].rs485en) { - gpio_request(gpio_cfg[board].rs485en, "rs485_en"); - gpio_direction_output(gpio_cfg[board].rs485en, 0); - } - - /* GPS_SHDN */ - if (gpio_cfg[board].gps_shdn) { - gpio_request(gpio_cfg[board].gps_shdn, "gps_shdn"); - gpio_direction_output(gpio_cfg[board].gps_shdn, 1); - } - - /* Analog video codec power enable */ - if (gpio_cfg[board].vidin_en) { - gpio_request(gpio_cfg[board].vidin_en, "anavidin_en"); - gpio_direction_output(gpio_cfg[board].vidin_en, 1); - } - - /* DIOI2C_DIS# */ - if (gpio_cfg[board].dioi2c_en) { - gpio_request(gpio_cfg[board].dioi2c_en, "dioi2c_dis#"); - gpio_direction_output(gpio_cfg[board].dioi2c_en, 0); - } - - /* PCICK_SSON: disable spread-spectrum clock */ - if (gpio_cfg[board].pcie_sson) { - gpio_request(gpio_cfg[board].pcie_sson, "pci_sson"); - gpio_direction_output(gpio_cfg[board].pcie_sson, 0); - } - - /* USBOTG Select (PCISKT or FrontPanel) */ - if (gpio_cfg[board].usb_sel) { - gpio_request(gpio_cfg[board].usb_sel, "usb_pcisel"); - gpio_direction_output(gpio_cfg[board].usb_sel, - (hwconfig("usb_pcisel")) ? 1 : 0); - } - - - /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */ - if (gpio_cfg[board].wdis) { - gpio_request(gpio_cfg[board].wdis, "wlan_dis"); - gpio_direction_output(gpio_cfg[board].wdis, 1); - } - - /* - * Configure DIO pinmux/padctl registers - * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions - */ - for (i = 0; i < 4; i++) { - struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; - iomux_v3_cfg_t ctrl = DIO_PAD_CFG; - unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1; - - if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1]) - continue; - sprintf(arg, "dio%d", i); - if (!hwconfig(arg)) - continue; - s = hwconfig_subarg(arg, "padctrl", &len); - if (s) { - ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16) - & 0x1ffff) | MUX_MODE_SION; - } - if (hwconfig_subarg_cmp(arg, "mode", "gpio")) { - if (!quiet) { - printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i, - (cfg->gpio_param/32)+1, - cfg->gpio_param%32, - cfg->gpio_param); - } - imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] | - ctrl); - gpio_requestf(cfg->gpio_param, "dio%d", i); - gpio_direction_input(cfg->gpio_param); - } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") && - cfg->pwm_padmux) { - if (!quiet) - printf("DIO%d: pwm%d\n", i, cfg->pwm_param); - imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] | - MUX_PAD_CTRL(ctrl)); - } - } - - if (!quiet) { - if (is_cpu_type(MXC_CPU_MX6Q) && - (test_bit(EECONFIG_SATA, info->config))) { - printf("MSATA: %s\n", (hwconfig("msata") ? - "enabled" : "disabled")); - } - printf("RS232: %s\n", (hwconfig("rs232")) ? - "enabled" : "disabled"); - } -} - #if defined(CONFIG_CMD_PCI) int imx6_pcie_toggle_reset(void) { @@ -1369,13 +543,10 @@ void get_board_serial(struct tag_serialnr *serialnr) * Board Support */

-/* called from SPL board_init_f() */ int board_early_init_f(void) { setup_iomux_uart();

- gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */ - #if defined(CONFIG_VIDEO_IPUV3) setup_display(); #endif @@ -1405,15 +576,7 @@ int board_init(void) #ifdef CONFIG_MXC_SPI setup_spi(); #endif - if (is_cpu_type(MXC_CPU_MX6Q)) { - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2); - } else { - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2); - } + setup_ventana_i2c();

#ifdef CONFIG_CMD_SATA setup_sata(); @@ -1421,22 +584,7 @@ int board_init(void) /* read Gateworks EEPROM into global struct (used later) */ board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);

- /* board-specifc GPIO iomux */ - SETUP_IOMUX_PADS(gw_gpio_pads); - if (board_type < GW_UNKNOWN) { - iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads; - int count = gpio_cfg[board_type].num_pads; - - imx_iomux_v3_setup_multiple_pads(p, count); - - /* GW522x Uses GPIO3_IO23 for PCIE_RST# */ - if (board_type == GW52xx && ventana_info.model[4] == '2') - gpio_cfg[board_type].pcie_rst = IMX_GPIO_NR(3, 23); - - /* MSATA Enable - default to PCI */ - gpio_request(GP_MSATA_SEL, "msata_en"); - gpio_direction_output(GP_MSATA_SEL, 0); - } + setup_iomux_gpio(board_type, &ventana_info);

return 0; } @@ -1585,8 +733,8 @@ int misc_init_r(void) }

- /* setup baseboard specific GPIO pinmux and config */ - setup_board_gpio(board_type); + /* setup baseboard specific GPIO based on board and env */ + setup_board_gpio(board_type, info);

#ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes);

Avoid requiring board-model and probe pmic by its i2c address. This is in preparation for being able to call pmic_setup() from SPL and not need board type.

Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/common.c | 10 +++++++--- board/gateworks/gw_ventana/common.h | 2 +- board/gateworks/gw_ventana/gw_ventana.c | 2 +- 3 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c index 45c5b4c..5fa5d6a 100644 --- a/board/gateworks/gw_ventana/common.c +++ b/board/gateworks/gw_ventana/common.c @@ -759,13 +759,16 @@ void setup_board_gpio(int board, struct ventana_board_info *info) }

/* setup board specific PMIC */ -void setup_pmic(int board) +void setup_pmic(void) { struct pmic *p; u32 reg;

+ i2c_set_bus_num(CONFIG_I2C_PMIC); + /* configure PFUZE100 PMIC */ - if (board == GW54xx || board == GW54proto) { + if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR)) { + debug("probed PFUZE100@0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR); power_pfuze100_init(CONFIG_I2C_PMIC); p = pmic_get("PFUZE100"); if (p && !pmic_probe(p)) { @@ -787,7 +790,8 @@ void setup_pmic(int board) }

/* configure LTC3676 PMIC */ - else { + else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR)) { + debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR); power_ltc3676_init(CONFIG_I2C_PMIC); p = pmic_get("LTC3676_PMIC"); if (p && !pmic_probe(p)) { diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h index a303b55..b7c0e96 100644 --- a/board/gateworks/gw_ventana/common.h +++ b/board/gateworks/gw_ventana/common.h @@ -89,7 +89,7 @@ void setup_ventana_i2c(void); /* configure uart iomux */ void setup_iomux_uart(void); /* conifgure PMIC */ -void setup_pmic(int board); +void setup_pmic(void); /* configure gpio iomux/defaults */ void setup_iomux_gpio(int board, struct ventana_board_info *); /* late setup of GPIO (configuration per baseboard and env) */ diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 8c6f469..22f3b38 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -468,7 +468,7 @@ static void setup_display(void) /* setup board specific PMIC */ int power_init_board(void) { - setup_pmic(board_type); + setup_pmic(); return 0; }

If the SPL is to be used for Falcon mode then we need to make sure it configures basic GPIO (iomux, padconf, and default output levels).

Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana_spl.c | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 82078a0..cde04cf 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -510,6 +510,9 @@ void board_init_f(ulong dummy) /* read/validate EEPROM info to determine board model and SDRAM cfg */ board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info);

+ /* configure model-specific gpio */ + setup_iomux_gpio(board_model, &ventana_info); + /* provide some some default: 32bit 128MB */ if (GW_UNKNOWN == board_model) { ventana_info.sdram_width = 2;

If the SPL is to be used for Falcon mode then we need to make sure the SPL disable the GSC boot watchdog.

Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana_spl.c | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 1873d99..0d8ccb6 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -527,6 +527,9 @@ void board_init_f(ulong dummy) /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start);

+ /* disable boot watchdog */ + gsc_boot_wd_disable(); + /* load/boot image from boot device */ board_init_r(NULL, 0); }