Signed-off-by: Michael Schwingen michael@schwingen.org --- Changes for V2:

Changes for V3: - reformat to wrap long lines Changes for V4: - add changelog Changes for V5:

arch/arm/cpu/ixp/npe/npe.c | 7 +++++-- 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/ixp/npe/npe.c b/arch/arm/cpu/ixp/npe/npe.c index 857bcad..6d92c53 100644 --- a/arch/arm/cpu/ixp/npe/npe.c +++ b/arch/arm/cpu/ixp/npe/npe.c @@ -621,9 +621,12 @@ int npe_initialize(bd_t * bis) if (ixFeatureCtrlDeviceRead() == IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X) { switch (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK) { case IX_FEATURE_CTRL_SILICON_TYPE_B0: + default: /* newer than B0 */ /* - * If it is B0 Silicon, we only enable port when its corresponding - * Eth Coprocessor is available. + * If it is B0 or newer Silicon, we + * only enable port when its + * corresponding Eth Coprocessor is + * available. */ if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) == IX_FEATURE_CTRL_COMPONENT_ENABLED)

- jump to real flash location after reset before turning off flash mirror - fix timer system to use HZ == 1000, remove broken interrupt-based code

Signed-off-by: Michael Schwingen michael@schwingen.org --- Changes for V2: - fix patch description Changes for V3: - use I/O accessors - move timestamp variable from BSS to global data - coding style fixes Changes for V4: - add changelog Changes for V5: - fix one missing I/O accessor in get_ticks()

arch/arm/cpu/ixp/cpu.c | 5 -- arch/arm/cpu/ixp/start.S | 59 ++-------------- arch/arm/cpu/ixp/timer.c | 124 +++++++++++++++----------------- arch/arm/include/asm/arch-ixp/ixp425.h | 5 +- arch/arm/include/asm/global_data.h | 3 + 5 files changed, 68 insertions(+), 128 deletions(-)

diff --git a/arch/arm/cpu/ixp/cpu.c b/arch/arm/cpu/ixp/cpu.c index ce275e5..942845d 100644 --- a/arch/arm/cpu/ixp/cpu.c +++ b/arch/arm/cpu/ixp/cpu.c @@ -36,8 +36,6 @@ #include <asm/arch/ixp425.h> #include <asm/system.h>

-ulong loops_per_jiffy; - static void cache_flush(void);

#if defined(CONFIG_DISPLAY_CPUINFO) @@ -51,17 +49,14 @@ int print_cpuinfo (void) puts("CPU: Intel IXP425 at "); switch ((id & 0x000003f0) >> 4) { case 0x1c: - loops_per_jiffy = 887467; speed = 533; break;

case 0x1d: - loops_per_jiffy = 666016; speed = 400; break;

case 0x1f: - loops_per_jiffy = 442901; speed = 266; break; } diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S index 561c1f4..faa9a8f 100644 --- a/arch/arm/cpu/ixp/start.S +++ b/arch/arm/cpu/ixp/start.S @@ -65,7 +65,8 @@ .endm

.globl _start -_start: b reset +_start: + ldr pc, _reset ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -74,6 +75,7 @@ _start: b reset ldr pc, _irq ldr pc, _fiq

+_reset: .word reset _undefined_instruction: .word undefined_instruction _software_interrupt: .word software_interrupt _prefetch_abort: .word prefetch_abort @@ -167,12 +169,6 @@ reset: str r1, [r2]

/* make sure flash is visible at 0 */ -#if 0 - ldr r2, =IXP425_EXP_CFG0 - ldr r1, [r2] - orr r1, r1, #0x80000000 - str r1, [r2] -#endif mov r1, #CONFIG_SYS_SDR_CONFIG ldr r2, =IXP425_SDR_CONFIG str r1, [r2] @@ -216,19 +212,6 @@ reset: str r1, [r4] DELAY_FOR 0x4000, r0

- /* copy */ - mov r0, #0 - mov r4, r0 - add r2, r0, #CONFIG_SYS_MONITOR_LEN - mov r1, #0x10000000 - mov r5, r1 - - 30: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r0, r2 - bne 30b - /* invalidate I & D caches & BTB */ mcr p15, 0, r0, c7, c7, 0 CPWAIT r0 @@ -241,19 +224,12 @@ reset: mcr p15, 0, r0, c7, c10, 4 CPWAIT r0

- /* move flash to 0x50000000 */ + /* remove flash mirror at 0x00000000 */ ldr r2, =IXP425_EXP_CFG0 ldr r1, [r2] bic r1, r1, #0x80000000 str r1, [r2]

- nop - nop - nop - nop - nop - nop - /* invalidate I & Data TLB */ mcr p15, 0, r0, c8, c7, 0 CPWAIT r0 @@ -269,7 +245,7 @@ reset: orr r0,r0,#0x13 msr cpsr,r0

-/* Set stackpointer in internal RAM to call board_init_f */ +/* Set initial stackpointer in SDRAM to call board_init_f */ call_board_init_f: ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ @@ -580,28 +556,3 @@ reset_endless:

b reset_endless

-#ifdef CONFIG_USE_IRQ - -.LC0: .word loops_per_jiffy - -/* - * 0 <= r0 <= 2000 - */ -.globl __udelay -__udelay: - mov r2, #0x6800 - orr r2, r2, #0x00db - mul r0, r2, r0 - ldr r2, .LC0 - ldr r2, [r2] @ max = 0x0fffffff - mov r0, r0, lsr #11 @ max = 0x00003fff - mov r2, r2, lsr #11 @ max = 0x0003ffff - mul r0, r2, r0 @ max = 2^32-1 - movs r0, r0, lsr #6 - -delay_loop: - subs r0, r0, #1 - bne delay_loop - mov pc, lr - -#endif /* CONFIG_USE_IRQ */ diff --git a/arch/arm/cpu/ixp/timer.c b/arch/arm/cpu/ixp/timer.c index edf341f..9f3ea42 100644 --- a/arch/arm/cpu/ixp/timer.c +++ b/arch/arm/cpu/ixp/timer.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2010 + * Michael Schwingen, michael@schwingen.org + * * (C) Copyright 2006 * Stefan Roese, DENX Software Engineering, sr@denx.de. * @@ -31,105 +34,94 @@

#include <common.h> #include <asm/arch/ixp425.h> +#include <asm/io.h> +#include <div64.h>

-#ifdef CONFIG_TIMER_IRQ - -#define FREQ 66666666 -#define CLOCK_TICK_RATE (((FREQ / CONFIG_SYS_HZ & ~IXP425_OST_RELOAD_MASK) + 1) * CONFIG_SYS_HZ) -#define LATCH ((CLOCK_TICK_RATE + CONFIG_SYS_HZ/2) / CONFIG_SYS_HZ) /* For divider */ +DECLARE_GLOBAL_DATA_PTR;

/* - * When interrupts are enabled, use timer 2 for time/delay generation... + * The IXP42x time-stamp timer runs at 2*OSC_IN (66.666MHz when using a + * 33.333MHz crystal). */ - -static volatile ulong timestamp; - -static void timer_isr(void *data) +static inline unsigned long long tick_to_time(unsigned long long tick) { - unsigned int *pTime = (unsigned int *)data; - - (*pTime)++; - - /* - * Reset IRQ source - */ - *IXP425_OSST = IXP425_OSST_TIMER_2_PEND; + tick *= CONFIG_SYS_HZ; + do_div(tick, CONFIG_IXP425_TIMER_CLK); + return tick; }

-ulong get_timer (ulong base) +static inline unsigned long long time_to_tick(unsigned long long time) { - return timestamp - base; + time *= CONFIG_IXP425_TIMER_CLK; + do_div(time, CONFIG_SYS_HZ); + return time; }

-void reset_timer (void) +static inline unsigned long long us_to_tick(unsigned long long us) { - timestamp = 0; + us = us * CONFIG_IXP425_TIMER_CLK + 999999; + do_div(us, 1000000); + return us; }

-int timer_init (void) +unsigned long long get_ticks(void) { - /* install interrupt handler for timer */ - irq_install_handler(IXP425_TIMER_2_IRQ, timer_isr, (void *)&timestamp); - - /* setup the Timer counter value */ - *IXP425_OSRT2 = (LATCH & ~IXP425_OST_RELOAD_MASK) | IXP425_OST_ENABLE; + ulong now = readl(IXP425_OSTS_B); + + if (readl(IXP425_OSST) & IXP425_OSST_TIMER_TS_PEND) { + /* rollover of timestamp timer register */ + gd->timestamp += (0xFFFFFFFF - gd->lastinc) + now + 1; + writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST); + } else { + /* move stamp forward with absolut diff ticks */ + gd->timestamp += (now - gd->lastinc); + } + gd->lastinc = now; + return gd->timestamp; +}

- /* enable timer irq */ - *IXP425_ICMR = (1 << IXP425_TIMER_2_IRQ);

- return 0; -} -#else -ulong get_timer (ulong base) +void reset_timer_masked(void) { - return get_timer_masked () - base; + /* capture current timestamp counter */ + gd->lastinc = readl(IXP425_OSTS_B); + /* start "advancing" time stamp from 0 */ + gd->timestamp = 0; }

-void ixp425_udelay(unsigned long usec) +void reset_timer(void) { - /* - * This function has a max usec, but since it is called from udelay - * we should not have to worry... be happy - */ - unsigned long usecs = CONFIG_SYS_HZ/1000000L & ~IXP425_OST_RELOAD_MASK; - - *IXP425_OSST = IXP425_OSST_TIMER_1_PEND; - usecs |= IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE; - *IXP425_OSRT1 = usecs; - while (!(*IXP425_OSST & IXP425_OSST_TIMER_1_PEND)); + reset_timer_masked(); }

-void __udelay (unsigned long usec) +ulong get_timer_masked(void) { - while (usec--) ixp425_udelay(1); + return tick_to_time(get_ticks()); }

-static ulong reload_constant = 0xfffffff0; - -void reset_timer_masked (void) +ulong get_timer(ulong base) { - ulong reload = reload_constant | IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE; + return get_timer_masked() - base; +}

- *IXP425_OSST = IXP425_OSST_TIMER_1_PEND; - *IXP425_OSRT1 = reload; +void set_timer(ulong t) +{ + gd->timestamp = time_to_tick(t); }

-ulong get_timer_masked (void) +/* delay x useconds AND preserve advance timestamp value */ +void __udelay(unsigned long usec) { - /* - * Note that it is possible for this to wrap! - * In this case we return max. - */ - ulong current = *IXP425_OST1; - if (*IXP425_OSST & IXP425_OSST_TIMER_1_PEND) - { - return reload_constant; - } - return (reload_constant - current); + unsigned long long tmp; + + tmp = get_ticks() + us_to_tick(usec); + + while (get_ticks() < tmp) + ; }

int timer_init(void) { + writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST); return 0; } -#endif diff --git a/arch/arm/include/asm/arch-ixp/ixp425.h b/arch/arm/include/asm/arch-ixp/ixp425.h index 2114437..5132607 100644 --- a/arch/arm/include/asm/arch-ixp/ixp425.h +++ b/arch/arm/include/asm/arch-ixp/ixp425.h @@ -391,9 +391,8 @@ #define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x)) #endif

-#if 0 /* test-only: also defined in npe/include/... */ -#define IXP425_OSTS IXP425_TIMER_REG(IXP425_OSTS_OFFSET) -#endif +/* _B to avoid collision: also defined in npe/include/... */ +#define IXP425_OSTS_B IXP425_TIMER_REG(IXP425_OSTS_OFFSET) #define IXP425_OST1 IXP425_TIMER_REG(IXP425_OST1_OFFSET) #define IXP425_OSRT1 IXP425_TIMER_REG(IXP425_OSRT1_OFFSET) #define IXP425_OST2 IXP425_TIMER_REG(IXP425_OST2_OFFSET) diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 2a84d27..c1a59f2 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -64,6 +64,9 @@ typedef struct global_data { unsigned long long timer_reset_value; unsigned long lastinc; #endif +#ifdef CONFIG_IXP425 + unsigned long timestamp; +#endif unsigned long relocaddr; /* Start address of U-Boot in RAM */ phys_size_t ram_size; /* RAM size */ unsigned long mon_len; /* monitor len */

Signed-off-by: Michael Schwingen michael@schwingen.org --- Changes for V3: - new in V3, replaces config.mk files in earlier patches Changes for V4: - add changelog Changes for V5:

arch/arm/config.mk | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/arch/arm/config.mk b/arch/arm/config.mk index ec1b420..788d4c1 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -62,6 +62,13 @@ PLATFORM_LIBS += $(OBJTREE)/arch/arm/lib/eabi_compat.o endif endif

+ifdef CONFIG_SYS_LDSCRIPT +# need to strip off double quotes +LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT)) +else +LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds +endif + # needed for relocation ifndef CONFIG_NAND_SPL LDFLAGS_u-boot += -pie

Signed-off-by: Michael Schwingen michael@schwingen.org --- Changes for V2: - move -ffunction-sections/--gc-sections to board config.mk - add wildcard to bss segment in linker script Changes for V3: - use I/O accessors - coding style fixes - add PCI clock/reset initialization - use get_ram_size in dram_init - add PCI support - remove config.mk - remove unused definitions from config.h - add CONFIG_BOARD_SIZE_LIMIT Changes for V4: - add changelog - merge __bss_end change in u-boot.lds from master Changes for V5: board/actux1/actux1.c | 105 ++++++++++++++++++++++++---------------------- board/actux1/config.mk | 4 -- board/actux1/u-boot.lds | 41 +++++++++++++----- boards.cfg | 5 ++- include/configs/actux1.h | 62 ++++++++++++++++----------- 5 files changed, 124 insertions(+), 93 deletions(-) delete mode 100644 board/actux1/config.mk

diff --git a/board/actux1/actux1.c b/board/actux1/actux1.c index 85e3f9e..2f631b7 100644 --- a/board/actux1/actux1.c +++ b/board/actux1/actux1.c @@ -37,49 +37,57 @@ #include <asm/arch/ixp425.h> #include <asm/io.h> #include <miiphy.h> +#ifdef CONFIG_PCI +#include <pci.h> +#include <asm/arch/ixp425pci.h> +#endif

#include "actux1_hw.h"

DECLARE_GLOBAL_DATA_PTR;

-int board_init (void) +int board_early_init_f(void) +{ + /* CS5: Debug port */ + writel(0x9d520003, IXP425_EXP_CS5); + /* CS6: HwRel */ + writel(0x81860001, IXP425_EXP_CS6); + /* CS7: LEDs */ + writel(0x80900003, IXP425_EXP_CS7); + return 0; +} + +int board_init(void) { gd->bd->bi_arch_number = MACH_TYPE_ACTUX1;

/* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100;

- GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);

- /* Setup GPIO's for PCI INTA */ - GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI1_INTA); - GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI1_INTA); + /* Setup GPIOs for PCI INTA */ + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI1_INTA); + GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI1_INTA);

- /* Setup GPIO's for 33MHz clock output */ - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK); - *IXP425_GPIO_GPCLKR = 0x011001FF; + /* Setup GPIOs for 33MHz clock output */ + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); + writel(0x011001FF, IXP425_GPIO_GPCLKR);

- /* CS5: Debug port */ - *IXP425_EXP_CS5 = 0x9d520003; - /* CS6: HwRel */ - *IXP425_EXP_CS6 = 0x81860001; - /* CS7: LEDs */ - *IXP425_EXP_CS7 = 0x80900003; - - udelay (533); - GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST); + udelay(533); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);

- ACTUX1_LED1 (2); - ACTUX1_LED2 (2); - ACTUX1_LED3 (0); - ACTUX1_LED4 (0); - ACTUX1_LED5 (0); - ACTUX1_LED6 (0); - ACTUX1_LED7 (0); + ACTUX1_LED1(2); + ACTUX1_LED2(2); + ACTUX1_LED3(0); + ACTUX1_LED4(0); + ACTUX1_LED5(0); + ACTUX1_LED6(0); + ACTUX1_LED7(0);

- ACTUX1_HS (ACTUX1_HS_DCD); + ACTUX1_HS(ACTUX1_HS_DCD);

return 0; } @@ -87,21 +95,21 @@ int board_init (void) /* * Check Board Identity */ -int checkboard (void) +int checkboard(void) { char buf[64]; int i = getenv_f("serial#", buf, sizeof(buf));

- puts ("Board: AcTux-1 rev."); - putc (ACTUX1_BOARDREL + 'A' - 1); + puts("Board: AcTux-1 rev."); + putc(ACTUX1_BOARDREL + 'A' - 1);

if (i > 0) { puts(", serial# "); puts(buf); } - putc ('\n'); + putc('\n');

- return (0); + return 0; }

/************************************************************************* @@ -110,39 +118,36 @@ int checkboard (void) * 1 = Rev. A * 2 = Rev. B *************************************************************************/ -u32 get_board_rev (void) +u32 get_board_rev(void) { return ACTUX1_BOARDREL; }

-int dram_init (void) +int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); + gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); + return 0; }

-#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) -extern struct pci_controller hose; -extern void pci_ixp_init (struct pci_controller *hose);

-void pci_init_board (void) +#ifdef CONFIG_PCI +struct pci_controller hose; + +void pci_init_board(void) { - extern void pci_ixp_init (struct pci_controller *hose); - pci_ixp_init (&hose); + pci_ixp_init(&hose); } #endif

-void reset_phy (void) +void reset_phy(void) { u16 id1, id2;

/* initialize the PHY */ - miiphy_reset ("NPE0", CONFIG_PHY_ADDR); + miiphy_reset("NPE0", CONFIG_PHY_ADDR);

- miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1); - miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2); + miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1); + miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2);

id2 &= 0xFFF0; /* mask out revision bits */

@@ -153,9 +158,9 @@ void reset_phy (void) * LED2 (unused) = LINK, * LED3(red) = Coll */ - miiphy_write ("NPE0", CONFIG_PHY_ADDR, 20, 0xD432); + miiphy_write("NPE0", CONFIG_PHY_ADDR, 20, 0xD432); } else if (id1 == 0x143 && id2 == 0xbc30) { /* BCM5241: default values are OK */ } else - printf ("unknown ethernet PHY ID: %x %x\n", id1, id2); + printf("unknown ethernet PHY ID: %x %x\n", id1, id2); } diff --git a/board/actux1/config.mk b/board/actux1/config.mk deleted file mode 100644 index 9cb838b..0000000 --- a/board/actux1/config.mk +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x00e00000 - -# include NPE ethernet driver -BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds index 8be2b20..9dbaa6f 100644 --- a/board/actux1/u-boot.lds +++ b/board/actux1/u-boot.lds @@ -30,15 +30,15 @@ SECTIONS

. = ALIGN (4); .text : { - arch/arm/cpu/ixp/start.o(.text) - lib/string.o(.text) - lib/vsprintf.o(.text) - arch/arm/lib/board.o(.text) - common/dlmalloc.o(.text) - arch/arm/cpu/ixp/cpu.o(.text) + arch/arm/cpu/ixp/start.o(.text*) + net/libnet.o(.text*) + board/actux1/libactux1.o(.text*) + arch/arm/cpu/ixp/libixp.o(.text*) + drivers/serial/libserial.o(.text*) + . = env_offset; common/env_embedded.o(.ppcenv) - * (.text) + *(.text*) }

. = ALIGN (4); @@ -47,7 +47,7 @@ SECTIONS } . = ALIGN (4); .data : { - *(.data) + *(.data*) } . = ALIGN (4); .got : { @@ -61,10 +61,27 @@ SECTIONS __u_boot_cmd_end =.;

. = ALIGN (4); - __bss_start =.; - .bss (NOLOAD): { - *(.bss) - . = ALIGN(4); + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss*) + . = ALIGN(4); + _end = .; } __bss_end__ =.; + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } } diff --git a/boards.cfg b/boards.cfg index 9f2b118..da5120c 100644 --- a/boards.cfg +++ b/boards.cfg @@ -151,7 +151,10 @@ smdkc100 arm armv7 smdkc100 samsung s5pc210_universal arm armv7 universal_c210 samsung s5pc2xx harmony arm armv7 harmony nvidia tegra2 seaboard arm armv7 seaboard nvidia tegra2 -actux1 arm ixp +actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 +actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8 +actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB +actux1_8_32 arm ixp actux1 - - actux1:FLASH1X8,RAM_32MB actux2 arm ixp actux3 arm ixp actux4 arm ixp diff --git a/include/configs/actux1.h b/include/configs/actux1.h index 8121b27..160c10a 100644 --- a/include/configs/actux1.h +++ b/include/configs/actux1.h @@ -26,13 +26,6 @@ #ifndef __CONFIG_H #define __CONFIG_H

-/* 1: modified board with 32MB DRAM */ -#define CONFIG_ACTUX1_32MB 0 -/* 1: 2*2MB FLASH (standard) */ -#define CONFIG_ACTUX1_FLASH2X2 1 -/* 1: 1*8MB FLASH (upgraded boards) */ -#define CONFIG_ACTUX1_FLASH1X8 0 - #define CONFIG_IXP425 1 #define CONFIG_ACTUX1 1

@@ -44,12 +37,12 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_SYS_LDSCRIPT "board/actux1/u-boot.lds"

/*************************************************************** * U-boot generic defines start here. ***************************************************************/ -#undef CONFIG_USE_IRQ - /* * Size of malloc() pool */ @@ -62,8 +55,13 @@ #include <config_cmd_default.h>

#define CONFIG_CMD_ELF -#undef CONFIG_CMD_PCI -#undef CONFIG_PCI +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_PCI_PNP +#define CONFIG_IXP_PCI +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI_ENUM +#endif

#define CONFIG_BOOTCOMMAND "run boot_flash" /* enable passing of ATAGs */ @@ -93,8 +91,9 @@ #define CONFIG_SYS_MEMTEST_START 0x00400000 #define CONFIG_SYS_MEMTEST_END 0x00800000

-/* spec says 66.666 MHz, but it appears to be 33 */ -#define CONFIG_SYS_HZ 3333333 +/* timer clock - 2* OSC_IN system clock */ +#define CONFIG_IXP425_TIMER_CLK 66666666 +#define CONFIG_SYS_HZ 1000

/* default load address */ #define CONFIG_SYS_LOAD_ADDR 0x00010000 @@ -109,10 +108,6 @@ * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -# define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -# define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif

/* Expansion bus settings */ #define CONFIG_SYS_EXP_CS0 0xbd113842 @@ -120,9 +115,9 @@ /* SDRAM settings */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_DRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000

-#if CONFIG_ACTUX1_32MB +#ifdef CONFIG_RAM_32MB # define CONFIG_SYS_SDR_CONFIG 0x18 # define PHYS_SDRAM_1_SIZE 0x02000000 # define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a @@ -136,8 +131,11 @@ # define CONFIG_SYS_DRAM_SIZE 0x01000000 #endif

+ + /* FLASH organization */ -#if CONFIG_ACTUX1_FLASH2X2 +#define CONFIG_SYS_TEXT_BASE 0x50000000 +#ifdef CONFIG_FLASH2X2 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of sectors on one chip */ # define CONFIG_SYS_MAX_FLASH_SECT 40 @@ -145,7 +143,7 @@ # define PHYS_FLASH_2 0x50200000 # define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } #endif -#if CONFIG_ACTUX1_FLASH1X8 +#ifdef CONFIG_FLASH1X8 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of sectors on one chip */ # define CONFIG_SYS_MAX_FLASH_SECT 140 @@ -156,6 +154,7 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 #define CONFIG_SYS_MONITOR_LEN (256 << 10) +#define CONFIG_BOARD_SIZE_LIMIT 262144

/* Use common CFI driver */ #define CONFIG_SYS_FLASH_CFI @@ -172,12 +171,16 @@ #define CONFIG_NET_MULTI 1 /* NPE0 PHY address */ #define CONFIG_PHY_ADDR 0 +/* NPE1 PHY address (HW Release E only) */ +#define CONFIG_PHY1_ADDR 1 /* MII PHY management */ #define CONFIG_MII 1 /* Number of ethernet rx buffers & descriptors */ #define CONFIG_SYS_RX_ETH_BUFFER 16 #define CONFIG_RESET_PHY_R 1

+#define CONFIG_HAS_ETH1 1 + #define CONFIG_CMD_DHCP #define CONFIG_CMD_NET #define CONFIG_CMD_MII @@ -202,17 +205,19 @@ #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) #define CONFIG_SYS_USE_PPCENV 1

-#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CONFIG_EXTRA_ENV_SETTINGS \ "npe_ucode=50040000\0" \ "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ "kerneladdr=50050000\0" \ + "kernelfile=actux1/uImage\0" \ + "rootfile=actux1/rootfs\0" \ "rootaddr=50170000\0" \ "loadaddr=10000\0" \ "updateboot_ser=mw.b 10000 ff 40000;" \ " loady ${loadaddr};" \ " run eraseboot writeboot\0" \ "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} u-boot.bin;" \ + " tftp ${loadaddr} actux1/u-boot.bin;" \ " run eraseboot writeboot\0" \ "eraseboot=protect off 50000000 50003fff;" \ " protect off 50006000 5003ffff;" \ @@ -220,8 +225,9 @@ " erase 50006000 5003ffff\0" \ "writeboot=cp.b 10000 50000000 4000;" \ " cp.b 16000 50006000 3a000\0" \ - "eraseenv=protect off 50004000 50005fff;" \ - " erase 50004000 50005fff\0" \ + "updateucode=loady;" \ + " era ${npe_ucode} +${filesize};" \ + " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ "updateroot=tftp ${loadaddr} ${rootfile};" \ " era ${rootaddr} +${filesize};" \ " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ @@ -232,7 +238,7 @@ " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \ "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ "boot_flash=run flashargs addtty addeth;" \ " bootm ${kerneladdr}\0" \ @@ -240,4 +246,8 @@ " tftpboot ${loadaddr} ${kernelfile};" \ " bootm\0"

+/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + #endif /* __CONFIG_H */

Signed-off-by: Michael Schwingen michael@schwingen.org --- Changes for V2: - move -ffunction-sections/--gc-sections to board config.mk - add wildcard to bss segment in linker script Changes for V3: - use I/O accessors - coding style fixes - use get_ram_size in dram_init - remove config.mk - remove unused definitions from config.h - add CONFIG_BOARD_SIZE_LIMIT - add CONFIG_MII_NPE0_FIXEDLINK definition Changes for V4: - add changelog - merge __bss_end change in u-boot.lds from master Changes for V5:

board/actux3/actux3.c | 120 +++++++++++++++++++++++---------------------- board/actux3/config.mk | 4 -- board/actux3/u-boot.lds | 52 ++++++++++++-------- include/configs/actux3.h | 37 +++++++++----- 4 files changed, 117 insertions(+), 96 deletions(-) delete mode 100644 board/actux3/config.mk

diff --git a/board/actux3/actux3.c b/board/actux3/actux3.c index bace254..64e5215 100644 --- a/board/actux3/actux3.c +++ b/board/actux3/actux3.c @@ -36,72 +36,76 @@ #include <malloc.h> #include <asm/arch/ixp425.h> #include <asm/io.h> - #include <miiphy.h> - #include "actux3_hw.h"

DECLARE_GLOBAL_DATA_PTR;

-int board_init (void) +int board_early_init_f(void) +{ + /* CS1: IPAC-X */ + writel(0x94d10013, IXP425_EXP_CS1); + /* CS5: Debug port */ + writel(0x9d520003, IXP425_EXP_CS5); + /* CS6: Release/Option register */ + writel(0x81860001, IXP425_EXP_CS6); + /* CS7: LEDs */ + writel(0x80900003, IXP425_EXP_CS7); + + return 0; +} + +int board_init(void) { gd->bd->bi_arch_number = MACH_TYPE_ACTUX3;

/* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100;

- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED5_GN); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_RT); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_GN); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED5_GN); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_RT); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_GN);

- GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST);

- GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR); - GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD);

- GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED5_GN); - GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_RT); - GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_GN); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED5_GN); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_RT); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_GN);

/* * Setup GPIO's for Interrupt inputs */ - GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT); - GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT);

/* * Setup GPIO's for 33MHz clock output */ - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK); - *IXP425_GPIO_GPCLKR = 0x011001FF; - - /* CS1: IPAC-X */ - *IXP425_EXP_CS1 = 0x94d10013; - /* CS5: Debug port */ - *IXP425_EXP_CS5 = 0x9d520003; - /* CS6: Release/Option register */ - *IXP425_EXP_CS6 = 0x81860001; - /* CS7: LEDs */ - *IXP425_EXP_CS7 = 0x80900003; - - udelay (533); - GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST); - - ACTUX3_LED1_RT (1); - ACTUX3_LED1_GN (0); - ACTUX3_LED2_RT (0); - ACTUX3_LED2_GN (0); - ACTUX3_LED3_RT (0); - ACTUX3_LED3_GN (0); - ACTUX3_LED4_GN (0); - ACTUX3_LED5_RT (0); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); + writel(0x011001FF, IXP425_GPIO_GPCLKR); + + /* we need a minimum PCI reset pulse width after enabling the clock */ + udelay(533); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST); + + ACTUX3_LED1_RT(1); + ACTUX3_LED1_GN(0); + ACTUX3_LED2_RT(0); + ACTUX3_LED2_GN(0); + ACTUX3_LED3_RT(0); + ACTUX3_LED3_GN(0); + ACTUX3_LED4_GN(0); + ACTUX3_LED5_RT(0);

return 0; } @@ -109,21 +113,21 @@ int board_init (void) /* * Check Board Identity */ -int checkboard (void) +int checkboard(void) { char buf[64]; int i = getenv_f("serial#", buf, sizeof(buf));

- puts ("Board: AcTux-3 rev."); - putc (ACTUX3_BOARDREL + 'A' - 1); + puts("Board: AcTux-3 rev."); + putc(ACTUX3_BOARDREL + 'A' - 1);

if (i > 0) { puts (", serial# "); puts (buf); } - putc ('\n'); + putc('\n');

- return (0); + return 0; }

/************************************************************************* @@ -132,34 +136,32 @@ int checkboard (void) * 1 = Rev. A * 2 = Rev. B *************************************************************************/ -u32 get_board_rev (void) +u32 get_board_rev(void) { return ACTUX3_BOARDREL; }

-int dram_init (void) +int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); + gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); + return 0; }

-void reset_phy (void) +void reset_phy(void) { int i;

/* initialize the PHY */ - miiphy_reset ("NPE0", CONFIG_PHY_ADDR); + miiphy_reset("NPE0", CONFIG_PHY_ADDR);

/* all LED outputs = Link/Act */ - miiphy_write ("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA); + miiphy_write("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA);

/* * The Marvell 88E6060 switch comes up with all ports disabled. * set all ethernet switch ports to forwarding state */ for (i = 1; i <= 5; i++) - miiphy_write ("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03); + miiphy_write("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03);

} diff --git a/board/actux3/config.mk b/board/actux3/config.mk deleted file mode 100644 index 9cb838b..0000000 --- a/board/actux3/config.mk +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x00e00000 - -# include NPE ethernet driver -BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds index d3463cd..35aab29 100644 --- a/board/actux3/u-boot.lds +++ b/board/actux3/u-boot.lds @@ -30,34 +30,29 @@ SECTIONS

. = ALIGN (4); .text : { - arch/arm/cpu/ixp/start.o (.text) - lib/string.o (.text) - lib/vsprintf.o (.text) - arch/arm/lib/board.o (.text) - common/dlmalloc.o (.text) - arch/arm/cpu/ixp/cpu.o (.text) + arch/arm/cpu/ixp/start.o(.text*) + net/libnet.o(.text*) + board/actux3/libactux3.o(.text*) + arch/arm/cpu/ixp/libixp.o(.text*) + drivers/serial/libserial.o(.text*)

. = env_offset; - common/env_embedded.o (.ppcenv) - - * (.text) + common/env_embedded.o(.ppcenv) + *(.text*) }

- . = ALIGN (4); + . = ALIGN(4); .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN (4); + . = ALIGN(4); .data : { - *(.data) + *(.data*) } - - . = ALIGN (4); + . = ALIGN(4); .got : { *(.got) } - . =.; __u_boot_cmd_start =.; .u_boot_cmd : { @@ -66,10 +61,27 @@ SECTIONS __u_boot_cmd_end =.;

. = ALIGN (4); - __bss_start =.; - .bss (NOLOAD): { - *(.bss) - . = ALIGN(4); + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss*) + . = ALIGN(4); + _end = .; } __bss_end__ =.; + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } } diff --git a/include/configs/actux3.h b/include/configs/actux3.h index 91987cb..c103312 100644 --- a/include/configs/actux3.h +++ b/include/configs/actux3.h @@ -37,12 +37,12 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_SYS_LDSCRIPT "board/actux3/u-boot.lds"

/*************************************************************** * U-boot generic defines start here. ***************************************************************/ -#undef CONFIG_USE_IRQ - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)

@@ -82,8 +82,9 @@ #define CONFIG_SYS_MEMTEST_START 0x00400000 #define CONFIG_SYS_MEMTEST_END 0x00800000

-/* spec says 66.666 MHz, but it appears to be 33 */ -#define CONFIG_SYS_HZ 3333333 +/* timer clock - 2* OSC_IN system clock */ +#define CONFIG_IXP425_TIMER_CLK 66666666 +#define CONFIG_SYS_HZ 1000

/* default load address */ #define CONFIG_SYS_LOAD_ADDR 0x00010000 @@ -99,10 +100,6 @@ * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -# define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -# define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif

/* Expansion bus settings */ #define CONFIG_SYS_EXP_CS0 0xbd113442 @@ -110,7 +107,7 @@ /* SDRAM settings */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_DRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000

/* 16MB SDRAM */ #define CONFIG_SYS_SDR_CONFIG 0x3A @@ -120,6 +117,7 @@ #define CONFIG_SYS_DRAM_SIZE 0x01000000

/* FLASH organization */ +#define CONFIG_SYS_TEXT_BASE 0x50000000 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of sectors on one chip */ #define CONFIG_SYS_MAX_FLASH_SECT 140 @@ -129,6 +127,7 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 #define CONFIG_SYS_MONITOR_LEN (256 << 10) +#define CONFIG_BOARD_SIZE_LIMIT 262144

/* Use common CFI driver */ #define CONFIG_SYS_FLASH_CFI @@ -149,6 +148,11 @@ #define CONFIG_PHY_ADDR 0x10 /* MII PHY management */ #define CONFIG_MII 1 +/* fixed-speed switch without standard PHY registers on MII */ +#define CONFIG_MII_NPE0_FIXEDLINK 1 +#define CONFIG_MII_NPE0_SPEED 100 +#define CONFIG_MII_NPE0_FULLDUPLEX 1 + /* Number of ethernet rx buffers & descriptors */ #define CONFIG_SYS_RX_ETH_BUFFER 16 #define CONFIG_RESET_PHY_R 1 @@ -183,13 +187,15 @@ "npe_ucode=50040000\0" \ "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ "kerneladdr=50050000\0" \ + "kernelfile=actux3/uImage\0" \ + "rootfile=actux3/rootfs\0" \ "rootaddr=50170000\0" \ "loadaddr=10000\0" \ "updateboot_ser=mw.b 10000 ff 40000;" \ " loady ${loadaddr};" \ " run eraseboot writeboot\0" \ "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} u-boot.bin;" \ + " tftp ${loadaddr} actux3/u-boot.bin;" \ " run eraseboot writeboot\0" \ "eraseboot=protect off 50000000 50003fff;" \ " protect off 50006000 5003ffff;" \ @@ -197,8 +203,9 @@ " erase 50006000 5003ffff\0" \ "writeboot=cp.b 10000 50000000 4000;" \ " cp.b 16000 50006000 3a000\0" \ - "eraseenv=protect off 50004000 50005fff;" \ - " erase 50004000 50005fff\0" \ + "updateucode=loady;" \ + " era ${npe_ucode} +${filesize};" \ + " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ "updateroot=tftp ${loadaddr} ${rootfile};" \ " era ${rootaddr} +${filesize};" \ " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ @@ -209,7 +216,7 @@ " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \ "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ "boot_flash=run flashargs addtty addeth;" \ " bootm ${kerneladdr}\0" \ @@ -217,4 +224,8 @@ " tftpboot ${loadaddr} ${kernelfile};" \ " bootm\0"

+/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + #endif /* __CONFIG_H */

Signed-off-by: Michael Schwingen michael@schwingen.org --- Changes for V2: Changes for V3: - coding style / indentation cleanup - move config.h changes to AcTux2/AcTux3 board patches Changes for V4: - add changelog Changes for V5:

arch/arm/cpu/ixp/npe/npe.c | 67 +++++++++++++++++++++++++++---------------- 1 files changed, 42 insertions(+), 25 deletions(-)

diff --git a/arch/arm/cpu/ixp/npe/npe.c b/arch/arm/cpu/ixp/npe/npe.c index 6d92c53..f0e02bf 100644 --- a/arch/arm/cpu/ixp/npe/npe.c +++ b/arch/arm/cpu/ixp/npe/npe.c @@ -359,36 +359,53 @@ static int npe_init(struct eth_device *dev, bd_t * bis)

debug("%s: 1\n", __FUNCTION__);

- miiphy_read (dev->name, p_npe->phy_no, MII_BMSR, &reg_short); - - /* - * Wait if PHY is capable of autonegotiation and autonegotiation is not complete - */ - if ((reg_short & BMSR_ANEGCAPABLE) && !(reg_short & BMSR_ANEGCOMPLETE)) { - puts ("Waiting for PHY auto negotiation to complete"); - i = 0; - while (!(reg_short & BMSR_ANEGCOMPLETE)) { - /* - * Timeout reached ? - */ - if (i > PHY_AUTONEGOTIATE_TIMEOUT) { - puts (" TIMEOUT !\n"); - break; - } +#ifdef CONFIG_MII_NPE0_FIXEDLINK + if (0 == p_npe->eth_id) { + speed = CONFIG_MII_NPE0_SPEED; + duplex = CONFIG_MII_NPE0_FULLDUPLEX ? FULL : HALF; + } else +#endif +#ifdef CONFIG_MII_NPE1_FIXEDLINK + if (1 == p_npe->eth_id) { + speed = CONFIG_MII_NPE1_SPEED; + duplex = CONFIG_MII_NPE1_FULLDUPLEX ? FULL : HALF; + } else +#endif + { + miiphy_read(dev->name, p_npe->phy_no, MII_BMSR, &reg_short); + + /* + * Wait if PHY is capable of autonegotiation and + * autonegotiation is not complete + */ + if ((reg_short & BMSR_ANEGCAPABLE) && + !(reg_short & BMSR_ANEGCOMPLETE)) { + puts("Waiting for PHY auto negotiation to complete"); + i = 0; + while (!(reg_short & BMSR_ANEGCOMPLETE)) { + /* + * Timeout reached ? + */ + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + puts(" TIMEOUT !\n"); + break; + }

- if ((i++ % 1000) == 0) { - putc ('.'); - miiphy_read (dev->name, p_npe->phy_no, MII_BMSR, &reg_short); + if ((i++ % 1000) == 0) { + putc('.'); + miiphy_read(dev->name, p_npe->phy_no, + MII_BMSR, &reg_short); + } + udelay(1000); /* 1 ms */ } - udelay (1000); /* 1 ms */ + puts(" done\n"); + /* another 500 ms (results in faster booting) */ + udelay(500000); } - puts (" done\n"); - udelay (500000); /* another 500 ms (results in faster booting) */ + speed = miiphy_speed(dev->name, p_npe->phy_no); + duplex = miiphy_duplex(dev->name, p_npe->phy_no); }

- speed = miiphy_speed (dev->name, p_npe->phy_no); - duplex = miiphy_duplex (dev->name, p_npe->phy_no); - if (p_npe->print_speed) { p_npe->print_speed = 0; printf ("ENET Speed is %d Mbps - %s duplex connection\n",

Signed-off-by: Michael Schwingen michael@schwingen.org --- Changes for V3: - new in V3 (split from "update_fix some more IXP42x boards" in V2) Changes for V4: - add changelog Changes for V5:

board/ixdp425/config.mk | 2 - board/ixdp425/flash.c | 427 -------------------------------------------- board/ixdp425/ixdp425.c | 155 ++++++++++++++--- boards.cfg | 2 +- include/configs/ixdp425.h | 196 ++++++++++++++------- include/configs/ixdpg425.h | 11 +- 6 files changed, 276 insertions(+), 517 deletions(-) delete mode 100644 board/ixdp425/config.mk delete mode 100644 board/ixdp425/flash.c

diff --git a/board/ixdp425/config.mk b/board/ixdp425/config.mk deleted file mode 100644 index 509c894..0000000 --- a/board/ixdp425/config.mk +++ /dev/null @@ -1,2 +0,0 @@ -# -CONFIG_SYS_TEXT_BASE = 0x00f80000 diff --git a/board/ixdp425/flash.c b/board/ixdp425/flash.c deleted file mode 100644 index f1d9190..0000000 --- a/board/ixdp425/flash.c +++ /dev/null @@ -1,427 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <linux/byteorder/swab.h> - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) x -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - - switch (value) { - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer_masked () > - CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = (FPW) 0x00500050; /* clear status register cmd. */ - *addr = (FPW) 0x00FF00FF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, - (ulong) * addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/ixdp425/ixdp425.c b/board/ixdp425/ixdp425.c index a29d584..7269458 100644 --- a/board/ixdp425/ixdp425.c +++ b/board/ixdp425/ixdp425.c @@ -33,24 +33,82 @@ #include <malloc.h> #include <netdev.h> #include <asm/arch/ixp425.h> +#include <asm/io.h> +#ifdef CONFIG_PCI +#include <pci.h> +#include <asm/arch/ixp425pci.h> +#endif

DECLARE_GLOBAL_DATA_PTR;

+#define IXDP425_LED_PORT 0x52000000 /* 4-digit hex display */ + +int board_early_init_f(void) +{ + /* CS2: LED port */ + writel(0xbcff0002, IXP425_EXP_CS2); + writew(0x0001, IXDP425_LED_PORT); /* output postcode to LEDs */ + + return 0; +} + +#ifdef CONFIG_PCI +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_ixpdp425_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, PCI_ANY_ID, + pci_cfgfunc_config_device, + { 0x400, + 0x40000000, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } }, + + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x01, PCI_ANY_ID, + pci_cfgfunc_config_device, + { 0x800, + 0x40010000, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } }, + + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x02, PCI_ANY_ID, + pci_cfgfunc_config_device, + { 0xc00, + 0x40020000, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } }, + + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x03, PCI_ANY_ID, + pci_cfgfunc_config_device, + { 0x1000, + 0x40030000, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } }, + { } +}; +#endif + +struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_ixpdp425_config_table, +#endif +}; +#endif /* CONFIG_PCI */ + + /* * Miscelaneous platform dependent initialisations */ -int board_init (void) +int board_init(void) { + writew(0x0002, IXDP425_LED_PORT); /* output postcode to LEDs */ + +#ifdef CONFIG_IXDPG425 + /* arch number of IXDP */ + gd->bd->bi_arch_number = MACH_TYPE_IXDPG425; +#else /* arch number of IXDP */ gd->bd->bi_arch_number = MACH_TYPE_IXDP425; +#endif

/* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100;

#ifdef CONFIG_IXDPG425 - /* arch number of IXDP */ - gd->bd->bi_arch_number = MACH_TYPE_IXDPG425; - /* * Get realtek RTL8305 switch and SLIC out of reset */ @@ -60,19 +118,56 @@ int board_init (void) GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SLIC_RESET_N);

/* - * Setup GPIO's for PCI INTA & INTB + * Setup GPIOs for PCI INTA & INTB */ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA_N); GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA_N); GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB_N); GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB_N);

- /* - * Setup GPIO's for 33MHz clock output - */ - *IXP425_GPIO_GPCLKR = 0x01FF01FF; + /* Setup GPIOs for 33MHz clock output */ + writel(0x01FF01FF, IXP425_GPIO_GPCLKR); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); + + /* set GPIO8..11 interrupt type to active low */ + writel((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1, IXP425_GPIO_GPIT2R); + + /* clear pending interrupts */ + writel(-1, IXP425_GPIO_GPISR); + + /* assert PCI reset */ + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_SLIC_RESET_N); + + udelay(533); + + /* deassert PCI reset */ + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SLIC_RESET_N); + + udelay(533); + +#else /* IXDP425 */ + /* Setup GPIOs for 33MHz ExpBus and PCI clock output */ + writel(0x01FF01FF, IXP425_GPIO_GPCLKR); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_RESET_N); + + /* set GPIO8..11 interrupt type to active low */ + writel((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1, IXP425_GPIO_GPIT2R); + /* clear pending interrupts */ + writel(-1, IXP425_GPIO_GPISR); + + /* assert PCI reset */ + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PCI_RESET_N); + + udelay(533); + + /* deassert PCI reset */ + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_PCI_RESET_N); + + udelay(533); #endif

return 0; @@ -98,30 +193,46 @@ int checkboard(void) } putc('\n');

- return (0); + return 0; }

-int dram_init (void) +int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); + /* we can only map 64MB via PCI, so we limit memory + until a better solution is implemented. */ +#ifdef CONFIG_PCI + gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 64<<20); +#else + gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 256<<20); +#endif + return 0; }

-#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) -extern struct pci_controller hose; -extern void pci_ixp_init(struct pci_controller * hose); - +#ifdef CONFIG_PCI void pci_init_board(void) { - extern void pci_ixp_init (struct pci_controller *hose); - pci_ixp_init(&hose); } + +/* + * dev 0 on the PCI bus is not the host bridge, so we have to override + * these functions in order to not skip PCI slot 0 during configuration. +*/ +int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) +{ + return 0; +} +int pci_print_dev(struct pci_controller *hose, pci_dev_t dev) +{ + return 1; +} + #endif

int board_eth_init(bd_t *bis) { - return pci_eth_init(bis); +#ifdef CONFIG_PCI + pci_eth_init(bis); +#endif + return cpu_eth_init(bis); } diff --git a/boards.cfg b/boards.cfg index 05ebcf8..7a922c2 100644 --- a/boards.cfg +++ b/boards.cfg @@ -160,7 +160,7 @@ actux3 arm ixp actux4 arm ixp dvlhost arm ixp ixdp425 arm ixp -ixdpg425 arm ixp +ixdpg425 arm ixp ixdp425 lpd7a400 arm lh7a40x lpd7a40x lpd7a404 arm lh7a40x lpd7a40x balloon3 arm pxa diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h index 28d41e2..4bad31d 100644 --- a/include/configs/ixdp425.h +++ b/include/configs/ixdp425.h @@ -36,12 +36,19 @@ #define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ #define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */

+/* + * select serial console configuration + */ +#define CONFIG_IXP_SERIAL +#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOARD_EARLY_INIT_F 1 + /*************************************************************** * U-boot generic defines start here. ***************************************************************/

-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - /* * Size of malloc() pool */ @@ -50,9 +57,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE

-#define CONFIG_BAUDRATE 115200 - - /* * BOOTP options */ @@ -61,38 +65,33 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME

- -/* - * Command line configuration. - */ +/* Command line configuration. */ #include <config_cmd_default.h>

#define CONFIG_CMD_ELF -#define CONFIG_CMD_PCI -

#define CONFIG_PCI +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_PCI_PNP #define CONFIG_IXP_PCI -#define CONFIG_NET_MULTI +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI_ENUM #define CONFIG_EEPRO100 +#endif

-#define CONFIG_BOOTDELAY 3 -/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b*/ -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.0.21 -#define CONFIG_SERVERIP 192.168.0.148 -#define CONFIG_BOOTCOMMAND "bootm 50040000" -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" -#define CONFIG_CMDLINE_TAG +#define CONFIG_BOOTCOMMAND "run boot_flash" +/* enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1

#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif

-/* - * Miscellaneous configurable options - */ +/* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ @@ -103,10 +102,13 @@ #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */

-#define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */ +/* timer clock - 2* OSC_IN system clock */ +#define CONFIG_IXP425_TIMER_CLK 66666666 +#define CONFIG_SYS_HZ 1000 + +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x00010000

-#define CONFIG_SYS_HZ 3333333 /* spec says 66.666 MHz, but it appears to be 33 */ - /* valid baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }

/* @@ -115,10 +117,6 @@ * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif

/*************************************************************** * Platform/Board specific defines start here. @@ -129,71 +127,145 @@ */

-/* - * select serial console configuration - */ -#define CONFIG_IXP_SERIAL -#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */

/* * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ +#define CONFIG_SYS_TEXT_BASE 0x50000000

#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ #define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ #define PHYS_FLASH_BANK_SIZE 0x00800000 /* 8 MB Banks */ #define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */

-#define CONFIG_SYS_DRAM_BASE 0x00000000 -#define CONFIG_SYS_DRAM_SIZE 0x01000000 - #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CONFIG_BOARD_SIZE_LIMIT 262144

-/* - * Expansion bus settings - */ -#define CONFIG_SYS_EXP_CS0 0xbcd23c42 +/* Expansion bus settings */ +#define CONFIG_SYS_EXP_CS0 0xbcd23c42 + +/* SDRAM settings */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000

-/* - * SDRAM settings - */ #define CONFIG_SYS_SDR_CONFIG 0xd #define CONFIG_SYS_SDR_MODE_CONFIG 0x1 #define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a

/* - * GPIO settings - */ - -/* - * FLASH and environment organization - */ -/* * FLASH and environment organization */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */

-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CONFIG_ENV_IS_IN_FLASH 1

#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }

-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ - #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */

-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) +#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */

+/* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +/* no byte writes on IXP4xx */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +/* print 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_EMPTY_INFO + +/* Ethernet */ + +/* include IXP4xx NPE support */ +#define CONFIG_IXP4XX_NPE 1 +#define CONFIG_NET_MULTI 1 +/* NPE0 PHY address */ +#define CONFIG_PHY_ADDR 0 +/* NPE1 PHY address (HW Release E only) */ +#define CONFIG_PHY1_ADDR 1 +/* MII PHY management */ +#define CONFIG_MII 1 +/* Number of ethernet rx buffers & descriptors */ +#define CONFIG_SYS_RX_ETH_BUFFER 16 + +#define CONFIG_HAS_ETH1 1 + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#undef CONFIG_CMD_NFS + +/* Cache Configuration */ +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "npe_ucode=50060000\0" \ + "mtd=IXP4XX-Flash.0:256k(uboot),128k(env),128k(ucode),2048k(linux),-(root)\0" \ + "kerneladdr=50080000\0" \ + "kernelfile=ixdp425/uImage\0" \ + "rootfile=ixdp425/rootfs\0" \ + "rootaddr=50280000\0" \ + "loadaddr=10000\0" \ + "updateboot_ser=mw.b 10000 ff 40000;" \ + " loady ${loadaddr};" \ + " run eraseboot writeboot\0" \ + "updateboot_net=mw.b 10000 ff 40000;" \ + " tftp ${loadaddr} ixdp425/u-boot.bin;" \ + " run eraseboot writeboot\0" \ + "eraseboot=protect off 50000000 5003ffff;" \ + " erase 50000000 5003ffff\0" \ + "writeboot=cp.b 10000 50000000 ${filesize}\0" \ + "updateucode=loady;" \ + " era ${npe_ucode} +${filesize};" \ + " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ + "updateroot=tftp ${loadaddr} ${rootfile};" \ + " era ${rootaddr} +${filesize};" \ + " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ + "updatekern=tftp ${loadaddr} ${kernelfile};" \ + " era ${kerneladdr} +${filesize};" \ + " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ + "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \ + " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \ + " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ + "boot_flash=run flashargs addtty addeth;" \ + " bootm ${kerneladdr}\0" \ + "boot_net=run netargs addtty addeth;" \ + " tftpboot ${loadaddr} ${kernelfile};" \ + " bootm\0" + +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + + +/* + * GPIO settings + */ +#define CONFIG_SYS_GPIO_UTOPIA_GPIO1 0 +#define CONFIG_SYS_GPIO_UTOPIA_IRQ_N 1 +#define CONFIG_SYS_GPIO_HSS1_IRQ_N 2 +#define CONFIG_SYS_GPIO_HSS0_IRQ_N 3 +#define CONFIG_SYS_GPIO_ETH0_IRQ_N 4 +#define CONFIG_SYS_GPIO_ETH1_IRQ_N 5 +#define CONFIG_SYS_GPIO_I2C_SCL 6 +#define CONFIG_SYS_GPIO_I2C_SDA 7 +#define CONFIG_SYS_GPIO_PCI_INTD_N 8 +#define CONFIG_SYS_GPIO_PCI_INTC_N 9 +#define CONFIG_SYS_GPIO_PCI_INTB_N 10 +#define CONFIG_SYS_GPIO_PCI_INTA_N 11 +#define CONFIG_SYS_GPIO_UTOPIA_GPIO0 12 +#define CONFIG_SYS_GPIO_PCI_RESET_N 13 +#define CONFIG_SYS_GPIO_PCI_CLK 14 +#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 + #endif /* __CONFIG_H */ diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h index 637fd7d..3de0013 100644 --- a/include/configs/ixdpg425.h +++ b/include/configs/ixdpg425.h @@ -53,9 +53,6 @@ /* * Misc configuration options */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */ -#define CONFIG_TIMER_IRQ

#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */ #define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */ @@ -115,6 +112,7 @@ #define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ #define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */

+#define CONFIG_IXP425_TIMER_CLK 66666666 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */

/* valid baudrates */ @@ -179,6 +177,8 @@ #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */

+#define CONFIG_SYS_TEXT_BASE 0x50000000 + #define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ #define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ #define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ @@ -248,4 +248,9 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 32

+/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + #endif /* __CONFIG_H */

clean up IXP PCI handling: get rid of IXP-private bus scan, BAR assign etc. code and use u-boot's PCI infrastructure instead. Move board-specific PCI setup code (clock/reset) to board directory.

Signed-off-by: Michael Schwingen michael@schwingen.org --- Changes for V3: - new in V3 Changes for V4: - add changelog Changes for V5:

arch/arm/include/asm/arch-ixp/ixp425pci.h | 130 +------ drivers/pci/pci.c | 4 - drivers/pci/pci_indirect.c | 13 +- drivers/pci/pci_ixp.c | 612 ++++++++++------------------- 4 files changed, 210 insertions(+), 549 deletions(-)

diff --git a/arch/arm/include/asm/arch-ixp/ixp425pci.h b/arch/arm/include/asm/arch-ixp/ixp425pci.h index 9ea3319..acafea7 100644 --- a/arch/arm/include/asm/arch-ixp/ixp425pci.h +++ b/arch/arm/include/asm/arch-ixp/ixp425pci.h @@ -22,88 +22,21 @@ * MA 02111-1307 USA */

-#ifndef _IXP425PCI_H_ -#define _IXP425PCI_H_ +#ifndef _IXP425PCI_H +#define _IXP425PCI_H

-#define TRUE 1 -#define FALSE 0 #define OK 0 #define ERROR -1 -#define BOOL int

-#define IXP425_PCI_MAX_BAR_PER_FUNC 6 -#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \ - IXP425_PCI_MAX_FUNC_ON_BUS) - -enum PciBarId -{ - CSR_BAR=0, - IO_BAR, - SD_BAR, - NO_BAR -}; - -/*Base address register descriptor*/ -typedef struct -{ - unsigned int size; - unsigned int address; -} PciBar; - -typedef struct -{ - unsigned int bus; - unsigned int device; - unsigned int func; - unsigned int irq; - BOOL error; - unsigned short vendor_id; - unsigned short device_id; - /*We need an extra entry in this array for dummy placeholder*/ - PciBar bar[IXP425_PCI_MAX_BAR_PER_FUNC + 1]; -} PciDevice; +struct pci_controller; +extern void pci_ixp_init(struct pci_controller *hose);

/* Mask definitions*/ -#define IXP425_PCI_TOP_WORD_OF_LONG_MASK 0xffff0000 -#define IXP425_PCI_TOP_BYTE_OF_LONG_MASK 0xff000000 -#define IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK 0x0000ffff -#define IXP425_PCI_BOTTOM_TRIBYTES_OF_LONG_MASK 0x00ffffff #define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK 0x0000000f -#define IXP425_PCI_MAX_UINT32 0xffffffff - - -#define IXP425_PCI_BAR_QUERY 0xffffffff - -#define IXP425_PCI_BAR_MEM_BASE 0x100000 -#define IXP425_PCI_BAR_IO_BASE 0x000000 - -/*define the maximum number of bus segments - we support a single segment*/ -#define IXP425_PCI_MAX_BUS 1 -/*define the maximum number of cards per bus segment*/ -#define IXP425_PCI_MAX_DEV 4 -/*define the maximum number of functions per device*/ -#define IXP425_PCI_MAX_FUNC 8 -/* define the maximum number of separate functions that we can - potentially have on the bus*/ -#define IXP425_PCI_MAX_FUNC_ON_BUS (1+ IXP425_PCI_MAX_FUNC * \ - IXP425_PCI_MAX_DEV * \ - IXP425_PCI_MAX_BUS) -/*define the maximum number of BARs per function*/ -#define IXP425_PCI_MAX_BAR_PER_FUNC 6 -#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \ - IXP425_PCI_MAX_FUNC_ON_BUS)

#define PCI_NP_CBE_BESL (4) #define PCI_NP_AD_FUNCSL (8)

-#define REG_WRITE(b,o,v) (*(volatile unsigned int*)((b+o))=(v)) -#define REG_READ(b,o,v) ((v)=(*(volatile unsigned int*)((b+o)))) - -#define PCI_DELAY 500 -#define USEC_LOOP_COUNT 533 -#define PCI_SETTLE_USEC 200 -#define PCI_MIN_RESET_ASSERT_USEC 2000 - /*Register addressing definitions for PCI controller configuration and status registers*/

@@ -150,28 +83,6 @@ typedef struct #define NP_CMD_CONFIGWRITE (0xb) */

-/*define the default setting of the AHB memory base reg*/ -#define IXP425_PCI_AHBMEMBASE_DEFAULT 0x00010203 -#define IXP425_PCI_AHBIOBASE_DEFAULT 0x0 -#define IXP425_PCI_PCIMEMBASE_DEFAULT 0x0 - -/*define the default settings for the controller's BARs*/ -#ifdef IXP425_PCI_SIMPLE_MAPPING -#define IXP425_PCI_BAR_0_DEFAULT 0x00000000 -#define IXP425_PCI_BAR_1_DEFAULT 0x01000000 -#define IXP425_PCI_BAR_2_DEFAULT 0x02000000 -#define IXP425_PCI_BAR_3_DEFAULT 0x03000000 -#define IXP425_PCI_BAR_4_DEFAULT 0x00000000 -#define IXP425_PCI_BAR_5_DEFAULT 0x00000000 -#else -#define IXP425_PCI_BAR_0_DEFAULT 0x40000000 -#define IXP425_PCI_BAR_1_DEFAULT 0x41000000 -#define IXP425_PCI_BAR_2_DEFAULT 0x42000000 -#define IXP425_PCI_BAR_3_DEFAULT 0x43000000 -#define IXP425_PCI_BAR_4_DEFAULT 0x00000000 -#define IXP425_PCI_BAR_5_DEFAULT 0x00000000 -#endif - /*Configuration Port register bit definitions*/ #define PCI_CRP_WRITE BIT(16)

@@ -228,17 +139,6 @@ typedef struct #define PCI_CFG_SPECIAL_USE 0x41 #define PCI_CFG_MODE 0x43

-/*Specify the initial command we send to PCI devices*/ -#define INITIAL_PCI_CMD (PCI_CMD_IO_ENABLE \ - | PCI_CMD_MEM_ENABLE \ - | PCI_CMD_MASTER_ENABLE \ - | PCI_CMD_WI_ENABLE) - -/*define the sub vendor and subsystem to be used */ -#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000 - -#define PCI_IRQ_LINES 4 - #define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */ #define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */ #define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */ @@ -287,26 +187,4 @@ typedef struct #define PCI_DMACTRL_PADC1 BIT(14) #define PCI_DMACTRL_PADE1 BIT(15)

-/* GPIO related register */ -#undef IXP425_GPIO_GPOUTR -#undef IXP425_GPIO_GPOER -#undef IXP425_GPIO_GPINR -#undef IXP425_GPIO_GPISR -#undef IXP425_GPIO_GPIT1R -#undef IXP425_GPIO_GPIT2R -#undef IXP425_GPIO_GPCLKR - -#define IXP425_GPIO_GPOUTR 0xC8004000 -#define IXP425_GPIO_GPOER 0xC8004004 -#define IXP425_GPIO_GPINR 0xC8004008 -#define IXP425_GPIO_GPISR 0xC800400C -#define IXP425_GPIO_GPIT1R 0xC8004010 -#define IXP425_GPIO_GPIT2R 0xC8004014 -#define IXP425_GPIO_GPCLKR 0xC8004018 - -#define READ_GPIO_REG(addr,val) \ - (val) = *((volatile int *)(addr)); -#define WRITE_GPIO_REG(addr,val) \ - *((volatile int *)(addr)) = (val); - #endif diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index cdfc4fb..1a0b14c 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -50,7 +50,6 @@ PCI_HOSE_OP(write, byte, u8) PCI_HOSE_OP(write, word, u16) PCI_HOSE_OP(write, dword, u32)

-#ifndef CONFIG_IXP425 #define PCI_OP(rw, size, type, error_code) \ int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \ { \ @@ -71,7 +70,6 @@ PCI_OP(read, dword, u32 *, *value = 0xffffffff) PCI_OP(write, byte, u8, ) PCI_OP(write, word, u16, ) PCI_OP(write, dword, u32, ) -#endif /* CONFIG_IXP425 */

#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \ int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\ @@ -190,7 +188,6 @@ int pci_last_busno(void) return hose->last_busno; }

-#ifndef CONFIG_IXP425 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) { struct pci_controller * hose; @@ -246,7 +243,6 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)

return (-1); } -#endif /* CONFIG_IXP425 */

pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index) { diff --git a/drivers/pci/pci_indirect.c b/drivers/pci/pci_indirect.c index 2070d01..526a55c 100644 --- a/drivers/pci/pci_indirect.c +++ b/drivers/pci/pci_indirect.c @@ -11,7 +11,7 @@

#include <common.h>

-#if (!defined(__I386__) && !defined(CONFIG_IXDP425)) +#if !defined(__I386__)

#include <asm/processor.h> #include <asm/io.h> @@ -20,15 +20,6 @@ #define cfg_read(val, addr, type, op) *val = op((type)(addr)) #define cfg_write(val, addr, type, op) op((type *)(addr), (val))

-#ifdef CONFIG_IXP425 -extern unsigned char in_8 (volatile unsigned *addr); -extern unsigned short in_le16 (volatile unsigned *addr); -extern unsigned in_le32 (volatile unsigned *addr); -extern void out_8 (volatile unsigned *addr, char val); -extern void out_le16 (volatile unsigned *addr, unsigned short val); -extern void out_le32 (volatile unsigned *addr, unsigned int val); -#endif /* CONFIG_IXP425 */ - #if defined(CONFIG_MPC8260) #define INDIRECT_PCI_OP(rw, size, type, op, mask) \ static int \ @@ -134,4 +125,4 @@ void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) hose->cfg_data = (unsigned char *) cfg_data; }

-#endif /* !__I386__ && !CONFIG_IXDP425 */ +#endif /* !__I386__ */ diff --git a/drivers/pci/pci_ixp.c b/drivers/pci/pci_ixp.c index 3b303b4..5b5c915 100644 --- a/drivers/pci/pci_ixp.c +++ b/drivers/pci/pci_ixp.c @@ -1,5 +1,8 @@ /* * IXP PCI Init + * + * (C) Copyright 2011 + * Michael Schwingen, michael@schwingen.org * (C) Copyright 2004 eslab.whut.edu.cn * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com) * @@ -22,7 +25,6 @@ * MA 02111-1307 USA */

- #include <common.h> #include <asm/processor.h> #include <asm/io.h> @@ -30,542 +32,336 @@ #include <asm/arch/ixp425.h> #include <asm/arch/ixp425pci.h>

-static void non_prefetch_read (unsigned int addr, unsigned int cmd, - unsigned int *data); -static void non_prefetch_write (unsigned int addr, unsigned int cmd, - unsigned int data); -static void configure_pins (void); -static void sys_pci_gpio_clock_config (void); -static void pci_bus_scan (void); -static int pci_device_exists (unsigned int deviceNo); -static void sys_pci_bar_info_get (unsigned int devnum, unsigned int bus, - unsigned int dev, unsigned int func); -static void sys_pci_device_bars_write (void); -static void calc_bars (PciBar * Bars[], unsigned int nBars, - unsigned int startAddr); +DECLARE_GLOBAL_DATA_PTR; + +static void non_prefetch_read(unsigned int addr, unsigned int cmd, + unsigned int *data); +static void non_prefetch_write(unsigned int addr, unsigned int cmd, + unsigned int data); + +/*define the sub vendor and subsystem to be used */ +#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000

#define PCI_MEMORY_BUS 0x00000000 -#define PCI_MEMORY_PHY 0x48000000 +#define PCI_MEMORY_PHY 0x00000000 #define PCI_MEMORY_SIZE 0x04000000

-#define PCI_MEM_BUS 0x40000000 +#define PCI_MEM_BUS 0x48000000 #define PCI_MEM_PHY 0x00000000 #define PCI_MEM_SIZE 0x04000000

-#define PCI_IO_BUS 0x40000000 -#define PCI_IO_PHY 0x50000000 -#define PCI_IO_SIZE 0x10000000 +#define PCI_IO_BUS 0x00000000 +#define PCI_IO_PHY 0x00000000 +#define PCI_IO_SIZE 0x00010000 + +/* build address value for config sycle */ +static unsigned int pci_config_addr(pci_dev_t bdf, unsigned int reg) +{ + unsigned int bus = PCI_BUS(bdf); + unsigned int dev = PCI_DEV(bdf); + unsigned int func = PCI_FUNC(bdf); + unsigned int addr; + + if (bus) { /* secondary bus, use type 1 config cycle */ + addr = bdf | (reg & ~3) | 1; + } else { + /* + primary bus, type 0 config cycle. address bits 31:28 + specify the device 10:8 specify the function + */ + addr = BIT((31 - dev)) | (func << 8) | (reg & ~3); + } + + return addr; +} + +static int pci_config_status(void) +{ + unsigned int regval;

-struct pci_controller hose; + regval = readl(PCI_CSR_BASE + PCI_ISR_OFFSET); + if ((regval & PCI_ISR_PFE) == 0) + return OK;

-unsigned int nDevices; -unsigned int nMBars; -unsigned int nIOBars; -PciBar *memBars[IXP425_PCI_MAX_BAR]; -PciBar *ioBars[IXP425_PCI_MAX_BAR]; -PciDevice devices[IXP425_PCI_MAX_FUNC_ON_BUS]; + /* no device present, make sure that the master abort bit is reset */ + writel(PCI_ISR_PFE, PCI_CSR_BASE + PCI_ISR_OFFSET); + return ERROR; +}

-int pci_read_config_dword (pci_dev_t dev, int where, unsigned int *val) +static int pci_ixp_hose_read_config_dword(struct pci_controller *hose, + pci_dev_t bdf, int where, unsigned int *val) { unsigned int retval; unsigned int addr; + int stat;

- /*address bits 31:28 specify the device 10:8 specify the function */ + debug("pci_ixp_hose_read_config_dword: bdf %x, reg %x", bdf, where); /*Set the address to be read */ - addr = BIT ((31 - dev)) | (where & ~3); - non_prefetch_read (addr, NP_CMD_CONFIGREAD, &retval); - + addr = pci_config_addr(bdf, where); + non_prefetch_read(addr, NP_CMD_CONFIGREAD, &retval); *val = retval;

- return (OK); + stat = pci_config_status(); + if (stat < 0) + *val = -1; + debug("-> val %x, status %x\n", *val, stat); + return stat; }

-int pci_read_config_word (pci_dev_t dev, int where, unsigned short *val) +static int pci_ixp_hose_read_config_word(struct pci_controller *hose, + pci_dev_t bdf, int where, unsigned short *val) { unsigned int n; unsigned int retval; unsigned int addr; unsigned int byteEnables; + int stat;

+ debug("pci_ixp_hose_read_config_word: bdf %x, reg %x", bdf, where); n = where % 4; /*byte enables are 4 bits active low, the position of each bit maps to the byte that it enables */ byteEnables = - (~(BIT (n) | BIT ((n + 1)))) & + (~(BIT(n) | BIT((n + 1)))) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; byteEnables = byteEnables << PCI_NP_CBE_BESL; - /*address bits 31:28 specify the device 10:8 specify the function */ /*Set the address to be read */ - addr = BIT ((31 - dev)) | (where & ~3); - non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval); + addr = pci_config_addr(bdf, where); + non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval);

/*Pick out the word we are interested in */ - *val = (retval >> (8 * n)); + *val = retval >> (8 * n);

- return (OK); + stat = pci_config_status(); + if (stat < 0) + *val = -1; + debug("-> val %x, status %x\n", *val, stat); + return stat; }

-int pci_read_config_byte (pci_dev_t dev, int where, unsigned char *val) +static int pci_ixp_hose_read_config_byte(struct pci_controller *hose, + pci_dev_t bdf, int where, unsigned char *val) { unsigned int retval; unsigned int n; unsigned int byteEnables; unsigned int addr; + int stat;

+ debug("pci_ixp_hose_read_config_byte: bdf %x, reg %x", bdf, where); n = where % 4; /*byte enables are 4 bits, active low, the position of each bit maps to the byte that it enables */ - byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; + byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; byteEnables = byteEnables << PCI_NP_CBE_BESL;

- /*address bits 31:28 specify the device, 10:8 specify the function */ /*Set the address to be read */ - addr = BIT ((31 - dev)) | (where & ~3); - non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval); + addr = pci_config_addr(bdf, where); + non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval); /*Pick out the byte we are interested in */ - *val = (retval >> (8 * n)); + *val = retval >> (8 * n);

- return (OK); + stat = pci_config_status(); + if (stat < 0) + *val = -1; + debug("-> val %x, status %x\n", *val, stat); + return stat; }

-int pci_write_config_byte (pci_dev_t dev, int where, unsigned char val) +static int pci_ixp_hose_write_config_byte(struct pci_controller *hose, + pci_dev_t bdf, int where, unsigned char val) { unsigned int addr; unsigned int byteEnables; unsigned int n; unsigned int ldata; + int stat;

+ debug("pci_ixp_hose_write_config_byte: bdf %x, reg %x, val %x", + bdf, where, val); n = where % 4; /*byte enables are 4 bits active low, the position of each bit maps to the byte that it enables */ - byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; + byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; byteEnables = byteEnables << PCI_NP_CBE_BESL; ldata = val << (8 * n); - /*address bits 31:28 specify the device 10:8 specify the function */ /*Set the address to be written */ - addr = BIT ((31 - dev)) | (where & ~3); - non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata); + addr = pci_config_addr(bdf, where); + non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);

- return (OK); + stat = pci_config_status(); + debug("-> status %x\n", stat); + return stat; }

-int pci_write_config_word (pci_dev_t dev, int where, unsigned short val) +static int pci_ixp_hose_write_config_word(struct pci_controller *hose, + pci_dev_t bdf, int where, unsigned short val) { unsigned int addr; unsigned int byteEnables; unsigned int n; unsigned int ldata; + int stat;

+ debug("pci_ixp_hose_write_config_word: bdf %x, reg %x, val %x", + bdf, where, val); n = where % 4; /*byte enables are 4 bits active low, the position of each bit maps to the byte that it enables */ byteEnables = - (~(BIT (n) | BIT ((n + 1)))) & + (~(BIT(n) | BIT((n + 1)))) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; byteEnables = byteEnables << PCI_NP_CBE_BESL; ldata = val << (8 * n); - /*address bits 31:28 specify the device 10:8 specify the function */ /*Set the address to be written */ - addr = BIT (31 - dev) | (where & ~3); - non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata); + addr = pci_config_addr(bdf, where); + non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);

- return (OK); + stat = pci_config_status(); + debug("-> status %x\n", stat); + return stat; }

-int pci_write_config_dword (pci_dev_t dev, int where, unsigned int val) +static int pci_ixp_hose_write_config_dword(struct pci_controller *hose, + pci_dev_t bdf, int where, unsigned int val) { unsigned int addr; + int stat;

- /*address bits 31:28 specify the device 10:8 specify the function */ + debug("pci_ixp_hose_write_config_dword: bdf %x, reg %x, val %x", + bdf, where, val); /*Set the address to be written */ - addr = BIT (31 - dev) | (where & ~3); - non_prefetch_write (addr, NP_CMD_CONFIGWRITE, val); + addr = pci_config_addr(bdf, where); + non_prefetch_write(addr, NP_CMD_CONFIGWRITE, val);

- return (OK); + stat = pci_config_status(); + debug("-> status %x\n", stat); + return stat; }

-void non_prefetch_read (unsigned int addr, - unsigned int cmd, unsigned int *data) +static void non_prefetch_read(unsigned int addr, + unsigned int cmd, unsigned int *data) { - REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr); + writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET);

/*set up and execute the read */ - REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd); + writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET);

/*The result of the read is now in np_rdata */ - REG_READ (PCI_CSR_BASE, PCI_NP_RDATA_OFFSET, *data); + *data = readl(PCI_CSR_BASE + PCI_NP_RDATA_OFFSET);

return; }

-void non_prefetch_write (unsigned int addr, - unsigned int cmd, unsigned int data) +static void non_prefetch_write(unsigned int addr, + unsigned int cmd, unsigned int data) {

- REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr); + writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET); /*set up the write */ - REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd); + writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET); /*Execute the write by writing to NP_WDATA */ - REG_WRITE (PCI_CSR_BASE, PCI_NP_WDATA_OFFSET, data); + writel(data, PCI_CSR_BASE + PCI_NP_WDATA_OFFSET);

return; }

-/* - * PCI controller config registers are accessed through these functions - * i.e. these allow us to set up our own BARs etc. - */ -void crp_read (unsigned int offset, unsigned int *data) +static void crp_write(unsigned int offset, unsigned int data) { - REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET, offset); - REG_READ (PCI_CSR_BASE, PCI_CRP_RDATA_OFFSET, *data); -} - -void crp_write (unsigned int offset, unsigned int data) -{ - /*The CRP address register bit 16 indicates that we want to do a write */ - REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET, - PCI_CRP_WRITE | offset); - REG_WRITE (PCI_CSR_BASE, PCI_CRP_WDATA_OFFSET, data); -} - -/*struct pci_controller *hose*/ -void pci_ixp_init (struct pci_controller *hose) -{ - unsigned int regval; - - hose->first_busno = 0; - hose->last_busno = 0x00; - - /* System memory space */ - pci_set_region (hose->regions + 0, - PCI_MEMORY_BUS, - PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_SYS_MEMORY); - - /* PCI memory space */ - pci_set_region (hose->regions + 1, - PCI_MEM_BUS, - PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM); - /* PCI I/O space */ - pci_set_region (hose->regions + 2, - PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO); - - hose->region_count = 3; - - pci_register_hose (hose); - -/* - ========================================================== - Init IXP PCI - ========================================================== -*/ - REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); - regval |= 1 << 2; - REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); - - configure_pins (); - - READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval & (~(1 << 13))); - udelay (533); - sys_pci_gpio_clock_config (); - REG_WRITE (PCI_CSR_BASE, PCI_INTEN_OFFSET, 0); - udelay (100); - READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval | (1 << 13)); - udelay (533); - crp_write (PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_0_DEFAULT); - crp_write (PCI_CFG_BASE_ADDRESS_1, IXP425_PCI_BAR_1_DEFAULT); - crp_write (PCI_CFG_BASE_ADDRESS_2, IXP425_PCI_BAR_2_DEFAULT); - crp_write (PCI_CFG_BASE_ADDRESS_3, IXP425_PCI_BAR_3_DEFAULT); - crp_write (PCI_CFG_BASE_ADDRESS_4, IXP425_PCI_BAR_4_DEFAULT); - crp_write (PCI_CFG_BASE_ADDRESS_5, IXP425_PCI_BAR_5_DEFAULT); - /*Setup PCI-AHB and AHB-PCI address mappings */ - REG_WRITE (PCI_CSR_BASE, PCI_AHBMEMBASE_OFFSET, - IXP425_PCI_AHBMEMBASE_DEFAULT); - - REG_WRITE (PCI_CSR_BASE, PCI_AHBIOBASE_OFFSET, - IXP425_PCI_AHBIOBASE_DEFAULT); - - REG_WRITE (PCI_CSR_BASE, PCI_PCIMEMBASE_OFFSET, - IXP425_PCI_PCIMEMBASE_DEFAULT); - - crp_write (PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM); - - REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); - regval |= PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS; - REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); - crp_write (PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME); - udelay (1000); - - pci_write_config_word (0, PCI_CFG_COMMAND, INITIAL_PCI_CMD); - REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE - | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE); -#ifdef CONFIG_PCI_SCAN_SHOW - printf ("Device bus dev func deviceID vendorID \n"); -#endif - pci_bus_scan (); -} - -void configure_pins (void) -{ - unsigned int regval; - - /* Disable clock on GPIO PIN 14 */ - READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval & (~(1 << 8))); - READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); - - READ_GPIO_REG (IXP425_GPIO_GPOER, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPOER, - (((~(3 << 13)) & regval) | (0xf << 8))); - READ_GPIO_REG (IXP425_GPIO_GPOER, regval); - - READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPIT2R, - (regval & - ((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1))); - READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval); - - READ_GPIO_REG (IXP425_GPIO_GPISR, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPISR, (regval | (0xf << 8))); - READ_GPIO_REG (IXP425_GPIO_GPISR, regval); + /* + * The CRP address register bit 16 indicates that we want to do a + * write + */ + writel(PCI_CRP_WRITE | offset, PCI_CSR_BASE + PCI_CRP_AD_CBE_OFFSET); + writel(data, PCI_CSR_BASE + PCI_CRP_WDATA_OFFSET); }

-void sys_pci_gpio_clock_config (void) +void pci_ixp_init(struct pci_controller *hose) { - unsigned int regval; - - READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); - regval |= 0x1 << 4; - WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval); - READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); - regval |= 0x1 << 8; - WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval); -} + unsigned int csr;

-void pci_bus_scan (void) -{ - unsigned int bus = 0, dev, func = 0; - unsigned short data16; - unsigned int data32; - unsigned char intPin; - - /* Assign first device to ourselves */ - devices[0].bus = 0; - devices[0].device = 0; - devices[0].func = 0; - - crp_read (PCI_CFG_VENDOR_ID, &data32); - - devices[0].vendor_id = data32 & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK; - devices[0].device_id = data32 >> 16; - devices[0].error = FALSE; - devices[0].bar[NO_BAR].size = 0; /*dummy - required */ - - nDevices = 1; - - nMBars = 0; - nIOBars = 0; - - for (dev = 0; dev < IXP425_PCI_MAX_DEV; dev++) { - - /*Check whether a device is present */ - if (pci_device_exists (dev) != TRUE) { - - /*Clear error bits in ISR, write 1 to clear */ - REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE - | PCI_ISR_PFE | PCI_ISR_PPE | - PCI_ISR_AHBE); - continue; - } - - /*A device is present, add an entry to the array */ - devices[nDevices].bus = bus; - devices[nDevices].device = dev; - devices[nDevices].func = func; - - pci_read_config_word (dev, PCI_CFG_VENDOR_ID, &data16); - - devices[nDevices].vendor_id = data16; - - pci_read_config_word (dev, PCI_CFG_DEVICE_ID, &data16); - devices[nDevices].device_id = data16; - - /*The device is functioning correctly, set error to FALSE */ - devices[nDevices].error = FALSE; - - /*Figure out what BARs are on this device */ - sys_pci_bar_info_get (nDevices, bus, dev, func); - /*Figure out what INTX# line the card uses */ - pci_read_config_byte (dev, PCI_CFG_DEV_INT_PIN, &intPin); - - /*assign the appropriate irq line */ - if (intPin > PCI_IRQ_LINES) { - devices[nDevices].error = TRUE; - } else if (intPin != 0) { - /*This device uses an interrupt line */ - /*devices[nDevices].irq = ixp425PciIntTranslate[dev][intPin-1]; */ - devices[nDevices].irq = intPin; - } -#ifdef CONFIG_PCI_SCAN_SHOW - printf ("%06d %03d %03d %04d %08d %08x\n", nDevices, - devices[nDevices].vendor_id); + /* + * Specify that the AHB bus is operating in big endian mode. Set up + * byte lane swapping between little-endian PCI and the big-endian + * AHB bus + */ +#ifdef __ARMEB__ + csr = PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS; +#else + csr = PCI_CSR_ABE; #endif - nDevices++; - - } - - calc_bars (memBars, nMBars, IXP425_PCI_BAR_MEM_BASE); - sys_pci_device_bars_write (); - - REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE - | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE); -} - -void sys_pci_bar_info_get (unsigned int devnum, - unsigned int bus, - unsigned int dev, unsigned int func) -{ - unsigned int data32; - unsigned int tmp; - unsigned int size; - - pci_write_config_dword (devnum, - PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_QUERY); - pci_read_config_dword (devnum, PCI_CFG_BASE_ADDRESS_0, &data32); + writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET);

- devices[devnum].bar[0].address = (data32 & 1); + writel(0, PCI_CSR_BASE + PCI_INTEN_OFFSET);

- if (data32 & 1) { - /* IO space */ - tmp = data32 & ~0x3; - size = ~(tmp - 1); - devices[devnum].bar[0].size = size; - - if (nIOBars < IXP425_PCI_MAX_BAR) { - ioBars[nIOBars++] = &devices[devnum].bar[0]; - } - } else { - /* Mem space */ - tmp = data32 & ~IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - size = ~(tmp - 1); - devices[devnum].bar[0].size = size; - - if (nMBars < IXP425_PCI_MAX_BAR) { - memBars[nMBars++] = &devices[devnum].bar[0]; - } else { - devices[devnum].error = TRUE; - } - - } - - devices[devnum].bar[1].size = 0; -} - -void sortBars (PciBar * Bars[], unsigned int nBars) -{ - unsigned int i, j; - PciBar *tmp; - - if (nBars == 0) { - return; - } - - /* Sort biggest to smallest */ - for (i = 0; i < nBars - 1; i++) { - for (j = i + 1; j < nBars; j++) { - if (Bars[j]->size > Bars[i]->size) { - /* swap them */ - tmp = Bars[i]; - Bars[i] = Bars[j]; - Bars[j] = tmp; - } - } - } -} + /* + * We configure the PCI inbound memory windows to be + * 1:1 mapped to SDRAM + */ + crp_write(PCI_CFG_BASE_ADDRESS_0, 0x00000000); + crp_write(PCI_CFG_BASE_ADDRESS_1, 0x01000000); + crp_write(PCI_CFG_BASE_ADDRESS_2, 0x02000000); + crp_write(PCI_CFG_BASE_ADDRESS_3, 0x03000000); + + /* + * Enable CSR window at 64 MiB to allow PCI masters + * to continue prefetching past 64 MiB boundary. + */ + crp_write(PCI_CFG_BASE_ADDRESS_4, 0x04000000); + /* + * Enable the IO window to be way up high, at 0xfffffc00 + */ + crp_write(PCI_CFG_BASE_ADDRESS_5, 0xfffffc01);

-void calc_bars (PciBar * Bars[], unsigned int nBars, unsigned int startAddr) -{ - unsigned int i; + /*Setup PCI-AHB and AHB-PCI address mappings */ + writel(0x00010203, PCI_CSR_BASE + PCI_AHBMEMBASE_OFFSET);

- if (nBars == 0) { - return; - } + writel(0x00000000, PCI_CSR_BASE + PCI_AHBIOBASE_OFFSET);

- for (i = 0; i < nBars; i++) { - Bars[i]->address |= startAddr; - startAddr += Bars[i]->size; - } -} + writel(0x48494a4b, PCI_CSR_BASE + PCI_PCIMEMBASE_OFFSET);

-void sys_pci_device_bars_write (void) -{ - unsigned int i; - int addr; - - for (i = 1; i < nDevices; i++) { - if (devices[i].error) { - continue; - } - - pci_write_config_dword (devices[i].device, - PCI_CFG_BASE_ADDRESS_0, - devices[i].bar[0].address); - addr = BIT (31 - devices[i].device) | - (0 << PCI_NP_AD_FUNCSL) | - (PCI_CFG_BASE_ADDRESS_0 & ~3); - pci_write_config_dword (devices[i].device, - PCI_CFG_DEV_INT_LINE, devices[i].irq); - - pci_write_config_word (devices[i].device, - PCI_CFG_COMMAND, INITIAL_PCI_CMD); + crp_write(PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM);

- } -} + crp_write(PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME); + udelay(1000);

+ /* clear error bits in status register */ + writel(PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE, + PCI_CSR_BASE + PCI_ISR_OFFSET);

-int pci_device_exists (unsigned int deviceNo) -{ - unsigned int vendorId; - unsigned int regval; - - pci_read_config_dword (deviceNo, PCI_CFG_VENDOR_ID, &vendorId); - - /* There are two ways to find out an empty device. - * 1. check Master Abort bit after the access. - * 2. check whether the vendor id read back is 0x0. + /* + * Set Initialize Complete in PCI Control Register: allow IXP4XX to + * respond to PCI configuration cycles. */ - REG_READ (PCI_CSR_BASE, PCI_ISR_OFFSET, regval); - if ((vendorId != 0x0) && ((regval & PCI_ISR_PFE) == 0)) { - return TRUE; - } - /*no device present, make sure that the master abort bit is reset */ + csr |= PCI_CSR_IC; + writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET);

- REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PFE); - return FALSE; -} + hose->first_busno = 0; + hose->last_busno = 0;

-pci_dev_t pci_find_devices (struct pci_device_id * ids, int devNo) -{ - unsigned int i; - unsigned int devdidvid; - unsigned int didvid; - unsigned int vendorId, deviceId; + /* System memory space */ + pci_set_region(hose->regions + 0, + PCI_MEMORY_BUS, + PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_SYS_MEMORY);

- vendorId = ids->vendor; - deviceId = ids->device; - didvid = ((deviceId << 16) & IXP425_PCI_TOP_WORD_OF_LONG_MASK) | - (vendorId & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK); + /* PCI memory space */ + pci_set_region(hose->regions + 1, + PCI_MEM_BUS, + PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM); + /* PCI I/O space */ + pci_set_region(hose->regions + 2, + PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO);

- for (i = devNo + 1; i < nDevices; i++) { + hose->region_count = 3;

- pci_read_config_dword (devices[i].device, PCI_CFG_VENDOR_ID, - &devdidvid); + pci_set_ops(hose, + pci_ixp_hose_read_config_byte, + pci_ixp_hose_read_config_word, + pci_ixp_hose_read_config_dword, + pci_ixp_hose_write_config_byte, + pci_ixp_hose_write_config_word, + pci_ixp_hose_write_config_dword);

- if (devdidvid == didvid) { - return devices[i].device; - } - } - return -1; + pci_register_hose(hose); + hose->last_busno = pci_hose_scan(hose); }