[PATCH V2 1/2] imx: imx8mp_evk: fix boot issue
The u-boot-spl.bin pad with ddr firmware conflicts with the CONFIG_MALLOC_F_ADDR area, the ddr firmware will be overwritten by malloc in SPL stage and cause ddr initialization not able to finish. So update the related addresses to fix the issue.
Reported-by: Fabio Estevam festevam@gmail.com Signed-off-by: Peng Fan peng.fan@nxp.com ---
V2: None
include/configs/imx8mp_evk.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 80e5738961..b90a4f6932 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -23,15 +23,15 @@ #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" -#define CONFIG_SPL_STACK 0x990000 -#define CONFIG_SPL_BSS_START_ADDR 0x0095e000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SPL_STACK 0x98fc00 +#define CONFIG_SPL_BSS_START_ADDR 0x0098fc00 +#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */ #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ #define CONFIG_SYS_ICACHE_OFF #define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_MALLOC_F_ADDR 0x940000 +#define CONFIG_MALLOC_F_ADDR 0x950000
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
Simplify board SPL code - BSS area will be cleared by crt0_64.S - No need to get ccm device in spl_board_init - Use spl_early_init, not spl_init - timer_init has been invoked in arch_cpu_init
Signed-off-by: Peng Fan peng.fan@nxp.com ---
V2: Fix build warning
board/freescale/imx8mp_evk/spl.c | 30 ++---------------------------- 1 file changed, 2 insertions(+), 28 deletions(-)
diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index c5f640dc7b..7b02f43d95 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -25,11 +25,6 @@ #include <mmc.h> #include <asm/arch/ddr.h>
-#include <dm/uclass.h> -#include <dm/device.h> -#include <dm/uclass-internal.h> -#include <dm/device-internal.h> - DECLARE_GLOBAL_DATA_PTR;
int spl_board_boot_device(enum boot_device boot_dev_spl) @@ -44,16 +39,7 @@ void spl_dram_init(void)
void spl_board_init(void) { - struct udevice *dev; - int ret; - puts("Normal Boot\n"); - - ret = uclass_get_device_by_name(UCLASS_CLK, - "clock-controller@30380000", - &dev); - if (ret < 0) - printf("Failed to find clock node. Check device tree\n"); }
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) @@ -114,29 +100,19 @@ int board_fit_config_name_match(const char *name) } #endif
+/* Do not use BSS area in this phase */ void board_init_f(ulong dummy) { - int ret; - arch_cpu_init();
init_uart_clk(1);
board_early_init_f();
- timer_init(); + spl_early_init();
preloader_console_init();
- /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - ret = spl_init(); - if (ret) { - debug("spl_init() failed: %d\n", ret); - hang(); - } - enable_tzc380();
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); @@ -145,6 +121,4 @@ void board_init_f(ulong dummy)
/* DDR initialization */ spl_dram_init(); - - board_init_r(NULL, 0); }
Hi Peng,
On Mon, May 11, 2020 at 3:55 AM Peng Fan peng.fan@nxp.com wrote:
Simplify board SPL code
- BSS area will be cleared by crt0_64.S
- No need to get ccm device in spl_board_init
- Use spl_early_init, not spl_init
- timer_init has been invoked in arch_cpu_init
These are several changes in the same patch. It would be better to split them.
Signed-off-by: Peng Fan peng.fan@nxp.com
V2: Fix build warning
board/freescale/imx8mp_evk/spl.c | 30 ++---------------------------- 1 file changed, 2 insertions(+), 28 deletions(-)
diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index c5f640dc7b..7b02f43d95 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -25,11 +25,6 @@ #include <mmc.h> #include <asm/arch/ddr.h>
-#include <dm/uclass.h> -#include <dm/device.h> -#include <dm/uclass-internal.h> -#include <dm/device-internal.h>
DECLARE_GLOBAL_DATA_PTR;
int spl_board_boot_device(enum boot_device boot_dev_spl) @@ -44,16 +39,7 @@ void spl_dram_init(void)
void spl_board_init(void) {
struct udevice *dev;int ret;puts("Normal Boot\n");ret = uclass_get_device_by_name(UCLASS_CLK,"clock-controller@30380000",&dev);
We need this for the SPL watchdog driver, no?
I tried selecting CONFIG_SPL_CLK_IMX8MP=y and then the board does not boot anymore, so it looks like we need a better solution.
if (ret < 0)printf("Failed to find clock node. Check device tree\n");}
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) @@ -114,29 +100,19 @@ int board_fit_config_name_match(const char *name) } #endif
+/* Do not use BSS area in this phase */ void board_init_f(ulong dummy) {
int ret;arch_cpu_init(); init_uart_clk(1); board_early_init_f();timer_init();
spl_early_init();
You should check the returned value from spl_early_init().
If you send a v2, could you please:
Thanks
Subject: Re: [PATCH V2 2/2] imx8mp_evk: simplify board spl code
Hi Peng,
On Mon, May 11, 2020 at 3:55 AM Peng Fan peng.fan@nxp.com wrote:
Simplify board SPL code
- BSS area will be cleared by crt0_64.S
- No need to get ccm device in spl_board_init
- Use spl_early_init, not spl_init
- timer_init has been invoked in arch_cpu_init
These are several changes in the same patch. It would be better to split them..
ok
Signed-off-by: Peng Fan peng.fan@nxp.com
V2: Fix build warning
board/freescale/imx8mp_evk/spl.c | 30 ++---------------------------- 1 file changed, 2 insertions(+), 28 deletions(-)
diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index c5f640dc7b..7b02f43d95 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -25,11 +25,6 @@ #include <mmc.h> #include <asm/arch/ddr.h>
-#include <dm/uclass.h> -#include <dm/device.h> -#include <dm/uclass-internal.h> -#include <dm/device-internal.h>
DECLARE_GLOBAL_DATA_PTR;
int spl_board_boot_device(enum boot_device boot_dev_spl) @@ -44,16 +39,7 @@ void spl_dram_init(void)
void spl_board_init(void) {
struct udevice *dev;int ret;puts("Normal Boot\n");ret = uclass_get_device_by_name(UCLASS_CLK,"clock-controller@30380000",
&dev);We need this for the SPL watchdog driver, no?
No. clk is enabled in clock_imx8mm.c.
I tried selecting CONFIG_SPL_CLK_IMX8MP=y and then the board does not boot anymore, so it looks like we need a better solution.
Let's not enable this for SPL. We have limited ram, I plan to disable CCF in SPL.
if (ret < 0)printf("Failed to find clock node. Check device tree\n");}
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE
|
PAD_CTL_PE) @@ -114,29 +100,19 @@ int board_fit_config_name_match(const char *name) } #endif
+/* Do not use BSS area in this phase */ void board_init_f(ulong dummy) {
int ret;arch_cpu_init(); init_uart_clk(1); board_early_init_f();timer_init();
spl_early_init();You should check the returned value from spl_early_init().
ok.
Thanks, Peng.
If you send a v2, could you please:
Thanks
Hi Peng,
On Mon, May 11, 2020 at 3:55 AM Peng Fan peng.fan@nxp.com wrote:
The u-boot-spl.bin pad with ddr firmware conflicts with the CONFIG_MALLOC_F_ADDR area, the ddr firmware will be overwritten by malloc in SPL stage and cause ddr initialization not able to finish. So update the related addresses to fix the issue.
Reported-by: Fabio Estevam festevam@gmail.com Signed-off-by: Peng Fan peng.fan@nxp.com
It does allow to boot U-Boot, but 'reset' is broken:
U-Boot 2020.07-rc1-00001-gaedb60e072-dirty (May 11 2020 - 09:01:16 -0300)
CPU: Freescale i.MX8MP rev1.0 at 1000 MHz Reset cause: POR Model: NXP i.MX8MPlus EVK board DRAM: 6 GiB WDT: Started with servicing (60s timeout) MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 u-boot=> reset resetting ... "Synchronous Abort" handler, esr 0x5e000000 elr: 000000004020011c lr : 00000000402001a8 (reloc) elr: 00000000fff6311c lr : 00000000fff631a8 x0 : 0000000084000009 x1 : 0000000000000000 x2 : 0000000000000000 x3 : 0000000000000000 x4 : 0000000000000000 x5 : 0000000000000000 x6 : 0000000000000000 x7 : 0000000000000000 x8 : 00000000fdf5e0b0 x9 : 000000000000000c x10: 00000000000008d4 x11: 00000000fdf5dbfc x12: 00000000000008b5 x13: 0000000000003908 x14: 00000000fdf5dfa8 x15: 0000000000000002 x16: 0000000000001080 x17: 0000000000004190 x18: 00000000fdf62dd0 x19: 00000000ffffffda x20: 0000000000000001 x21: 0000000000000000 x22: 00000000fdf71680 x23: 0000000000000001 x24: 00000000fffdf924 x25: 0000000000000000 x26: 0000000000000000 x27: 0000000000000000 x28: 00000000fdf716c0 x29: 00000000fdf5dd90
Code: d65f03c0 17ffffc7 ffffffff d4000003 (f94003e4) Resetting CPU ...
Also, could you please make sure it can boot a NXP 5.4.3_2.0.0 kernel?
Thanks
Subject: Re: [PATCH V2 1/2] imx: imx8mp_evk: fix boot issue
Hi Peng,
On Mon, May 11, 2020 at 3:55 AM Peng Fan peng.fan@nxp.com wrote:
The u-boot-spl.bin pad with ddr firmware conflicts with the CONFIG_MALLOC_F_ADDR area, the ddr firmware will be overwritten by malloc in SPL stage and cause ddr initialization not able to finish. So update the related addresses to fix the issue.
Reported-by: Fabio Estevam festevam@gmail.com Signed-off-by: Peng Fan peng.fan@nxp.com
It does allow to boot U-Boot, but 'reset' is broken:
U-Boot 2020.07-rc1-00001-gaedb60e072-dirty (May 11 2020 - 09:01:16 -0300)
CPU: Freescale i.MX8MP rev1.0 at 1000 MHz Reset cause: POR Model: NXP i.MX8MPlus EVK board DRAM: 6 GiB WDT: Started with servicing (60s timeout) MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 u-boot=> reset resetting ... "Synchronous Abort" handler, esr 0x5e000000 elr: 000000004020011c lr : 00000000402001a8 (reloc) elr: 00000000fff6311c lr : 00000000fff631a8 x0 : 0000000084000009 x1 : 0000000000000000 x2 : 0000000000000000 x3 : 0000000000000000 x4 : 0000000000000000 x5 : 0000000000000000 x6 : 0000000000000000 x7 : 0000000000000000 x8 : 00000000fdf5e0b0 x9 : 000000000000000c x10: 00000000000008d4 x11: 00000000fdf5dbfc x12: 00000000000008b5 x13: 0000000000003908 x14: 00000000fdf5dfa8 x15: 0000000000000002 x16: 0000000000001080 x17: 0000000000004190 x18: 00000000fdf62dd0 x19: 00000000ffffffda x20: 0000000000000001 x21: 0000000000000000 x22: 00000000fdf71680 x23: 0000000000000001 x24: 00000000fffdf924 x25: 0000000000000000 x26: 0000000000000000 x27: 0000000000000000 x28: 00000000fdf716c0 x29: 00000000fdf5dd90
Code: d65f03c0 17ffffc7 ffffffff d4000003 (f94003e4) Resetting CPU ...
U-Boot proper should use ATF to reset. I think it might be using wdog here.
Also, could you please make sure it can boot a NXP 5.4.3_2.0.0 kernel?
ok, will give a try.
Thanks, Peng.
Thanks
participants (2)
-
Fabio Estevam -
Peng Fan