[U-Boot] [PATCH 1/5] [PATCH 1/5] Add missing constant to mx27
Signed-off-by: Philippe Reynes tremyfr@yahoo.fr Signed-off-by: Eric Jarrige eric.jarrige@armadeus.org --- arch/arm/cpu/arm926ejs/mx27/asm-offsets.c | 34 ++++++++++++ arch/arm/include/asm/arch-mx27/imx-regs.h | 11 ++++- arch/arm/include/asm/arch-mx27/mxc_nand.h | 83 +++++++++++++++++++++++++++++ 3 files changed, 127 insertions(+), 1 deletions(-) create mode 100644 arch/arm/include/asm/arch-mx27/mxc_nand.h
diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c index f3a8d7b..b95c58c 100644 --- a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c +++ b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c @@ -34,6 +34,7 @@ int main(void) DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); + DEFINE(CCSR, IMX_PLL_BASE + offsetof(struct pll_regs, ccsr));
DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0)); DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0)); @@ -41,5 +42,38 @@ int main(void) DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1)); DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
+ DEFINE(GPCR, IMX_SYSTEM_CTL_BASE + + offsetof(struct system_control_regs, gpcr)); + DEFINE(FMCR, IMX_SYSTEM_CTL_BASE + + offsetof(struct system_control_regs, fmcr)); + DEFINE(DSCR2, IMX_SYSTEM_CTL_BASE + + offsetof(struct system_control_regs, dscr2)); + DEFINE(DSCR3, IMX_SYSTEM_CTL_BASE + + offsetof(struct system_control_regs, dscr3)); + DEFINE(DSCR7, IMX_SYSTEM_CTL_BASE + + offsetof(struct system_control_regs, dscr7)); + DEFINE(DSCR10, IMX_SYSTEM_CTL_BASE + + offsetof(struct system_control_regs, dscr10)); + + DEFINE(CS0U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0u)); + DEFINE(CS0L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0l)); + DEFINE(CS0A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0a)); + DEFINE(CS1U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1u)); + DEFINE(CS1L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1l)); + DEFINE(CS1A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1a)); + DEFINE(CS2U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2u)); + DEFINE(CS2L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2l)); + DEFINE(CS2A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2a)); + DEFINE(CS3U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3u)); + DEFINE(CS3L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3l)); + DEFINE(CS3A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3a)); + DEFINE(CS4U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4u)); + DEFINE(CS4L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4l)); + DEFINE(CS4A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4a)); + DEFINE(CS5U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5u)); + DEFINE(CS5L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5l)); + DEFINE(CS5A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5a)); + DEFINE(EIM, IMX_WEIM_BASE + offsetof(struct weim_regs, eim)); + return 0; } diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h index ced5b2a..fe2861e 100644 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -206,7 +206,7 @@ struct iim_regs { struct fuse_bank { u32 fuse_regs[0x20]; u32 fuse_rsvd[0xe0]; - } bank[1]; + } bank[2]; };
struct fuse_bank0_regs { @@ -522,4 +522,13 @@ struct fuse_bank0_regs { #define IIM_ERR_SNSE (1 << 2) #define IIM_ERR_PARITYE (1 << 1)
+/* + * Memory areas of the NFC + */ +#define IMX_NFC_BASE (0xD8000000) +#define IMX_NFC_MAIN_AREA0 (0xD8000000) +#define IMX_NFC_MAIN_AREA1 (0xD8000200) +#define IMX_NFC_SPARE_AREA0 (0xD8000800) +#define IMX_NFC_REGS (0xD8000E00) + #endif /* _IMX_REGS_H */ diff --git a/arch/arm/include/asm/arch-mx27/mxc_nand.h b/arch/arm/include/asm/arch-mx27/mxc_nand.h new file mode 100644 index 0000000..3429601 --- /dev/null +++ b/arch/arm/include/asm/arch-mx27/mxc_nand.h @@ -0,0 +1,83 @@ +/* + * (c) 2012 Philippe Reynes tremyfr@yahoo.fr + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MXC_NAND_H +#define __MXC_NAND_H + +/* + * NFC registers address offest + */ +#define NFC_OFFSET_BUFSIZE (0x00) /* Internal SRAM Size */ +#define NFC_OFFSET_BLCK_ADD_LOCK (0x02) /* NAND Flash Block Address for + Lock Check */ +#define NFC_OFFSET_BUF_ADDR (0x04) /* Buffer Number for Page Data + Transfer To/From Flash Mem */ +#define NFC_OFFSET_FLASH_ADDR (0x06) /* NAND Flash Address */ +#define NFC_OFFSET_FLASH_CMD (0x08) /* NAND Flash Command */ +#define NFC_OFFSET_CONFIG (0x0A) /* NFC Internal Buffer Lock + Control */ +#define NFC_OFFSET_ECC_STATUS_RESULT (0x0C) /* Controller Status/Result of + Flash Operation */ +#define NFC_OFFSET_ECC_RSLT_MAIN_AREA (0x0E) /* ECC Error Position of Main + Area Data Error */ +#define NFC_OFFSET_ECC_RSLT_SPARE_AREA (0x10) /* ECC Error Position of Spare + Area Data Error */ +#define NFC_OFFSET_WRPROT (0x12) /* Nand Flash Write Protection */ +#define NFC_OFFSET_UNLOCKSTART_BLKADDR (0x14) /* Start Address for Write + Protection Unlock */ +#define NFC_OFFSET_UNLOCKEND_BLKADDR (0x16) /* End Address for Write + Protection Unlock */ +#define NFC_OFFSET_WRPR_STAT (0x18) /* Current Nand Flash Write + Protection Status */ +#define NFC_OFFSET_CONFIG1 (0x1A) /* Nand Flash Operation + Configuration 1 */ +#define NFC_OFFSET_CONFIG2 (0x1C) /* Nand Flash Operation + Configuration 2 */ + +/* NFC_ECC_STATUS_RESULT Status Register Bit Fields */ +#define NFC_ECC_STAT_ERM_SHFT (2) /* ERM shift */ +#define NFC_ECC_STAT_ERS_MASK (0x03) /* ERS mask */ +#define NFC_ECC_STAT_ERROR1 (1<<0) /* correctable error */ +#define NFC_ECC_STAT_ERROR2 (1<<1) /* non correctable error */ + +/* NFC_CONFIG Control Register Bit Fields */ +#define NFC_CONFIG_UNLOCKED (1<<1) /* unlocked */ +#define NFC_CONFIG_LOCKED (1<<0) /* locked */ + +/* NFC_CONFIG1 Control Register Bit Fields */ +#define NFC_CONFIG1_CEn (1<<7) /* Flash force CE */ +#define NFC_CONFIG1_RST (1<<6) /* Reset */ +#define NFC_CONFIG1_BIG (1<<5) /* Big Endian Mode */ +#define NFC_CONFIG1_INT_MSK (1<<4) /* Mask Interrupt Bit */ +#define NFC_CONFIG1_ECC_EN (1<<3) /* ECC operation enable */ +#define NFC_CONFIG1_SP_EN (1<<2) /* Flash spare enable */ + +/* NFC_CONFIG2 Control Register Bit Fields */ +#define NFC_CONFIG2_INT (1<<15) /* Interrupt */ +#define NFC_CONFIG2_FDO_STATUS (4<<3) /* Flash status output */ +#define NFC_CONFIG2_FDO_ID (2<<3) /* Flash ID output */ +#define NFC_CONFIG2_FDO_PAGE (1<<3) /* Flash data output */ +#define NFC_CONFIG2_FDI (1<<2) /* Flash data input */ +#define NFC_CONFIG2_FADD (1<<1) /* Flash address input */ +#define NFC_CONFIG2_FCMD (1<<0) /* Flash command input */ + +#endif
Signed-off-by: Philippe Reynes tremyfr@yahoo.fr Signed-off-by: Eric Jarrige eric.jarrige@armadeus.org Signed-off-by: Nicolas Colombain nicolas.colombain@armadeus.com --- board/armadeus/apf27/Makefile | 52 ++++++ board/armadeus/apf27/apf27.c | 310 ++++++++++++++++++++++++++++++++++ board/armadeus/apf27/config.mk | 38 ++++ board/armadeus/apf27/lowlevel_init.S | 275 ++++++++++++++++++++++++++++++ boards.cfg | 1 + 5 files changed, 676 insertions(+), 0 deletions(-) create mode 100644 board/armadeus/apf27/Makefile create mode 100644 board/armadeus/apf27/apf27.c create mode 100644 board/armadeus/apf27/config.mk create mode 100644 board/armadeus/apf27/lowlevel_init.S
diff --git a/board/armadeus/apf27/Makefile b/board/armadeus/apf27/Makefile new file mode 100644 index 0000000..fe6ba5c --- /dev/null +++ b/board/armadeus/apf27/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2012 +# Eric Jarrige eric.jarrige@armadeus.org +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := apf27.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c new file mode 100644 index 0000000..75be2c1 --- /dev/null +++ b/board/armadeus/apf27/apf27.c @@ -0,0 +1,310 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * Copyright (C) 2008-2012 Eric Jarrige eric.jarrige@armadeus.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include "crc.h" +#include <jffs2/jffs2.h> +#include <nand.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 get_board_rev(void) +{ + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + + return readl(&iim->bank[1].fuse_regs[8]); +} + +int get_num_ram_bank(void) +{ + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + int nr_dram_banks = 1; + + if ((get_board_rev() > 0) && (CONFIG_NR_DRAM_BANKS > 1)) + nr_dram_banks += readl(&iim->bank[1].fuse_regs[9]) & 0x01; + else + nr_dram_banks = CONFIG_NR_DRAM_POPULATED; + + return nr_dram_banks; +} + +static void apf27_gpio_init(void) +{ + struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE; + + /* PORT A */ + writel(CONFIG_SYS_DR_A_VAL, ®s->port[PORTA].dr); + writel(CONFIG_SYS_OCR1_A_VAL, ®s->port[PORTA].ocr1); + writel(CONFIG_SYS_OCR2_A_VAL, ®s->port[PORTA].ocr2); + writel(CONFIG_SYS_ICFA1_A_VAL, ®s->port[PORTA].iconfa1); + writel(CONFIG_SYS_ICFA2_A_VAL, ®s->port[PORTA].iconfa2); + writel(CONFIG_SYS_ICFB1_A_VAL, ®s->port[PORTA].iconfb1); + writel(CONFIG_SYS_ICFB2_A_VAL, ®s->port[PORTA].iconfb2); + writel(CONFIG_SYS_ICR1_A_VAL, ®s->port[PORTA].icr1); + writel(CONFIG_SYS_ICR2_A_VAL, ®s->port[PORTA].icr2); + writel(CONFIG_SYS_IMR_A_VAL, ®s->port[PORTA].imr); + writel(CONFIG_SYS_DDIR_A_VAL, ®s->port[PORTA].ddir); + writel(CONFIG_SYS_GPR_A_VAL, ®s->port[PORTA].gpr); + writel(CONFIG_SYS_PUEN_A_VAL, ®s->port[PORTA].puen); + writel(CONFIG_SYS_GIUS_A_VAL, ®s->port[PORTA].gius); + + /* PORT B */ + writel(CONFIG_SYS_DR_B_VAL, ®s->port[PORTB].dr); + writel(CONFIG_SYS_OCR1_B_VAL, ®s->port[PORTB].ocr1); + writel(CONFIG_SYS_OCR2_B_VAL, ®s->port[PORTB].ocr2); + writel(CONFIG_SYS_ICFA1_B_VAL, ®s->port[PORTB].iconfa1); + writel(CONFIG_SYS_ICFA2_B_VAL, ®s->port[PORTB].iconfa2); + writel(CONFIG_SYS_ICFB1_B_VAL, ®s->port[PORTB].iconfb1); + writel(CONFIG_SYS_ICFB2_B_VAL, ®s->port[PORTB].iconfb2); + writel(CONFIG_SYS_ICR1_B_VAL, ®s->port[PORTB].icr1); + writel(CONFIG_SYS_ICR2_B_VAL, ®s->port[PORTB].icr2); + writel(CONFIG_SYS_IMR_B_VAL, ®s->port[PORTB].imr); + writel(CONFIG_SYS_DDIR_B_VAL, ®s->port[PORTB].ddir); + writel(CONFIG_SYS_GPR_B_VAL, ®s->port[PORTB].gpr); + writel(CONFIG_SYS_PUEN_B_VAL, ®s->port[PORTB].puen); + writel(CONFIG_SYS_GIUS_B_VAL, ®s->port[PORTB].gius); + + /* PORT C */ + writel(CONFIG_SYS_DR_C_VAL, ®s->port[PORTC].dr); + writel(CONFIG_SYS_OCR1_C_VAL, ®s->port[PORTC].ocr1); + writel(CONFIG_SYS_OCR2_C_VAL, ®s->port[PORTC].ocr2); + writel(CONFIG_SYS_ICFA1_C_VAL, ®s->port[PORTC].iconfa1); + writel(CONFIG_SYS_ICFA2_C_VAL, ®s->port[PORTC].iconfa2); + writel(CONFIG_SYS_ICFB1_C_VAL, ®s->port[PORTC].iconfb1); + writel(CONFIG_SYS_ICFB2_C_VAL, ®s->port[PORTC].iconfb2); + writel(CONFIG_SYS_ICR1_C_VAL, ®s->port[PORTC].icr1); + writel(CONFIG_SYS_ICR2_C_VAL, ®s->port[PORTC].icr2); + writel(CONFIG_SYS_IMR_C_VAL, ®s->port[PORTC].imr); + writel(CONFIG_SYS_DDIR_C_VAL, ®s->port[PORTC].ddir); + writel(CONFIG_SYS_GPR_C_VAL, ®s->port[PORTC].gpr); + writel(CONFIG_SYS_PUEN_C_VAL, ®s->port[PORTC].puen); + writel(CONFIG_SYS_GIUS_C_VAL, ®s->port[PORTC].gius); + + /* PORT D */ + writel(CONFIG_SYS_DR_D_VAL, ®s->port[PORTD].dr); + writel(CONFIG_SYS_OCR1_D_VAL, ®s->port[PORTD].ocr1); + writel(CONFIG_SYS_OCR2_D_VAL, ®s->port[PORTD].ocr2); + writel(CONFIG_SYS_ICFA1_D_VAL, ®s->port[PORTD].iconfa1); + writel(CONFIG_SYS_ICFA2_D_VAL, ®s->port[PORTD].iconfa2); + writel(CONFIG_SYS_ICFB1_D_VAL, ®s->port[PORTD].iconfb1); + writel(CONFIG_SYS_ICFB2_D_VAL, ®s->port[PORTD].iconfb2); + writel(CONFIG_SYS_ICR1_D_VAL, ®s->port[PORTD].icr1); + writel(CONFIG_SYS_ICR2_D_VAL, ®s->port[PORTD].icr2); + writel(CONFIG_SYS_IMR_D_VAL, ®s->port[PORTD].imr); + writel(CONFIG_SYS_DDIR_D_VAL, ®s->port[PORTD].ddir); + writel(CONFIG_SYS_GPR_D_VAL, ®s->port[PORTD].gpr); + writel(CONFIG_SYS_PUEN_D_VAL, ®s->port[PORTD].puen); + writel(CONFIG_SYS_GIUS_D_VAL, ®s->port[PORTD].gius); + + /* PORT E */ + writel(CONFIG_SYS_DR_E_VAL, ®s->port[PORTE].dr); + writel(CONFIG_SYS_OCR1_E_VAL, ®s->port[PORTE].ocr1); + writel(CONFIG_SYS_OCR2_E_VAL, ®s->port[PORTE].ocr2); + writel(CONFIG_SYS_ICFA1_E_VAL, ®s->port[PORTE].iconfa1); + writel(CONFIG_SYS_ICFA2_E_VAL, ®s->port[PORTE].iconfa2); + writel(CONFIG_SYS_ICFB1_E_VAL, ®s->port[PORTE].iconfb1); + writel(CONFIG_SYS_ICFB2_E_VAL, ®s->port[PORTE].iconfb2); + writel(CONFIG_SYS_ICR1_E_VAL, ®s->port[PORTE].icr1); + writel(CONFIG_SYS_ICR2_E_VAL, ®s->port[PORTE].icr2); + writel(CONFIG_SYS_IMR_E_VAL, ®s->port[PORTE].imr); + writel(CONFIG_SYS_DDIR_E_VAL, ®s->port[PORTE].ddir); + writel(CONFIG_SYS_GPR_E_VAL, ®s->port[PORTE].gpr); + writel(CONFIG_SYS_PUEN_E_VAL, ®s->port[PORTE].puen); + writel(CONFIG_SYS_GIUS_E_VAL, ®s->port[PORTE].gius); + + /* PORT F */ + writel(CONFIG_SYS_DR_F_VAL, ®s->port[PORTF].dr); + writel(CONFIG_SYS_OCR1_F_VAL, ®s->port[PORTF].ocr1); + writel(CONFIG_SYS_OCR2_F_VAL, ®s->port[PORTF].ocr2); + writel(CONFIG_SYS_ICFA1_F_VAL, ®s->port[PORTF].iconfa1); + writel(CONFIG_SYS_ICFA2_F_VAL, ®s->port[PORTF].iconfa2); + writel(CONFIG_SYS_ICFB1_F_VAL, ®s->port[PORTF].iconfb1); + writel(CONFIG_SYS_ICFB2_F_VAL, ®s->port[PORTF].iconfb2); + writel(CONFIG_SYS_ICR1_F_VAL, ®s->port[PORTF].icr1); + writel(CONFIG_SYS_ICR2_F_VAL, ®s->port[PORTF].icr2); + writel(CONFIG_SYS_IMR_F_VAL, ®s->port[PORTF].imr); + writel(CONFIG_SYS_DDIR_F_VAL, ®s->port[PORTF].ddir); + writel(CONFIG_SYS_GPR_F_VAL, ®s->port[PORTF].gpr); + writel(CONFIG_SYS_PUEN_F_VAL, ®s->port[PORTF].puen); + writel(CONFIG_SYS_GIUS_F_VAL, ®s->port[PORTF].gius); +} + +static int apf27_devices_init(void) +{ + struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE; + int i; + unsigned int mode[] = { + PD0_AIN_FEC_TXD0, + PD1_AIN_FEC_TXD1, + PD2_AIN_FEC_TXD2, + PD3_AIN_FEC_TXD3, + PD4_AOUT_FEC_RX_ER, + PD5_AOUT_FEC_RXD1, + PD6_AOUT_FEC_RXD2, + PD7_AOUT_FEC_RXD3, + PD8_AF_FEC_MDIO, + PD9_AIN_FEC_MDC | GPIO_PUEN, + PD10_AOUT_FEC_CRS, + PD11_AOUT_FEC_TX_CLK, + PD12_AOUT_FEC_RXD0, + PD13_AOUT_FEC_RX_DV, + PD14_AOUT_FEC_CLR, + PD15_AOUT_FEC_COL, + PD16_AIN_FEC_TX_ER, + PF23_AIN_FEC_TX_EN, + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + }; + + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + +#ifdef CONFIG_MXC_MMC + mx27_sd2_init_pins(); + imx_gpio_mode((GPIO_PORTF | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 16)); + writel(readl(®s->port[PORTF].dr) | (1 << 16), + ®s->port[PORTF].dr); +#endif + return 0; +} + +int +board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + apf27_gpio_init(); + apf27_devices_init(); + + return 0; +} + +int +dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + if (get_num_ram_bank() > 1) { + gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2, + PHYS_SDRAM_2_SIZE); + } + + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = gd->ram_size / get_num_ram_bank(); + if (CONFIG_NR_DRAM_BANKS > 1) { + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = \ + gd->ram_size - gd->bd->bi_dram[0].size; + } +} + +/* + * Miscellaneous intialization + */ +int +misc_init_r(void) +{ + char *s; + u_char * firmware_buffer = (u_char *)(CONFIG_SYS_LOAD_ADDR + \ + CONFIG_SYS_MONITOR_LEN); + size_t size = 0; + size_t offset = -1; + char *autoload = getenv("firmware_autoload"); + u8 pnum; + struct mtd_device *dev; + struct part_info *part; + + /* detect compatibility issue of environment version */ + s = getenv("env_version"); + if ((NULL == s) || (0 != strcmp(s, CONFIG_ENV_VERSION))) { + printf("*** Warning - Environment version change suggests: " + "run flash_reset_env; reset\n"); + } + + /* Unlock whole flash but U-Boot */ + s = getenv("env_offset"); + offset = CONFIG_ENV_OFFSET; + if ((s != NULL) && (0 != strcmp(s, "0"))) + offset = simple_strtoul(s, NULL, 16); + + if (nand_unlock(&nand_info[0], offset, nand_info[0].size - offset)) + printf("NAND flash lock/unlocked failed\n"); + + + return 0; +} + +void +show_boot_progress(int status) +{ +#ifdef CONFIG_SHOW_BOOT_PROGRESS +#endif + return; +} + +int checkboard(void) +{ + printf("Board: Armadeus APF27 revision %d\n", get_board_rev()); + return 0; +} + +int board_eth_init(bd_t *bis) +{ +#define STR_ENV_ETHADDR "ethaddr" + int rc = -ENODEV; + +#if defined(CONFIG_FEC_MXC) + struct eth_device *dev; + uchar eth_addr[6]; + + rc = fecmxc_initialize(bis); + + if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) { + dev = eth_get_dev_by_index(0); + if (dev) { + eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr); + } else { + printf("FEC APF27: Couldn't get eth device\n"); + rc = -1; + } + } +#endif + + return rc; +} + +void enable_caches(void) +{ +#ifndef CONFIG_SYS_DCACHE_OFF + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +#endif +} + diff --git a/board/armadeus/apf27/config.mk b/board/armadeus/apf27/config.mk new file mode 100644 index 0000000..9713e69 --- /dev/null +++ b/board/armadeus/apf27/config.mk @@ -0,0 +1,38 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2012 +# Eric Jarrige eric.jarrige@armadeus.org +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# This config file is used for compilation of armadeus sources +# +# You might change location of U-Boot in memory by setting right TEXT_BASE. +# This allows for example having one copy located at the end of ram and stored +# in flash device and later on while developing use other location to test +# the code in RAM device only. +# + +ifndef TEXT_BASE +TEXT_BASE = 0xAFF00000 +endif + diff --git a/board/armadeus/apf27/lowlevel_init.S b/board/armadeus/apf27/lowlevel_init.S new file mode 100644 index 0000000..f5dbbb4 --- /dev/null +++ b/board/armadeus/apf27/lowlevel_init.S @@ -0,0 +1,275 @@ +/* + * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia + * Applications Processor Reference Manual, Rev. 0.2". + * + * (C) Copyright 2008-2012 Eric Jarrige eric.jarrige@armadeus.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <config.h> +#include <version.h> +#include <asm/macro.h> +#include <asm/arch/imx-regs.h> +#include <generated/asm-offsets.h> + + + + +.macro port_init + write32 FMCR, CONFIG_SYS_FMCR_VAL +.endm /* port_init */ + +.macro init_aipi + /* + * setup AIPI1 and AIPI2 + */ + write32 AIPI1_PSR0, CONFIG_SYS_AIPI1_PSR0_VAL + write32 AIPI1_PSR1, CONFIG_SYS_AIPI1_PSR1_VAL + write32 AIPI2_PSR0, CONFIG_SYS_AIPI2_PSR0_VAL + write32 AIPI2_PSR1, CONFIG_SYS_AIPI2_PSR1_VAL + + /* Change SDRAM signal strengh */ + ldr r0, =GPCR + ldr r1, =CONFIG_SYS_GPCR_VAL + ldr r5, [r0] + orr r5, r5, r1 + str r5, [r0] + +.endm /* init_aipi */ + +.macro init_clock + ldr r0, =CSCR + /* disable MPLL/SPLL first */ + ldr r1, [r0] + bic r1, r1, #(CSCR_MPEN|CSCR_SPEN) + str r1, [r0] + + /* + * pll clock initialization predefined in apf27.h + */ + write32 MPCTL0, CONFIG_SYS_MPCTL0_VAL + write32 SPCTL0, CONFIG_SYS_SPCTL0_VAL + + write32 CSCR, CONFIG_SYS_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART + + /* + * add some delay here + */ + mov r1, #0x1000 + 1: subs r1, r1, #0x1 + bne 1b + + /* peripheral clock divider */ + write32 PCDR0, CONFIG_SYS_PCDR0_VAL + write32 PCDR1, CONFIG_SYS_PCDR1_VAL + + /* Configure PCCR0 and PCCR1 */ + write32 PCCR0, CONFIG_SYS_PCCR0_VAL + write32 PCCR1, CONFIG_SYS_PCCR1_VAL + + +.endm /* init_clock */ + +.macro sdram_init + /* wait for SDRAM/LPDDR ready (SDRAMRDY) */ + ldr r0, =IMX_ESD_BASE + ldr r4, =ESDMISC_SDRAM_RDY +2: ldr r1, [r0, #ESDMISC_ROF] + ands r1, r1, r4 + bpl 2b + + /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */ + ldr r0, =IMX_ESD_BASE + ldr r4, =CONFIG_SYS_ESDMISC_VAL + orr r1, r4, #ESDMISC_MDDR_DL_RST + str r1, [r0, #ESDMISC_ROF] + + /* Hold for more than 200ns */ + ldr r1, =0x10000 + 1: subs r1, r1, #0x1 + bne 1b + + str r4, [r0] + + /* write32 ESDCFG0, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL */ + ldr r0, =IMX_ESD_BASE + ldr r1, =CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL + str r1, [r0, #ESDCFG0_ROF] + + /* writel(ESDCTL0, CONFIG_SYS_PRECHARGE_CMD) */ + ldr r0, =IMX_ESD_BASE + ldr r1, =CONFIG_SYS_PRECHARGE_CMD + str r1, [r0, #ESDCTL0_ROF] + + /* writeb(0xA0001000, any value) */ + ldr r1, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL + strb r2, [r1] + + /* writel(ESDCTL0, CONFIG_SYS_AUTOREFRESH_CMD) */ + ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD + str r1, [r0, #ESDCTL0_ROF] + + ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */ + + ldr r6,=0x7 /* load loop counter */ +1: str r5,[r4] /* run auto-refresh cycle to array 0 */ + subs r6,r6,#1 /* decrease counter value */ + bne 1b + + /* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_SET_MODE_REG_CMD) */ + ldr r1, =CONFIG_SYS_SET_MODE_REG_CMD + str r1, [r0, #ESDCTL0_ROF] + + /* set standard mode register */ + ldr r4, = PHYS_SDRAM_1+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL + strb r2, [r4] + + /* set extended mode register */ + ldr r4, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL + strb r5, [r4] + + /* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_NORMAL_RW_CMD) */ + ldr r1, =CONFIG_SYS_NORMAL_RW_CMD + str r1, [r0, #ESDCTL0_ROF] + + /* 2nd sdram */ + /* write32 ESDCFG1, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL */ + ldr r1, =CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL + str r1, [r0, #ESDCFG1_ROF] + + /* writel(ESDCTL1, CONFIG_SYS_PRECHARGE_CMD) */ + ldr r1, =CONFIG_SYS_PRECHARGE_CMD + str r1, [r0, #ESDCTL1_ROF] + + /* writeb(0xB0001000, any value) */ + ldr r1, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL + strb r2, [r1] + + /* writel(ESDCTL1, CONFIG_SYS_AUTOREFRESH_CMD) */ + ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD + str r1, [r0, #ESDCTL1_ROF] + + ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */ + + ldr r6,=0x7 /* load loop counter */ +1: str r5,[r4] /* run auto-refresh cycle to array 0 */ + subs r6,r6,#1 /* decrease counter value */ + bne 1b + + /* writel(ESDCTL1, CONFIG_SYS_SET_MODE_REG_CMD) */ + ldr r1, =CONFIG_SYS_SET_MODE_REG_CMD + str r1, [r0, #ESDCTL1_ROF] + + /* set standard mode register */ + ldr r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL + strb r2, [r4] + + /* set extended mode register */ + ldr r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL + strb r2, [r4] + + /* writel(ESDCTL1, CONFIG_SYS_NORMAL_RW_CMD) */ + ldr r1, =CONFIG_SYS_NORMAL_RW_CMD + str r1, [r0, #ESDCTL1_ROF] +.endm /* sdram_init */ + +.globl board_init_lowlevel +board_init_lowlevel: +.globl lowlevel_init +lowlevel_init: + + init_aipi + + /* configure csx */ + write32 CS0U, CONFIG_SYS_CS0U_VAL + write32 CS0L, CONFIG_SYS_CS0L_VAL + write32 CS0A, CONFIG_SYS_CS0A_VAL + + write32 CS1U, CONFIG_SYS_CS1U_VAL + write32 CS1L, CONFIG_SYS_CS1L_VAL + write32 CS1A, CONFIG_SYS_CS1A_VAL + + write32 CS2U, CONFIG_SYS_CS2U_VAL + write32 CS2L, CONFIG_SYS_CS2L_VAL + write32 CS2A, CONFIG_SYS_CS2A_VAL + + write32 CS3U, CONFIG_SYS_CS3U_VAL + write32 CS3L, CONFIG_SYS_CS3L_VAL + write32 CS3A, CONFIG_SYS_CS3A_VAL + + write32 CS4U, CONFIG_SYS_CS4U_VAL + write32 CS4L, CONFIG_SYS_CS4L_VAL + write32 CS4A, CONFIG_SYS_CS4A_VAL + + write32 CS5U, CONFIG_SYS_CS5U_VAL + write32 CS5L, CONFIG_SYS_CS5L_VAL + write32 CS5A, CONFIG_SYS_CS5A_VAL + + write32 EIM, CONFIG_SYS_EIM_VAL + + port_init + + /* Configure FPGA CLKO */ + write32 CCSR, CONFIG_SYS_CCSR_VAL + + /* Configure strentgh for FPGA */ + write32 DSCR10, CONFIG_SYS_DSCR10_VAL + write32 DSCR3, CONFIG_SYS_DSCR3_VAL + write32 DSCR7, CONFIG_SYS_DSCR7_VAL + write32 DSCR2, CONFIG_SYS_DSCR2_VAL + + init_clock + + /* skip clock and sdram initialization if we run from ram */ + cmp pc, #0xa0000000 + bls 1f + cmp pc, #0xc0000000 + bhi 1f + + b copy2ram +1: + sdram_init + +/* make U-Boot runnable form "almost" anywhere */ +/* but SYS_TEXT_BASE should be in RAM */ +copy2ram: /* populate _TEXT_BASE with U-Boot from load addr */ + ldr r0, _start_adr + ldr r1, _copy2ram + sub r1, r1, r0 + adr r0, copy2ram + sub r0, r0, r1 + ldr r1, =CONFIG_SYS_TEXT_BASE + cmp r0, r1 + beq end_of_copy2ram /* skip U-Boot copy */ + ldr r2, =CONFIG_SYS_MONITOR_LEN + add r2, r2, r0 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r9-r10} /* copy from source address [r0] */ + stmia r1!, {r9-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop + +end_of_copy2ram: + mov pc,lr + +_copy2ram: + .word copy2ram +_start_adr: + .word _start /* r12 saved upper lr*/ + diff --git a/boards.cfg b/boards.cfg index a723f67..d77ce77 100644 --- a/boards.cfg +++ b/boards.cfg @@ -69,6 +69,7 @@ integratorcp_cm926ejs arm arm926ejs integrator armltd aspenite arm arm926ejs - Marvell armada100 gplugd arm arm926ejs - Marvell armada100 afeb9260 arm arm926ejs - - at91 +apf27 arm arm926ejs apf27 armadeus mx27 at91sam9260ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0 at91sam9260ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1 at91sam9260ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH
Hi Philippe,
On Thu, Jun 28, 2012 at 5:36 PM, Philippe Reynes tremyfr@yahoo.fr wrote:
Signed-off-by: Philippe Reynes tremyfr@yahoo.fr Signed-off-by: Eric Jarrige eric.jarrige@armadeus.org
Here we have armadeus.org
Signed-off-by: Nicolas Colombain nicolas.colombain@armadeus.com
,and here it is armadeus.com. Which one is correct?
board/armadeus/apf27/Makefile | 52 ++++++ board/armadeus/apf27/apf27.c | 310 ++++++++++++++++++++++++++++++++++ board/armadeus/apf27/config.mk | 38 ++++ board/armadeus/apf27/lowlevel_init.S | 275 ++++++++++++++++++++++++++++++ boards.cfg | 1 +
You missed an entry to the MAINTAINERS file.
+void +show_boot_progress(int status) +{ +#ifdef CONFIG_SHOW_BOOT_PROGRESS +#endif
This ifdef seems to be useless at this location.
--- /dev/null +++ b/board/armadeus/apf27/lowlevel_init.S
Can't this be converted into a C file instead?
Check board/hale/tt01/tt01.c, for example.
+#include <config.h> +#include <version.h> +#include <asm/macro.h> +#include <asm/arch/imx-regs.h> +#include <generated/asm-offsets.h>
To many new lines here.
Hi Fabio,
On 29 juin 2012, at 01:06, Fabio Estevam wrote:
Hi Philippe,
On Thu, Jun 28, 2012 at 5:36 PM, Philippe Reynes tremyfr@yahoo.fr wrote:
Signed-off-by: Philippe Reynes tremyfr@yahoo.fr Signed-off-by: Eric Jarrige eric.jarrige@armadeus.org
Here we have armadeus.org
Signed-off-by: Nicolas Colombain nicolas.colombain@armadeus.com
,and here it is armadeus.com. Which one is correct?
Both are correct. I am just answering to clarify this point that is not directly related to the patch . Many members of the Armadeus project are not involved in the homonym company. That's the reason why both domain names exist.
Regards, Eric
On 28/06/2012 22:36, Philippe Reynes wrote:
Signed-off-by: Philippe Reynes tremyfr@yahoo.fr Signed-off-by: Eric Jarrige eric.jarrige@armadeus.org Signed-off-by: Nicolas Colombain nicolas.colombain@armadeus.com
Hi Philippe,
- rm -f $(SOBJS) $(OBJS)
+distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
clean / distclean are not needed, drop these rules
+#include <common.h> +#include "crc.h" +#include <jffs2/jffs2.h> +#include <nand.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/errno.h>
+DECLARE_GLOBAL_DATA_PTR;
+u32 get_board_rev(void) +{
- struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
- return readl(&iim->bank[1].fuse_regs[8]);
For my understanding: who does store the version number in the fuses ? The board's manufacturer ?
+int get_num_ram_bank(void) +{
- struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
- int nr_dram_banks = 1;
- if ((get_board_rev() > 0) && (CONFIG_NR_DRAM_BANKS > 1))
nr_dram_banks += readl(&iim->bank[1].fuse_regs[9]) & 0x01;
It seems to me there are some hidden important information in the fuses. Maybe can you document them adding a map of the relevant fuses for this board ?
- /* Unlock whole flash but U-Boot */
- s = getenv("env_offset");
- offset = CONFIG_ENV_OFFSET;
- if ((s != NULL) && (0 != strcmp(s, "0")))
offset = simple_strtoul(s, NULL, 16);- if (nand_unlock(&nand_info[0], offset, nand_info[0].size - offset))
printf("NAND flash lock/unlocked failed\n");
Why is it needed ?
+void +show_boot_progress(int status) +{ +#ifdef CONFIG_SHOW_BOOT_PROGRESS +#endif
- return;
+}
This is quite dead code..
+#if defined(CONFIG_FEC_MXC)
- struct eth_device *dev;
- uchar eth_addr[6];
- rc = fecmxc_initialize(bis);
- if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
dev = eth_get_dev_by_index(0);if (dev) {eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);} else {printf("FEC APF27: Couldn't get eth device\n");rc = -1;}
It is not clear to me why you have your special way to set up the MAC address instead of rely on the already working code. The FEC is already initialized for i.MX27 by general SOC code, see imx27lite.
+void enable_caches(void) +{ +#ifndef CONFIG_SYS_DCACHE_OFF
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
+#endif
This is SOC-related, and not board related. It belongs to the SOC code.
diff --git a/board/armadeus/apf27/config.mk b/board/armadeus/apf27/config.mk new file mode 100644 index 0000000..9713e69 --- /dev/null +++ b/board/armadeus/apf27/config.mk @@ -0,0 +1,38 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2012 +# Eric Jarrige eric.jarrige@armadeus.org +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +#
+# +# This config file is used for compilation of armadeus sources +# +# You might change location of U-Boot in memory by setting right TEXT_BASE. +# This allows for example having one copy located at the end of ram and stored +# in flash device and later on while developing use other location to test +# the code in RAM device only. +#
+ifndef TEXT_BASE +TEXT_BASE = 0xAFF00000 +endif
config.mk is obsolete and must not be added for new boards. TEXT_BASE must be set in the configuration file, see CONFIG_SYS_TEXT_BASE.
diff --git a/board/armadeus/apf27/lowlevel_init.S b/board/armadeus/apf27/lowlevel_init.S
diff --git a/boards.cfg b/boards.cfg index a723f67..d77ce77 100644 --- a/boards.cfg +++ b/boards.cfg @@ -69,6 +69,7 @@ integratorcp_cm926ejs arm arm926ejs integrator armltd aspenite arm arm926ejs - Marvell armada100 gplugd arm arm926ejs - Marvell armada100 afeb9260 arm arm926ejs - - at91 +apf27 arm arm926ejs apf27 armadeus mx27
The board are grouped for SOC, and then sorted alphabetically. The entry for your board should go before the imx27lite / magnesium boards.
Best regards, Stefano Babic
Signed-off-by: Philippe Reynes tremyfr@yahoo.fr Signed-off-by: Eric Jarrige eric.jarrige@armadeus.org --- nand_spl/board/armadeus/apf27/Makefile | 79 +++++ nand_spl/board/armadeus/apf27/config.mk | 45 +++ nand_spl/board/armadeus/apf27/start.S | 548 ++++++++++++++++++++++++++++++ nand_spl/board/armadeus/apf27/u-boot.lds | 39 +++ 4 files changed, 711 insertions(+), 0 deletions(-) create mode 100644 nand_spl/board/armadeus/apf27/Makefile create mode 100644 nand_spl/board/armadeus/apf27/config.mk create mode 100644 nand_spl/board/armadeus/apf27/start.S create mode 100644 nand_spl/board/armadeus/apf27/u-boot.lds
diff --git a/nand_spl/board/armadeus/apf27/Makefile b/nand_spl/board/armadeus/apf27/Makefile new file mode 100644 index 0000000..600ef6b --- /dev/null +++ b/nand_spl/board/armadeus/apf27/Makefile @@ -0,0 +1,79 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# (C) Copyright 2012 +# Eric Jarrige eric.jarrige@armadeus.org +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o +COBJS = + +SRCS := $(addprefix $(src),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \ + $(nandobj)System.map + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +$(nandobj)System.map: $(nandobj)u-boot-spl + @$(NM) $< | \ + grep -v '(compiled)|(.o$$)|( [aUw] )|(..ng$$)|(LASH[RL]DI)' | \ + sort > $(nandobj)System.map + + +######################################################################### + +$(obj)%.o: %.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: %.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/armadeus/apf27/config.mk b/nand_spl/board/armadeus/apf27/config.mk new file mode 100644 index 0000000..3063c89 --- /dev/null +++ b/nand_spl/board/armadeus/apf27/config.mk @@ -0,0 +1,45 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# (C) Copyright 2012 +# Eric Jarrige eric.jarrige@armadeus.org +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +# This config file is used for compilation of armadeus apf27 board +# + +# +# TEXT_BASE for SPL: +# +# +# This config file is used for compilation of armadeus sources +# +# You might change location of U-Boot in memory by setting right TEXT_BASE. +# This allows for example having one copy located at the end of ram and stored +# in flash device and later on while developing use other location to test +# the code in RAM device only. +# + +TEXT_BASE = 0xa0000000 + +# PAD_TO used to generate a 2kByte binary needed for the combined image +# -> PAD_TO = TEXT_BASE + 0x0800 +PAD_TO = 0xa0000800 diff --git a/nand_spl/board/armadeus/apf27/start.S b/nand_spl/board/armadeus/apf27/start.S new file mode 100644 index 0000000..5b5c5c8 --- /dev/null +++ b/nand_spl/board/armadeus/apf27/start.S @@ -0,0 +1,548 @@ +/* + * IMX27 NAND Flash SPL (Secondary Program Loader) + * + * Copyright (c) 2008 Armadeus Project / eja + * + * Based on Freescale NAND SPL + * + * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. + * Copyright (c) 2008-2012 Eric Jarrige eric.jarrige@armadeus.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <config.h> +#include <version.h> +#include <asm/macro.h> +#include <asm/arch/mxc_nand.h> +#include <asm/arch/imx-regs.h> +#include <generated/asm-offsets.h> + +/* + * Standard NAND flash commands + */ +#define NAND_CMD_READ0 0 +#define NAND_CMD_READ1 1 +#define NAND_CMD_PAGEPROG 0x10 +#define NAND_CMD_READOOB 0x50 +#define NAND_CMD_ERASE1 0x60 +#define NAND_CMD_STATUS 0x70 +#define NAND_CMD_STATUS_MULTI 0x71 +#define NAND_CMD_SEQIN 0x80 +#define NAND_CMD_READID 0x90 +#define NAND_CMD_ERASE2 0xd0 +#define NAND_CMD_RESET 0xff + +/* Extended commands for large page devices */ +#define NAND_CMD_READSTART 0x30 +#define NAND_CMD_CACHEDPROG 0x15 + +/* Status bits */ +#define NAND_STATUS_FAIL 0x01 +#define NAND_STATUS_FAIL_N1 0x02 +#define NAND_STATUS_TRUE_READY 0x20 +#define NAND_STATUS_READY 0x40 +#define NAND_STATUS_WP 0x80 + + .macro nand_boot + +#ifdef CONFIG_BOOT_TRACE_REG +/* + * If CONFIG_BOOT_TRACE_REG is a SDRAM address then be sure to use the following + * 2 command after SDRAM init + */ + +/* Backup state of previous boot to CONFIG_BOOT_TRACE_REG+4*/ +#define BACKUP_TRACE() \ + ldr r4, =CONFIG_BOOT_TRACE_REG; \ + ldr r3, [r4]; \ + str r3, [r4, #0x04]; + +/* Save a state of boot at CONFIG_BOOT_TRACE_REG */ +#define BOOT_TRACE(val) \ + ldr r4, =CONFIG_BOOT_TRACE_REG; \ + ldr r3, =val; \ + str r3, [r4]; +#else +#define BACKUP_TRACE() +#define BOOT_TRACE(val) +#endif + +nand_boot_setup: + + /* Copy SPL image from flash to SDRAM first */ + BOOT_TRACE(1) + ldr r0, =IMX_NFC_MAIN_AREA0 + add r2, r0, #(IMX_NFC_SPARE_AREA0-IMX_NFC_MAIN_AREA0) //2KB NFC Buff + ldr r1, =CONFIG_SYS_NAND_U_BOOT_DST + + BOOT_TRACE(2) +1: ldmia r0!, {r3-r10} + stmia r1!, {r3-r10} + cmp r0, r2 + blo 1b + + + + /* Jump to SDRAM */ + BOOT_TRACE(3) + ldr r1, =0xFFF + and r0, pc, r1 /* offset of pc */ + ldr r1, =CONFIG_SYS_NAND_U_BOOT_DST + add r1, r1, #0x10 + add pc, r0, r1 + nop + nop + nop + nop + +NAND_Copy_Main: + BOOT_TRACE(4) + /* r0: nfc base. Reloaded after each page copying */ + ldr r0, =IMX_NFC_MAIN_AREA0 + + /* r1: starting flash addr to be copied. Updated constantly */ + /* bypass the first preloaded pages */ + ldr r1, =(IMX_NFC_SPARE_AREA0-IMX_NFC_MAIN_AREA0) + + /* r2: end of 1st RAM buf. Doesn't change */ + ldr r2, =IMX_NFC_MAIN_AREA1 + + /* r12: NFC register base. Doesn't change */ + ldr r12, =IMX_NFC_REGS + + ldr r11, =CONFIG_SYS_NAND_U_BOOT_DST + + /* r13: end of SDRAM address for copying. Doesn't change */ + add r13, r11, #CONFIG_SYS_NAND_U_BOOT_SIZE + + /* r11: starting SDRAM address for copying. Updated constantly */ + add r11, r11, r1 + + /* unlock internal buffer */ + ldr r3, =NFC_CONFIG_UNLOCKED + strh r3, [r12, #NFC_OFFSET_CONFIG] + + /* enable ECC and mask interrupts */ + ldr r3, =(NFC_CONFIG1_ECC_EN | NFC_CONFIG1_INT_MSK) + strh r3, [r12, #NFC_OFFSET_CONFIG1] + +Nfc_Read_Page: + BOOT_TRACE(5) + /* send NAND_CMD_READ0 command */ + ldr r3, =NAND_CMD_READ0; + strh r3, [r12, #NFC_OFFSET_FLASH_CMD] + + ldr r3, =NFC_CONFIG2_FCMD + strh r3, [r12, #NFC_OFFSET_CONFIG2] + bl do_wait_op_done + + /* send NAND address to read. TODO small page support */ + BOOT_TRACE(6) + mov r3, r1, lsr #1 + bl do_addr_input /* 1st addr cycle */ + + mov r3, r1, lsr #9 + and r3, r3, #0x03 + bl do_addr_input /* 2nd addr cycle */ + + mov r3, r1, lsr #11 + bl do_addr_input /* 3rd addr cycle */ + + mov r3, r1, lsr #19 + bl do_addr_input /* 4th addr cycle */ + + /* Small NAND flashs (== 1Gb) support 5 addr cycles */ + mov r3, r1, lsr #27 + bl do_addr_input /* 5th addr cycle */ + + /* send NAND_CMD_READSTART command. TODO small page support */ + BOOT_TRACE(7) + mov r3, #NAND_CMD_READSTART; + strh r3, [r12, #NFC_OFFSET_FLASH_CMD] + mov r3, #NFC_CONFIG2_FCMD + strh r3, [r12, #NFC_OFFSET_CONFIG2] + bl do_wait_op_done + + /* read and copy buf 0 */ + BOOT_TRACE(8) + mov r3, #0 + strh r3, [r12, #NFC_OFFSET_BUF_ADDR] + + mov r3, #NFC_CONFIG2_FDO_PAGE + strh r3, [r12, #NFC_OFFSET_CONFIG2] + bl do_wait_op_done + + bl Test_And_Copy_Buffer + + /* read and copy buf 1 */ + mov r3, #1 + strh r3, [r12, #NFC_OFFSET_BUF_ADDR] + + mov r3, #NFC_CONFIG2_FDO_PAGE + strh r3, [r12, #NFC_OFFSET_CONFIG2] + bl do_wait_op_done + + bl Test_And_Copy_Buffer + + /* here we should test if 512B page flash and bypass next buffers */ + /* read and copy buf 2. TODO small page support */ + mov r3, #2 + strh r3, [r12, #NFC_OFFSET_BUF_ADDR] + + mov r3, #NFC_CONFIG2_FDO_PAGE + strh r3, [r12, #NFC_OFFSET_CONFIG2] + bl do_wait_op_done + + bl Test_And_Copy_Buffer + + /* read and copy buf 3 */ + mov r3, #3 + strh r3, [r12, #NFC_OFFSET_BUF_ADDR] + + mov r3, #NFC_CONFIG2_FDO_PAGE + strh r3, [r12, #NFC_OFFSET_CONFIG2] + bl do_wait_op_done + + bl Test_And_Copy_Buffer + + /* is the last page ? */ + BOOT_TRACE(12) + cmp r11, r13 + bge NAND_Copy_Main_done + + /* r0: nfc base. Reloaded after each page copying */ + ldr r0, =IMX_NFC_MAIN_AREA0 + /* r2: end of 1st RAM buf. Doesn't change */ + ldr r2, =IMX_NFC_MAIN_AREA1 + b Nfc_Read_Page + +NAND_Copy_Main_done: + BOOT_TRACE(13) + .endm /* nand_boot */ + + .macro init_aipi + /* + * setup AIPI1 and AIPI2 + */ + write32 AIPI1_PSR0, CONFIG_SYS_AIPI1_PSR0_VAL + write32 AIPI1_PSR1, CONFIG_SYS_AIPI1_PSR1_VAL + write32 AIPI2_PSR0, CONFIG_SYS_AIPI2_PSR0_VAL + write32 AIPI2_PSR1, CONFIG_SYS_AIPI2_PSR1_VAL + + /* Change SDRAM signal strengh */ + ldr r0, =GPCR + ldr r1, =CONFIG_SYS_GPCR_VAL + ldr r5, [r0] + orr r5, r5, r1 + str r5, [r0] + + .endm /* init_aipi */ + + .macro init_clock + ldr r0, =CSCR + /* disable MPLL/SPLL first */ + ldr r1, [r0] + bic r1, r1, #(CSCR_MPEN|CSCR_SPEN) + str r1, [r0] + + /* + * pll clock initialization predefined in apf27.h + */ + write32 MPCTL0, CONFIG_SYS_MPCTL0_VAL + write32 SPCTL0, CONFIG_SYS_SPCTL0_VAL + + write32 CSCR, CONFIG_SYS_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART + + /* + * add some delay here + */ + mov r1, #0x1000 + 1: subs r1, r1, #0x1 + bne 1b + + /* peripheral clock divider */ + write32 PCDR0, CONFIG_SYS_PCDR0_VAL + write32 PCDR1, CONFIG_SYS_PCDR1_VAL + + /* Configure PCCR0 and PCCR1 */ + write32 PCCR0, CONFIG_SYS_PCCR0_VAL + write32 PCCR1, CONFIG_SYS_PCCR1_VAL + + .endm /* init_clock */ + +/* + ************************************************************************* + * + * No jump vector table. Use reset vector as direct entry point. + * Do not support any interrupt event within SPL + * + ************************************************************************* + */ + + +.globl _start +_start: + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * setup Memory and board specific bits prior to relocation. + * relocate armboot to ram + * setup stack + * + ************************************************************************* + */ + + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * invalidate I/D cache/TLB and drain write buffer + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ + mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ + mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */ + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ + bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ + orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ + orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ + mcr p15, 0, r0, c1, c0, 0 + +init_aipi_start: + init_aipi + + /* check if sdram has been setup (running within sdram) */ + cmp pc, #0xa0000000 /* start of first sdram memory space */ + blo init_clock_start + cmp pc, #0xc0000000 /* end of second sdram memory space */ + blo regular_boot + + /* running from sdram with full code present -> regular_boot */ +init_clock_start: + init_clock + +init_sdram_start: + bl setup_sdram_ddr + + /* save state of previous boot (SDRAM is configured)*/ + BACKUP_TRACE() + + /* nand_boot BOOT_TRACE(1..13) */ + + nand_boot + + BOOT_TRACE(14) /* start regular U-Boot */ + +regular_boot: /* jump to start of next 2kiB block (U-Boot) */ + ldr r0, =0xfffff800 + and r0, r0, pc + add pc, r0, #0x800 + +do_wait_op_done: + 1: + ldrh r3, [r12, #NFC_OFFSET_CONFIG2] + ands r3, r3, #NFC_CONFIG2_INT + beq 1b + mov r3, #0x0 + strh r3, [r12, #NFC_OFFSET_CONFIG2] + mov pc, lr + +do_addr_input: + mov r9, lr + and r3, r3, #0xFF + strh r3, [r12, #NFC_OFFSET_FLASH_ADDR] + mov r3, #NFC_CONFIG2_FADD + strh r3, [r12, #NFC_OFFSET_CONFIG2] + bl do_wait_op_done + mov pc, r9 + +Test_And_Copy_Buffer: + /* check for bad block (2 bits error in main or spare are)*/ + BOOT_TRACE(9) + ldrh r4, [r12, #NFC_OFFSET_ECC_STATUS_RESULT] + ands r4, r4, #(NFC_ECC_STAT_ERROR2| \ + (NFC_ECC_STAT_ERROR2<<NFC_ECC_STAT_ERM_SHFT)) + bne Skip_Bad_Buffer + + /* check BI byte of the current spare buffer */ + ldr r4, =IMX_NFC_SPARE_AREA0 + ldrh r3, [r12, #NFC_OFFSET_BUF_ADDR] /* for the current buffer */ + orr r4, r3, lsl #0x04 + + /* at bi word offset 4. + Fixme position change betwwen 8 and 16 bits bus */ + ldrh r4, [r4, #0x04] + and r4, r4, #0x0FF00 /* has to be 0xFFxx */ + cmp r4, #0x0FF00 + bne Skip_Bad_Buffer + +Copy_Good_Buffer: + /* copying 512 bytes buffer */ + BOOT_TRACE(10) +1: ldmia r0!, {r3-r10} + stmia r11!, {r3-r10} + cmp r0, r2 + blo 1b + b End_Of_Copy + +Skip_Bad_Buffer: + BOOT_TRACE(11) + /* bad pages do not contain valid data and have to be skip */ + add r0, r0, #0x200 + + /* rewind ram addr to start of buffer */ + ldr r3, =(~0x1FF) + and r11, r11, r3 + +End_Of_Copy: + add r2, r2, #0x200 + add r1, r1, #0x200 + + mov pc, lr + + +setup_sdram_ddr: + + /* wait for SDRAM/LPDDR ready (SDRAMRDY) */ + ldr r0, =IMX_ESD_BASE + ldr r4, =ESDMISC_SDRAM_RDY +2: ldr r1, [r0, #ESDMISC_ROF] + ands r1, r1, r4 + bpl 2b + + /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */ + ldr r0, =IMX_ESD_BASE + ldr r4, =CONFIG_SYS_ESDMISC_VAL + orr r1, r4, #ESDMISC_MDDR_DL_RST + str r1, [r0, #ESDMISC_ROF] + + /* Hold for more than 200ns */ + ldr r1, =0x10000 + 1: subs r1, r1, #0x1 + bne 1b + + str r4, [r0] + + /* write32(ESDCFG0, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL) */ + ldr r0, =IMX_ESD_BASE + ldr r1, =CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL + str r1, [r0, #ESDCFG0_ROF] + + /* write32(ESDCTL0, CONFIG_SYS_PRECHARGE_CMD) */ + ldr r0, =IMX_ESD_BASE + ldr r1, =CONFIG_SYS_PRECHARGE_CMD + str r1, [r0, #ESDCTL0_ROF] + + /* write8(0xA0001000, any value) */ + ldr r1, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL + strb r2, [r1] + + /* write32(ESDCTL0, CONFIG_SYS_AUTOREFRESH_CMD) */ + ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD + str r1, [r0, #ESDCTL0_ROF] + + ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */ + + ldr r6,=0x7 /* load loop counter */ +1: str r5,[r4] /* run auto-refresh cycle to array 0 */ + subs r6,r6,#1 /* decrease counter value */ + bne 1b + + /* write32(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_SET_MODE_REG_CMD) */ + ldr r1, =CONFIG_SYS_SET_MODE_REG_CMD + str r1, [r0, #ESDCTL0_ROF] + + /* set standard mode register */ + ldr r4, = PHYS_SDRAM_1+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL + strb r2, [r4] + + /* set extended mode register */ + ldr r4, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL + strb r5, [r4] + + /* write32(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_NORMAL_RW_CMD) */ + ldr r1, =CONFIG_SYS_NORMAL_RW_CMD + str r1, [r0, #ESDCTL0_ROF] + + /* 2nd sdram */ + /* write32(ESDCFG1, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL ) */ + ldr r0, =IMX_ESD_BASE + ldr r1, =CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL + str r1, [r0, #ESDCFG1_ROF] + + /* write32(ESDCTL1, CONFIG_SYS_PRECHARGE_CMD) */ + ldr r0, =IMX_ESD_BASE + ldr r1, =CONFIG_SYS_PRECHARGE_CMD + str r1, [r0, #ESDCTL1_ROF] + + /* write8(0xB0001000, any value) */ + ldr r1, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL + strb r2, [r1] + + /* write32(ESDCTL1, CONFIG_SYS_AUTOREFRESH_CMD) */ + ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD + str r1, [r0, #ESDCTL1_ROF] + + ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */ + + ldr r6,=0x7 /* load loop counter */ +1: str r5,[r4] /* run auto-refresh cycle to array 0 */ + subs r6,r6,#1 /* decrease counter value */ + bne 1b + + /* write32(ESDCTL1, CONFIG_SYS_SET_MODE_REG_CMD) */ + ldr r1, =CONFIG_SYS_SET_MODE_REG_CMD + str r1, [r0, #ESDCTL1_ROF] + + /* set standard mode register */ + ldr r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL + strb r2, [r4] + + /* set extended mode register */ + ldr r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL + strb r2, [r4] + + /* write32(ESDCTL1, CONFIG_SYS_NORMAL_RW_CMD) */ + ldr r1, =CONFIG_SYS_NORMAL_RW_CMD + str r1, [r0, #ESDCTL1_ROF] + + mov pc, lr + diff --git a/nand_spl/board/armadeus/apf27/u-boot.lds b/nand_spl/board/armadeus/apf27/u-boot.lds new file mode 100644 index 0000000..2c5ee19 --- /dev/null +++ b/nand_spl/board/armadeus/apf27/u-boot.lds @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * (C) Copyright 2012 + * Eric Jarrige eric.jarrige@armadeus.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + start.o (.text) + *(.text) + } +}
On 06/28/2012 03:36 PM, Philippe Reynes wrote:
Signed-off-by: Philippe Reynes tremyfr@yahoo.fr Signed-off-by: Eric Jarrige eric.jarrige@armadeus.org
nand_spl/board/armadeus/apf27/Makefile | 79 +++++ nand_spl/board/armadeus/apf27/config.mk | 45 +++ nand_spl/board/armadeus/apf27/start.S | 548 ++++++++++++++++++++++++++++++ nand_spl/board/armadeus/apf27/u-boot.lds | 39 +++ 4 files changed, 711 insertions(+), 0 deletions(-) create mode 100644 nand_spl/board/armadeus/apf27/Makefile create mode 100644 nand_spl/board/armadeus/apf27/config.mk create mode 100644 nand_spl/board/armadeus/apf27/start.S create mode 100644 nand_spl/board/armadeus/apf27/u-boot.lds
nand_spl is deprecated -- please use the new spl/ infrastructure.
-Scott
+/*
- Standard NAND flash commands
- */
+#define NAND_CMD_READ0 0 +#define NAND_CMD_READ1 1 +#define NAND_CMD_PAGEPROG 0x10 +#define NAND_CMD_READOOB 0x50 +#define NAND_CMD_ERASE1 0x60 +#define NAND_CMD_STATUS 0x70 +#define NAND_CMD_STATUS_MULTI 0x71 +#define NAND_CMD_SEQIN 0x80 +#define NAND_CMD_READID 0x90 +#define NAND_CMD_ERASE2 0xd0 +#define NAND_CMD_RESET 0xff
+/* Extended commands for large page devices */ +#define NAND_CMD_READSTART 0x30 +#define NAND_CMD_CACHEDPROG 0x15
+/* Status bits */ +#define NAND_STATUS_FAIL 0x01 +#define NAND_STATUS_FAIL_N1 0x02 +#define NAND_STATUS_TRUE_READY 0x20 +#define NAND_STATUS_READY 0x40 +#define NAND_STATUS_WP 0x80
Why do you need to redefine this stuff?
-Scott
On 28/06/2012 22:36, Philippe Reynes wrote:
Signed-off-by: Philippe Reynes tremyfr@yahoo.fr Signed-off-by: Eric Jarrige eric.jarrige@armadeus.org
Hi Philippe,
nand_spl/board/armadeus/apf27/Makefile | 79 +++++ nand_spl/board/armadeus/apf27/config.mk | 45 +++ nand_spl/board/armadeus/apf27/start.S | 548 ++++++++++++++++++++++++++++++ nand_spl/board/armadeus/apf27/u-boot.lds | 39 +++ 4 files changed, 711 insertions(+), 0 deletions(-) create mode 100644 nand_spl/board/armadeus/apf27/Makefile create mode 100644 nand_spl/board/armadeus/apf27/config.mk create mode 100644 nand_spl/board/armadeus/apf27/start.S create mode 100644 nand_spl/board/armadeus/apf27/u-boot.lds
nand_spl is obsolete - new boards should add spl support with the newer SPL framework (using spl/ instead of nand_spl/)
Best regards, Stefano Babic
Signed-off-by: Philippe Reynes tremyfr@yahoo.fr Signed-off-by: Eric Jarrige eric.jarrige@armadeus.org --- board/armadeus/apf27/Makefile | 2 +- board/armadeus/apf27/apf27.c | 16 +++ board/armadeus/apf27/fpga.c | 272 +++++++++++++++++++++++++++++++++++++++++ board/armadeus/apf27/fpga.h | 39 ++++++ 4 files changed, 328 insertions(+), 1 deletions(-) create mode 100644 board/armadeus/apf27/fpga.c create mode 100644 board/armadeus/apf27/fpga.h
diff --git a/board/armadeus/apf27/Makefile b/board/armadeus/apf27/Makefile index fe6ba5c..7a39426 100644 --- a/board/armadeus/apf27/Makefile +++ b/board/armadeus/apf27/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
-COBJS := apf27.o +COBJS := apf27.o fpga.o SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c index 75be2c1..b073703 100644 --- a/board/armadeus/apf27/apf27.c +++ b/board/armadeus/apf27/apf27.c @@ -21,6 +21,7 @@
#include <common.h> #include "crc.h" +#include "fpga.h" #include <jffs2/jffs2.h> #include <nand.h> #include <netdev.h> @@ -241,6 +242,21 @@ misc_init_r(void) struct mtd_device *dev; struct part_info *part;
+#if defined(CONFIG_FPGA) + /* init and download fpga */ + if ((autoload) && (0 == strcmp(autoload, "1"))) { + if (mtdparts_init() == 0) + if (find_dev_and_part("firmware", + &dev, &pnum, &part) == 0) { + size = part->size; + if (nand_read_skip_bad(&nand_info[0], + part->offset, &size, firmware_buffer)) + size = 0; + } + } + APF27_init_fpga(firmware_buffer, size); +#endif + /* detect compatibility issue of environment version */ s = getenv("env_version"); if ((NULL == s) || (0 != strcmp(s, CONFIG_ENV_VERSION))) { diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c new file mode 100644 index 0000000..9a9e8da --- /dev/null +++ b/board/armadeus/apf27/fpga.c @@ -0,0 +1,272 @@ +/* + * (C) Copyright 2002-2012 + * Eric Jarrige eric.jarrige@armadeus.org + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include <common.h> + +#if defined(CONFIG_FPGA) + +#include <asm/arch/imx-regs.h> +#include <asm/io.h> +#include <command.h> +#include <config.h> +#include "fpga.h" +#include <spartan3.h> + +#define GPIO_PORT(x) ((x & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT) +#define GPIO_SET(x) writel(readl(&gpregs->port[GPIO_PORT(x)].dr) | \ + (1 << (x & GPIO_PIN_MASK)), &gpregs->port[GPIO_PORT(x)].dr) + +/* (DR(GPIO_PORT(x)) |= (1<<(x & GPIO_PIN_MASK))) */ +#define GPIO_CLEAR(x) writel(readl(&gpregs->port[GPIO_PORT(x)].dr) & \ + ~(1 << (x & GPIO_PIN_MASK)), &gpregs->port[GPIO_PORT(x)].dr) +/* (DR(GPIO_PORT(x)) &= ~(1<<(x & GPIO_PIN_MASK))) */ +#define GPIO_WRITE(x, y) (y ? GPIO_SET(x) : GPIO_CLEAR(x)) +#define GPIO_READ(x) ((readl(&gpregs->port[GPIO_PORT(x)].ssr) & \ + (1 << (x & GPIO_PIN_MASK))) >> (x & GPIO_PIN_MASK)) +/* ((SSR (GPIO_PORT(x)) & (1<<(x & GPIO_PIN_MASK)))>> (x & GPIO_PIN_MASK)) */ +#ifdef FPGA_DEBUG +#define PRINTF(fmt, args...) printf(fmt, ##args) +#else +#define PRINTF(fmt, args...) +#endif + +/* Note that these are pointers to code that is in Flash. They will be + * relocated at runtime. + * Spartan2 code is used to download our Spartan 3 :) code is compatible. + * Just take care about the file size +*/ +Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = { + fpga_pre_fn, + fpga_pgm_fn, + fpga_init_fn, + NULL, + fpga_done_fn, + fpga_clk_fn, + fpga_cs_fn, + fpga_wr_fn, + fpga_rdata_fn, + fpga_wdata_fn, + fpga_busy_fn, + fpga_abort_fn, + fpga_post_fn, +}; + +Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { + {Xilinx_Spartan3, + slave_parallel, + 1196128l/8, + (void *) &fpga_fns, + 0} +}; + +/* + * nitialize GPIO port B before download + */ +int +fpga_pre_fn(int cookie) +{ + struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE; + /* Initialize GPIO pins */ + GPIO_SET(CONFIG_SYS_FPGA_PWR); + imx_gpio_mode(CONFIG_SYS_FPGA_INIT | GPIO_IN | GPIO_PUEN | GPIO_GPIO); + imx_gpio_mode(CONFIG_SYS_FPGA_DONE | GPIO_IN | GPIO_PUEN | GPIO_GPIO); + imx_gpio_mode(CONFIG_SYS_FPGA_PRG | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); + imx_gpio_mode(CONFIG_SYS_FPGA_CLK | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); + imx_gpio_mode(CONFIG_SYS_FPGA_RW | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); + imx_gpio_mode(CONFIG_SYS_FPGA_CS | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); + imx_gpio_mode(CONFIG_SYS_FPGA_SUSPEND|GPIO_OUT|GPIO_PUEN|GPIO_GPIO); + GPIO_SET(CONFIG_SYS_FPGA_RESET); + imx_gpio_mode(CONFIG_SYS_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); + imx_gpio_mode(CONFIG_SYS_FPGA_PWR | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); + GPIO_SET(CONFIG_SYS_FPGA_PRG); + GPIO_SET(CONFIG_SYS_FPGA_CLK); + GPIO_SET(CONFIG_SYS_FPGA_RW); + GPIO_SET(CONFIG_SYS_FPGA_CS); + GPIO_CLEAR(CONFIG_SYS_FPGA_SUSPEND); +/* GPIO_CLEAR(CONFIG_SYS_FPGA_RESET); */ + GPIO_CLEAR(CONFIG_SYS_FPGA_PWR); + + return cookie; +} + +/* + * Set the FPGA's active-low program line to the specified level + */ +int +fpga_pgm_fn(int assert, int flush, int cookie) +{ + struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE; + PRINTF("%s:%d: FPGA PROGRAM %s", __func__, __LINE__, + assert ? "high" : "low"); + GPIO_WRITE(CONFIG_SYS_FPGA_PRG, !assert); + return assert; +} + +/* + * Set the FPGA's active-high clock line to the specified level + */ +int +fpga_clk_fn(int assert_clk, int flush, int cookie) +{ + struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE; + PRINTF("%s:%d: FPGA CLOCK %s", __func__, __LINE__, + assert_clk ? "high" : "low"); + GPIO_WRITE(CONFIG_SYS_FPGA_CLK, !assert_clk); + return assert_clk; +} + +/* + * Test the state of the active-low FPGA INIT line. Return 1 on INIT + * asserted (low). + */ +int +fpga_init_fn(int cookie) +{ + struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE; + int value; + PRINTF("%s:%d: INIT check... ", __func__, __LINE__); + value = GPIO_READ(CONFIG_SYS_FPGA_INIT); + /* printf("init value read %x",value); */ +#ifdef CONFIG_SYS_FPGA_IS_PROTO + return value; +#else + return !value; +#endif +} + +/* + * Test the state of the active-high FPGA DONE pin + */ +int +fpga_done_fn(int cookie) +{ + struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE; + PRINTF("%s:%d: DONE check... %s", __func__, __LINE__, + GPIO_READ(CONFIG_SYS_FPGA_DONE) ? "high" : "low"); + return GPIO_READ(CONFIG_SYS_FPGA_DONE) ? FPGA_SUCCESS : FPGA_FAIL; +} + +/* + * Set the FPGA's wr line to the specified level + */ +int +fpga_wr_fn(int assert_write, int flush, int cookie) +{ + struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE; + PRINTF("%s:%d: FPGA RW... %s ", __func__, __LINE__, + assert_write ? "high" : "low"); + GPIO_WRITE(CONFIG_SYS_FPGA_RW, !assert_write); + return assert_write; +} + +int +fpga_cs_fn(int assert_cs, int flush, int cookie) +{ + struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE; + PRINTF("%s:%d: FPGA CS %s ", __func__, __LINE__, + assert_cs ? "high" : "low"); + GPIO_WRITE(CONFIG_SYS_FPGA_CS, !assert_cs); + return assert_cs; +} + +int +fpga_rdata_fn(unsigned char *data, int cookie) +{ + PRINTF("%s:%d: FPGA READ DATA %02X ", __func__, __LINE__, + *((char *)CONFIG_SYS_FPGA_RDATA)); + *data = (unsigned char) \ + ((*((unsigned short *)CONFIG_SYS_FPGA_RDATA))&0x00FF); + return *data; +} + +int +fpga_wdata_fn(unsigned char data, int cookie) +{ + PRINTF("%s:%d: FPGA WRITE DATA %02X ", __func__, __LINE__, + data); + *((unsigned short *)CONFIG_SYS_FPGA_WDATA) = data; + return data; +} + +int +fpga_abort_fn(int cookie) +{ + return cookie; +} + + +int +fpga_busy_fn(int cookie) +{ + return 1; +} + +int +fpga_post_fn(int cookie) +{ + struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE; + PRINTF("%s:%d: FPGA POST ", __func__, __LINE__); + + imx_gpio_mode(CONFIG_SYS_FPGA_RW | GPIO_PF | GPIO_PUEN); + imx_gpio_mode(CONFIG_SYS_FPGA_CS | GPIO_PF | GPIO_PUEN); + imx_gpio_mode(CONFIG_SYS_FPGA_CLK | GPIO_PF | GPIO_PUEN); + GPIO_SET(CONFIG_SYS_FPGA_PRG); + GPIO_CLEAR(CONFIG_SYS_FPGA_RESET); + imx_gpio_mode(CONFIG_SYS_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO); + return cookie; +} + +/* + * Initialize the fpga. Return 1 on success, 0 on failure. + */ +int +APF27_init_fpga(u_char *buffer, size_t size) +{ + char *autoload = getenv("firmware_autoload"); + + int i, lout = 0; + + fpga_init(); + + for (i = 0; i < CONFIG_FPGA_COUNT; i++) { + PRINTF("%s:%d: Adding fpga %d\n", __func__, __LINE__, i); + fpga_add(fpga_xilinx, &fpga[i]); + } + + if ((size >= fpga[0].size) && (autoload) && + (0 == strcmp(autoload, "1"))) { + if (ctrlc()) { + printf("Firmware download stopped!\n"); + } else if (FPGA_SUCCESS != fpga_load(0, (void *)buffer, size)) { + printf("Firmware download failed!\n"); + } else { + printf("Firmware successfully programmed\n"); + lout = 1; + } + } + return lout; +} + +#endif /* CONFIG_FPGA */ diff --git a/board/armadeus/apf27/fpga.h b/board/armadeus/apf27/fpga.h new file mode 100644 index 0000000..b11b24c --- /dev/null +++ b/board/armadeus/apf27/fpga.h @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2002-2012 + * Eric Jarrige eric.jarrige@armadeus.org + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +extern int APF27_init_fpga(u_char *buffer, size_t size); + +extern int fpga_pre_fn(int cookie); +extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); +extern int fpga_cs_fn(int assert_cs, int flush, int cookie); +extern int fpga_init_fn(int cookie); +extern int fpga_done_fn(int cookie); +extern int fpga_clk_fn(int assert_clk, int flush, int cookie); +extern int fpga_wr_fn(int assert_write, int flush, int cookie); +extern int fpga_rdata_fn(unsigned char *data, int cookie); +extern int fpga_wdata_fn(unsigned char data, int cookie); +extern int fpga_abort_fn(int cookie); +extern int fpga_post_fn(int cookie); +extern int fpga_busy_fn(int cookie);
On 28/06/2012 22:36, Philippe Reynes wrote:
Signed-off-by: Philippe Reynes tremyfr@yahoo.fr Signed-off-by: Eric Jarrige eric.jarrige@armadeus.org
Hi Philippe,
- */
+#include <common.h>
+#if defined(CONFIG_FPGA)
Maybe you can drop this and compiling this file only if CONFIG_FPGA is set, changing your Makefile
+#define GPIO_PORT(x) ((x & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT) +#define GPIO_SET(x) writel(readl(&gpregs->port[GPIO_PORT(x)].dr) | \
(1 << (x & GPIO_PIN_MASK)), &gpregs->port[GPIO_PORT(x)].dr)+/* (DR(GPIO_PORT(x)) |= (1<<(x & GPIO_PIN_MASK))) */ +#define GPIO_CLEAR(x) writel(readl(&gpregs->port[GPIO_PORT(x)].dr) & \
~(1 << (x & GPIO_PIN_MASK)), &gpregs->port[GPIO_PORT(x)].dr)+/* (DR(GPIO_PORT(x)) &= ~(1<<(x & GPIO_PIN_MASK))) */ +#define GPIO_WRITE(x, y) (y ? GPIO_SET(x) : GPIO_CLEAR(x)) +#define GPIO_READ(x) ((readl(&gpregs->port[GPIO_PORT(x)].ssr) & \
(1 << (x & GPIO_PIN_MASK))) >> (x & GPIO_PIN_MASK))
No, we have in u-boot a GPIO API to access the GPIOs. Check ./include/asm-generic/gpio.h, and the implementation for other i.MX SOCs.
+#ifdef FPGA_DEBUG +#define PRINTF(fmt, args...) printf(fmt, ##args) +#else +#define PRINTF(fmt, args...) +#endif
Do not set your special version - use DEBUG instead
+/* Note that these are pointers to code that is in Flash. They will be
- relocated at runtime.
- Spartan2 code is used to download our Spartan 3 :) code is compatible.
- Just take care about the file size
+*/
Wrong multiline comment - it should be like this:
/* * Part of your multiline * comment */
Please check this issue everywhere in your code
+Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = {
- fpga_pre_fn,
- fpga_pgm_fn,
- fpga_init_fn,
- NULL,
- fpga_done_fn,
- fpga_clk_fn,
- fpga_cs_fn,
- fpga_wr_fn,
- fpga_rdata_fn,
- fpga_wdata_fn,
- fpga_busy_fn,
- fpga_abort_fn,
- fpga_post_fn,
+};
+Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
- {Xilinx_Spartan3,
slave_parallel,1196128l/8,(void *) &fpga_fns,0}+};
+/*
- nitialize GPIO port B before download
initialize
Best regards, Stefano Babic
Signed-off-by: Philippe Reynes tremyfr@yahoo.fr --- include/configs/apf27.h | 916 +++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 916 insertions(+), 0 deletions(-) create mode 100644 include/configs/apf27.h
diff --git a/include/configs/apf27.h b/include/configs/apf27.h new file mode 100644 index 0000000..985fa1a --- /dev/null +++ b/include/configs/apf27.h @@ -0,0 +1,916 @@ +/* + * + * Configuration settings for the Armadeus Project motherboard APF27 + * + * Copyright (C) 2008-2012 ej / Armadeus Project eric.jarrige@armadeus.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_VERSION_VARIABLE +#define CONFIG_ENV_VERSION "3.1" +#define CONFIG_IDENT_STRING " apf27 patch 3.6" +#define CONFIG_BOARD_NAME apf27 + +/* + * SoC configurations + */ +#define CONFIG_ARM926EJS /* this is an ARM926EJS CPU */ +#define CONFIG_MX27 /* in a Freescale i.MX27 Chip */ +#define CONFIG_MACH_TYPE 1698 /* APF27 */ + +/* + * Enable the call to miscellaneous platform dependent initialization. + */ +#define CONFIG_SYS_NO_FLASH /* to be define before <config_cmd_default.h> */ +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_MISC_INIT_R + +/* + * Board display option + */ +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_DISPLAY_CPUINFO + +/* + * SPL + */ +#define CONFIG_NAND_U_BOOT +/* Copy SPL+U-Boot here */ +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_LOAD_ADDR +/* Size is the partion size */ +#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 + +#define CONFIG_HOSTNAME CONFIG_BOARD_NAME +#define CONFIG_ROOTPATH "/tftpboot/" MK_STR(CONFIG_BOARD_NAME) "-root" + +/* + * U-Boot Commands + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV /* ask for env variable */ +#define CONFIG_CMD_BSP /* Board Specific functions */ +#define CONFIG_CMD_CACHE /* icache, dcache */ +/*#define CONFIG_CMD_DATE */ /* support for RTC, date/time...*/ +#define CONFIG_CMD_DHCP /* DHCP Support */ +#define CONFIG_CMD_DNS +/*#define CONFIG_CMD_EEPROM */ /* EEPROM read/write support */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT /* FAT support */ +/*#define CONFIG_CMD_I2C */ /* I2C serial bus support */ +#define CONFIG_CMD_IMX_FUSE /* imx iim fuse */ +#define CONFIG_CMD_MII /* MII support */ +#define CONFIG_CMD_MMC +#define CONFIG_CMD_MTDPARTS /* MTD partition support */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_NAND_LOCK_UNLOCK +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_PING /* ping support */ +#define CONFIG_CMD_SETEXPR /* setexpr support */ +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS + +/* + * Memory configurations + */ +#define CONFIG_NR_DRAM_POPULATED 1 +#define CONFIG_NR_DRAM_BANKS 2 + +#define CONFIG_SYS_SDRAM_MBYTE_SYZE 64 + +#define PHYS_SDRAM_1 0xA0000000 +#define PHYS_SDRAM_2 0xB0000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10)) +#define CONFIG_SYS_GBL_DATA_SIZE 256 /* Initial data */ +#define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */ +#define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */ + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \ + + PHYS_SDRAM_1_SIZE - 0x0100000) + +#define CONFIG_SYS_TEXT_BASE 0xA1000000 + +/* + * FLASH organization + */ +/*#define CONFIG_SYS_MONITOR_BASE 0xAFF00000*/ +#define CONFIG_SYS_MONITOR_OFFSET 0x00000000 +#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */ +#define CONFIG_ENV_SIZE 0x00020000 /* 128kB */ +#define CONFIG_ENV_RANGE 0X00080000 /* 512kB */ +#define CONFIG_ENV_OFFSET_REDUND \ + (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */ +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */ +#define CONFIG_FIRMWARE_OFFSET 0x00200000 +#define CONFIG_KERNEL_OFFSET 0x00300000 +#define CONFIG_ROOTFS_OFFSET 0x00800000 + +#define CONFIG_MTDMAP "mxc_nand.0" +#define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP +#define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP \ + ":1M(u-boot)ro," \ + "512K(env)," \ + "512K(env2)," \ + "512K(firmware)," \ + "512K(dtb)," \ + "5M(kernel)," \ + "-(rootfs)" + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "BIOS> " /* prompt string */ +#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 16 /* max command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_HUSH_PARSER /* enable the "hush" shell */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* secondary prompt string */ + +/* + * Boot Linux + */ +#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ +#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ +#define CONFIG_INITRD_TAG /* send initrd params */ + +/* #define CONFIG_REVISION_TAG */ +#define CONFIG_OF_LIBFDT + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_BOOTFILE MK_STR(CONFIG_BOARD_NAME) "-linux.bin" +#define CONFIG_BOOTARGS "console=" MK_STR(ACFG_CONSOLE_DEV) "," \ + MK_STR(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \ + " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs " + +#define ACFG_CONSOLE_DEV ttySMX0 +#define CONFIG_BOOTCOMMAND "run ubifsboot" +#define CONFIG_SYS_AUTOLOAD "no" +/* + * Default load address for user programs and kernel + */ +#define CONFIG_LOADADDR 0xA0000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_TFTP_LOADADDR CONFIG_LOADADDR + +/* + * Extra Environments + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "env_version=" CONFIG_ENV_VERSION "\0" \ + "consoledev=" MK_STR(ACFG_CONSOLE_DEV) "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "partition=nand0,6\0" \ + "u-boot_addr=" MK_STR(CONFIG_SYS_MONITOR_OFFSET) "\0" \ + "env_addr=" MK_STR(CONFIG_ENV_OFFSET) "\0" \ + "firmware_addr=" MK_STR(CONFIG_FIRMWARE_OFFSET) "\0" \ + "kernel_addr=" MK_STR(CONFIG_KERNEL_OFFSET) "\0" \ + "rootfs_addr=" MK_STR(CONFIG_ROOTFS_OFFSET) "\0" \ + "board_name=" MK_STR(CONFIG_BOARD_NAME) "\0" \ + "kernel_addr_r=A0000000\0" \ + "addnfsargs=setenv bootargs ${bootargs} " \ + "root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ + "addubifsargs=setenv bootargs ${bootargs} " \ + "ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \ + "addmmcargs=setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk0p1 rootfstype=ext2\0" \ + "addipargs=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ + "${hostname}:eth0:off \0" \ + "nfsboot=setenv bootargs console=${consoledev},${baudrate} " \ + "${mtdparts}; run addnfsargs addipargs;" \ + "nfs ${kernel_addr_r} " \ + "${serverip}:${rootpath}/boot/${board_name}-linux.bin;" \ + "if test -n ${fdt_addr_r} ; then " \ + "nand read ${fdt_addr_r} dtb; fi;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "ubifsboot=setenv bootargs console=${consoledev},${baudrate} " \ + "${mtdparts};run addubifsargs addipargs;" \ + "if test -n ${fdt_addr_r} ; then " \ + "nand read ${fdt_addr_r} dtb; fi;" \ + "nboot ${kernel_addr_r} kernel;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "mmcboot=setenv bootargs console=${consoledev},${baudrate} " \ + "${mtdparts}; run addmmcargs addipargs;" \ + "if test -n ${fdt_addr_r} ; then " \ + "nand read ${fdt_addr_r} dtb; fi;" \ + "mmc dev 0; ext2load mmc 0 ${kernel_addr_r}" \ + " /boot/${board_name}-linux.bin;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "boot_nfs_fallback_flash=if ping ${serverip};" \ + "then echo Boot over NFS; run nfsboot;" \ + "else echo Boot from the board; run ubifsboot;" \ + "fi\0" \ + "firmware_autoload=0\0" \ + "flash_uboot=nand unlock ${u-boot_addr} ;" \ + "nand erase.part u-boot;" \ + "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\ + "then nand lock; nand unlock ${env_addr};" \ + "echo Flashing of uboot succeed;" \ + "else echo Flashing of uboot failed;" \ + "fi; \0" \ + "flash_firmware=nand erase.part firmware;" \ + "if nand write.trimffs ${fileaddr} ${firmware_addr} ${filesize};"\ + "then echo Flashing of Firmware succeed;" \ + "else echo Flashing of Firmware failed;" \ + "fi\0" \ + "flash_kernel=nand erase.part kernel;" \ + "if nand write.trimffs ${fileaddr} ${kernel_addr} ${filesize};"\ + "then echo Flashing of kernel succeed;" \ + "else echo Flashing of kernel failed;" \ + "fi\0" \ + "flash_rootfs=nand erase.part rootfs;" \ + "if nand write.trimffs ${fileaddr} ${rootfs_addr} ${filesize};"\ + "then echo Flashing of rootfs succeed;" \ + "else echo Flashing of rootfs failed;" \ + "fi\0" \ + "flash_dtb=nand erase.part dtb;" \ + "if nand write.trimffs ${fileaddr} dtb ${filesize};" \ + "then echo Flashing of rootfs succeed;" \ + "else echo Flashing of rootfs failed;" \ + "fi\0" \ + "flash_reset_env=env default -f; saveenv;" \ + "echo Flash environment variables erased!\0" \ + "download_uboot=tftpboot ${loadaddr} ${board_name}-u-boot-nand.bin\0" \ + "download_kernel=tftpboot ${loadaddr} ${board_name}-linux.bin\0" \ + "download_rootfs=tftpboot ${loadaddr} ${board_name}-rootfs.ubi\0" \ + "download_dtb=tftpboot ${loadaddr} imx27-${board_name}.dtb\0" \ + "update_uboot=run download_uboot flash_uboot\0" \ + "update_kernel=run download_kernel flash_kernel\0" \ + "update_rootfs=run download_rootfs flash_rootfs\0" \ + "update_dtb=run download_dtb flash_dtb\0" \ + "update_all=run download_kernel flash_kernel download_rootfs " \ + "flash_rootfs download_uboot flash_uboot\0" \ + "unlock_regs=mw 10000008 0; mw 10020008 0\0" \ + +/* + * Serial Driver + */ +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX27_UART1 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_BAUDRATE 115200 +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* + * GPIO + */ + +/* + * NOR + */ + +/* + * NAND + */ +#define CONFIG_NAND_MXC + +#define CONFIG_MXC_NAND_REGS_BASE 0xD8000000 +#define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define CONFIG_MXC_NAND_HWECC +#define CONFIG_SYS_NAND_LARGEPAGE +#define IMX27_NAND_16BITS +#define NAND_MAX_CHIPS 1 + +/* #define CONFIG_SYS_DIRECT_FLASH_TFTP */ +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_SYS_NAND_QUIET 1 + +#define CONFIG_BOOT_TRACE_REG 0xAFFFFFF8 /* Addr to store traces of SPL boot*/ + +/* + * Partitions & Filsystems + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_VFAT + +/* + * UBIFS + */ +#define CONFIG_RBTREE +#define CONFIG_LZO + +/* + * Ethernet (on SOC imx FEC) + */ +#define CONFIG_FEC_MXC + +#define CONFIG_NET_MULTI +#define CONFIG_FEC_MXC_PHYADDR 0x1f +#define CONFIG_MII 1 /* MII PHY management */ + +/* + * FPGA + */ +#define CONFIG_FPGA CONFIG_SYS_SPARTAN3 +#define CONFIG_FPGA_COUNT 1 +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_SPARTAN3 +#define CONFIG_SYS_FPGA_WAIT 20000 /* 20 ms */ +#define CONFIG_SYS_FPGA_PROG_FEEDBACK +#define CONFIG_SYS_FPGA_CHECK_CTRLC +#define CONFIG_SYS_FPGA_CHECK_ERROR +#if 0 +#define CONFIG_SYS_FPGA_IS_PROTO /* to be defined with apf27 board prototype */ +#endif + +/* FPGA program pin configuration */ +#define CONFIG_SYS_FPGA_PWR (GPIO_PORTF | 19) /* FPGA prog pin */ +#define CONFIG_SYS_FPGA_PRG (GPIO_PORTF | 11) /* FPGA prog pin */ +#define CONFIG_SYS_FPGA_CLK (GPIO_PORTF | 15) /* FPGA clk pin */ +#define CONFIG_SYS_FPGA_RDATA 0xD6000000 /* FPGA data addr */ +#define CONFIG_SYS_FPGA_WDATA 0xD6000000 /* FPGA data addr */ +#define CONFIG_SYS_FPGA_INIT (GPIO_PORTF | 12) /* FPGA init pin */ +#define CONFIG_SYS_FPGA_DONE (GPIO_PORTF | 9) /* FPGA done pin */ +#define CONFIG_SYS_FPGA_RW (GPIO_PORTF | 21) /* FPGA done pin */ +#define CONFIG_SYS_FPGA_CS (GPIO_PORTF | 22) /* FPGA done pin */ +#define CONFIG_SYS_FPGA_SUSPEND (GPIO_PORTF | 10) /* FPGA done pin */ +#define CONFIG_SYS_FPGA_RESET (GPIO_PORTF | 7) /* FPGA done pin */ + +/* + * Fuses - IIM + */ +#ifdef CONFIG_CMD_IMX_FUSE +#define IIM_MAC_BANK 0 +#define IIM_MAC_ROW 5 +#define IIM0_SCC_KEY 11 +#define IIM1_SUID 1 +#endif + +/* + * I2C + */ + +#ifdef CONFIG_CMD_I2C +#define CONFIG_HARD_I2C 1 + +#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ +#define CONFIG_SYS_I2C_SLAVE 0x7F + +#define CONFIG_I2C_CMD_TREE +#define CONFIG_I2C_MULTI_BUS 2 +#define CONFIG_SYS_I2C_NOPROBES { } + +#ifdef CONFIG_CMD_EEPROM +# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */ +# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */ +#endif /* CONFIG_CMD_EEPROM */ +#endif /* CONFIG_CMD_I2C */ + +/* + * SPI + */ + +/* + * SD/MMC + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MXC_MMC +#define CONFIG_MXC_MCI_REGS_BASE 0x10014000 +#endif + +/* + * RTC + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_DS1374 +#define CONFIG_SYS_RTC_BUS_NUM 0 +#endif /* CONFIG_CMD_DATE */ + +/* + * Watchdog Config + */ + +/* + * USB + */ + +/* + * Clocks + */ +#define CONFIG_SYS_HZ 1000 /* Ticks per second */ + +/* + * PLL + * + * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0 + * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------| + */ +#define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */ +#undef CONFIG_MX27_CLK26 /* No external 26MHz external clock */ + +/* MPU CLOCK source before PLL */ +/* CONFIG_SYS_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ) */ +#ifndef CONFIG_MX27_CLK26 +#if (CONFIG_MX27_CLK32 == 32000) +#define CONFIG_SYS_MPCTL0_VAL 0x00211803 /* 398.998 MHz */ +#define CONFIG_SYS_MPCTL1_VAL 0 +#define CONFIG_MPLL_FREQ 399 +#else /* CONFIG_MX27_CLK32 == 32768*/ +#define CONFIG_SYS_MPCTL0_VAL 0x01EF15D5 /* 399.000 MHz */ +#define CONFIG_SYS_MPCTL1_VAL 0 +#define CONFIG_MPLL_FREQ 399 +#endif /* CONFIG_MX27_CLK32 */ +#else /* CONFIG_MX27_CLK26 in use*/ +#define CONFIG_SYS_MPCTL0_VAL 0x00331C23 /* 399.000 MHz */ +#define CONFIG_SYS_MPCTL1_VAL 0 +#define CONFIG_MPLL_FREQ 399 +#endif /* CONFIG_MX27_CLK26 */ + +#define CONFIG_SYS_CLK_FREQ (CONFIG_MPLL_FREQ*2/3) /* 266 MHz */ + +/* Serial clock source before PLL (should be named CONFIG_SYS_SYSPLL_CLK_FREQ)*/ +#ifndef CONFIG_MX27_CLK26 +/*#define CONFIG_SYSPLL_CLK_FREQ (1024*CONFIG_MX27_CLK32)*/ +#if (CONFIG_MX27_CLK32 == 32000) +#define CONFIG_SYS_SPCTL0_VAL 0x04A02419 /* 300.00020 MHz */ +#define CONFIG_SYS_SPCTL1_VAL 0 +#define CONFIG_SPLL_FREQ 300 /* MHz */ +#else /* CONFIG_MX27_CLK32 == 32768*/ +#define CONFIG_SYS_SPCTL0_VAL 0x0475206F /* 299.99937 MHz */ +#define CONFIG_SYS_SPCTL1_VAL 0 +#define CONFIG_SPLL_FREQ 300 /* MHz */ +#endif /* CONFIG_MX27_CLK32 */ +#else /* CONFIG_MX27_CLK26 in use*/ +/*#define CONFIG_SYSPLL_CLK_FREQ CONFIG_MX27_CLK26*/ +#define CONFIG_SYS_SPCTL0_VAL 0x040C2C07 /* 300 MHz */ +#define CONFIG_SYS_SPCTL1_VAL 0x0 +#define CONFIG_SPLL_FREQ 300 /* MHz */ +#endif /* CONFIG_MX27_CLK26 */ + +/* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */ +#define CONFIG_ARM_FREQ 399 /* up to 400 MHz */ + +/* external bus frequency (have to be a CONFIG_SYS_CLK_FREQ ratio) */ +#define CONFIG_HCLK_FREQ 133 /* (CONFIG_SYS_CLK_FREQ/2) */ + +#define CONFIG_PERIF1_FREQ 16 /* 16.625 MHz UART, GPT, PWM*/ +#define CONFIG_PERIF2_FREQ 33 /* 33.25 MHz CSPI and SDHC */ +#define CONFIG_PERIF3_FREQ 33 /* 33.25 MHz LCD*/ +#define CONFIG_PERIF4_FREQ 33 /* 33.25 MHz CSI*/ +#define CONFIG_SSI1_FREQ 66 /* 66.50 MHz SSI1*/ +#define CONFIG_SSI2_FREQ 66 /* 66.50 MHz SSI2*/ +#define CONFIG_MSHC_FREQ 66 /* 66.50 MHz MSHC*/ +#define CONFIG_H264_FREQ 66 /* 66.50 MHz H264*/ +#define CONFIG_CLK0_DIV 3 /* Divide CLK0 by 4 */ +#define CONFIG_CLK0_EN 1 /* CLK0 enabled */ + +/* external bus frequency (have to be a CONFIG_HCLK_FREQ ratio) */ +#define CONFIG_NFC_FREQ 44 /* NFC Clock up to 44 MHz wh 133MHz*/ + +/* external serial bus frequency (have to be a CONFIG_SPLL_FREQ ratio) */ +#define CONFIG_USB_FREQ 60 /* 60 MHz */ + +/* + * SDRAM + */ +#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ +/* micron 64MB */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ +#define CONFIG_SYS_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 + column address bits */ +#define CONFIG_SYS_SDRAM_NUM_ROW 13 /* 11, 12 or 13 + row address bits */ +#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 + 2=4096 3=8192 refresh */ +#define CONFIG_SYS_SDRAM_EXIT_PWD 25 /* ns exit power + down delay */ +#define CONFIG_SYS_SDRAM_W2R_DELAY 1 /* write to read + cycle delay > 0 */ +#define CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ +#define CONFIG_SYS_SDRAM_TMRD_DELAY 2 /* Load mode register + cycle delay 1..4 */ +#define CONFIG_SYS_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck; + SDRAM: 0=1ck 1=2ck*/ +#define CONFIG_SYS_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE + delay */ +#define CONFIG_SYS_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE + delay */ +#define CONFIG_SYS_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ +#define CONFIG_SYS_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC + refresh to command) */ +#define CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time + estimated fo CL=1 + 0=force 3 for lpddr */ +#define CONFIG_SYS_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater + 3=Eighth 4=Sixteenth */ +#define CONFIG_SYS_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half + 2=quater 3=Eighth */ +#define CONFIG_SYS_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ +#define CONFIG_SYS_SDRAM_SINGLE_ACCESS 0 /* 1= single access; + 0 = Burst mode */ +#endif + +#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 128) +/* micron 128MB */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ +#define CONFIG_SYS_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 + column address bits */ +#define CONFIG_SYS_SDRAM_NUM_ROW 14 /* 11, 12 or 13 + row address bits */ +#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 + 2=4096 3=8192 refresh */ +#define CONFIG_SYS_SDRAM_EXIT_PWD 25 /* ns exit power + down delay */ +#define CONFIG_SYS_SDRAM_W2R_DELAY 1 /* write to read + cycle delay > 0 */ +#define CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ +#define CONFIG_SYS_SDRAM_TMRD_DELAY 2 /* Load mode register + cycle delay 1..4 */ +#define CONFIG_SYS_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck; + SDRAM: 0=1ck 1=2ck*/ +#define CONFIG_SYS_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE + delay */ +#define CONFIG_SYS_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE + delay */ +#define CONFIG_SYS_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ +#define CONFIG_SYS_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC + refresh to command)*/ +#define CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time + estimated fo CL=1 + 0=force 3 for lpddr*/ +#define CONFIG_SYS_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater + 3=Eighth 4=Sixteenth */ +#define CONFIG_SYS_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half + 2=quater 3=Eighth */ +#define CONFIG_SYS_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ +#define CONFIG_SYS_SDRAM_SINGLE_ACCESS 0 /* 1= single access; + 0 = Burst mode */ +#endif + +#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 256) +/* micron 256MB */ +#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ +#define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */ +#define CONFIG_SYS_SDRAM_NUM_COL 10 /* 8, 9, 10 or 11 + column address bits */ +#define CONFIG_SYS_SDRAM_NUM_ROW 14 /* 11, 12 or 13 + row address bits */ +#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 + 2=4096 3=8192 refresh */ +#define CONFIG_SYS_SDRAM_EXIT_PWD 25 /* ns exit power + down delay */ +#define CONFIG_SYS_SDRAM_W2R_DELAY 1 /* write to read cycle + delay > 0 */ +#define CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ +#define CONFIG_SYS_SDRAM_TMRD_DELAY 2 /* Load mode register + cycle delay 1..4 */ +#define CONFIG_SYS_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck; + SDRAM: 0=1ck 1=2ck */ +#define CONFIG_SYS_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE + delay */ +#define CONFIG_SYS_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE + delay */ +#define CONFIG_SYS_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ +#define CONFIG_SYS_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC + refresh to command) */ +#define CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time + estimated fo CL=1 + 0=force 3 for lpddr */ +#define CONFIG_SYS_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater + 3=Eighth 4=Sixteenth */ +#define CONFIG_SYS_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength + 1=half + 2=quater + 3=Eighth */ +#define CONFIG_SYS_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ +#define CONFIG_SYS_SDRAM_SINGLE_ACCESS 0 /* 1= single access; + 0 = Burst mode */ +#endif + +/* + * External interface + */ +/* + * CSCRxU_VAL: + * 31| x | x | x x |x x x x| x x | x | x |x x x x|16 + * |SP |WP | BCD | BCS | PSZ |PME|SYNC| DOL | + * + * 15| x x | x x x x x x | x | x x x x | x x x x |0 + * | CNC | WSC |EW | WWS | EDC | + * + * CSCRxL_VAL: + * 31| x x x x | x x x x | x x x x | x x x x |16 + * | OEA | OEN | EBWA | EBWN | + * 15|x x x x| x |x x x |x x x x| x | x | x | x | 0 + * | CSA |EBC| DSZ | CSN |PSR|CRE|WRAP|CSEN| + * + * CSCRxA_VAL: + * 31| x x x x | x x x x | x x x x | x x x x |16 + * | EBRA | EBRN | RWA | RWN | + * 15| x | x x |x x x|x x|x x|x x| x | x | x | x | 0 + * |MUM| LAH | LBN |LBA|DWW|DCT|WWU|AGE|CNC2|FCE| + */ + +/* CS0 configuration for 16 bit nor flash */ +#define CONFIG_SYS_CS0U_VAL 0x0000CC03 +#define CONFIG_SYS_CS0L_VAL 0xa0330D01 +#define CONFIG_SYS_CS0A_VAL 0x00220800 + +#define CONFIG_SYS_CS1U_VAL 0x00000f00 +#define CONFIG_SYS_CS1L_VAL 0x00000D01 +#define CONFIG_SYS_CS1A_VAL 0 + +#define CONFIG_SYS_CS2U_VAL 0 +#define CONFIG_SYS_CS2L_VAL 0 +#define CONFIG_SYS_CS2A_VAL 0 + +#define CONFIG_SYS_CS3U_VAL 0 +#define CONFIG_SYS_CS3L_VAL 0 +#define CONFIG_SYS_CS3A_VAL 0 + +#define CONFIG_SYS_CS4U_VAL 0 +#define CONFIG_SYS_CS4L_VAL 0 +#define CONFIG_SYS_CS4A_VAL 0 + +/* FPGA 16 bit data bus */ +#define CONFIG_SYS_CS5U_VAL 0x00000600 +#define CONFIG_SYS_CS5L_VAL 0x00000D01 +#define CONFIG_SYS_CS5A_VAL 0 + +#define CONFIG_SYS_EIM_VAL 0x00002200 + +/* FPGA specific settings */ +/* CLKO */ +#define CONFIG_SYS_CCSR_VAL 0x00000305 +/* drive strength CLKO set to 2*/ +#define CONFIG_SYS_DSCR10_VAL 0x00020000 +/* drive strength A1..A12 set to 2*/ +#define CONFIG_SYS_DSCR3_VAL 0x02AAAAA8 +/* drive strength ctrl*/ +#define CONFIG_SYS_DSCR7_VAL 0x00020880 +/* drive strength data*/ +#define CONFIG_SYS_DSCR2_VAL 0xAAAAAAAA + + +/* + * Default configuration for GPIOs and peripherals + */ +#define CONFIG_SYS_DDIR_A_VAL 0x00000000 +#define CONFIG_SYS_OCR1_A_VAL 0x00000000 +#define CONFIG_SYS_OCR2_A_VAL 0x00000000 +#define CONFIG_SYS_ICFA1_A_VAL 0xFFFFFFFF +#define CONFIG_SYS_ICFA2_A_VAL 0xFFFFFFFF +#define CONFIG_SYS_ICFB1_A_VAL 0xFFFFFFFF +#define CONFIG_SYS_ICFB2_A_VAL 0xFFFFFFFF +#define CONFIG_SYS_DR_A_VAL 0x00000000 +#define CONFIG_SYS_GIUS_A_VAL 0xFFFFFFFF +#define CONFIG_SYS_ICR1_A_VAL 0x00000000 +#define CONFIG_SYS_ICR2_A_VAL 0x00000000 +#define CONFIG_SYS_IMR_A_VAL 0x00000000 +#define CONFIG_SYS_GPR_A_VAL 0x00000000 +#define CONFIG_SYS_PUEN_A_VAL 0xFFFFFFFF + +#define CONFIG_SYS_DDIR_B_VAL 0x00000000 +#define CONFIG_SYS_OCR1_B_VAL 0x00000000 +#define CONFIG_SYS_OCR2_B_VAL 0x00000000 +#define CONFIG_SYS_ICFA1_B_VAL 0xFFFFFFFF +#define CONFIG_SYS_ICFA2_B_VAL 0xFFFFFFFF +#define CONFIG_SYS_ICFB1_B_VAL 0xFFFFFFFF +#define CONFIG_SYS_ICFB2_B_VAL 0xFFFFFFFF +#define CONFIG_SYS_DR_B_VAL 0x00000000 +#define CONFIG_SYS_GIUS_B_VAL 0xFF3FFFF0 +#define CONFIG_SYS_ICR1_B_VAL 0x00000000 +#define CONFIG_SYS_ICR2_B_VAL 0x00000000 +#define CONFIG_SYS_IMR_B_VAL 0x00000000 +#define CONFIG_SYS_GPR_B_VAL 0x00000000 +#define CONFIG_SYS_PUEN_B_VAL 0xFFFFFFFF + +#define CONFIG_SYS_DDIR_C_VAL 0x00000000 +#define CONFIG_SYS_OCR1_C_VAL 0x00000000 +#define CONFIG_SYS_OCR2_C_VAL 0x00000000 +#define CONFIG_SYS_ICFA1_C_VAL 0xFFFFFFFF +#define CONFIG_SYS_ICFA2_C_VAL 0xFFFFFFFF +#define CONFIG_SYS_ICFB1_C_VAL 0xFFFFFFFF +#define CONFIG_SYS_ICFB2_C_VAL 0xFFFFFFFF +#define CONFIG_SYS_DR_C_VAL 0x00000000 +#define CONFIG_SYS_GIUS_C_VAL 0xFFFFC07F +#define CONFIG_SYS_ICR1_C_VAL 0x00000000 +#define CONFIG_SYS_ICR2_C_VAL 0x00000000 +#define CONFIG_SYS_IMR_C_VAL 0x00000000 +#define CONFIG_SYS_GPR_C_VAL 0x00000000 +#define CONFIG_SYS_PUEN_C_VAL 0xFFFFFF87 + +#define CONFIG_SYS_DDIR_D_VAL 0x00000000 +#define CONFIG_SYS_OCR1_D_VAL 0x00000000 +#define CONFIG_SYS_OCR2_D_VAL 0x00000000 +#define CONFIG_SYS_ICFA1_D_VAL 0xFFFFFFFF +#define CONFIG_SYS_ICFA2_D_VAL 0xFFFFFFFF +#define CONFIG_SYS_ICFB1_D_VAL 0xFFFFFFFF +#define CONFIG_SYS_ICFB2_D_VAL 0xFFFFFFFF +#define CONFIG_SYS_DR_D_VAL 0x00000000 +#define CONFIG_SYS_GIUS_D_VAL 0xFFFFFFFF +#define CONFIG_SYS_ICR1_D_VAL 0x00000000 +#define CONFIG_SYS_ICR2_D_VAL 0x00000000 +#define CONFIG_SYS_IMR_D_VAL 0x00000000 +#define CONFIG_SYS_GPR_D_VAL 0x00000000 +#define CONFIG_SYS_PUEN_D_VAL 0xFFFFFFFF + +#define CONFIG_SYS_DDIR_E_VAL 0x00000000 +#define CONFIG_SYS_OCR1_E_VAL 0x00000000 +#define CONFIG_SYS_OCR2_E_VAL 0x00000000 +#define CONFIG_SYS_ICFA1_E_VAL 0xFFFFFFFF +#define CONFIG_SYS_ICFA2_E_VAL 0xFFFFFFFF +#define CONFIG_SYS_ICFB1_E_VAL 0xFFFFFFFF +#define CONFIG_SYS_ICFB2_E_VAL 0xFFFFFFFF +#define CONFIG_SYS_DR_E_VAL 0x00000000 +#define CONFIG_SYS_GIUS_E_VAL 0xFCFFCCF8 +#define CONFIG_SYS_ICR1_E_VAL 0x00000000 +#define CONFIG_SYS_ICR2_E_VAL 0x00000000 +#define CONFIG_SYS_IMR_E_VAL 0x00000000 +#define CONFIG_SYS_GPR_E_VAL 0x00000000 +#define CONFIG_SYS_PUEN_E_VAL 0xFFFFFFFF + +#define CONFIG_SYS_DDIR_F_VAL 0x00000000 +#define CONFIG_SYS_OCR1_F_VAL 0x00000000 +#define CONFIG_SYS_OCR2_F_VAL 0x00000000 +#define CONFIG_SYS_ICFA1_F_VAL 0xFFFFFFFF +#define CONFIG_SYS_ICFA2_F_VAL 0xFFFFFFFF +#define CONFIG_SYS_ICFB1_F_VAL 0xFFFFFFFF +#define CONFIG_SYS_ICFB2_F_VAL 0xFFFFFFFF +#define CONFIG_SYS_DR_F_VAL 0x00000000 +#define CONFIG_SYS_GIUS_F_VAL 0xFF7F8000 +#define CONFIG_SYS_ICR1_F_VAL 0x00000000 +#define CONFIG_SYS_ICR2_F_VAL 0x00000000 +#define CONFIG_SYS_IMR_F_VAL 0x00000000 +#define CONFIG_SYS_GPR_F_VAL 0x00000000 +#define CONFIG_SYS_PUEN_F_VAL 0xFFFFFFFF + +/* Enforce DDR signal strengh & enable USB/PP/DMA burst override bits */ +#define CONFIG_SYS_GPCR_VAL 0x0003000F + +#define CONFIG_SYS_ESDMISC_VAL ESDMISC_LHD+ESDMISC_MDDREN + +/* FMCR select num LPDDR RAMs and nand 16bits, 2KB pages */ +#if (CONFIG_NR_DRAM_BANKS == 1) +#define CONFIG_SYS_FMCR_VAL 0xFFFFFFF9 +#elif (CONFIG_NR_DRAM_BANKS == 2) +#define CONFIG_SYS_FMCR_VAL 0xFFFFFFFB +#endif + +#define CONFIG_SYS_AIPI1_PSR0_VAL 0x20040304 +#define CONFIG_SYS_AIPI1_PSR1_VAL 0xDFFBFCFB +#define CONFIG_SYS_AIPI2_PSR0_VAL 0x00000000 +#define CONFIG_SYS_AIPI2_PSR1_VAL 0xFFFFFFFF + +/* PCCR enable DMA FEC I2C1 IIM SDHC1 */ +#define CONFIG_SYS_PCCR0_VAL 0x05070410 +#define CONFIG_SYS_PCCR1_VAL 0xA14A0608 + +/* + * From here, there should not be any user configuration. + * All Equations are automatic + */ + +/* fixme none integer value (7.5ns) => 2*hclock = 15ns */ +#define CONFIG_SYS_2XHCLK_LGTH (2000/CONFIG_HCLK_FREQ) /* ns */ + +/* USB 60 MHz ; ARM up to 400; HClK up to 133MHz*/ +#ifdef CONFIG_MX27_CLK26 +#define CSCR_MASK 0x0303800D +#else +#define CSCR_MASK 0x0300800D +#endif +#define CONFIG_SYS_CSCR_VAL\ + (CSCR_MASK \ + |((((CONFIG_SPLL_FREQ/CONFIG_USB_FREQ)-1)&0x07) << 28) \ + |((((CONFIG_MPLL_FREQ/CONFIG_ARM_FREQ)-1)&0x03) << 12) \ + |((((CONFIG_SYS_CLK_FREQ/CONFIG_HCLK_FREQ)-1)&0x03) << 8)) + +/* SSIx CLKO NFC H264 MSHC */ +#define CONFIG_SYS_PCDR0_VAL\ + (((((CONFIG_SYS_CLK_FREQ/CONFIG_MSHC_FREQ)-1)&0x3F)<<0) \ + |((((CONFIG_HCLK_FREQ/CONFIG_NFC_FREQ)-1)&0x0F)<<6) \ + |(((((CONFIG_SYS_CLK_FREQ/CONFIG_H264_FREQ)-2)*2)&0x3F)<<10)\ + |(((((CONFIG_SYS_CLK_FREQ/CONFIG_SSI1_FREQ)-2)*2)&0x3F)<<16)\ + |(((CONFIG_CLK0_DIV)&0x07)<<22)\ + |(((CONFIG_CLK0_EN)&0x01)<<25)\ + |(((((CONFIG_SYS_CLK_FREQ/CONFIG_SSI2_FREQ)-2)*2)&0x3F)<<26)) + +/* PERCLKx */ +#define CONFIG_SYS_PCDR1_VAL\ + (((((CONFIG_SYS_CLK_FREQ/CONFIG_PERIF1_FREQ)-1)&0x3F)<<0) \ + |((((CONFIG_SYS_CLK_FREQ/CONFIG_PERIF2_FREQ)-1)&0x3F)<<8) \ + |((((CONFIG_SYS_CLK_FREQ/CONFIG_PERIF3_FREQ)-1)&0x3F)<<16) \ + |((((CONFIG_SYS_CLK_FREQ/CONFIG_PERIF4_FREQ)-1)&0x3F)<<24)) + +/* SDRAM controller programming Values */ +#if (((2*CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1) > (3*CONFIG_SYS_2XHCLK_LGTH)) \ + || (CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1 < 1)) +#define REG_FIELD_SCL_VAL 3 +#define REG_FIELD_SCLIMX_VAL 0 +#else +#define REG_FIELD_SCL_VAL\ + ((2*CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1+CONFIG_SYS_2XHCLK_LGTH-1)/ \ + CONFIG_SYS_2XHCLK_LGTH) +#define REG_FIELD_SCLIMX_VAL REG_FIELD_SCL_VAL +#endif + +/* #define REG_FIELD_SCL_VAL 3 */ +/* #define REG_FIELD_SCLIMX_VAL 3 */ + +#if ((2*CONFIG_SYS_SDRAM_RC_DELAY) > (16*CONFIG_SYS_2XHCLK_LGTH)) +#define REG_FIELD_SRC_VAL 0 +#else +#define REG_FIELD_SRC_VAL\ + ((2*CONFIG_SYS_SDRAM_RC_DELAY+CONFIG_SYS_2XHCLK_LGTH-1)/ \ + CONFIG_SYS_2XHCLK_LGTH) +#endif + +/* TBD Power down timer ; PRCT Bit Field Encoding; burst length 8 ; FP = 0*/ +#define REG_ESDCTL_BASE_CONFIG (0x80020485\ + | (((CONFIG_SYS_SDRAM_NUM_ROW-11)&0x7)<<24)\ + | (((CONFIG_SYS_SDRAM_NUM_COL-8)&0x3)<<20)\ + | (((CONFIG_SYS_SDRAM_REFRESH)&0x7)<<13)) + +#define CONFIG_SYS_NORMAL_RW_CMD ((0x0<<28)+REG_ESDCTL_BASE_CONFIG) +#define CONFIG_SYS_PRECHARGE_CMD ((0x1<<28)+REG_ESDCTL_BASE_CONFIG) +#define CONFIG_SYS_AUTOREFRESH_CMD ((0x2<<28)+REG_ESDCTL_BASE_CONFIG) +#define CONFIG_SYS_SET_MODE_REG_CMD ((0x3<<28)+REG_ESDCTL_BASE_CONFIG) + +/* ESDRAMC Configuration Registers : force CL=3 to lpddr */ +#define CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL (0x0\ + | (((((2*CONFIG_SYS_SDRAM_EXIT_PWD+CONFIG_SYS_2XHCLK_LGTH-1)/ \ + CONFIG_SYS_2XHCLK_LGTH)-1)&0x3)<<21)\ + | (((CONFIG_SYS_SDRAM_W2R_DELAY-1)&0x1)<<20)\ + | (((((2*CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY+ \ + CONFIG_SYS_2XHCLK_LGTH-1)/CONFIG_SYS_2XHCLK_LGTH)-1)&0x3)<<18) \ + | (((CONFIG_SYS_SDRAM_TMRD_DELAY-1)&0x3)<<16)\ + | (((CONFIG_SYS_SDRAM_TWR_DELAY)&0x1)<<15)\ + | (((((2*CONFIG_SYS_SDRAM_RAS_DELAY+CONFIG_SYS_2XHCLK_LGTH-1)/ \ + CONFIG_SYS_2XHCLK_LGTH)-1)&0x7)<<12) \ + | (((((2*CONFIG_SYS_SDRAM_RRD_DELAY+CONFIG_SYS_2XHCLK_LGTH-1)/ \ + CONFIG_SYS_2XHCLK_LGTH)-1)&0x3)<<10) \ + | (((REG_FIELD_SCLIMX_VAL)&0x3)<<8)\ + | (((((2*CONFIG_SYS_SDRAM_RCD_DELAY+CONFIG_SYS_2XHCLK_LGTH-1)/ \ + CONFIG_SYS_2XHCLK_LGTH)-1)&0x7)<<4) \ + | (((REG_FIELD_SRC_VAL)&0x0F)<<0)) + +/* Issue Mode register Command to SDRAM*/ +#define CONFIG_SYS_SDRAM_MODE_REGISTER_VAL\ + ((((CONFIG_SYS_SDRAM_BURST_LENGTH)&0x7)<<(0))\ + | (((REG_FIELD_SCL_VAL)&0x7)<<(4))\ + | ((0)<<(3)) /* sequentiql access */ \ + /*| (((CONFIG_SYS_SDRAM_SINGLE_ACCESS)&0x1)<<(1))*/) + +/* Issue Extended Mode register Command to SDRAM*/ +#define CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL\ + ((CONFIG_SYS_SDRAM_PARTIAL_ARRAY_SR<<0)\ + | (CONFIG_SYS_SDRAM_DRIVE_STRENGH<<(5))\ + | (1<<(CONFIG_SYS_SDRAM_NUM_COL+CONFIG_SYS_SDRAM_NUM_ROW+1+2))) + +/* Issue Precharge all Command to SDRAM*/ +#define CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL (1<<10) + +#endif /* __CONFIG_H */
On 28/06/2012 22:36, Philippe Reynes wrote:
Signed-off-by: Philippe Reynes tremyfr@yahoo.fr
Hi Philippe,
include/configs/apf27.h | 916 +++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 916 insertions(+), 0 deletions(-) create mode 100644 include/configs/apf27.h
diff --git a/include/configs/apf27.h b/include/configs/apf27.h new file mode 100644
Really this patch must be merged with patch 2/5: "Add support for the armadeus APF27". They belong together, and it maintains the tree bisectable.
+#ifndef __CONFIG_H +#define __CONFIG_H
+#define CONFIG_VERSION_VARIABLE +#define CONFIG_ENV_VERSION "3.1" +#define CONFIG_IDENT_STRING " apf27 patch 3.6" +#define CONFIG_BOARD_NAME apf27
+/*
- SoC configurations
- */
+#define CONFIG_ARM926EJS /* this is an ARM926EJS CPU */ +#define CONFIG_MX27 /* in a Freescale i.MX27 Chip */ +#define CONFIG_MACH_TYPE 1698 /* APF27 */
+/*
- Enable the call to miscellaneous platform dependent initialization.
- */
+#define CONFIG_SYS_NO_FLASH /* to be define before <config_cmd_default.h> */ +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_MISC_INIT_R
+/*
- Board display option
- */
+#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_DISPLAY_CPUINFO
+/*
- SPL
- */
+#define CONFIG_NAND_U_BOOT +/* Copy SPL+U-Boot here */ +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_LOAD_ADDR +/* Size is the partion size */ +#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN
See my comment about the SPL patch.
+#define PHYS_SDRAM_1 0xA0000000 +#define PHYS_SDRAM_2 0xB0000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10)) +#define CONFIG_SYS_GBL_DATA_SIZE 256 /* Initial data */
We use a macro for CONFIG_SYS_GBL_DATA_SIZE. Is it not suitable for your needs ?
+#define CONFIG_SYS_TEXT_BASE 0xA1000000
+/*
- FLASH organization
- */
+/*#define CONFIG_SYS_MONITOR_BASE 0xAFF00000*/
Do not let dead code
+#define CONFIG_FIRMWARE_OFFSET 0x00200000 +#define CONFIG_KERNEL_OFFSET 0x00300000 +#define CONFIG_ROOTFS_OFFSET 0x00800000
+#define CONFIG_MTDMAP "mxc_nand.0" +#define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP +#define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP \
":1M(u-boot)ro," \"512K(env)," \"512K(env2)," \"512K(firmware)," \"512K(dtb)," \"5M(kernel)," \"-(rootfs)"+/*
- U-Boot general configurations
- */
+#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "BIOS> " /* prompt string */ +#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */ +#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)/* Print buffer size */+#define CONFIG_SYS_MAXARGS 16 /* max command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */+#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_HUSH_PARSER /* enable the "hush" shell */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* secondary prompt string */
+/*
- Boot Linux
- */
+#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ +#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ +#define CONFIG_INITRD_TAG /* send initrd params */
+/* #define CONFIG_REVISION_TAG */
Drop also this line - check in the whole file for these occurrencies
+#if 0 +#define CONFIG_SYS_FPGA_IS_PROTO /* to be defined with apf27 board prototype */ +#endif
drop also this dead code
+#ifndef CONFIG_MX27_CLK26 +#if (CONFIG_MX27_CLK32 == 32000) +#define CONFIG_SYS_MPCTL0_VAL 0x00211803 /* 398.998 MHz */ +#define CONFIG_SYS_MPCTL1_VAL 0 +#define CONFIG_MPLL_FREQ 399 +#else /* CONFIG_MX27_CLK32 == 32768*/ +#define CONFIG_SYS_MPCTL0_VAL 0x01EF15D5 /* 399.000 MHz */ +#define CONFIG_SYS_MPCTL1_VAL 0 +#define CONFIG_MPLL_FREQ 399 +#endif /* CONFIG_MX27_CLK32 */ +#else /* CONFIG_MX27_CLK26 in use*/ +#define CONFIG_SYS_MPCTL0_VAL 0x00331C23 /* 399.000 MHz */ +#define CONFIG_SYS_MPCTL1_VAL 0 +#define CONFIG_MPLL_FREQ 399 +#endif /* CONFIG_MX27_CLK26 */
Do you have several hardware version of the same board or which is the reason for that ?
+/* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */ +#define CONFIG_ARM_FREQ 399 /* up to 400 MHz */
+/* external bus frequency (have to be a CONFIG_SYS_CLK_FREQ ratio) */ +#define CONFIG_HCLK_FREQ 133 /* (CONFIG_SYS_CLK_FREQ/2) */
+#define CONFIG_PERIF1_FREQ 16 /* 16.625 MHz UART, GPT, PWM*/ +#define CONFIG_PERIF2_FREQ 33 /* 33.25 MHz CSPI and SDHC */ +#define CONFIG_PERIF3_FREQ 33 /* 33.25 MHz LCD*/ +#define CONFIG_PERIF4_FREQ 33 /* 33.25 MHz CSI*/ +#define CONFIG_SSI1_FREQ 66 /* 66.50 MHz SSI1*/ +#define CONFIG_SSI2_FREQ 66 /* 66.50 MHz SSI2*/ +#define CONFIG_MSHC_FREQ 66 /* 66.50 MHz MSHC*/ +#define CONFIG_H264_FREQ 66 /* 66.50 MHz H264*/ +#define CONFIG_CLK0_DIV 3 /* Divide CLK0 by 4 */ +#define CONFIG_CLK0_EN 1 /* CLK0 enabled */
Really there is another way to get the peripheral clocks for the i.MX. Each SOC implements or should implement mxc_get_clock(), passing as parameter the peripheral you need to know the clock.
+/*
- SDRAM
- */
+#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ +/* micron 64MB */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ +#define CONFIG_SYS_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11
column address bits */+#define CONFIG_SYS_SDRAM_NUM_ROW 13 /* 11, 12 or 13
row address bits */+#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048
2=4096 3=8192 refresh */+#define CONFIG_SYS_SDRAM_EXIT_PWD 25 /* ns exit power
down delay */+#define CONFIG_SYS_SDRAM_W2R_DELAY 1 /* write to read
cycle delay > 0 */+#define CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ +#define CONFIG_SYS_SDRAM_TMRD_DELAY 2 /* Load mode register
cycle delay 1..4 */+#define CONFIG_SYS_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck;
SDRAM: 0=1ck 1=2ck*/+#define CONFIG_SYS_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE
delay */+#define CONFIG_SYS_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE
delay */+#define CONFIG_SYS_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ +#define CONFIG_SYS_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC
refresh to command) */+#define CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time
estimated fo CL=10=force 3 for lpddr */+#define CONFIG_SYS_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater
3=Eighth 4=Sixteenth */+#define CONFIG_SYS_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half
2=quater 3=Eighth */+#define CONFIG_SYS_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ +#define CONFIG_SYS_SDRAM_SINGLE_ACCESS 0 /* 1= single access;
0 = Burst mode */+#endif
Why do these config belong to the config file ? You introduce several new CONFIG_SYS, and they must be documented. Anyway, you do not need it, because I assume all these values are used only in the board directory, not generally for other subsystem of u-boot.
+/* FPGA specific settings */ +/* CLKO */ +#define CONFIG_SYS_CCSR_VAL 0x00000305 +/* drive strength CLKO set to 2*/ +#define CONFIG_SYS_DSCR10_VAL 0x00020000 +/* drive strength A1..A12 set to 2*/ +#define CONFIG_SYS_DSCR3_VAL 0x02AAAAA8 +/* drive strength ctrl*/ +#define CONFIG_SYS_DSCR7_VAL 0x00020880 +/* drive strength data*/ +#define CONFIG_SYS_DSCR2_VAL 0xAAAAAAAA
Maybe you should move also FPGA related values to the fpga file - and as I said, a CONFIG_SYS_ define has meaning for the whole code across architectures, and this is not the case. The same comment for the GPIOs and so on.
Best regards, Stefano Babic
participants (5)
-
Eric Jarrige -
Fabio Estevam -
Philippe Reynes -
Scott Wood -
Stefano Babic