[U-Boot] [PATCH v3 1/4] dts: Bring in Chrome OS keyboard device tree definition
This will be used by nyan, but bring it in in a separate patch since it will be common to other boards.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v3: - Add patch to bring in cros-ec-keyboard.dtsi
Changes in v2: None
arch/arm/dts/cros-ec-keyboard.dtsi | 105 +++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 arch/arm/dts/cros-ec-keyboard.dtsi
diff --git a/arch/arm/dts/cros-ec-keyboard.dtsi b/arch/arm/dts/cros-ec-keyboard.dtsi new file mode 100644 index 0000000..9c7fb0a --- /dev/null +++ b/arch/arm/dts/cros-ec-keyboard.dtsi @@ -0,0 +1,105 @@ +/* + * Keyboard dts fragment for devices that use cros-ec-keyboard + * + * Copyright (c) 2014 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <dt-bindings/input/input.h> + +&cros_ec { + keyboard-controller { + compatible = "google,cros-ec-keyb"; + keypad,num-rows = <8>; + keypad,num-columns = <13>; + google,needs-ghost-filter; + + linux,keymap = < + MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA) + MATRIX_KEY(0x00, 0x02, KEY_F1) + MATRIX_KEY(0x00, 0x03, KEY_B) + MATRIX_KEY(0x00, 0x04, KEY_F10) + MATRIX_KEY(0x00, 0x06, KEY_N) + MATRIX_KEY(0x00, 0x08, KEY_EQUAL) + MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) + + MATRIX_KEY(0x01, 0x01, KEY_ESC) + MATRIX_KEY(0x01, 0x02, KEY_F4) + MATRIX_KEY(0x01, 0x03, KEY_G) + MATRIX_KEY(0x01, 0x04, KEY_F7) + MATRIX_KEY(0x01, 0x06, KEY_H) + MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) + MATRIX_KEY(0x01, 0x09, KEY_F9) + MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) + + MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) + MATRIX_KEY(0x02, 0x01, KEY_TAB) + MATRIX_KEY(0x02, 0x02, KEY_F3) + MATRIX_KEY(0x02, 0x03, KEY_T) + MATRIX_KEY(0x02, 0x04, KEY_F6) + MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE) + MATRIX_KEY(0x02, 0x06, KEY_Y) + MATRIX_KEY(0x02, 0x07, KEY_102ND) + MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) + MATRIX_KEY(0x02, 0x09, KEY_F8) + + MATRIX_KEY(0x03, 0x01, KEY_GRAVE) + MATRIX_KEY(0x03, 0x02, KEY_F2) + MATRIX_KEY(0x03, 0x03, KEY_5) + MATRIX_KEY(0x03, 0x04, KEY_F5) + MATRIX_KEY(0x03, 0x06, KEY_6) + MATRIX_KEY(0x03, 0x08, KEY_MINUS) + MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) + + MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) + MATRIX_KEY(0x04, 0x01, KEY_A) + MATRIX_KEY(0x04, 0x02, KEY_D) + MATRIX_KEY(0x04, 0x03, KEY_F) + MATRIX_KEY(0x04, 0x04, KEY_S) + MATRIX_KEY(0x04, 0x05, KEY_K) + MATRIX_KEY(0x04, 0x06, KEY_J) + MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON) + MATRIX_KEY(0x04, 0x09, KEY_L) + MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH) + MATRIX_KEY(0x04, 0x0b, KEY_ENTER) + + MATRIX_KEY(0x05, 0x01, KEY_Z) + MATRIX_KEY(0x05, 0x02, KEY_C) + MATRIX_KEY(0x05, 0x03, KEY_V) + MATRIX_KEY(0x05, 0x04, KEY_X) + MATRIX_KEY(0x05, 0x05, KEY_COMMA) + MATRIX_KEY(0x05, 0x06, KEY_M) + MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT) + MATRIX_KEY(0x05, 0x08, KEY_SLASH) + MATRIX_KEY(0x05, 0x09, KEY_DOT) + MATRIX_KEY(0x05, 0x0b, KEY_SPACE) + + MATRIX_KEY(0x06, 0x01, KEY_1) + MATRIX_KEY(0x06, 0x02, KEY_3) + MATRIX_KEY(0x06, 0x03, KEY_4) + MATRIX_KEY(0x06, 0x04, KEY_2) + MATRIX_KEY(0x06, 0x05, KEY_8) + MATRIX_KEY(0x06, 0x06, KEY_7) + MATRIX_KEY(0x06, 0x08, KEY_0) + MATRIX_KEY(0x06, 0x09, KEY_9) + MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT) + MATRIX_KEY(0x06, 0x0b, KEY_DOWN) + MATRIX_KEY(0x06, 0x0c, KEY_RIGHT) + + MATRIX_KEY(0x07, 0x01, KEY_Q) + MATRIX_KEY(0x07, 0x02, KEY_E) + MATRIX_KEY(0x07, 0x03, KEY_R) + MATRIX_KEY(0x07, 0x04, KEY_W) + MATRIX_KEY(0x07, 0x05, KEY_I) + MATRIX_KEY(0x07, 0x06, KEY_U) + MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT) + MATRIX_KEY(0x07, 0x08, KEY_P) + MATRIX_KEY(0x07, 0x09, KEY_O) + MATRIX_KEY(0x07, 0x0b, KEY_UP) + MATRIX_KEY(0x07, 0x0c, KEY_LEFT) + >; + }; +};
Sync this up with Linux v3.18-rc5. Exclude features that are unlikely to supported in U-Boot soon (regulators, pinmux). Also the addresses are updated to 32-bit. Otherwise it is the same. Also bring in the dt-bindings for pinctrl.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v3: - Add patch to update tegra124.dtsi from Linux v3.18-rc5
Changes in v2: None
arch/arm/dts/tegra124.dtsi | 114 ++++++++++++++++++++++++++++ include/dt-bindings/pinctrl/pinctrl-tegra.h | 45 +++++++++++ 2 files changed, 159 insertions(+) create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra.h
diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi index 3288f28..6b5c2be 100644 --- a/arch/arm/dts/tegra124.dtsi +++ b/arch/arm/dts/tegra124.dtsi @@ -1,5 +1,6 @@ #include <dt-bindings/clock/tegra124-car.h> #include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi" @@ -192,6 +193,16 @@ status = "disabled"; };
+ pwm: pwm@7000a000 { + compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; + reg = <0x7000a000 0x100>; + #pwm-cells = <2>; + clocks = <&tegra_car TEGRA124_CLK_PWM>; + resets = <&tegra_car 17>; + reset-names = "pwm"; + status = "disabled"; + }; + spi@7000d400 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; reg = <0x7000d400 0x200>; @@ -290,6 +301,109 @@ status = "disabled"; };
+ ahub@70300000 { + compatible = "nvidia,tegra124-ahub"; + reg = <0x70300000 0x200>, + <0x70300800 0x800>, + <0x70300200 0x600>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, + <&tegra_car TEGRA124_CLK_APBIF>; + clock-names = "d_audio", "apbif"; + resets = <&tegra_car 106>, /* d_audio */ + <&tegra_car 107>, /* apbif */ + <&tegra_car 30>, /* i2s0 */ + <&tegra_car 11>, /* i2s1 */ + <&tegra_car 18>, /* i2s2 */ + <&tegra_car 101>, /* i2s3 */ + <&tegra_car 102>, /* i2s4 */ + <&tegra_car 108>, /* dam0 */ + <&tegra_car 109>, /* dam1 */ + <&tegra_car 110>, /* dam2 */ + <&tegra_car 10>, /* spdif */ + <&tegra_car 153>, /* amx */ + <&tegra_car 185>, /* amx1 */ + <&tegra_car 154>, /* adx */ + <&tegra_car 180>, /* adx1 */ + <&tegra_car 186>, /* afc0 */ + <&tegra_car 187>, /* afc1 */ + <&tegra_car 188>, /* afc2 */ + <&tegra_car 189>, /* afc3 */ + <&tegra_car 190>, /* afc4 */ + <&tegra_car 191>; /* afc5 */ + reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", + "i2s3", "i2s4", "dam0", "dam1", "dam2", + "spdif", "amx", "amx1", "adx", "adx1", + "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; + dmas = <&apbdma 1>, <&apbdma 1>, + <&apbdma 2>, <&apbdma 2>, + <&apbdma 3>, <&apbdma 3>, + <&apbdma 4>, <&apbdma 4>, + <&apbdma 6>, <&apbdma 6>, + <&apbdma 7>, <&apbdma 7>, + <&apbdma 12>, <&apbdma 12>, + <&apbdma 13>, <&apbdma 13>, + <&apbdma 14>, <&apbdma 14>, + <&apbdma 29>, <&apbdma 29>; + dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", + "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", + "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", + "rx9", "tx9"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + tegra_i2s0: i2s@70301000 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x70301000 0x100>; + nvidia,ahub-cif-ids = <4 4>; + clocks = <&tegra_car TEGRA124_CLK_I2S0>; + resets = <&tegra_car 30>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s1: i2s@70301100 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x70301100 0x100>; + nvidia,ahub-cif-ids = <5 5>; + clocks = <&tegra_car TEGRA124_CLK_I2S1>; + resets = <&tegra_car 11>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s2: i2s@70301200 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x70301200 0x100>; + nvidia,ahub-cif-ids = <6 6>; + clocks = <&tegra_car TEGRA124_CLK_I2S2>; + resets = <&tegra_car 18>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s3: i2s@70301300 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x70301300 0x100>; + nvidia,ahub-cif-ids = <7 7>; + clocks = <&tegra_car TEGRA124_CLK_I2S3>; + resets = <&tegra_car 101>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s4: i2s@70301400 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x70301400 0x100>; + nvidia,ahub-cif-ids = <8 8>; + clocks = <&tegra_car TEGRA124_CLK_I2S4>; + resets = <&tegra_car 102>; + reset-names = "i2s"; + status = "disabled"; + }; + }; + usb@7d000000 { compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; reg = <0x7d000000 0x4000>; diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h new file mode 100644 index 0000000..ebafa49 --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-tegra.h @@ -0,0 +1,45 @@ +/* + * This header provides constants for Tegra pinctrl bindings. + * + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * Author: Laxman Dewangan ldewangan@nvidia.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H +#define _DT_BINDINGS_PINCTRL_TEGRA_H + +/* + * Enable/disable for diffeent dt properties. This is applicable for + * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain, + * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt. + */ +#define TEGRA_PIN_DISABLE 0 +#define TEGRA_PIN_ENABLE 1 + +#define TEGRA_PIN_PULL_NONE 0 +#define TEGRA_PIN_PULL_DOWN 1 +#define TEGRA_PIN_PULL_UP 2 + +/* Low power mode driver */ +#define TEGRA_PIN_LP_DRIVE_DIV_8 0 +#define TEGRA_PIN_LP_DRIVE_DIV_4 1 +#define TEGRA_PIN_LP_DRIVE_DIV_2 2 +#define TEGRA_PIN_LP_DRIVE_DIV_1 3 + +/* Rising/Falling slew rate */ +#define TEGRA_PIN_SLEW_RATE_FASTEST 0 +#define TEGRA_PIN_SLEW_RATE_FAST 1 +#define TEGRA_PIN_SLEW_RATE_SLOW 2 +#define TEGRA_PIN_SLEW_RATE_SLOWEST 3 + +#endif
On 11/23/2014 09:12 AM, Simon Glass wrote:
Sync this up with Linux v3.18-rc5. Exclude features that are unlikely to supported in U-Boot soon (regulators, pinmux). Also the addresses are updated to 32-bit. Otherwise it is the same. Also bring in the dt-bindings for pinctrl.
Assuming this content exactly matches the kernel, Acked-by: Stephen Warren swarren@nvidia.com
Do all the existing nodes exactly match the kernel already?
Hi Stephen,
On 24 November 2014 at 10:09, Stephen Warren swarren@wwwdotorg.org wrote:
On 11/23/2014 09:12 AM, Simon Glass wrote:
Sync this up with Linux v3.18-rc5. Exclude features that are unlikely to supported in U-Boot soon (regulators, pinmux). Also the addresses are updated to 32-bit. Otherwise it is the same. Also bring in the dt-bindings for pinctrl.
Assuming this content exactly matches the kernel, Acked-by: Stephen Warren swarren@nvidia.com
Do all the existing nodes exactly match the kernel already?
Apart from the differences noted in the commit message, yes.
Regards, Simon
Modern kernels require a device tree to boot. Enable FIT support to permit booting these images, rather than just legacy images. This allows booting of Chrome OS kernels, among other things.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v3: - Add new patch to enable FIT support for Tegra boards
Changes in v2: None
include/configs/tegra-common.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 5d2b12a..c8c2366 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -162,6 +162,9 @@ #define CONFIG_BOUNCE_BUFFER #define CONFIG_CRC32_VERIFY
+#define CONFIG_FIT +#define CONFIG_OF_LIBFDT + #ifndef CONFIG_SPL_BUILD #include <config_distro_defaults.h> #endif
On 11/23/2014 09:12 AM, Simon Glass wrote:
Modern kernels require a device tree to boot.
True.
Enable FIT support to permit booting these images, rather than just legacy images.
I don't understand this? Modern kernels boot perfectly well without FIT support. U-Boot supports the kernel's standard separate DTB and zImage file formats just fine.
To be honest, I'd strongly prefer not to enable support for non-universal (bootloader-specific) formats such as FIT.
This allows booting of Chrome OS kernels, among other things.
This might be a reasonable justification to support FIT. However, it'd be best to enable FIT support only on boards that are actually supported by ChromeOS, so as not to pollute other boards' configuration.
Hi Stephen,
On 24 November 2014 at 10:11, Stephen Warren swarren@wwwdotorg.org wrote:
On 11/23/2014 09:12 AM, Simon Glass wrote:
Modern kernels require a device tree to boot.
True.
Enable FIT support to permit
booting these images, rather than just legacy images.
I don't understand this? Modern kernels boot perfectly well without FIT support. U-Boot supports the kernel's standard separate DTB and zImage file formats just fine.
To be honest, I'd strongly prefer not to enable support for non-universal (bootloader-specific) formats such as FIT.
In U-Boot? FIT is U-Boot's standard format and avoids all the mess that is zImage with a single attached DTB, etc.
This allows booting of Chrome OS kernels, among other things.
This might be a reasonable justification to support FIT. However, it'd be best to enable FIT support only on boards that are actually supported by ChromeOS, so as not to pollute other boards' configuration.
I feel that FIT is a pretty core feature for U-Boot. Are you worried about the space?
Regards, Simon
On 11/24/2014 04:49 PM, Simon Glass wrote:
Hi Stephen,
On 24 November 2014 at 10:11, Stephen Warren swarren@wwwdotorg.org wrote:
On 11/23/2014 09:12 AM, Simon Glass wrote:
Modern kernels require a device tree to boot.
True.
Enable FIT support to permit
booting these images, rather than just legacy images.
I don't understand this? Modern kernels boot perfectly well without FIT support. U-Boot supports the kernel's standard separate DTB and zImage file formats just fine.
To be honest, I'd strongly prefer not to enable support for non-universal (bootloader-specific) formats such as FIT.
In U-Boot? FIT is U-Boot's standard format
That's rather my point: FIT is *U-Boot's* standard format, not a global standard format.
I want to strongly guide anyone using Tegra towards globally standard formats, not intimate that they should be using bootloader-specific formats.
zImage (without appended DTB) is a standard Linux format that all booatloaders should support.
Raw DTB in a separate file (or perhaps provided by earlier firmware directly in RAM/ROM) is a standard Linux format that all bootloaders should support.
extlinux.conf is something that all bootloaders should support.
Linux distros that install binaries or config files in those standard formats should expect them to work with any bootloader, on any board. This way, distros won't have to write explicit support for any board; they'll just install standard files and everything will just work anywhere.
and avoids all the mess that is zImage with a single attached DTB, etc.
Yes, we should avoid appended DTB where possible. However, there's no need to use appended DTB even when not using FIT; just put the zImage and DTB in separate files. To load them, either use a simple extlinux.conf config file, or a set of U-Boot commands to load each file; see https://github.com/NVIDIA/tegra-uboot-scripts for something that'll generates some examples.
Example /boot/extlinux.conf (for media-based booting) or pxelinux.cfg/default (for network booting via syslinux command):
TIMEOUT 100
MENU TITLE TFTP boot options
LABEL jetson-tk1-emmc MENU LABEL ../zImage root on Jetson TK1 eMMC LINUX ../zImage FDTDIR ../ APPEND console=ttyS0,115200n8 console=tty1 loglevel=8 rootwait rw earlyprintk root=/dev/mmcblk0p1 #root=UUID=8eac677f-8ea8-4270-8479-d5ddbb797450
LABEL sdcard MENU LABEL ../zImage, root on 2GB sdcard LINUX ../zImage FDTDIR ../ APPEND console=ttyS0,115200n8 console=tty1 loglevel=8 rootwait rw earlyprintk root=PARTUUID=b2f82cda-2535-4779-b467-094a210fbae7
LABEL venice2-emmc MENU LABEL ../zImage root on Venice2 eMMC LINUX ../zImage FDTDIR ../ APPEND console=ttyS0,115200n8 console=tty1 loglevel=8 rootwait rw earlyprintk root=PARTUUID=5f71e06f-be08-48ed-b1ef-ee4800cc860f ...
This allows booting of Chrome OS kernels, among other things.
This might be a reasonable justification to support FIT. However, it'd be best to enable FIT support only on boards that are actually supported by ChromeOS, so as not to pollute other boards' configuration.
I feel that FIT is a pretty core feature for U-Boot. Are you worried about the space?
I'm worried about guiding people towards non-standard file formats and protocols that lock people into a particular boot-loader.
For use-cases where it makes sense, I think it's fine to enable FIT. As a general feature across all boards, I would strongly prefer not to. One use-case that makes sense might be to boot ChromeOS. Of course, that's only applicable to boards that ChromeOS (or ChromiumOS) supports, and hence FIT should only be enabled in those boards' config files, not globally.
Hi Stephen,
On 25 November 2014 at 09:23, Stephen Warren swarren@wwwdotorg.org wrote:
On 11/24/2014 04:49 PM, Simon Glass wrote:
Hi Stephen,
On 24 November 2014 at 10:11, Stephen Warren swarren@wwwdotorg.org wrote:
On 11/23/2014 09:12 AM, Simon Glass wrote:
Modern kernels require a device tree to boot.
True.
Enable FIT support to permit
booting these images, rather than just legacy images.
I don't understand this? Modern kernels boot perfectly well without FIT support. U-Boot supports the kernel's standard separate DTB and zImage file formats just fine.
To be honest, I'd strongly prefer not to enable support for non-universal (bootloader-specific) formats such as FIT.
In U-Boot? FIT is U-Boot's standard format
That's rather my point: FIT is *U-Boot's* standard format, not a global standard format.
I want to strongly guide anyone using Tegra towards globally standard formats, not intimate that they should be using bootloader-specific formats.
zImage (without appended DTB) is a standard Linux format that all booatloaders should support.
Raw DTB in a separate file (or perhaps provided by earlier firmware directly in RAM/ROM) is a standard Linux format that all bootloaders should support.
extlinux.conf is something that all bootloaders should support.
Linux distros that install binaries or config files in those standard formats should expect them to work with any bootloader, on any board. This way, distros won't have to write explicit support for any board; they'll just install standard files and everything will just work anywhere.
Just so I am clear, on ARM what is the list of bootloaders that you are concerned with? FIT is actually not a difficult thing to add to a boot loader. Presumably they all support libfdt, so it is just a case of plumbing in the FIT access stuff.
I'm really not keen on this lowest-common-denominator approach, it's just a sad situation. Also I don't see why extlinux.conf should preclude people using FIT if they want to.
and avoids all the mess that is zImage with a single attached DTB, etc.
Yes, we should avoid appended DTB where possible. However, there's no need to use appended DTB even when not using FIT; just put the zImage and DTB in separate files. To load them, either use a simple extlinux.conf config file, or a set of U-Boot commands to load each file; see https://github.com/NVIDIA/tegra-uboot-scripts for something that'll generates some examples.
Example /boot/extlinux.conf (for media-based booting) or pxelinux.cfg/default (for network booting via syslinux command):
TIMEOUT 100
MENU TITLE TFTP boot options
LABEL jetson-tk1-emmc MENU LABEL ../zImage root on Jetson TK1 eMMC LINUX ../zImage FDTDIR ../ APPEND console=ttyS0,115200n8 console=tty1 loglevel=8 rootwait rw earlyprintk root=/dev/mmcblk0p1 #root=UUID=8eac677f-8ea8-4270-8479-d5ddbb797450
LABEL sdcard MENU LABEL ../zImage, root on 2GB sdcard LINUX ../zImage FDTDIR ../ APPEND console=ttyS0,115200n8 console=tty1 loglevel=8 rootwait rw earlyprintk root=PARTUUID=b2f82cda-2535-4779-b467-094a210fbae7
LABEL venice2-emmc MENU LABEL ../zImage root on Venice2 eMMC LINUX ../zImage FDTDIR ../ APPEND console=ttyS0,115200n8 console=tty1 loglevel=8 rootwait rw earlyprintk root=PARTUUID=5f71e06f-be08-48ed-b1ef-ee4800cc860f ...
Sounds good. I guess if the zImage were an image.fit then this would still work on U-Boot. We could even enable verified boot!
How does U-Boot select which device tree to pass to the kernel with the scheme above? We shouldn't rely on the user, right? With FIT we use CONFIG_FIT_BEST_MATCH.
This allows booting of Chrome OS kernels, among other things.
This might be a reasonable justification to support FIT. However, it'd be best to enable FIT support only on boards that are actually supported by ChromeOS, so as not to pollute other boards' configuration.
I feel that FIT is a pretty core feature for U-Boot. Are you worried about the space?
I'm worried about guiding people towards non-standard file formats and protocols that lock people into a particular boot-loader.
For use-cases where it makes sense, I think it's fine to enable FIT. As a general feature across all boards, I would strongly prefer not to. One use-case that makes sense might be to boot ChromeOS. Of course, that's only applicable to boards that ChromeOS (or ChromiumOS) supports, and hence FIT should only be enabled in those boards' config files, not globally.
Without it we wouldn't be able to boot a kernel. Still I don't see why enabling the feature is going to break anything. It's like bike owners wanting to ban cars.
Regards, Simon
On 11/25/2014 10:44 AM, Simon Glass wrote:
Hi Stephen,
On 25 November 2014 at 09:23, Stephen Warren swarren@wwwdotorg.org wrote:
On 11/24/2014 04:49 PM, Simon Glass wrote:
Hi Stephen,
On 24 November 2014 at 10:11, Stephen Warren swarren@wwwdotorg.org wrote:
On 11/23/2014 09:12 AM, Simon Glass wrote:
Modern kernels require a device tree to boot.
True.
Enable FIT support to permit booting these images, rather than just legacy images.
I don't understand this? Modern kernels boot perfectly well without FIT support. U-Boot supports the kernel's standard separate DTB and zImage file formats just fine.
To be honest, I'd strongly prefer not to enable support for non-universal (bootloader-specific) formats such as FIT.
In U-Boot? FIT is U-Boot's standard format
That's rather my point: FIT is *U-Boot's* standard format, not a global standard format.
I want to strongly guide anyone using Tegra towards globally standard formats, not intimate that they should be using bootloader-specific formats.
zImage (without appended DTB) is a standard Linux format that all booatloaders should support.
Raw DTB in a separate file (or perhaps provided by earlier firmware directly in RAM/ROM) is a standard Linux format that all bootloaders should support.
extlinux.conf is something that all bootloaders should support.
Linux distros that install binaries or config files in those standard formats should expect them to work with any bootloader, on any board. This way, distros won't have to write explicit support for any board; they'll just install standard files and everything will just work anywhere.
Just so I am clear, on ARM what is the list of bootloaders that you are concerned with? FIT is actually not a difficult thing to add to a boot loader. Presumably they all support libfdt, so it is just a case of plumbing in the FIT access stuff.
I believe that Barebox supports extlinux.conf too.
I'm really not keen on this lowest-common-denominator approach, it's just a sad situation. Also I don't see why extlinux.conf should preclude people using FIT if they want to.
It doesn't. My point is that it's unlikely people will want FIT support except in certain specific cases (such as ChromeOS compatibility), and we shouldn't enable it except where there's a demonstrable use-case, so we don't confuse people with non-standard options and accidentally lead them down the wrong path.
...
Example /boot/extlinux.conf (for media-based booting) or pxelinux.cfg/default (for network booting via syslinux command):
...
How does U-Boot select which device tree to pass to the kernel with the scheme above? We shouldn't rely on the user, right? With FIT we use CONFIG_FIT_BEST_MATCH.
extlinux.conf can specify a particular DTB filename if it wants. Alternatively, it can specify a directory containing a set of DTBs, and the bootloader must select which DTB to load.
If $fdtfile is set in U-Boot's environment, that file is used.
Otherwise, the U-Boot syslinux code uses some other environment variables to calculate a default DTB filename; ${soc}-${board}.dtb.
Hi Stephen,
On 1 December 2014 at 11:41, Stephen Warren swarren@wwwdotorg.org wrote:
On 11/25/2014 10:44 AM, Simon Glass wrote:
Hi Stephen,
On 25 November 2014 at 09:23, Stephen Warren swarren@wwwdotorg.org wrote:
On 11/24/2014 04:49 PM, Simon Glass wrote:
Hi Stephen,
On 24 November 2014 at 10:11, Stephen Warren swarren@wwwdotorg.org wrote:
On 11/23/2014 09:12 AM, Simon Glass wrote:
Modern kernels require a device tree to boot.
True.
Enable FIT support to permit booting these images, rather than just legacy images.
I don't understand this? Modern kernels boot perfectly well without FIT support. U-Boot supports the kernel's standard separate DTB and zImage file formats just fine.
To be honest, I'd strongly prefer not to enable support for non-universal (bootloader-specific) formats such as FIT.
In U-Boot? FIT is U-Boot's standard format
That's rather my point: FIT is *U-Boot's* standard format, not a global standard format.
I want to strongly guide anyone using Tegra towards globally standard formats, not intimate that they should be using bootloader-specific formats.
zImage (without appended DTB) is a standard Linux format that all booatloaders should support.
Raw DTB in a separate file (or perhaps provided by earlier firmware directly in RAM/ROM) is a standard Linux format that all bootloaders should support.
extlinux.conf is something that all bootloaders should support.
Linux distros that install binaries or config files in those standard formats should expect them to work with any bootloader, on any board. This way, distros won't have to write explicit support for any board; they'll just install standard files and everything will just work anywhere.
Just so I am clear, on ARM what is the list of bootloaders that you are concerned with? FIT is actually not a difficult thing to add to a boot loader. Presumably they all support libfdt, so it is just a case of plumbing in the FIT access stuff.
I believe that Barebox supports extlinux.conf too.
OK so I wonder if this problem would go away if Barebox supported FIT. I haven't played with Barebox but could perhaps take a look.
I'm really not keen on this lowest-common-denominator approach, it's just a sad situation. Also I don't see why extlinux.conf should preclude people using FIT if they want to.
It doesn't. My point is that it's unlikely people will want FIT support except in certain specific cases (such as ChromeOS compatibility), and we shouldn't enable it except where there's a demonstrable use-case, so we don't confuse people with non-standard options and accidentally lead them down the wrong path.
My use case is to have one or more kernels, lots of device trees and be able to boot on any arch. I think that is the same for you, but in your case you rely on a filesystem to provide a large number of FDTs. This means that we can't provide a kernel release as a single file, nor can we support verified boot. With FIT we can support these.
...
Example /boot/extlinux.conf (for media-based booting) or pxelinux.cfg/default (for network booting via syslinux command):
...
How does U-Boot select which device tree to pass to the kernel with the scheme above? We shouldn't rely on the user, right? With FIT we use CONFIG_FIT_BEST_MATCH.
extlinux.conf can specify a particular DTB filename if it wants. Alternatively, it can specify a directory containing a set of DTBs, and the bootloader must select which DTB to load.
If $fdtfile is set in U-Boot's environment, that file is used.
Otherwise, the U-Boot syslinux code uses some other environment variables to calculate a default DTB filename; ${soc}-${board}.dtb.
OK I remember your patches now, sounds good.
Let me know if there is some other blocker (besides Barebox) to supporting FIT more widely for kernel + device tree distribution.
Regards, Simon
From: Allen Martin amartin@nvidia.com
Nyan is a Tegra124 clamshell board that is very similar to venice2, but it has a different panel, the sdcard cd and wp sense are flipped, and it has a different revision of the AS3722 PMIC.
This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA Tegra K1, 2GB). The display is not currently supported, so it should boot on other nyan-based Chromebooks also, but only the device tree for nyan-big is provided here.
The device tree file is from Linux but with features removed which are unlikely to be supported in U-Boot soon (regulators, pinmux). Also the addresses are updated to 32-bit.
Signed-off-by: Allen Martin amartin@nvidia.com Signed-off-by: Simon Glass sjg@chromium.org (rebase, change to 'nyan', fix pinmux that resets nyan)
---
Changes in v3: - Rename to nyan from norrin - Bring in device tree file from Linux v3.18-rc5 - Generate pinmux file from tegra-pinmux-scripts
Changes in v2: - Rebase and adjust for Kconfig - Fix up pinmux that reset norrin - Add note as to the Chromebook's retail name, since it is now released
arch/arm/cpu/armv7/tegra124/Kconfig | 11 + arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra124-nyan-big.dts | 365 +++++++++++++++++++++++++++++++++ board/nvidia/nyan/Kconfig | 24 +++ board/nvidia/nyan/MAINTAINERS | 6 + board/nvidia/nyan/Makefile | 9 + board/nvidia/nyan/nyan.c | 29 +++ board/nvidia/nyan/pinmux-config-nyan.h | 287 ++++++++++++++++++++++++++ board/nvidia/venice2/as3722_init.h | 2 +- configs/nyan_defconfig | 5 + include/configs/nyan.h | 76 +++++++ 11 files changed, 814 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/tegra124-nyan-big.dts create mode 100644 board/nvidia/nyan/Kconfig create mode 100644 board/nvidia/nyan/MAINTAINERS create mode 100644 board/nvidia/nyan/Makefile create mode 100644 board/nvidia/nyan/nyan.c create mode 100644 board/nvidia/nyan/pinmux-config-nyan.h create mode 100644 configs/nyan_defconfig create mode 100644 include/configs/nyan.h
diff --git a/arch/arm/cpu/armv7/tegra124/Kconfig b/arch/arm/cpu/armv7/tegra124/Kconfig index 6a1c83a..4238107 100644 --- a/arch/arm/cpu/armv7/tegra124/Kconfig +++ b/arch/arm/cpu/armv7/tegra124/Kconfig @@ -6,6 +6,16 @@ choice config TARGET_JETSON_TK1 bool "NVIDIA Tegra124 Jetson TK1 board"
+config TARGET_NYAN + bool "Google/NVIDIA Nyan Chrombook" + help + Norrin (PM370) is a Tegra124 clamshell board that is very similar + to venice2, but it has a different panel, the sdcard CD and WP + sense are flipped, and it has a different revision of the AS3722 + PMIC. This board is also refered to as "nyan" in the Chrome OS + trees. The retail name is the Acer Chromebook 13 CB5-311-T7NN + (13.3-inch HD, NVIDIA Tegra K1, 2GB). + config TARGET_VENICE2 bool "NVIDIA Tegra124 Venice2"
@@ -15,6 +25,7 @@ config SYS_SOC default "tegra124"
source "board/nvidia/jetson-tk1/Kconfig" +source "board/nvidia/nyan/Kconfig" source "board/nvidia/venice2/Kconfig"
endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ba6dec9..2d2dd31 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -30,6 +30,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra30-tec-ng.dtb \ tegra114-dalmore.dtb \ tegra124-jetson-tk1.dtb \ + tegra124-nyan-big.dtb \ tegra124-venice2.dtb dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \ zynq-zc706.dtb \ diff --git a/arch/arm/dts/tegra124-nyan-big.dts b/arch/arm/dts/tegra124-nyan-big.dts new file mode 100644 index 0000000..c1f35a0 --- /dev/null +++ b/arch/arm/dts/tegra124-nyan-big.dts @@ -0,0 +1,365 @@ +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "tegra124.dtsi" + +/ { + model = "Acer Chromebook 13 CB5-311"; + compatible = "google,nyan-big", "nvidia,tegra124"; + + aliases { + console = &uarta; + i2c0 = "/i2c@7000d000"; + i2c1 = "/i2c@7000c000"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; + i2c4 = "/i2c@7000c700"; + i2c5 = "/i2c@7000d100"; + rtc0 = "/i2c@0,7000d000/pmic@40"; + rtc1 = "/rtc@0,7000e000"; + sdhci0 = "/sdhci@700b0600"; + sdhci1 = "/sdhci@700b0400"; + spi0 = "/spi@7000d400"; + spi1 = "/spi@7000da00"; + usb0 = "/usb@7d000000"; + usb1 = "/usb@7d008000"; + }; + + memory { + reg = <0x80000000 0x80000000>; + }; + + serial@70006000 { + /* Debug connector on the bottom of the board near SD card. */ + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + + acodec: audio-codec@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; + }; + + temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; + + #thermal-sensor-cells = <1>; + }; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@40 { + compatible = "ams,as3722"; + reg = <0x40>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + + ams,system-power-controller; + + #interrupt-cells = <2>; + interrupt-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&as3722_default>; + + as3722_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + bias-pull-down; + }; + + gpio1 { + pins = "gpio1"; + function = "gpio"; + bias-pull-up; + }; + + gpio2_4_7 { + pins = "gpio2", "gpio4", "gpio7"; + function = "gpio"; + bias-pull-up; + }; + + gpio3_6 { + pins = "gpio3", "gpio6"; + bias-high-impedance; + }; + + gpio5 { + pins = "gpio5"; + function = "clk32k-out"; + bias-pull-down; + }; + }; + }; + }; + + spi@7000d400 { + status = "okay"; + + cros_ec: cros-ec@0 { + compatible = "google,cros-ec-spi"; + spi-max-frequency = <3000000>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; + reg = <0>; + + google,cros-ec-spi-msg-delay = <2000>; + + i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + #address-cells = <1>; + #size-cells = <0>; + + google,remote-bus = <0>; + + charger: bq24735@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(J, 0) + GPIO_ACTIVE_HIGH>; + ti,ac-detect-gpios = <&gpio + TEGRA_GPIO(J, 0) + GPIO_ACTIVE_HIGH>; + }; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <10>; + power-supplies = <&charger>; + }; + }; + }; + }; + + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + + flash@0 { + compatible = "winbond,w25q32dw"; + reg = <0>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <641 3845>; + nvidia,core-pwr-off-time = <61036>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + }; + + hda@70030000 { + status = "okay"; + }; + + sdhci@700b0000 { /* WiFi/BT on this bus */ + status = "okay"; + power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + no-1-8-v; + non-removable; + }; + + sdhci@700b0400 { /* SD Card on this bus */ + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + bus-width = <4>; + no-1-8-v; + }; + + sdhci@700b0600 { /* eMMC on this bus */ + status = "okay"; + bus-width = <8>; + no-1-8-v; + non-removable; + }; + + ahub@70300000 { + i2s@70301100 { + status = "okay"; + }; + }; + + usb@7d000000 { /* Rear external USB port. */ + status = "okay"; + }; + + usb-phy@7d000000 { + status = "okay"; + }; + + usb@7d004000 { /* Internal webcam. */ + status = "okay"; + }; + + usb-phy@7d004000 { + status = "okay"; + }; + + usb@7d008000 { /* Left external USB port. */ + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + pwms = <&pwm 1 1000000>; + + default-brightness-level = <224>; + brightness-levels = + < 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + 256>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + lid { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; + linux,input-type = <5>; + linux,code = <KEY_RESERVED>; + debounce-interval = <1>; + gpio-key,wakeup; + }; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + debounce-interval = <30>; + gpio-key,wakeup; + }; + }; + + panel: panel { + compatible = "auo,b133xtn01"; + + backlight = <&backlight>; + }; + + sound { + compatible = "nvidia,tegra-audio-max98090-nyan-big", + "nvidia,tegra-audio-max98090"; + nvidia,model = "Acer Chromebook 13"; + + nvidia,audio-routing = + "Headphones", "HPR", + "Headphones", "HPL", + "Speakers", "SPKR", + "Speakers", "SPKL", + "Mic Jack", "MICBIAS", + "DMICL", "Int Mic", + "DMICR", "Int Mic", + "IN34", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&acodec>; + + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; + }; +}; + +#include "cros-ec-keyboard.dtsi" diff --git a/board/nvidia/nyan/Kconfig b/board/nvidia/nyan/Kconfig new file mode 100644 index 0000000..2157961 --- /dev/null +++ b/board/nvidia/nyan/Kconfig @@ -0,0 +1,24 @@ +if TARGET_NYAN + +config SYS_CPU + string + default "arm720t" if SPL_BUILD + default "armv7" if !SPL_BUILD + +config SYS_BOARD + string + default "nyan" + +config SYS_VENDOR + string + default "nvidia" + +config SYS_SOC + string + default "tegra124" + +config SYS_CONFIG_NAME + string + default "nyan" + +endif diff --git a/board/nvidia/nyan/MAINTAINERS b/board/nvidia/nyan/MAINTAINERS new file mode 100644 index 0000000..35fd43f --- /dev/null +++ b/board/nvidia/nyan/MAINTAINERS @@ -0,0 +1,6 @@ +NORRIN BOARD +M: Allen Martin amartin@nvidia.com +S: Maintained +F: board/nvidia/nyan/ +F: include/configs/nyan.h +F: configs/nyan_defconfig diff --git a/board/nvidia/nyan/Makefile b/board/nvidia/nyan/Makefile new file mode 100644 index 0000000..4d4fb05 --- /dev/null +++ b/board/nvidia/nyan/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2014 +# NVIDIA Corporation <www.nvidia.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ../venice2/as3722_init.o +obj-y += nyan.o diff --git a/board/nvidia/nyan/nyan.c b/board/nvidia/nyan/nyan.c new file mode 100644 index 0000000..b533271 --- /dev/null +++ b/board/nvidia/nyan/nyan.c @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pinmux.h> +#include "pinmux-config-nyan.h" + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_set_tristate_input_clamping(); + + gpio_config_table(nyan_gpio_inits, + ARRAY_SIZE(nyan_gpio_inits)); + + pinmux_config_pingrp_table(nyan_pingrps, + ARRAY_SIZE(nyan_pingrps)); + + pinmux_config_drvgrp_table(nyan_drvgrps, + ARRAY_SIZE(nyan_drvgrps)); +} diff --git a/board/nvidia/nyan/pinmux-config-nyan.h b/board/nvidia/nyan/pinmux-config-nyan.h new file mode 100644 index 0000000..56ee356 --- /dev/null +++ b/board/nvidia/nyan/pinmux-config-nyan.h @@ -0,0 +1,287 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PINMUX_CONFIG_NYAN_H_ +#define _PINMUX_CONFIG_NYAN_H_ + +#define GPIO_INIT(_gpio, _init) \ + { \ + .gpio = GPIO_P##_gpio, \ + .init = TEGRA_GPIO_INIT_##_init, \ + } + +static const struct tegra_gpio_config nyan_gpio_inits[] = { + /* gpio, init_val */ + GPIO_INIT(A0, IN), + GPIO_INIT(C7, IN), + GPIO_INIT(G0, IN), + GPIO_INIT(G1, IN), + GPIO_INIT(G2, IN), + GPIO_INIT(G3, IN), + GPIO_INIT(H2, IN), + GPIO_INIT(H4, IN), + GPIO_INIT(H6, IN), + GPIO_INIT(H7, OUT1), + GPIO_INIT(I0, IN), + GPIO_INIT(I1, IN), + GPIO_INIT(I5, OUT1), + GPIO_INIT(I6, IN), + GPIO_INIT(I7, IN), + GPIO_INIT(J0, IN), + GPIO_INIT(J7, IN), + GPIO_INIT(K1, OUT0), + GPIO_INIT(K2, IN), + GPIO_INIT(K4, OUT0), + GPIO_INIT(K6, OUT0), + GPIO_INIT(K7, IN), + GPIO_INIT(N7, IN), + GPIO_INIT(P2, OUT0), + GPIO_INIT(Q0, IN), + GPIO_INIT(Q2, IN), + GPIO_INIT(Q3, IN), + GPIO_INIT(Q6, IN), + GPIO_INIT(Q7, IN), + GPIO_INIT(R0, OUT0), + GPIO_INIT(R1, IN), + GPIO_INIT(R4, IN), + GPIO_INIT(R7, IN), + GPIO_INIT(S3, OUT0), + GPIO_INIT(S4, OUT0), + GPIO_INIT(S7, IN), + GPIO_INIT(T1, IN), + GPIO_INIT(U4, IN), + GPIO_INIT(U5, IN), + GPIO_INIT(U6, IN), + GPIO_INIT(V0, IN), + GPIO_INIT(W3, IN), + GPIO_INIT(X1, IN), + GPIO_INIT(X4, IN), + GPIO_INIT(X7, OUT0), +}; + +#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .od = PMUX_PIN_OD_##_od, \ + .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +static const struct pmux_pingrp_config nyan_pingrps[] = { + /* pingrp, mux, pull, tri, e_input, od, rcv_sel */ + PINCFG(CLK_32K_OUT_PA0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART3_CTS_N_PA1, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PB0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PB1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART3_RTS_N_PC0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_TXD_PC2, IRDA, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_RXD_PC3, IRDA, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(PC7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI4, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI5, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_CTS_N_PJ5, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_RTS_N_PJ6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PJ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK4, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SPDIF_IN_PK6, DEFAULT, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_FS_PN0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_DOUT_PN2, I2S0, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA0_PO1, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA1_PO2, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA3_PO4, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA4_PO5, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA5_PO6, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA6_PO7, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_FS_PP4, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_DIN_PP5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_DOUT_PP6, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_SCLK_PP7, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL0_PQ0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL2_PQ2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL5_PQ5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL6_PQ6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL7_PQ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW2_PR2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW6_PR6, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW7_PR7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW8_PS0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW9_PS1, UARTA, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW10_PS2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW16_PT0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PV0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PV1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_W3_AUD_PW3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK2_OUT_PW5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART3_TXD_PW6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART3_RXD_PW7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X3_AUD_PX3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PBB0, VGP6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CAM_I2C_SCL_PBB1, RSVD3, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_I2C_SDA_PBB2, RSVD3, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PBB3, VGP3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB4, VGP4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CAM_MCLK_PCC0, VI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PCC1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PCC2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(CLK2_REQ_PCC5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L0_RST_N_PDD1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L0_CLKREQ_N_PDD2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_WAKE_N_PDD3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L1_RST_N_PDD5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L1_CLKREQ_N_PDD6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK3_OUT_PEE0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP_MCLK1_REQ_PEE2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PWR_INT_N, PMI, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL), + PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), +}; + +#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static const struct pmux_drvgrp_config nyan_drvgrps[] = { +}; + +#endif /* PINMUX_CONFIG_NYAN_H */ diff --git a/board/nvidia/venice2/as3722_init.h b/board/nvidia/venice2/as3722_init.h index 06c366e..bf0f1c8 100644 --- a/board/nvidia/venice2/as3722_init.h +++ b/board/nvidia/venice2/as3722_init.h @@ -18,7 +18,7 @@ #define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */ #define AS3722_LDCONTROL_REG 0x4E
-#ifdef CONFIG_TARGET_JETSON_TK1 +#if defined(CONFIG_TARGET_JETSON_TK1) || defined(CONFIG_TARGET_NYAN) #define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG) #else #define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG) diff --git a/configs/nyan_defconfig b/configs/nyan_defconfig new file mode 100644 index 0000000..b8a406c --- /dev/null +++ b/configs/nyan_defconfig @@ -0,0 +1,5 @@ ++S:CONFIG_ARM=y ++S:CONFIG_TEGRA=y ++S:CONFIG_TEGRA124=y ++S:CONFIG_TARGET_NYAN=y +CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big" diff --git a/include/configs/nyan.h b/include/configs/nyan.h new file mode 100644 index 0000000..d32d0d9 --- /dev/null +++ b/include/configs/nyan.h @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <linux/sizes.h> + +#include "tegra124-common.h" + +/* High-level configuration options */ +#define V_PROMPT "Tegra124 (Nyan) # " +#define CONFIG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_BOARD_EARLY_INIT_F + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) + +/* SPI */ +#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */ +#define CONFIG_TEGRA114_SPI_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */
Hi,
On 23 November 2014 at 09:12, Simon Glass sjg@chromium.org wrote:
From: Allen Martin amartin@nvidia.com
Nyan is a Tegra124 clamshell board that is very similar to venice2, but it has a different panel, the sdcard cd and wp sense are flipped, and it has a different revision of the AS3722 PMIC.
This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA Tegra K1, 2GB). The display is not currently supported, so it should boot on other nyan-based Chromebooks also, but only the device tree for nyan-big is provided here.
The device tree file is from Linux but with features removed which are unlikely to be supported in U-Boot soon (regulators, pinmux). Also the addresses are updated to 32-bit.
Signed-off-by: Allen Martin amartin@nvidia.com Signed-off-by: Simon Glass sjg@chromium.org (rebase, change to 'nyan', fix pinmux that resets nyan)
Changes in v3:
- Rename to nyan from norrin
- Bring in device tree file from Linux v3.18-rc5
- Generate pinmux file from tegra-pinmux-scripts
I should say that I'm not thrilled with this approach, particularly as the files it generate have no mentioned that they are auto-generated. Here we have a case where Nyan and Norrin apparently different by one pixmux setting but there is no way to exploit this commonality.
I think this was discussed a while ago (the idea of static pinmux being set up at start of day). If I recall I expressed my objections at the time. If U-Boot headed this way in general it would be unfortunate. You get a whole load of pinmux settings with no idea what they are for, and no idea how to change them for your board. It almost feels similar to a 'binary blob'.
I recently saw a patch to (from what I can tell) remove all the pinmux information from the device tree in Linux, presumably on the assumption it can never be changed except very early in the boot. If this is a limitation of Tegra then it seems unfortunate to me.
Regards, Simon
On 11/23/2014 10:02 AM, Simon Glass wrote:
Hi,
On 23 November 2014 at 09:12, Simon Glass sjg@chromium.org wrote:
From: Allen Martin amartin@nvidia.com
Nyan is a Tegra124 clamshell board that is very similar to venice2, but it has a different panel, the sdcard cd and wp sense are flipped, and it has a different revision of the AS3722 PMIC.
This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA Tegra K1, 2GB). The display is not currently supported, so it should boot on other nyan-based Chromebooks also, but only the device tree for nyan-big is provided here.
The device tree file is from Linux but with features removed which are unlikely to be supported in U-Boot soon (regulators, pinmux). Also the addresses are updated to 32-bit.
Signed-off-by: Allen Martin amartin@nvidia.com Signed-off-by: Simon Glass sjg@chromium.org (rebase, change to 'nyan', fix pinmux that resets nyan)
Changes in v3:
- Rename to nyan from norrin
- Bring in device tree file from Linux v3.18-rc5
- Generate pinmux file from tegra-pinmux-scripts
I should say that I'm not thrilled with this approach, particularly as the files it generate have no mentioned that they are auto-generated. Here we have a case where Nyan and Norrin apparently different by one pixmux setting but there is no way to exploit this commonality.
I think this was discussed a while ago (the idea of static pinmux being set up at start of day). If I recall I expressed my objections at the time. If U-Boot headed this way in general it would be unfortunate. You get a whole load of pinmux settings with no idea what they are for, and no idea how to change them for your board. It almost feels similar to a 'binary blob'.
That's the entire point; people should not be randomly fiddling with the pinmux data in U-Boot for any reason.
The model for Tegra boards is that whoever designs the boards fills out a spreadsheet to define the pinmux for the board. That spreadsheet is coded to detect and avoid a lot of mistakes (such as multiple pins muxed to/from the same signal, redundant pull-ups enabled on board and SoC, pins used for purposes incompatible with what the SoC supports, etc.). Any pinmux changes should be made in that spreadsheet, and all SW should use the values exported from or derived from the spreadsheet. There's no reason to modify the values afterwards.
This is similar to a binary blob in that the data shouldn't be modified.
This is quite different from a binary blob in that it's quite obvious exactly what the data represents semantically; it's a quite "plain-text" format. with non-obfuscated code to implement it, which directly maps to reasonably well documented hardware.
I recently saw a patch to (from what I can tell) remove all the pinmux information from the device tree in Linux, presumably on the assumption it can never be changed except very early in the boot. If this is a limitation of Tegra then it seems unfortunate to me.
It's to avoid redundant work. Bootloaders are expected to set up 100% of the pinmux[1]. Given that, there's no point the kernel repeating the process of setting up the exact same configuration.
[1] This is the only sane way to avoid conflicts between mux settings of different pins. Only partially programming the pinmux can leave other pins muxed to the same controller/signal for example. Resolving that requires hit-and-miss testing or complex table lookups to reprogram pins that conflict that otherwise wouldn't be programmed. That approach could cause undesired glitches on pins as they're continually reprogrammed between different states to avoid conflicts. The simplest and only 100% guaranteed way to avoid this is to simply program everything directly to the desired final configuration. This issue isn't anything Tegra specific either, but applies to any pinmux controller where the same signal can be routed to multiple pins/pads. I believe the only reason this hasn't been so explicitly addressed before is that people just haven't thought it through at this level.
On 11/23/2014 10:02 AM, Simon Glass wrote:
Hi,
On 23 November 2014 at 09:12, Simon Glass sjg@chromium.org wrote:
From: Allen Martin amartin@nvidia.com
Nyan is a Tegra124 clamshell board that is very similar to venice2, but it has a different panel, the sdcard cd and wp sense are flipped, and it has a different revision of the AS3722 PMIC.
This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA Tegra K1, 2GB). The display is not currently supported, so it should boot on other nyan-based Chromebooks also, but only the device tree for nyan-big is provided here.
The device tree file is from Linux but with features removed which are unlikely to be supported in U-Boot soon (regulators, pinmux). Also the addresses are updated to 32-bit.
Signed-off-by: Allen Martin amartin@nvidia.com Signed-off-by: Simon Glass sjg@chromium.org (rebase, change to 'nyan', fix pinmux that resets nyan)
Changes in v3:
- Rename to nyan from norrin
- Bring in device tree file from Linux v3.18-rc5
- Generate pinmux file from tegra-pinmux-scripts
I should say that I'm not thrilled with this approach, particularly as the files it generate have no mentioned that they are auto-generated.
Oh I forgot to mention - feel free to send a patch for that. I mainly didn't add such a message earlier, since I when I wrote the U-Boot header generator in tegra-pinmux-scripts, I wanted to generate exactly the same data as was already there in U-Boot in the manually written files. If you think updating those files to add a "this is auto-generated" message would be useful, feel free to send a patch to tegra-pinmux-scripts and we can add it.
On 11/23/2014 09:12 AM, Simon Glass wrote:
From: Allen Martin amartin@nvidia.com
Nyan is a Tegra124 clamshell board that is very similar to venice2, but it has a different panel, the sdcard cd and wp sense are flipped, and it has a different revision of the AS3722 PMIC.
This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA Tegra K1, 2GB). The display is not currently supported, so it should boot on other nyan-based Chromebooks also, but only the device tree for nyan-big is provided here.
As Olof explained it to me, Nyan is a family of boards, of which "Nyan Big" is a particular member. In other words, "Nyan Big" is the CB5. As such, I believe the U-Boot board should be named "Nyan Big" not "Nyan", unless we expect the U-Boot support for work for the various other Nyan family boards; I believe the HP Tegra Chromebooks are also in the Nyan family. Either way though (i.e. even if nyan.c gets shared between the Acer and HP Tegra Chromebooks), I still think we want separate top-level U-Boot board names for the two, so that it's easy for people to build the right DT into their U-Boot binary for example.
Hi Stephen,
On 24 November 2014 at 10:28, Stephen Warren swarren@wwwdotorg.org wrote:
On 11/23/2014 09:12 AM, Simon Glass wrote:
From: Allen Martin amartin@nvidia.com
Nyan is a Tegra124 clamshell board that is very similar to venice2, but it has a different panel, the sdcard cd and wp sense are flipped, and it has a different revision of the AS3722 PMIC.
This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA Tegra K1, 2GB). The display is not currently supported, so it should boot on other nyan-based Chromebooks also, but only the device tree for nyan-big is provided here.
As Olof explained it to me, Nyan is a family of boards, of which "Nyan Big" is a particular member. In other words, "Nyan Big" is the CB5. As such, I believe the U-Boot board should be named "Nyan Big" not "Nyan", unless we expect the U-Boot support for work for the various other Nyan family boards; I believe the HP Tegra Chromebooks are also in the Nyan family. Either way though (i.e. even if nyan.c gets shared between the Acer and HP Tegra Chromebooks), I still think we want separate top-level U-Boot board names for the two, so that it's easy for people to build the right DT into their U-Boot binary for example.
What change are you requesting for this patch?
Regards, Simon
On 11/24/2014 04:48 PM, Simon Glass wrote:
Hi Stephen,
On 24 November 2014 at 10:28, Stephen Warren swarren@wwwdotorg.org wrote:
On 11/23/2014 09:12 AM, Simon Glass wrote:
From: Allen Martin amartin@nvidia.com
Nyan is a Tegra124 clamshell board that is very similar to venice2, but it has a different panel, the sdcard cd and wp sense are flipped, and it has a different revision of the AS3722 PMIC.
This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA Tegra K1, 2GB). The display is not currently supported, so it should boot on other nyan-based Chromebooks also, but only the device tree for nyan-big is provided here.
As Olof explained it to me, Nyan is a family of boards, of which "Nyan Big" is a particular member. In other words, "Nyan Big" is the CB5. As such, I believe the U-Boot board should be named "Nyan Big" not "Nyan", unless we expect the U-Boot support for work for the various other Nyan family boards; I believe the HP Tegra Chromebooks are also in the Nyan family. Either way though (i.e. even if nyan.c gets shared between the Acer and HP Tegra Chromebooks), I still think we want separate top-level U-Boot board names for the two, so that it's easy for people to build the right DT into their U-Boot binary for example.
What change are you requesting for this patch?
Given Andrew's description of the board naming, I think this patch (patch subject/description, filenames, file content) and anything else for this board should call it nyan-big not nyan. The Acer Chrombook is apparently nyan-big, whereas plain nyan means Norrin.
Hi Stephen,
On 25 November 2014 at 09:14, Stephen Warren swarren@wwwdotorg.org wrote:
On 11/24/2014 04:48 PM, Simon Glass wrote:
Hi Stephen,
On 24 November 2014 at 10:28, Stephen Warren swarren@wwwdotorg.org wrote:
On 11/23/2014 09:12 AM, Simon Glass wrote:
From: Allen Martin amartin@nvidia.com
Nyan is a Tegra124 clamshell board that is very similar to venice2, but it has a different panel, the sdcard cd and wp sense are flipped, and it has a different revision of the AS3722 PMIC.
This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA Tegra K1, 2GB). The display is not currently supported, so it should boot on other nyan-based Chromebooks also, but only the device tree for nyan-big is provided here.
As Olof explained it to me, Nyan is a family of boards, of which "Nyan Big" is a particular member. In other words, "Nyan Big" is the CB5. As such, I believe the U-Boot board should be named "Nyan Big" not "Nyan", unless we expect the U-Boot support for work for the various other Nyan family boards; I believe the HP Tegra Chromebooks are also in the Nyan family. Either way though (i.e. even if nyan.c gets shared between the Acer and HP Tegra Chromebooks), I still think we want separate top-level U-Boot board names for the two, so that it's easy for people to build the right DT into their U-Boot binary for example.
What change are you requesting for this patch?
Given Andrew's description of the board naming, I think this patch (patch subject/description, filenames, file content) and anything else for this board should call it nyan-big not nyan. The Acer Chrombook is apparently nyan-big, whereas plain nyan means Norrin.
OK I think there are still a few nyans, so will purge. If we end up supporting more from this range I'd like to avoid duplicating lots of code (ideally it would just be a different device tree). But let's cross that bridge when we come to it.
Regards, Simon
participants (2)
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Simon Glass -
Stephen Warren