[PATCH] riscv: mbv: Align DT with QEMU
Align U-Boot with QEMU amd-microblaze-v-virt platform to be able to wire it with CI.
Signed-off-by: Michal Simek michal.simek@amd.com ---
I am sending it to be in queue. Qemu patch hasn't been merged to qemu yet but here is the latest version. https://lore.kernel.org/r/20241017072507.4033413-1-sai.pavan.boddu@amd.com --- arch/riscv/dts/xilinx-mbv32.dts | 30 ++++++++++-------------------- board/xilinx/mbv/Kconfig | 6 +++--- configs/xilinx_mbv32_defconfig | 12 ++++++------ 3 files changed, 19 insertions(+), 29 deletions(-)
diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts index 48ee11549566..4050ce2f051d 100644 --- a/arch/riscv/dts/xilinx-mbv32.dts +++ b/arch/riscv/dts/xilinx-mbv32.dts @@ -20,7 +20,7 @@ cpus: cpus { #address-cells = <1>; #size-cells = <0>; - timebase-frequency = <102000000>; + timebase-frequency = <100000000>; cpu_0: cpu@0 { compatible = "amd,mbv32", "riscv"; device_type = "cpu"; @@ -28,7 +28,7 @@ riscv,isa = "rv32imafdc"; i-cache-size = <32768>; d-cache-size = <32768>; - clock-frequency = <102000000>; + clock-frequency = <100000000>; cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; interrupt-controller; @@ -46,15 +46,15 @@ stdout-path = "serial0:115200n8"; };
- memory@20000000 { + memory@80000000 { device_type = "memory"; - reg = <0x20000000 0x20000000>; + reg = <0x80000000 0x40000000>; };
- clk102: clock { + clk100: clock { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <102000000>; + clock-frequency = <100000000>; };
axi: axi { @@ -77,30 +77,20 @@ compatible = "xlnx,xps-timer-1.00.a"; reg = <0x41c00000 0x1000>; interrupt-parent = <&axi_intc>; - interrupts = <1 2>; - bootph-all; - xlnx,one-timer-only = <0>; - clock-names = "s_axi_aclk"; - clocks = <&clk102>; - }; - - xlnx_timer1: timer@41c20000 { - compatible = "xlnx,xps-timer-1.00.a"; - reg = <0x41c20000 0x1000>; - interrupt-parent = <&axi_intc>; interrupts = <0 2>; + bootph-all; xlnx,one-timer-only = <0>; clock-names = "s_axi_aclk"; - clocks = <&clk102>; + clocks = <&clk100>; };
uart0: serial@40600000 { compatible = "xlnx,xps-uartlite-1.00.a"; reg = <0x40600000 0x1000>; interrupt-parent = <&axi_intc>; - interrupts = <2 2>; + interrupts = <1 2>; bootph-all; - clocks = <&clk102>; + clocks = <&clk100>; current-speed = <115200>; xlnx,data-bits = <8>; xlnx,use-parity = <0>; diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig index a3a6f2125770..c52ba1870b0b 100644 --- a/board/xilinx/mbv/Kconfig +++ b/board/xilinx/mbv/Kconfig @@ -10,14 +10,14 @@ config SYS_CPU default "generic"
config TEXT_BASE - default 0x21200000 + default 0x81200000
config SPL_TEXT_BASE - default 0x20000000 + default 0x80000000
config SPL_OPENSBI_LOAD_ADDR hex - default 0x20200000 + default 0x80200000
config BOARD_SPECIFIC_OPTIONS def_bool y diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index 3983b20c2d80..7333413267ec 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -2,17 +2,17 @@ CONFIG_RISCV=y CONFIG_SYS_MALLOC_LEN=0xe00000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x21200000 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" -CONFIG_SPL_STACK=0x20200000 -CONFIG_SPL_BSS_START_ADDR=0x24000000 +CONFIG_SPL_STACK=0x80200000 +CONFIG_SPL_BSS_START_ADDR=0x84000000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 -CONFIG_SYS_LOAD_ADDR=0x20200000 +CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0x40600000 -CONFIG_DEBUG_UART_CLOCK=1000000 +CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_SYS_CLK_FREQ=100000000 CONFIG_BOOT_SCRIPT_OFFSET=0x0 CONFIG_DEBUG_UART=y @@ -20,7 +20,7 @@ CONFIG_TARGET_XILINX_MBV=y # CONFIG_SPL_SMP is not set CONFIG_REMAKE_ELF=y CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x20200000 +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y
From: Simek, Michal michal.simek@amd.com Sent: Wednesday, October 23, 2024 11:37 AM To: u-boot@lists.denx.de; git@xilinx.com Cc: Leo ycliang@andestech.com; Padmarao Begari padmarao.begari@microchip.com; Rick Chen rick@andestech.com; Tom Rini trini@konsulko.com Subject: [PATCH] riscv: mbv: Align DT with QEMU
Align U-Boot with QEMU amd-microblaze-v-virt platform to be able to wire it with CI.
Signed-off-by: Michal Simek michal.simek@amd.com
Reviewed-by: Padmarao Begari padmarao.begari@amd.com
I am sending it to be in queue. Qemu patch hasn't been merged to qemu yet but here is the latest version. https://lore.kernel.org/r/20241017072507.4033413-1-sai.pavan.boddu@amd.com
arch/riscv/dts/xilinx-mbv32.dts | 30 ++++++++++-------------------- board/xilinx/mbv/Kconfig | 6 +++--- configs/xilinx_mbv32_defconfig | 12 ++++++------ 3 files changed, 19 insertions(+), 29 deletions(-)
diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts index 48ee11549566..4050ce2f051d 100644 --- a/arch/riscv/dts/xilinx-mbv32.dts +++ b/arch/riscv/dts/xilinx-mbv32.dts @@ -20,7 +20,7 @@ cpus: cpus { #address-cells = <1>; #size-cells = <0>;
timebase-frequency = <102000000>;
timebase-frequency = <100000000>;@@ -28,7 +28,7 @@ riscv,isa = "rv32imafdc"; i-cache-size = <32768>; d-cache-size = <32768>;
clock-frequency = <102000000>;
clock-frequency = <100000000>; cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; interrupt-controller;@@ -46,15 +46,15 @@ stdout-path = "serial0:115200n8"; };
- memory@20000000 {
- memory@80000000 { device_type = "memory";
reg = <0x20000000 0x20000000>;
reg = <0x80000000 0x40000000>;
- clk102: clock {
- clk100: clock { compatible = "fixed-clock"; #clock-cells = <0>;
clock-frequency = <102000000>;
clock-frequency = <100000000>;};
axi: axi {
@@ -77,30 +77,20 @@ compatible = "xlnx,xps-timer-1.00.a"; reg = <0x41c00000 0x1000>; interrupt-parent = <&axi_intc>;
interrupts = <1 2>;bootph-all;xlnx,one-timer-only = <0>;clock-names = "s_axi_aclk";clocks = <&clk102>;};xlnx_timer1: timer@41c20000 {compatible = "xlnx,xps-timer-1.00.a";reg = <0x41c20000 0x1000>;interrupt-parent = <&axi_intc>; interrupts = <0 2>;
bootph-all; xlnx,one-timer-only = <0>; clock-names = "s_axi_aclk";
clocks = <&clk102>;
clocks = <&clk100>;};
uart0: serial@40600000 { compatible = "xlnx,xps-uartlite-1.00.a"; reg = <0x40600000 0x1000>; interrupt-parent = <&axi_intc>;
interrupts = <2 2>;
interrupts = <1 2>; bootph-all;
clocks = <&clk102>;
clocks = <&clk100>; current-speed = <115200>; xlnx,data-bits = <8>; xlnx,use-parity = <0>;diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig index a3a6f2125770..c52ba1870b0b 100644 --- a/board/xilinx/mbv/Kconfig +++ b/board/xilinx/mbv/Kconfig @@ -10,14 +10,14 @@ config SYS_CPU default "generic"
config TEXT_BASE
- default 0x21200000
- default 0x81200000
config SPL_TEXT_BASE
- default 0x20000000
- default 0x80000000
config SPL_OPENSBI_LOAD_ADDR hex
- default 0x20200000
- default 0x80200000
config BOARD_SPECIFIC_OPTIONS def_bool y diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index 3983b20c2d80..7333413267ec 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -2,17 +2,17 @@ CONFIG_RISCV=y CONFIG_SYS_MALLOC_LEN=0xe00000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x21200000 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" -CONFIG_SPL_STACK=0x20200000 -CONFIG_SPL_BSS_START_ADDR=0x24000000 +CONFIG_SPL_STACK=0x80200000 +CONFIG_SPL_BSS_START_ADDR=0x84000000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 -CONFIG_SYS_LOAD_ADDR=0x20200000 +CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0x40600000 -CONFIG_DEBUG_UART_CLOCK=1000000 +CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_SYS_CLK_FREQ=100000000 CONFIG_BOOT_SCRIPT_OFFSET=0x0 CONFIG_DEBUG_UART=y @@ -20,7 +20,7 @@ CONFIG_TARGET_XILINX_MBV=y # CONFIG_SPL_SMP is not set CONFIG_REMAKE_ELF=y CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x20200000 +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y -- 2.43.0
participants (2)
-
Begari, Padmarao -
Michal Simek