[U-Boot] [PATCH 0/4] sf: SST changes, Byte program

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[U-Boot] ti, am3517: errata 430973...

Jagannadha Sutradharudu Teki

9 Dec 2014 9 Dec '14

4:29 p.m.

This patch-set added byte program support for sst flashes and some implementation changes in sf to support array slow and byte program specific controllers.

Bin Meng (1): spi: sf: Support byte program for sst spi flash

Jagannadha Sutradharudu Teki (2): sf: Fix look for the fastest read command sf: Enable byte program support

Simon Glass (1): spi: Fix flag collision for SST_WP

drivers/mtd/spi/sf_internal.h | 22 ++++++--- drivers/mtd/spi/sf_ops.c | 31 +++++++++++++ drivers/mtd/spi/sf_params.c | 102 +++++++++++++++++++++--------------------- drivers/mtd/spi/sf_probe.c | 9 +++- include/spi.h | 1 + 5 files changed, 105 insertions(+), 60 deletions(-)

-- 1.9.1

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Jagannadha Sutradharudu Teki

9 Dec 9 Dec

4:29 p.m.

New subject: [U-Boot] [PATCH 1/4] sf: Fix look for the fastest read command

Few of the spi controllers are only supports array slow read which is quite different behaviour compared to others.

So this fix on sf will correctly handle the slow read supported controllers.

Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com --- drivers/mtd/spi/sf_internal.h | 13 +++--- drivers/mtd/spi/sf_params.c | 102 +++++++++++++++++++++--------------------- drivers/mtd/spi/sf_probe.c | 1 + 3 files changed, 60 insertions(+), 56 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 5b7670c..e159f04 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -23,13 +23,16 @@ enum spi_dual_flash { /* Enum list - Full read commands */ enum spi_read_cmds { ARRAY_SLOW = 1 << 0, - DUAL_OUTPUT_FAST = 1 << 1, - DUAL_IO_FAST = 1 << 2, - QUAD_OUTPUT_FAST = 1 << 3, - QUAD_IO_FAST = 1 << 4, + ARRAY_FAST = 1 << 1, + DUAL_OUTPUT_FAST = 1 << 2, + DUAL_IO_FAST = 1 << 3, + QUAD_OUTPUT_FAST = 1 << 4, + QUAD_IO_FAST = 1 << 5, };

-#define RD_EXTN (ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST) +/* Normal - Extended - Full command set */ +#define RD_NORM (ARRAY_SLOW | ARRAY_FAST) +#define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST) #define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)

/* sf param flags */ diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 61545ca..0f1f837 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -15,42 +15,42 @@ /* SPI/QSPI flash device params structure */ const struct spi_flash_params spi_flash_params_table[] = { #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ - {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, 0, SECT_4K}, - {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, 0, SECT_4K}, - {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, 0, SECT_4K}, - {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, 0, SECT_4K}, - {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, 0, SECT_4K}, - {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, 0, SECT_4K}, - {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, 0, SECT_4K}, - {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, 0, SECT_4K}, + {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K}, + {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K}, + {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K}, + {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K}, + {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K}, + {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, + {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, + {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, #endif #ifdef CONFIG_SPI_FLASH_EON /* EON */ - {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0, 0}, - {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, 0, SECT_4K}, - {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0, 0}, - {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0, 0}, + {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, RD_NORM, 0}, + {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, + {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, RD_NORM, 0}, + {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, RD_NORM, 0}, #endif #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ - {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, 0, SECT_4K}, - {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, 0, SECT_4K}, + {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, + {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ - {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0, 0}, - {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0, 0}, - {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0, 0}, - {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0, 0}, - {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0, 0}, - {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0, 0}, + {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, RD_NORM, 0}, + {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, RD_NORM, 0}, + {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, RD_NORM, 0}, + {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, RD_NORM, 0}, + {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, RD_NORM, 0}, + {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, RD_NORM, 0}, {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP}, {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP}, {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ - {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0, 0}, - {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0, 0}, - {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0, 0}, - {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0, 0}, + {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, RD_NORM, 0}, + {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, RD_NORM, 0}, + {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, RD_NORM, 0}, + {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, RD_NORM, 0}, {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP}, {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP}, {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP}, @@ -64,17 +64,17 @@ const struct spi_flash_params spi_flash_params_table[] = { {"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP}, #endif #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ - {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0, 0}, - {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0, 0}, - {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0, 0}, - {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0, 0}, - {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0, 0}, - {"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, 0, 0}, + {"M25P10", 0x202011, 0x0, 32 * 1024, 4, RD_NORM, 0}, + {"M25P20", 0x202012, 0x0, 64 * 1024, 4, RD_NORM, 0}, + {"M25P40", 0x202013, 0x0, 64 * 1024, 8, RD_NORM, 0}, + {"M25P80", 0x202014, 0x0, 64 * 1024, 16, RD_NORM, 0}, + {"M25P16", 0x202015, 0x0, 64 * 1024, 32, RD_NORM, 0}, + {"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, RD_NORM, 0}, {"M25PX16", 0x207115, 0x1000, 64 * 1024, 32, RD_EXTN, 0}, - {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0, 0}, - {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0, 0}, - {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0, 0}, - {"M25PX64", 0x207117, 0x0, 64 * 1024, 128, 0, SECT_4K}, + {"M25P32", 0x202016, 0x0, 64 * 1024, 64, RD_NORM, 0}, + {"M25P64", 0x202017, 0x0, 64 * 1024, 128, RD_NORM, 0}, + {"M25P128", 0x202018, 0x0, 256 * 1024, 64, RD_NORM, 0}, + {"M25PX64", 0x207117, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, @@ -89,25 +89,25 @@ const struct spi_flash_params spi_flash_params_table[] = { {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, #endif #ifdef CONFIG_SPI_FLASH_SST /* SST */ - {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP}, - {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP}, - {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, 0, SECT_4K | SST_WP}, - {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, 0, SECT_4K | SST_WP}, - {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, 0, SECT_4K}, - {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, 0, SECT_4K | SST_WP}, - {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, 0, SECT_4K | SST_WP}, - {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, 0, SECT_4K | SST_WP}, - {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP}, - {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP}, + {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WP}, + {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WP}, + {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K | SST_WP}, + {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K | SST_WP}, + {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, + {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, RD_NORM, SECT_4K | SST_WP}, + {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM, SECT_4K | SST_WP}, + {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K | SST_WP}, + {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WP}, + {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WP}, #endif #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ - {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0, 0}, - {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0, 0}, - {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0, 0}, - {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, 0, SECT_4K}, - {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, 0, SECT_4K}, - {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, 0, SECT_4K}, - {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, 0, SECT_4K}, + {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, RD_NORM, 0}, + {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, RD_NORM, 0}, + {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, RD_NORM, 0}, + {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K}, + {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K}, + {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, + {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K}, {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K}, {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 2636426..7cde4c0 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -24,6 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; /* Read commands array */ static u8 spi_read_cmds_array[] = { CMD_READ_ARRAY_SLOW, + CMD_READ_ARRAY_FAST, CMD_READ_DUAL_OUTPUT_FAST, CMD_READ_DUAL_IO_FAST, CMD_READ_QUAD_OUTPUT_FAST,

-- 1.9.1

Bin Meng

10 Dec 10 Dec

9:15 a.m.

New subject: [U-Boot] [PATCH 1/4] sf: Fix look for the fastest read command

Hi Jagan,

On Tue, Dec 9, 2014 at 11:29 PM, Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com wrote:

...

Few of the spi controllers are only supports array slow read which is quite different behaviour compared to others.

So this fix on sf will correctly handle the slow read supported controllers.

Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com

drivers/mtd/spi/sf_internal.h | 13 +++--- drivers/mtd/spi/sf_params.c | 102 +++++++++++++++++++++--------------------- drivers/mtd/spi/sf_probe.c | 1 + 3 files changed, 60 insertions(+), 56 deletions(-)

```
  DUAL_OUTPUT_FAST        = 1 << 1,
```
```
  DUAL_IO_FAST            = 1 << 2,
```
```
  QUAD_OUTPUT_FAST        = 1 << 3,
```
```
  QUAD_IO_FAST            = 1 << 4,
```

```
  ARRAY_FAST              = 1 << 1,
```
```
  DUAL_OUTPUT_FAST        = 1 << 2,
```
```
  DUAL_IO_FAST            = 1 << 3,
```
```
  QUAD_OUTPUT_FAST        = 1 << 4,
```
```
  QUAD_IO_FAST            = 1 << 5,
```

};

  {"AT45DB011D",     0x1f2200, 0x0,       64 * 1024,     4,       0,                  SECT_4K},

  {"AT45DB021D",     0x1f2300, 0x0,       64 * 1024,     8,       0,                  SECT_4K},

  {"AT45DB041D",     0x1f2400, 0x0,       64 * 1024,     8,       0,                  SECT_4K},

  {"AT45DB081D",     0x1f2500, 0x0,       64 * 1024,    16,       0,                  SECT_4K},

  {"AT45DB161D",     0x1f2600, 0x0,       64 * 1024,    32,       0,                  SECT_4K},

  {"AT45DB321D",     0x1f2700, 0x0,       64 * 1024,    64,       0,                  SECT_4K},

  {"AT45DB641D",     0x1f2800, 0x0,       64 * 1024,   128,       0,                  SECT_4K},

  {"AT25DF321",      0x1f4701, 0x0,       64 * 1024,    64,       0,                  SECT_4K},

  {"AT45DB011D",     0x1f2200, 0x0,       64 * 1024,     4, RD_NORM,                  SECT_4K},

  {"AT45DB021D",     0x1f2300, 0x0,       64 * 1024,     8, RD_NORM,                  SECT_4K},

  {"AT45DB041D",     0x1f2400, 0x0,       64 * 1024,     8, RD_NORM,                  SECT_4K},

  {"AT45DB081D",     0x1f2500, 0x0,       64 * 1024,    16, RD_NORM,                  SECT_4K},

  {"AT45DB161D",     0x1f2600, 0x0,       64 * 1024,    32, RD_NORM,                  SECT_4K},

  {"AT45DB321D",     0x1f2700, 0x0,       64 * 1024,    64, RD_NORM,                  SECT_4K},

  {"AT45DB641D",     0x1f2800, 0x0,       64 * 1024,   128, RD_NORM,                  SECT_4K},

  {"AT25DF321",      0x1f4701, 0x0,       64 * 1024,    64, RD_NORM,                  SECT_4K},

#endif #ifdef CONFIG_SPI_FLASH_EON /* EON */

  {"EN25Q32B",       0x1c3016, 0x0,       64 * 1024,    64,       0,                        0},

  {"EN25Q64",        0x1c3017, 0x0,       64 * 1024,   128,       0,                  SECT_4K},

  {"EN25Q128B",      0x1c3018, 0x0,       64 * 1024,   256,       0,                        0},

  {"EN25S64",        0x1c3817, 0x0,       64 * 1024,   128,       0,                        0},

  {"EN25Q32B",       0x1c3016, 0x0,       64 * 1024,    64, RD_NORM,                        0},

  {"EN25Q64",        0x1c3017, 0x0,       64 * 1024,   128, RD_NORM,                  SECT_4K},

  {"EN25Q128B",      0x1c3018, 0x0,       64 * 1024,   256, RD_NORM,                        0},

  {"EN25S64",        0x1c3817, 0x0,       64 * 1024,   128, RD_NORM,                        0},

#endif #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */

  {"GD25Q64B",       0xc84017, 0x0,       64 * 1024,   128,       0,                  SECT_4K},

  {"GD25LQ32",       0xc86016, 0x0,       64 * 1024,    64,       0,                  SECT_4K},

  {"GD25Q64B",       0xc84017, 0x0,       64 * 1024,   128, RD_NORM,                  SECT_4K},

  {"GD25LQ32",       0xc86016, 0x0,       64 * 1024,    64, RD_NORM,                  SECT_4K},

#endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */

  {"MX25L2006E",     0xc22012, 0x0,       64 * 1024,     4,       0,                        0},

  {"MX25L4005",      0xc22013, 0x0,       64 * 1024,     8,       0,                        0},

  {"MX25L8005",      0xc22014, 0x0,       64 * 1024,    16,       0,                        0},

  {"MX25L1605D",     0xc22015, 0x0,       64 * 1024,    32,       0,                        0},

  {"MX25L3205D",     0xc22016, 0x0,       64 * 1024,    64,       0,                        0},

  {"MX25L6405D",     0xc22017, 0x0,       64 * 1024,   128,       0,                        0},

  {"MX25L2006E",     0xc22012, 0x0,       64 * 1024,     4, RD_NORM,                        0},

  {"MX25L4005",      0xc22013, 0x0,       64 * 1024,     8, RD_NORM,                        0},

  {"MX25L8005",      0xc22014, 0x0,       64 * 1024,    16, RD_NORM,                        0},

  {"MX25L1605D",     0xc22015, 0x0,       64 * 1024,    32, RD_NORM,                        0},

  {"MX25L3205D",     0xc22016, 0x0,       64 * 1024,    64, RD_NORM,                        0},

  {"MX25L6405D",     0xc22017, 0x0,       64 * 1024,   128, RD_NORM,                        0},
  {"MX25L12805",     0xc22018, 0x0,       64 * 1024,   256, RD_FULL,                   WR_QPP},
  {"MX25L25635F",    0xc22019, 0x0,       64 * 1024,   512, RD_FULL,                   WR_QPP},
  {"MX25L51235F",    0xc2201a, 0x0,       64 * 1024,  1024, RD_FULL,                   WR_QPP},
  {"MX25L12855E",    0xc22618, 0x0,       64 * 1024,   256, RD_FULL,                   WR_QPP},

#endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */

  {"S25FL008A",      0x010213, 0x0,       64 * 1024,    16,       0,                        0},

  {"S25FL016A",      0x010214, 0x0,       64 * 1024,    32,       0,                        0},

  {"S25FL032A",      0x010215, 0x0,       64 * 1024,    64,       0,                        0},

  {"S25FL064A",      0x010216, 0x0,       64 * 1024,   128,       0,                        0},

  {"S25FL008A",      0x010213, 0x0,       64 * 1024,    16, RD_NORM,                        0},

  {"S25FL016A",      0x010214, 0x0,       64 * 1024,    32, RD_NORM,                        0},

  {"S25FL032A",      0x010215, 0x0,       64 * 1024,    64, RD_NORM,                        0},

  {"S25FL064A",      0x010216, 0x0,       64 * 1024,   128, RD_NORM,                        0},
  {"S25FL128P_256K", 0x012018, 0x0300,   256 * 1024,    64, RD_FULL,                   WR_QPP},
  {"S25FL128P_64K",  0x012018, 0x0301,    64 * 1024,   256, RD_FULL,                   WR_QPP},
  {"S25FL032P",      0x010215, 0x4d00,    64 * 1024,    64, RD_FULL,                   WR_QPP},

@@ -64,17 +64,17 @@ const struct spi_flash_params spi_flash_params_table[] = { {"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP}, #endif #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */

  {"M25P10",         0x202011, 0x0,       32 * 1024,     4,       0,                        0},

  {"M25P20",         0x202012, 0x0,       64 * 1024,     4,       0,                        0},

  {"M25P40",         0x202013, 0x0,       64 * 1024,     8,       0,                        0},

  {"M25P80",         0x202014, 0x0,       64 * 1024,    16,       0,                        0},

  {"M25P16",         0x202015, 0x0,       64 * 1024,    32,       0,                        0},

  {"M25PE16",        0x208015, 0x1000,    64 * 1024,    32,       0,                        0},

  {"M25P10",         0x202011, 0x0,       32 * 1024,     4, RD_NORM,                        0},

  {"M25P20",         0x202012, 0x0,       64 * 1024,     4, RD_NORM,                        0},

  {"M25P40",         0x202013, 0x0,       64 * 1024,     8, RD_NORM,                        0},

  {"M25P80",         0x202014, 0x0,       64 * 1024,    16, RD_NORM,                        0},

  {"M25P16",         0x202015, 0x0,       64 * 1024,    32, RD_NORM,                        0},

  {"M25PE16",        0x208015, 0x1000,    64 * 1024,    32, RD_NORM,                        0},
  {"M25PX16",        0x207115, 0x1000,    64 * 1024,    32, RD_EXTN,                        0},

  {"M25P32",         0x202016, 0x0,       64 * 1024,    64,       0,                        0},

  {"M25P64",         0x202017, 0x0,       64 * 1024,   128,       0,                        0},

  {"M25P128",        0x202018, 0x0,      256 * 1024,    64,       0,                        0},

  {"M25PX64",        0x207117, 0x0,       64 * 1024,   128,       0,                  SECT_4K},

  {"M25P32",         0x202016, 0x0,       64 * 1024,    64, RD_NORM,                        0},

  {"M25P64",         0x202017, 0x0,       64 * 1024,   128, RD_NORM,                        0},

  {"M25P128",        0x202018, 0x0,      256 * 1024,    64, RD_NORM,                        0},

  {"M25PX64",        0x207117, 0x0,       64 * 1024,   128, RD_NORM,                  SECT_4K},
  {"N25Q32",         0x20ba16, 0x0,       64 * 1024,    64, RD_FULL,         WR_QPP | SECT_4K},
  {"N25Q32A",        0x20bb16, 0x0,       64 * 1024,    64, RD_FULL,         WR_QPP | SECT_4K},
  {"N25Q64",         0x20ba17, 0x0,       64 * 1024,   128, RD_FULL,         WR_QPP | SECT_4K},

@@ -89,25 +89,25 @@ const struct spi_flash_params spi_flash_params_table[] = { {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, #endif #ifdef CONFIG_SPI_FLASH_SST /* SST */

  {"SST25VF040B",    0xbf258d, 0x0,       64 * 1024,     8,       0,          SECT_4K | SST_WP},

  {"SST25VF080B",    0xbf258e, 0x0,       64 * 1024,    16,       0,          SECT_4K | SST_WP},

  {"SST25VF016B",    0xbf2541, 0x0,       64 * 1024,    32,       0,          SECT_4K | SST_WP},

  {"SST25VF032B",    0xbf254a, 0x0,       64 * 1024,    64,       0,          SECT_4K | SST_WP},

  {"SST25VF064C",    0xbf254b, 0x0,       64 * 1024,   128,       0,                   SECT_4K},

  {"SST25WF512",     0xbf2501, 0x0,       64 * 1024,     1,       0,          SECT_4K | SST_WP},

  {"SST25WF010",     0xbf2502, 0x0,       64 * 1024,     2,       0,          SECT_4K | SST_WP},

  {"SST25WF020",     0xbf2503, 0x0,       64 * 1024,     4,       0,          SECT_4K | SST_WP},

  {"SST25WF040",     0xbf2504, 0x0,       64 * 1024,     8,       0,          SECT_4K | SST_WP},

  {"SST25WF080",     0xbf2505, 0x0,       64 * 1024,    16,       0,          SECT_4K | SST_WP},

  {"SST25VF040B",    0xbf258d, 0x0,       64 * 1024,     8, RD_NORM,          SECT_4K | SST_WP},

  {"SST25VF080B",    0xbf258e, 0x0,       64 * 1024,    16, RD_NORM,          SECT_4K | SST_WP},

  {"SST25VF016B",    0xbf2541, 0x0,       64 * 1024,    32, RD_NORM,          SECT_4K | SST_WP},

  {"SST25VF032B",    0xbf254a, 0x0,       64 * 1024,    64, RD_NORM,          SECT_4K | SST_WP},

  {"SST25VF064C",    0xbf254b, 0x0,       64 * 1024,   128, RD_NORM,                   SECT_4K},

  {"SST25WF512",     0xbf2501, 0x0,       64 * 1024,     1, RD_NORM,          SECT_4K | SST_WP},

  {"SST25WF010",     0xbf2502, 0x0,       64 * 1024,     2, RD_NORM,          SECT_4K | SST_WP},

  {"SST25WF020",     0xbf2503, 0x0,       64 * 1024,     4, RD_NORM,          SECT_4K | SST_WP},

  {"SST25WF040",     0xbf2504, 0x0,       64 * 1024,     8, RD_NORM,          SECT_4K | SST_WP},

  {"SST25WF080",     0xbf2505, 0x0,       64 * 1024,    16, RD_NORM,          SECT_4K | SST_WP},

#endif #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */

  {"W25P80",         0xef2014, 0x0,       64 * 1024,    16,       0,                         0},

  {"W25P16",         0xef2015, 0x0,       64 * 1024,    32,       0,                         0},

  {"W25P32",         0xef2016, 0x0,       64 * 1024,    64,       0,                         0},

  {"W25X40",         0xef3013, 0x0,       64 * 1024,     8,       0,                   SECT_4K},

  {"W25X16",         0xef3015, 0x0,       64 * 1024,    32,       0,                   SECT_4K},

  {"W25X32",         0xef3016, 0x0,       64 * 1024,    64,       0,                   SECT_4K},

  {"W25X64",         0xef3017, 0x0,       64 * 1024,   128,       0,                   SECT_4K},

  {"W25P80",         0xef2014, 0x0,       64 * 1024,    16, RD_NORM,                         0},

  {"W25P16",         0xef2015, 0x0,       64 * 1024,    32, RD_NORM,                         0},

  {"W25P32",         0xef2016, 0x0,       64 * 1024,    64, RD_NORM,                         0},

  {"W25X40",         0xef3013, 0x0,       64 * 1024,     8, RD_NORM,                   SECT_4K},

  {"W25X16",         0xef3015, 0x0,       64 * 1024,    32, RD_NORM,                   SECT_4K},

  {"W25X32",         0xef3016, 0x0,       64 * 1024,    64, RD_NORM,                   SECT_4K},

  {"W25X64",         0xef3017, 0x0,       64 * 1024,   128, RD_NORM,                   SECT_4K},
  {"W25Q80BL",       0xef4014, 0x0,       64 * 1024,    16, RD_FULL,          WR_QPP | SECT_4K},
  {"W25Q16CL",       0xef4015, 0x0,       64 * 1024,    32, RD_FULL,          WR_QPP | SECT_4K},
  {"W25Q32BV",       0xef4016, 0x0,       64 * 1024,    64, RD_FULL,          WR_QPP | SECT_4K},

diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 2636426..7cde4c0 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -24,6 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; /* Read commands array */ static u8 spi_read_cmds_array[] = { CMD_READ_ARRAY_SLOW,

  CMD_READ_ARRAY_FAST,
  CMD_READ_DUAL_OUTPUT_FAST,
  CMD_READ_DUAL_IO_FAST,
  CMD_READ_QUAD_OUTPUT_FAST,

-- 1.9.1

Tested-by: Bin Meng bmeng.cn@gmail.com

Regards, Bin

Jagannadha Sutradharudu Teki

9 Dec 9 Dec

4:29 p.m.

New subject: [U-Boot] [PATCH 2/4] spi: Fix flag collision for SST_WP

From: Simon Glass sjg@chromium.org

At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix this so that the table in sf_params.c can be used correctly.

Reported-by: Jens Rottmann Jens.Rottmann@adlinktech.com Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com --- drivers/mtd/spi/sf_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index e159f04..7218e69 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -41,6 +41,7 @@ enum { SECT_32K = 1 << 1, E_FSR = 1 << 2, WR_QPP = 1 << 3, + SST_WP = 1 << 4, };

#define SPI_FLASH_3B_ADDR_LEN 3 @@ -104,7 +105,6 @@ enum {

/* SST specific */ #ifdef CONFIG_SPI_FLASH_SST -# define SST_WP 0x01 /* Supports AAI word program */ # define CMD_SST_BP 0x02 /* Byte Program */ # define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */

-- 1.9.1

Jagannadha Sutradharudu Teki

4:29 p.m.

New subject: [U-Boot] [PATCH 3/4] spi: sf: Support byte program for sst spi flash

From: Bin Meng bmeng.cn@gmail.com

Currently if SST flash advertises SST_WP flag in the params table the word program command (ADh) with auto address increment will be used for the flash write op. However some SPI controllers do not support the word program command (like the Intel ICH 7), the byte programm command (02h) has to be used.

A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI controller to use byte program op for SST flash.

Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org Tested-by: Simon Glass sjg@chromium.org --- drivers/mtd/spi/sf_internal.h | 2 ++ drivers/mtd/spi/sf_ops.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 7218e69..fb53cb0 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -110,6 +110,8 @@ enum {

int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf); +int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, + const void *buf); #endif

/** diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 759231f..34bc54e 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -517,4 +517,35 @@ int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, spi_release_bus(flash->spi); return ret; } + +int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, + const void *buf) +{ + size_t actual; + int ret; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: Unable to claim SPI bus\n"); + return ret; + } + + for (actual = 0; actual < len; actual++) { + ret = sst_byte_write(flash, offset, buf + actual); + if (ret) { + debug("SF: sst byte program failed\n"); + break; + } + offset++; + } + + if (!ret) + ret = spi_flash_cmd_write_disable(flash); + + debug("SF: sst: program %s %zu bytes @ 0x%zx\n", + ret ? "failure" : "success", len, offset - actual); + + spi_release_bus(flash->spi); + return ret; +} #endif

-- 1.9.1

Bin Meng

10 Dec 10 Dec

9:10 a.m.

New subject: [U-Boot] [PATCH 3/4] spi: sf: Support byte program for sst spi flash

Hi Jagan,

On Tue, Dec 9, 2014 at 11:29 PM, Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com wrote:

...

From: Bin Meng bmeng.cn@gmail.com

Currently if SST flash advertises SST_WP flag in the params table the word program command (ADh) with auto address increment will be used for the flash write op. However some SPI controllers do not support the word program command (like the Intel ICH 7), the byte programm command (02h) has to be used.

A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI controller to use byte program op for SST flash.

This paragraph should be removed from the commit message. The SPI_OPM_TX_BP was introduced in my original patch, but not in this new patch. You may need move this commit message to your patch#4 as SPI_OPM_TX_BP is moved to there.

...

Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org Tested-by: Simon Glass sjg@chromium.org

drivers/mtd/spi/sf_internal.h | 2 ++ drivers/mtd/spi/sf_ops.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 7218e69..fb53cb0 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -110,6 +110,8 @@ enum {

int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf); +int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
          const void *buf);
#endif

/** diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 759231f..34bc54e 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -517,4 +517,35 @@ int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, spi_release_bus(flash->spi); return ret; }

+int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
          const void *buf)
+{
  size_t actual;
  int ret;
  ret = spi_claim_bus(flash->spi);
  if (ret) {
          debug("SF: Unable to claim SPI bus\n");
          return ret;
  }
  for (actual = 0; actual < len; actual++) {
          ret = sst_byte_write(flash, offset, buf + actual);
          if (ret) {
                  debug("SF: sst byte program failed\n");
                  break;
          }
          offset++;
  }
  if (!ret)
          ret = spi_flash_cmd_write_disable(flash);
  debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
        ret ? "failure" : "success", len, offset - actual);
  spi_release_bus(flash->spi);
  return ret;
+}

#endif

1.9.1

Regards, Bin

Jagan Teki

11:02 a.m.

New subject: [U-Boot] [PATCH 3/4] spi: sf: Support byte program for sst spi flash

On 10 December 2014 at 13:40, Bin Meng bmeng.cn@gmail.com wrote:

...

Hi Jagan,

On Tue, Dec 9, 2014 at 11:29 PM, Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com wrote:

...
From: Bin Meng bmeng.cn@gmail.com

Currently if SST flash advertises SST_WP flag in the params table the word program command (ADh) with auto address increment will be used for the flash write op. However some SPI controllers do not support the word program command (like the Intel ICH 7), the byte programm command (02h) has to be used.

A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI controller to use byte program op for SST flash.

This paragraph should be removed from the commit message. The SPI_OPM_TX_BP was introduced in my original patch, but not in this new patch. You may need move this commit message to your patch#4 as SPI_OPM_TX_BP is moved to there.

Ok, Will update the same.

Please send the rest of the patches, will test my whole system again. Do the same from your side too.

...

...
Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org Tested-by: Simon Glass sjg@chromium.org

drivers/mtd/spi/sf_internal.h | 2 ++ drivers/mtd/spi/sf_ops.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 7218e69..fb53cb0 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -110,6 +110,8 @@ enum {

int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf); +int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
          const void *buf);
#endif

/** diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 759231f..34bc54e 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -517,4 +517,35 @@ int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, spi_release_bus(flash->spi); return ret; }

+int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
          const void *buf)
+{
  size_t actual;
  int ret;
  ret = spi_claim_bus(flash->spi);
  if (ret) {
          debug("SF: Unable to claim SPI bus\n");
          return ret;
  }
  for (actual = 0; actual < len; actual++) {
          ret = sst_byte_write(flash, offset, buf + actual);
          if (ret) {
                  debug("SF: sst byte program failed\n");
                  break;
          }
          offset++;
  }
  if (!ret)
          ret = spi_flash_cmd_write_disable(flash);
  debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
        ret ? "failure" : "success", len, offset - actual);
  spi_release_bus(flash->spi);
  return ret;
+}

#endif

1.9.1

thanks!

-- Jagan.

Bin Meng

11:18 a.m.

New subject: [U-Boot] [PATCH 3/4] spi: sf: Support byte program for sst spi flash

Hi Jagan,

On Wed, Dec 10, 2014 at 6:02 PM, Jagan Teki jagannadh.teki@gmail.com wrote:

...

On 10 December 2014 at 13:40, Bin Meng bmeng.cn@gmail.com wrote:

...
Hi Jagan,

On Tue, Dec 9, 2014 at 11:29 PM, Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com wrote:

...
From: Bin Meng bmeng.cn@gmail.com

Currently if SST flash advertises SST_WP flag in the params table the word program command (ADh) with auto address increment will be used for the flash write op. However some SPI controllers do not support the word program command (like the Intel ICH 7), the byte programm command (02h) has to be used.

A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI controller to use byte program op for SST flash.

This paragraph should be removed from the commit message. The SPI_OPM_TX_BP was introduced in my original patch, but not in this new patch. You may need move this commit message to your patch#4 as SPI_OPM_TX_BP is moved to there.

Ok, Will update the same.

Please send the rest of the patches, will test my whole system again. Do the same from your side too.

Sure, will rebase on yours and send the rest of my patches soon.

[snip]

Regards, Bin

Jagannadha Sutradharudu Teki

9 Dec 9 Dec

4:29 p.m.

New subject: [U-Boot] [PATCH 4/4] sf: Enable byte program support

Enabled byte program support for sst flashes in sf.

Few controllers will only support BP, so this patch gives a rx transfer flag to set the BP so-that sf will operate on byte program transfer.

Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com --- drivers/mtd/spi/sf_internal.h | 5 ++++- drivers/mtd/spi/sf_params.c | 18 +++++++++--------- drivers/mtd/spi/sf_probe.c | 8 ++++++-- include/spi.h | 1 + 4 files changed, 20 insertions(+), 12 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index fb53cb0..785f7a9 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -40,10 +40,13 @@ enum { SECT_4K = 1 << 0, SECT_32K = 1 << 1, E_FSR = 1 << 2, - WR_QPP = 1 << 3, + SST_BP = 1 << 3, SST_WP = 1 << 4, + WR_QPP = 1 << 5, };

+#define SST_WR (SST_BP | SST_WP) + #define SPI_FLASH_3B_ADDR_LEN 3 #define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) #define SPI_FLASH_16MB_BOUN 0x1000000 diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 0f1f837..30875b3 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -89,16 +89,16 @@ const struct spi_flash_params spi_flash_params_table[] = { {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, #endif #ifdef CONFIG_SPI_FLASH_SST /* SST */ - {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WP}, - {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WP}, - {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K | SST_WP}, - {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K | SST_WP}, + {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR}, + {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR}, + {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K | SST_WR}, + {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K | SST_WR}, {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, - {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, RD_NORM, SECT_4K | SST_WP}, - {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM, SECT_4K | SST_WP}, - {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K | SST_WP}, - {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WP}, - {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WP}, + {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, RD_NORM, SECT_4K | SST_WR}, + {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM, SECT_4K | SST_WR}, + {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K | SST_WR}, + {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR}, + {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR}, #endif #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, RD_NORM, 0}, diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 7cde4c0..ce9987f 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -136,8 +136,12 @@ static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode, #ifndef CONFIG_DM_SPI_FLASH flash->write = spi_flash_cmd_write_ops; #if defined(CONFIG_SPI_FLASH_SST) - if (params->flags & SST_WP) - flash->write = sst_write_wp; + if (params->flags & SST_WR) { + if (flash->spi->op_mode_tx & SPI_OPM_TX_BP) + flash->write = sst_write_bp; + else + flash->write = sst_write_wp; + } #endif flash->erase = spi_flash_cmd_erase_ops; flash->read = spi_flash_cmd_read_ops; diff --git a/include/spi.h b/include/spi.h index 5b78271..ec17bd0 100644 --- a/include/spi.h +++ b/include/spi.h @@ -34,6 +34,7 @@

/* SPI TX operation modes */ #define SPI_OPM_TX_QPP (1 << 0) +#define SPI_OPM_TX_BP (1 << 1)

/* SPI RX operation modes */ #define SPI_OPM_RX_AS (1 << 0)

-- 1.9.1

Bin Meng

10 Dec 10 Dec

9:13 a.m.

New subject: [U-Boot] [PATCH 4/4] sf: Enable byte program support

Hi Jagan,

On Tue, Dec 9, 2014 at 11:29 PM, Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com wrote:

...

Enabled byte program support for sst flashes in sf.

Few controllers will only support BP, so this patch gives a rx transfer flag to set the BP so-that sf

Actually it is a tx transfer flag.

...

will operate on byte program transfer.

Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com

drivers/mtd/spi/sf_internal.h | 5 ++++- drivers/mtd/spi/sf_params.c | 18 +++++++++--------- drivers/mtd/spi/sf_probe.c | 8 ++++++-- include/spi.h | 1 + 4 files changed, 20 insertions(+), 12 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index fb53cb0..785f7a9 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -40,10 +40,13 @@ enum { SECT_4K = 1 << 0, SECT_32K = 1 << 1, E_FSR = 1 << 2,
  WR_QPP          = 1 << 3,
  SST_BP          = 1 << 3,
  SST_WP          = 1 << 4,
  WR_QPP          = 1 << 5,
};

+#define SST_WR (SST_BP | SST_WP)

#define SPI_FLASH_3B_ADDR_LEN 3 #define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) #define SPI_FLASH_16MB_BOUN 0x1000000 diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 0f1f837..30875b3 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -89,16 +89,16 @@ const struct spi_flash_params spi_flash_params_table[] = { {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, #endif #ifdef CONFIG_SPI_FLASH_SST /* SST */
  {"SST25VF040B",    0xbf258d, 0x0,       64 * 1024,     8, RD_NORM,          SECT_4K | SST_WP},
  {"SST25VF080B",    0xbf258e, 0x0,       64 * 1024,    16, RD_NORM,          SECT_4K | SST_WP},
  {"SST25VF016B",    0xbf2541, 0x0,       64 * 1024,    32, RD_NORM,          SECT_4K | SST_WP},
  {"SST25VF032B",    0xbf254a, 0x0,       64 * 1024,    64, RD_NORM,          SECT_4K | SST_WP},
  {"SST25VF040B",    0xbf258d, 0x0,       64 * 1024,     8, RD_NORM,          SECT_4K | SST_WR},
  {"SST25VF080B",    0xbf258e, 0x0,       64 * 1024,    16, RD_NORM,          SECT_4K | SST_WR},
  {"SST25VF016B",    0xbf2541, 0x0,       64 * 1024,    32, RD_NORM,          SECT_4K | SST_WR},
  {"SST25VF032B",    0xbf254a, 0x0,       64 * 1024,    64, RD_NORM,          SECT_4K | SST_WR},
  {"SST25VF064C",    0xbf254b, 0x0,       64 * 1024,   128, RD_NORM,                   SECT_4K},
  {"SST25WF512",     0xbf2501, 0x0,       64 * 1024,     1, RD_NORM,          SECT_4K | SST_WP},
  {"SST25WF010",     0xbf2502, 0x0,       64 * 1024,     2, RD_NORM,          SECT_4K | SST_WP},
  {"SST25WF020",     0xbf2503, 0x0,       64 * 1024,     4, RD_NORM,          SECT_4K | SST_WP},
  {"SST25WF040",     0xbf2504, 0x0,       64 * 1024,     8, RD_NORM,          SECT_4K | SST_WP},
  {"SST25WF080",     0xbf2505, 0x0,       64 * 1024,    16, RD_NORM,          SECT_4K | SST_WP},
  {"SST25WF512",     0xbf2501, 0x0,       64 * 1024,     1, RD_NORM,          SECT_4K | SST_WR},
  {"SST25WF010",     0xbf2502, 0x0,       64 * 1024,     2, RD_NORM,          SECT_4K | SST_WR},
  {"SST25WF020",     0xbf2503, 0x0,       64 * 1024,     4, RD_NORM,          SECT_4K | SST_WR},
  {"SST25WF040",     0xbf2504, 0x0,       64 * 1024,     8, RD_NORM,          SECT_4K | SST_WR},
  {"SST25WF080",     0xbf2505, 0x0,       64 * 1024,    16, RD_NORM,          SECT_4K | SST_WR},
#endif #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, RD_NORM, 0}, diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 7cde4c0..ce9987f 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -136,8 +136,12 @@ static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode, #ifndef CONFIG_DM_SPI_FLASH flash->write = spi_flash_cmd_write_ops; #if defined(CONFIG_SPI_FLASH_SST)
  if (params->flags & SST_WP)
          flash->write = sst_write_wp;
  if (params->flags & SST_WR) {
          if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
                  flash->write = sst_write_bp;
          else
                  flash->write = sst_write_wp;
  }
#endif flash->erase = spi_flash_cmd_erase_ops; flash->read = spi_flash_cmd_read_ops; diff --git a/include/spi.h b/include/spi.h index 5b78271..ec17bd0 100644 --- a/include/spi.h +++ b/include/spi.h @@ -34,6 +34,7 @@

/* SPI TX operation modes */ #define SPI_OPM_TX_QPP (1 << 0) +#define SPI_OPM_TX_BP (1 << 1)

/* SPI RX operation modes */

#define SPI_OPM_RX_AS (1 << 0)

1.9.1

Tested-by: Bin Meng bmeng.cn@gmail.com

Regards, Bin

Jagan Teki

9 Dec 9 Dec

4:32 p.m.

Hi Bin,

On 9 December 2014 at 20:59, Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com wrote:

...

This patch-set added byte program support for sst flashes and some implementation changes in sf to support array slow and byte program specific controllers.

Bin Meng (1): spi: sf: Support byte program for sst spi flash

Jagannadha Sutradharudu Teki (2): sf: Fix look for the fastest read command sf: Enable byte program support

Simon Glass (1): spi: Fix flag collision for SST_WP

Please re-base your previous patch-set on top of this series and send the same.

...

drivers/mtd/spi/sf_internal.h | 22 ++++++--- drivers/mtd/spi/sf_ops.c | 31 +++++++++++++ drivers/mtd/spi/sf_params.c | 102 +++++++++++++++++++++--------------------- drivers/mtd/spi/sf_probe.c | 9 +++- include/spi.h | 1 + 5 files changed, 105 insertions(+), 60 deletions(-)

-- 1.9.1

thanks!

-- Jagan.

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Bin Meng
Jagan Teki
Jagannadha Sutradharudu Teki