[U-Boot] [PATCH 00/20] ARM: uniphier: various refactoring for v2017.11-rc2
- Reactor of GPIO, clk, reset drivers. - Clean up SOC code - Sync DT - Use more clock drivers - Split U-Boot specific DT property
Masahiro Yamada (20): ARM: uniphier: switch to CONFIG_ENV_IS_NOWHERE gpio: uniphier: rework single device node model ARM: dts: uniphier: update GPIO nodes pinctrl: uniphier: set PUPD_SIMPLE cap flag for PXs3 pinctrl: uniphier: simplify input enable and delete pin arrays ARM: uniphier: use pr_() instead of printf() where appropriate usb: dwc3-uniphier: replace <common.h> with <linux/bitops.h> i2c: uniphier: replace debug() with dev_dbg() i2c: uniphier-f: replace debug() with dev_dbg() clk: uniphier: rework for better clock tree structure clk: uniphier: add PXs3 clock data clk: uniphier: add peripheral clock data reset: uniphier: fix the first argument passed to dev_err() i2c: uniphier: use clk for enable and get_rate i2c: uniphier-f: use clk for enable and get_rate ARM: uniphier: split u-boot,dm-pre-reloc out to uniphier-v7-u-boot.dtsi ARM: dts: uniphier: prepare to use clock for serial serial: uniphier: use clk for enable and get_rate ARM: dts: uniphier: sync DT with Linux 4.14-rc4 ARM: uniphier: change the default of SoC select to UNIPHIER_V7_MULTI
arch/arm/dts/uniphier-ld11.dtsi | 38 ++- arch/arm/dts/uniphier-ld20.dtsi | 97 ++++++- arch/arm/dts/uniphier-ld4-ref.dts | 9 +- arch/arm/dts/uniphier-ld4.dtsi | 122 +-------- arch/arm/dts/uniphier-ld6b-ref.dts | 9 +- arch/arm/dts/uniphier-pinctrl.dtsi | 15 ++ arch/arm/dts/uniphier-pro4-ace.dts | 9 - arch/arm/dts/uniphier-pro4-ref.dts | 9 - arch/arm/dts/uniphier-pro4-sanji.dts | 21 -- arch/arm/dts/uniphier-pro4.dtsi | 214 +--------------- arch/arm/dts/uniphier-pro5-4kbox.dts | 9 - arch/arm/dts/uniphier-pro5.dtsi | 214 +--------------- arch/arm/dts/uniphier-pxs2-gentil.dts | 21 -- arch/arm/dts/uniphier-pxs2-vodka.dts | 21 -- arch/arm/dts/uniphier-pxs2.dtsi | 256 ++++--------------- arch/arm/dts/uniphier-pxs3.dtsi | 7 +- arch/arm/dts/uniphier-sld8-ref.dts | 9 +- arch/arm/dts/uniphier-sld8.dtsi | 126 +--------- arch/arm/dts/uniphier-v7-u-boot.dtsi | 69 +++++ arch/arm/dts/uniphier-v8-u-boot.dtsi | 13 + arch/arm/mach-uniphier/Kconfig | 5 +- arch/arm/mach-uniphier/arm32/psci.c | 4 +- arch/arm/mach-uniphier/board_late_init.c | 4 +- arch/arm/mach-uniphier/boot-device/boot-device.c | 1 + arch/arm/mach-uniphier/cpu-info.c | 7 +- arch/arm/mach-uniphier/dram/cmd_ddrmphy.c | 4 +- arch/arm/mach-uniphier/dram/cmd_ddrphy.c | 4 +- arch/arm/mach-uniphier/dram/ddrphy-ld4.c | 5 +- arch/arm/mach-uniphier/dram/umc-pxs2.c | 18 +- arch/arm/mach-uniphier/dram_init.c | 7 +- drivers/clk/uniphier/Makefile | 2 + drivers/clk/uniphier/clk-uniphier-core.c | 308 +++++++++++++++++------ drivers/clk/uniphier/clk-uniphier-mio.c | 118 ++++----- drivers/clk/uniphier/clk-uniphier-peri.c | 113 +++++++++ drivers/clk/uniphier/clk-uniphier-sys.c | 52 ++-- drivers/clk/uniphier/clk-uniphier.h | 85 ++++--- drivers/gpio/gpio-uniphier.c | 140 +++++++---- drivers/i2c/i2c-uniphier-f.c | 131 +++++----- drivers/i2c/i2c-uniphier.c | 82 +++--- drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 17 +- drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c | 16 -- drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c | 5 - drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c | 15 -- drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c | 9 - drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c | 3 +- drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c | 30 --- drivers/reset/reset-uniphier.c | 3 +- drivers/serial/serial_uniphier.c | 16 +- drivers/usb/dwc3/dwc3-uniphier.c | 2 +- env/Kconfig | 1 - 50 files changed, 1082 insertions(+), 1413 deletions(-) create mode 100644 arch/arm/dts/uniphier-v7-u-boot.dtsi create mode 100644 arch/arm/dts/uniphier-v8-u-boot.dtsi create mode 100644 drivers/clk/uniphier/clk-uniphier-peri.c
The non-volatile storage varies board by board. The default should be NOWHERE. Please choose a proper device via Kconfig.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
env/Kconfig | 1 - 1 file changed, 1 deletion(-)
diff --git a/env/Kconfig b/env/Kconfig index 024d4d7..20516a5 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -3,7 +3,6 @@ menu "Environment" choice prompt "Select the location of the environment" default ENV_IS_IN_MMC if ARCH_SUNXI - default ENV_IS_IN_MMC if ARCH_UNIPHIER default ENV_IS_IN_MMC if ARCH_EXYNOS4 default ENV_IS_IN_MMC if MX6SX || MX7D default ENV_IS_IN_MMC if TEGRA30 || TEGRA124
First, I implemented this driver as per-bank model, but it was a design mistake.
- There are 31 banks in the maximum case. It is painful to add so many nodes to DT.
- The IRQ control registers are shared between banks. Per-bank design is a problem for Linux. The counterpart for Linux turned around to the single node model.
Rework based on the driver for Linux.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
drivers/gpio/gpio-uniphier.c | 140 +++++++++++++++++++++++++++---------------- 1 file changed, 89 insertions(+), 51 deletions(-)
diff --git a/drivers/gpio/gpio-uniphier.c b/drivers/gpio/gpio-uniphier.c index c11e953..107c3fc 100644 --- a/drivers/gpio/gpio-uniphier.c +++ b/drivers/gpio/gpio-uniphier.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Socionext Inc. + * Copyright (C) 2016-2017 Socionext Inc. * Author: Masahiro Yamada yamada.masahiro@socionext.com * * SPDX-License-Identifier: GPL-2.0+ @@ -11,73 +11,123 @@ #include <linux/io.h> #include <linux/sizes.h> #include <linux/errno.h> +#include <asm/global_data.h> #include <asm/gpio.h>
-#define UNIPHIER_GPIO_PORTS_PER_BANK 8 +#define UNIPHIER_GPIO_LINES_PER_BANK 8
-#define UNIPHIER_GPIO_REG_DATA 0 /* data */ -#define UNIPHIER_GPIO_REG_DIR 4 /* direction (1:in, 0:out) */ +#define UNIPHIER_GPIO_PORT_DATA 0x0 /* data */ +#define UNIPHIER_GPIO_PORT_DIR 0x4 /* direction (1:in, 0:out) */ +#define UNIPHIER_GPIO_IRQ_EN 0x90 /* irq enable */
struct uniphier_gpio_priv { - void __iomem *base; - char bank_name[16]; + void __iomem *regs; };
-static void uniphier_gpio_offset_write(struct udevice *dev, unsigned offset, - unsigned reg, int value) +static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank) +{ + unsigned int reg; + + reg = (bank + 1) * 8; + + /* + * Unfortunately, the GPIO port registers are not contiguous because + * offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region. + */ + if (reg >= UNIPHIER_GPIO_IRQ_EN) + reg += 0x10; + + return reg; +} + +static void uniphier_gpio_get_bank_and_mask(unsigned int offset, + unsigned int *bank, u32 *mask) +{ + *bank = offset / UNIPHIER_GPIO_LINES_PER_BANK; + *mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK); +} + +static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv, + unsigned int reg, u32 mask, u32 val) { - struct uniphier_gpio_priv *priv = dev_get_priv(dev); u32 tmp;
- tmp = readl(priv->base + reg); - if (value) - tmp |= BIT(offset); - else - tmp &= ~BIT(offset); - writel(tmp, priv->base + reg); + tmp = readl(priv->regs + reg); + tmp &= ~mask; + tmp |= mask & val; + writel(tmp, priv->regs + reg); }
-static int uniphier_gpio_offset_read(struct udevice *dev, unsigned offset, - unsigned reg) +static void uniphier_gpio_bank_write(struct udevice *dev, unsigned int bank, + unsigned int reg, u32 mask, u32 val) { struct uniphier_gpio_priv *priv = dev_get_priv(dev);
- return !!(readl(priv->base + reg) & BIT(offset)); + if (!mask) + return; + + uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg, + mask, val); }
-static int uniphier_gpio_direction_input(struct udevice *dev, unsigned offset) +static void uniphier_gpio_offset_write(struct udevice *dev, unsigned int offset, + unsigned int reg, int val) { - uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DIR, 1); + unsigned int bank; + u32 mask;
- return 0; + uniphier_gpio_get_bank_and_mask(offset, &bank, &mask); + + uniphier_gpio_bank_write(dev, bank, reg, mask, val ? mask : 0); }
-static int uniphier_gpio_direction_output(struct udevice *dev, unsigned offset, - int value) +static int uniphier_gpio_offset_read(struct udevice *dev, + unsigned int offset, unsigned int reg) { - uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DATA, value); - uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DIR, 0); + struct uniphier_gpio_priv *priv = dev_get_priv(dev); + unsigned int bank, reg_offset; + u32 mask;
- return 0; + uniphier_gpio_get_bank_and_mask(offset, &bank, &mask); + reg_offset = uniphier_gpio_bank_to_reg(bank) + reg; + + return !!(readl(priv->regs + reg_offset) & mask); }
-static int uniphier_gpio_get_value(struct udevice *dev, unsigned offset) +static int uniphier_gpio_get_function(struct udevice *dev, unsigned int offset) { - return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_REG_DATA); + return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DIR) ? + GPIOF_INPUT : GPIOF_OUTPUT; }
-static int uniphier_gpio_set_value(struct udevice *dev, unsigned offset, - int value) +static int uniphier_gpio_direction_input(struct udevice *dev, + unsigned int offset) { - uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DATA, value); + uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 1);
return 0; }
-static int uniphier_gpio_get_function(struct udevice *dev, unsigned offset) +static int uniphier_gpio_direction_output(struct udevice *dev, + unsigned int offset, int value) { - return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_REG_DIR) ? - GPIOF_INPUT : GPIOF_OUTPUT; + uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value); + uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 0); + + return 0; +} + +static int uniphier_gpio_get_value(struct udevice *dev, unsigned int offset) +{ + return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DATA); +} + +static int uniphier_gpio_set_value(struct udevice *dev, + unsigned int offset, int value) +{ + uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value); + + return 0; }
static const struct dm_gpio_ops uniphier_gpio_ops = { @@ -93,40 +143,28 @@ static int uniphier_gpio_probe(struct udevice *dev) struct uniphier_gpio_priv *priv = dev_get_priv(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); fdt_addr_t addr; - unsigned int tmp;
addr = devfdt_get_addr(dev); if (addr == FDT_ADDR_T_NONE) return -EINVAL;
- priv->base = devm_ioremap(dev, addr, SZ_8); - if (!priv->base) + priv->regs = devm_ioremap(dev, addr, SZ_512); + if (!priv->regs) return -ENOMEM;
- uc_priv->gpio_count = UNIPHIER_GPIO_PORTS_PER_BANK; - - tmp = (addr & 0xfff); - - /* Unfortunately, there is a register hole at offset 0x90-0x9f. */ - if (tmp > 0x90) - tmp -= 0x10; - - snprintf(priv->bank_name, sizeof(priv->bank_name) - 1, - "port%d-", (tmp - 8) / 8); - - uc_priv->bank_name = priv->bank_name; + uc_priv->gpio_count = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), + "ngpios", 0);
return 0; }
-/* .data = the number of GPIO banks */ static const struct udevice_id uniphier_gpio_match[] = { { .compatible = "socionext,uniphier-gpio" }, { /* sentinel */ } };
U_BOOT_DRIVER(uniphier_gpio) = { - .name = "uniphier_gpio", + .name = "uniphier-gpio", .id = UCLASS_GPIO, .of_match = uniphier_gpio_match, .probe = uniphier_gpio_probe,
Switch to the single node design.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/dts/uniphier-ld11.dtsi | 23 +++++ arch/arm/dts/uniphier-ld4.dtsi | 115 ++-------------------- arch/arm/dts/uniphier-pro4.dtsi | 206 ++-------------------------------------- arch/arm/dts/uniphier-pro5.dtsi | 206 ++-------------------------------------- arch/arm/dts/uniphier-pxs2.dtsi | 201 ++------------------------------------- arch/arm/dts/uniphier-pxs3.dtsi | 3 +- arch/arm/dts/uniphier-sld8.dtsi | 119 +++-------------------- 7 files changed, 71 insertions(+), 802 deletions(-)
diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi index 0f172c3..0cc6fd7 100644 --- a/arch/arm/dts/uniphier-ld11.dtsi +++ b/arch/arm/dts/uniphier-ld11.dtsi @@ -154,6 +154,29 @@ clock-frequency = <58820000>; };
+ gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>, + <&pinctrl 43 0 0>, + <&pinctrl 51 0 0>, + <&pinctrl 96 0 0>, + <&pinctrl 160 0 0>, + <&pinctrl 184 0 0>; + gpio-ranges-group-names = "gpio_range0", + "gpio_range1", + "gpio_range2", + "gpio_range3", + "gpio_range4", + "gpio_range5"; + ngpios = <200>; + }; + i2c0: i2c@58780000 { compatible = "socionext,uniphier-fi2c"; status = "disabled"; diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi index a3bcf22..b816038 100644 --- a/arch/arm/dts/uniphier-ld4.dtsi +++ b/arch/arm/dts/uniphier-ld4.dtsi @@ -108,116 +108,17 @@ clock-frequency = <36864000>; };
- port0x: gpio@55000008 { + gpio: gpio@55000000 { compatible = "socionext,uniphier-gpio"; - reg = <0x55000008 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port1x: gpio@55000010 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000010 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port2x: gpio@55000018 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000018 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port3x: gpio@55000020 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000020 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port4: gpio@55000028 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000028 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port5x: gpio@55000030 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000030 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port6x: gpio@55000038 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000038 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port7x: gpio@55000040 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000040 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port8x: gpio@55000048 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000048 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port9x: gpio@55000050 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000050 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port10x: gpio@55000058 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000058 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port11x: gpio@55000060 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000060 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port12x: gpio@55000068 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000068 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port13x: gpio@55000070 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000070 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port14x: gpio@55000078 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000078 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port16x: gpio@55000088 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000088 0x8>; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>; + gpio-ranges-group-names = "gpio_range"; + ngpios = <136>; };
i2c0: i2c@58400000 { diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi index b45f23c..5f39972 100644 --- a/arch/arm/dts/uniphier-pro4.dtsi +++ b/arch/arm/dts/uniphier-pro4.dtsi @@ -116,207 +116,17 @@ clock-frequency = <73728000>; };
- port0x: gpio@55000008 { + gpio: gpio@55000000 { compatible = "socionext,uniphier-gpio"; - reg = <0x55000008 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port1x: gpio@55000010 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000010 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port2x: gpio@55000018 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000018 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port3x: gpio@55000020 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000020 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port4: gpio@55000028 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000028 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port5x: gpio@55000030 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000030 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port6x: gpio@55000038 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000038 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port7x: gpio@55000040 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000040 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port8x: gpio@55000048 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000048 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port9x: gpio@55000050 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000050 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port10x: gpio@55000058 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000058 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port11x: gpio@55000060 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000060 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port12x: gpio@55000068 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000068 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port13x: gpio@55000070 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000070 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port14x: gpio@55000078 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000078 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port17x: gpio@550000a0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000a0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port18x: gpio@550000a8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000a8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port19x: gpio@550000b0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000b0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port20x: gpio@550000b8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000b8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port21x: gpio@550000c0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000c0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port22x: gpio@550000c8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000c8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port23x: gpio@550000d0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000d0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port24x: gpio@550000d8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000d8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port25x: gpio@550000e0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000e0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port26x: gpio@550000e8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000e8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port27x: gpio@550000f0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000f0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port28x: gpio@550000f8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000f8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port29x: gpio@55000100 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000100 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port30x: gpio@55000108 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000108 0x8>; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>; + gpio-ranges-group-names = "gpio_range"; + ngpios = <248>; };
i2c0: i2c@58780000 { diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi index 94eb656..950b02c 100644 --- a/arch/arm/dts/uniphier-pro5.dtsi +++ b/arch/arm/dts/uniphier-pro5.dtsi @@ -203,207 +203,17 @@ clock-frequency = <73728000>; };
- port0x: gpio@55000008 { + gpio: gpio@55000000 { compatible = "socionext,uniphier-gpio"; - reg = <0x55000008 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port1x: gpio@55000010 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000010 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port2x: gpio@55000018 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000018 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port3x: gpio@55000020 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000020 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port4: gpio@55000028 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000028 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port5x: gpio@55000030 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000030 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port6x: gpio@55000038 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000038 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port7x: gpio@55000040 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000040 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port8x: gpio@55000048 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000048 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port9x: gpio@55000050 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000050 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port10x: gpio@55000058 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000058 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port11x: gpio@55000060 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000060 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port12x: gpio@55000068 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000068 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port13x: gpio@55000070 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000070 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port14x: gpio@55000078 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000078 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port17x: gpio@550000a0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000a0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port18x: gpio@550000a8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000a8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port19x: gpio@550000b0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000b0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port20x: gpio@550000b8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000b8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port21x: gpio@550000c0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000c0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port22x: gpio@550000c8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000c8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port23x: gpio@550000d0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000d0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port24x: gpio@550000d8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000d8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port25x: gpio@550000e0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000e0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port26x: gpio@550000e8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000e8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port27x: gpio@550000f0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000f0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port28x: gpio@550000f8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000f8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port29x: gpio@55000100 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000100 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port30x: gpio@55000108 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000108 0x8>; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>; + gpio-ranges-group-names = "gpio_range"; + ngpios = <248>; };
i2c0: i2c@58780000 { diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi index c304d90..ac84d15 100644 --- a/arch/arm/dts/uniphier-pxs2.dtsi +++ b/arch/arm/dts/uniphier-pxs2.dtsi @@ -178,200 +178,19 @@ clock-frequency = <88900000>; };
- port0x: gpio@55000008 { + gpio: gpio@55000000 { compatible = "socionext,uniphier-gpio"; - reg = <0x55000008 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port1x: gpio@55000010 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000010 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port2x: gpio@55000018 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000018 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port3x: gpio@55000020 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000020 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port4: gpio@55000028 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000028 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port5x: gpio@55000030 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000030 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port6x: gpio@55000038 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000038 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port7x: gpio@55000040 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000040 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port8x: gpio@55000048 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000048 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port9x: gpio@55000050 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000050 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port10x: gpio@55000058 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000058 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port12x: gpio@55000068 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000068 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port13x: gpio@55000070 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000070 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port14x: gpio@55000078 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000078 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port15x: gpio@55000080 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000080 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port16x: gpio@55000088 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000088 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port17x: gpio@550000a0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000a0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port18x: gpio@550000a8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000a8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port19x: gpio@550000b0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000b0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port20x: gpio@550000b8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000b8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port21x: gpio@550000c0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000c0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port22x: gpio@550000c8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000c8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port23x: gpio@550000d0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000d0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port24x: gpio@550000d8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000d8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port25x: gpio@550000e0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000e0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port26x: gpio@550000e8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000e8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port27x: gpio@550000f0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000f0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port28x: gpio@550000f8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000f8 0x8>; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>, + <&pinctrl 96 0 0>; + gpio-ranges-group-names = "gpio_range0", + "gpio_range1"; + ngpios = <232>; };
i2c0: i2c@58780000 { diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi index 8944005..a004bd1 100644 --- a/arch/arm/dts/uniphier-pxs3.dtsi +++ b/arch/arm/dts/uniphier-pxs3.dtsi @@ -183,7 +183,7 @@ };
gpio: gpio@55000000 { - compatible = "socionext,uniphier-pxs3-gpio"; + compatible = "socionext,uniphier-gpio"; reg = <0x55000000 0x200>; interrupt-parent = <&aidet>; interrupt-controller; @@ -196,6 +196,7 @@ gpio-ranges-group-names = "gpio_range0", "gpio_range1", "gpio_range2"; + ngpios = <286>; };
i2c0: i2c@58780000 { diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi index a3de26b..70a5ea4 100644 --- a/arch/arm/dts/uniphier-sld8.dtsi +++ b/arch/arm/dts/uniphier-sld8.dtsi @@ -108,116 +108,21 @@ clock-frequency = <80000000>; };
- port0x: gpio@55000008 { + gpio: gpio@55000000 { compatible = "socionext,uniphier-gpio"; - reg = <0x55000008 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port1x: gpio@55000010 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000010 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port2x: gpio@55000018 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000018 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port3x: gpio@55000020 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000020 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port4: gpio@55000028 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000028 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port5x: gpio@55000030 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000030 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port6x: gpio@55000038 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000038 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port7x: gpio@55000040 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000040 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port8x: gpio@55000048 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000048 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port9x: gpio@55000050 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000050 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port10x: gpio@55000058 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000058 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port11x: gpio@55000060 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000060 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port12x: gpio@55000068 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000068 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port13x: gpio@55000070 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000070 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port14x: gpio@55000078 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000078 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port16x: gpio@55000088 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000088 0x8>; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>, + <&pinctrl 104 0 0>, + <&pinctrl 112 0 0>; + gpio-ranges-group-names = "gpio_range0", + "gpio_range1", + "gpio_range2"; + ngpios = <136>; };
i2c0: i2c@58400000 {
Like other recenct UniPhier SoCs, the pupdctrl number of PXs3 matches to the pin number.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c index 423e48b..7c54d37 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c @@ -118,7 +118,8 @@ static struct uniphier_pinctrl_socdata uniphier_pxs3_pinctrl_socdata = { .groups_count = ARRAY_SIZE(uniphier_pxs3_groups), .functions = uniphier_pxs3_functions, .functions_count = ARRAY_SIZE(uniphier_pxs3_functions), - .caps = UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL, + .caps = UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE | + UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL, };
static int uniphier_pxs3_pinctrl_probe(struct udevice *dev)
The pin data are implemented for old SoCs to specify the bit shift of the IECTRL register. They are not wortwhile given the required memory footprint. Delete all the pin data and enable all bits of the IECTRL register.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 17 +++----------- drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c | 16 ------------- drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c | 5 ---- drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c | 15 ------------ drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c | 9 ------- drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c | 30 ------------------------ 6 files changed, 3 insertions(+), 89 deletions(-)
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index d314482..215b19e 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -9,6 +9,7 @@ #include <dm.h> #include <linux/io.h> #include <linux/err.h> +#include <linux/kernel.h> #include <linux/sizes.h> #include <dm/pinctrl.h>
@@ -81,9 +82,6 @@ static int uniphier_pinconf_input_enable_legacy(struct udevice *dev, unsigned int pin, int enable) { struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); - int pins_count = priv->socdata->pins_count; - const struct uniphier_pinctrl_pin *pins = priv->socdata->pins; - int i;
/* * Multiple pins share one input enable, per-pin disabling is @@ -92,17 +90,8 @@ static int uniphier_pinconf_input_enable_legacy(struct udevice *dev, if (!enable) return -EINVAL;
- for (i = 0; i < pins_count; i++) { - if (pins[i].number == pin) { - unsigned int iectrl; - u32 tmp; - - iectrl = uniphier_pin_get_iectrl(pins[i].data); - tmp = readl(priv->base + UNIPHIER_PINCTRL_IECTRL); - tmp |= 1 << iectrl; - writel(tmp, priv->base + UNIPHIER_PINCTRL_IECTRL); - } - } + /* Set all bits instead of having a bunch of pin data */ + writel(U32_MAX, priv->base + UNIPHIER_PINCTRL_IECTRL);
return 0; } diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c index 709b005..7eb693d 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c @@ -11,20 +11,6 @@
#include "pinctrl-uniphier.h"
-static const struct uniphier_pinctrl_pin uniphier_ld4_pins[] = { - UNIPHIER_PINCTRL_PIN(53, 0), - UNIPHIER_PINCTRL_PIN(54, 0), - UNIPHIER_PINCTRL_PIN(55, 0), - UNIPHIER_PINCTRL_PIN(56, 0), - UNIPHIER_PINCTRL_PIN(67, 0), - UNIPHIER_PINCTRL_PIN(68, 0), - UNIPHIER_PINCTRL_PIN(69, 0), - UNIPHIER_PINCTRL_PIN(70, 0), - UNIPHIER_PINCTRL_PIN(85, 0), - UNIPHIER_PINCTRL_PIN(88, 0), - UNIPHIER_PINCTRL_PIN(156, 0), -}; - static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27}; static const int emmc_muxvals[] = {0, 1, 1, 1, 1, 1, 1}; static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31}; @@ -132,8 +118,6 @@ static const char * const uniphier_ld4_functions[] = { };
static struct uniphier_pinctrl_socdata uniphier_ld4_pinctrl_socdata = { - .pins = uniphier_ld4_pins, - .pins_count = ARRAY_SIZE(uniphier_ld4_pins), .groups = uniphier_ld4_groups, .groups_count = ARRAY_SIZE(uniphier_ld4_groups), .functions = uniphier_ld4_functions, diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c index df5f2d8..0695e07 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c @@ -11,9 +11,6 @@
#include "pinctrl-uniphier.h"
-static const struct uniphier_pinctrl_pin uniphier_pro4_pins[] = { -}; - static const unsigned emmc_pins[] = {40, 41, 42, 43, 51, 52, 53}; static const int emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1}; static const unsigned emmc_dat8_pins[] = {44, 45, 46, 47}; @@ -151,8 +148,6 @@ static const char * const uniphier_pro4_functions[] = { };
static struct uniphier_pinctrl_socdata uniphier_pro4_pinctrl_socdata = { - .pins = uniphier_pro4_pins, - .pins_count = ARRAY_SIZE(uniphier_pro4_pins), .groups = uniphier_pro4_groups, .groups_count = ARRAY_SIZE(uniphier_pro4_groups), .functions = uniphier_pro4_functions, diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c index 7b14662..39cdd95 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c @@ -11,19 +11,6 @@
#include "pinctrl-uniphier.h"
-static const struct uniphier_pinctrl_pin uniphier_pro5_pins[] = { - UNIPHIER_PINCTRL_PIN(47, 0), - UNIPHIER_PINCTRL_PIN(48, 0), - UNIPHIER_PINCTRL_PIN(49, 0), - UNIPHIER_PINCTRL_PIN(50, 0), - UNIPHIER_PINCTRL_PIN(53, 0), - UNIPHIER_PINCTRL_PIN(54, 0), - UNIPHIER_PINCTRL_PIN(87, 0), - UNIPHIER_PINCTRL_PIN(88, 0), - UNIPHIER_PINCTRL_PIN(101, 0), - UNIPHIER_PINCTRL_PIN(102, 0), -}; - static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42}; static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0}; static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46}; @@ -142,8 +129,6 @@ static const char * const uniphier_pro5_functions[] = { };
static struct uniphier_pinctrl_socdata uniphier_pro5_pinctrl_socdata = { - .pins = uniphier_pro5_pins, - .pins_count = ARRAY_SIZE(uniphier_pro5_pins), .groups = uniphier_pro5_groups, .groups_count = ARRAY_SIZE(uniphier_pro5_groups), .functions = uniphier_pro5_functions, diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c index 90d6329..70c985d 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c @@ -11,13 +11,6 @@
#include "pinctrl-uniphier.h"
-static const struct uniphier_pinctrl_pin uniphier_pxs2_pins[] = { - UNIPHIER_PINCTRL_PIN(113, 0), - UNIPHIER_PINCTRL_PIN(114, 0), - UNIPHIER_PINCTRL_PIN(115, 0), - UNIPHIER_PINCTRL_PIN(116, 0), -}; - static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42}; static const int emmc_muxvals[] = {9, 9, 9, 9, 9, 9, 9}; static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46}; @@ -135,8 +128,6 @@ static const char * const uniphier_pxs2_functions[] = { };
static struct uniphier_pinctrl_socdata uniphier_pxs2_pinctrl_socdata = { - .pins = uniphier_pxs2_pins, - .pins_count = ARRAY_SIZE(uniphier_pxs2_pins), .groups = uniphier_pxs2_groups, .groups_count = ARRAY_SIZE(uniphier_pxs2_groups), .functions = uniphier_pxs2_functions, diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c index 897ce15..5168bbe 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c @@ -11,34 +11,6 @@
#include "pinctrl-uniphier.h"
-static const struct uniphier_pinctrl_pin uniphier_sld8_pins[] = { - UNIPHIER_PINCTRL_PIN(32, 8), - UNIPHIER_PINCTRL_PIN(33, 8), - UNIPHIER_PINCTRL_PIN(34, 8), - UNIPHIER_PINCTRL_PIN(35, 8), - UNIPHIER_PINCTRL_PIN(36, 8), - UNIPHIER_PINCTRL_PIN(37, 8), - UNIPHIER_PINCTRL_PIN(38, 8), - UNIPHIER_PINCTRL_PIN(39, 8), - UNIPHIER_PINCTRL_PIN(40, 9), - UNIPHIER_PINCTRL_PIN(41, 0), - UNIPHIER_PINCTRL_PIN(42, 0), - UNIPHIER_PINCTRL_PIN(43, 0), - UNIPHIER_PINCTRL_PIN(44, 0), - UNIPHIER_PINCTRL_PIN(70, 0), - UNIPHIER_PINCTRL_PIN(71, 0), - UNIPHIER_PINCTRL_PIN(102, 10), - UNIPHIER_PINCTRL_PIN(103, 10), - UNIPHIER_PINCTRL_PIN(104, 11), - UNIPHIER_PINCTRL_PIN(105, 11), - UNIPHIER_PINCTRL_PIN(108, 13), - UNIPHIER_PINCTRL_PIN(109, 13), - UNIPHIER_PINCTRL_PIN(112, 0), - UNIPHIER_PINCTRL_PIN(113, 0), - UNIPHIER_PINCTRL_PIN(114, 0), - UNIPHIER_PINCTRL_PIN(115, 0), -}; - static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27}; static const int emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1}; static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31}; @@ -143,8 +115,6 @@ static const char * const uniphier_sld8_functions[] = { };
static struct uniphier_pinctrl_socdata uniphier_sld8_pinctrl_socdata = { - .pins = uniphier_sld8_pins, - .pins_count = ARRAY_SIZE(uniphier_sld8_pins), .groups = uniphier_sld8_groups, .groups_count = ARRAY_SIZE(uniphier_sld8_groups), .functions = uniphier_sld8_functions,
Replace printf() with pr_() to specify proper loglevel.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/mach-uniphier/arm32/psci.c | 4 +++- arch/arm/mach-uniphier/board_late_init.c | 4 +++- arch/arm/mach-uniphier/boot-device/boot-device.c | 1 + arch/arm/mach-uniphier/cpu-info.c | 7 ++++--- arch/arm/mach-uniphier/dram/cmd_ddrmphy.c | 4 +++- arch/arm/mach-uniphier/dram/cmd_ddrphy.c | 4 +++- arch/arm/mach-uniphier/dram/ddrphy-ld4.c | 5 +++-- arch/arm/mach-uniphier/dram/umc-pxs2.c | 18 ++++++++++-------- arch/arm/mach-uniphier/dram_init.c | 7 +++++-- 9 files changed, 35 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-uniphier/arm32/psci.c b/arch/arm/mach-uniphier/arm32/psci.c index 3ab101a..efe7419 100644 --- a/arch/arm/mach-uniphier/arm32/psci.c +++ b/arch/arm/mach-uniphier/arm32/psci.c @@ -7,8 +7,10 @@
#include <common.h> #include <linux/bitops.h> +#include <linux/delay.h> #include <linux/io.h> #include <linux/kernel.h> +#include <linux/printk.h> #include <linux/psci.h> #include <linux/sizes.h> #include <asm/processor.h> @@ -91,7 +93,7 @@ static void uniphier_smp_kick_all_cpus(void) }
if (!timeout) - printf("warning: some of secondary CPUs may not boot\n"); + pr_warn("warning: some of secondary CPUs may not boot\n");
uniphier_cache_disable(); } diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index b9a2cbe..6849b3d 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -10,7 +10,9 @@ #include <spl.h> #include <libfdt.h> #include <nand.h> +#include <stdio.h> #include <linux/io.h> +#include <linux/printk.h> #include <../drivers/mtd/nand/denali.h>
#include "init.h" @@ -92,7 +94,7 @@ int board_late_init(void) printf("\n");
if (uniphier_set_fdt_file()) - printf("fdt_file environment was not set correctly\n"); + pr_warn("fdt_file environment was not set correctly\n");
return 0; } diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c index 0f93926..2818b50 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device.c @@ -7,6 +7,7 @@
#include <common.h> #include <spl.h> +#include <stdio.h> #include <linux/log2.h>
#include "../init.h" diff --git a/arch/arm/mach-uniphier/cpu-info.c b/arch/arm/mach-uniphier/cpu-info.c index 90ef411..bf41d05 100644 --- a/arch/arm/mach-uniphier/cpu-info.c +++ b/arch/arm/mach-uniphier/cpu-info.c @@ -6,9 +6,10 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#include <common.h> +#include <stdio.h> #include <linux/errno.h> #include <linux/io.h> +#include <linux/printk.h>
#include "soc-info.h"
@@ -59,11 +60,11 @@ int print_cpuinfo(void) printf(" (model %d, revision %d)\n", model, rev);
if (model < required_model) { - printf("Only model %d or newer is supported.\n", + pr_err("Only model %d or newer is supported.\n", required_model); return -ENOTSUPP; } else if (rev < required_rev) { - printf("Only revision %d or newer is supported.\n", + pr_err("Only revision %d or newer is supported.\n", required_rev); return -ENOTSUPP; } diff --git a/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c index 873dad2..50f0dde 100644 --- a/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c +++ b/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c @@ -6,7 +6,9 @@ */
#include <common.h> +#include <stdio.h> #include <linux/io.h> +#include <linux/printk.h> #include <linux/sizes.h>
#include "../soc-info.h" @@ -297,7 +299,7 @@ static int do_ddrm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
param = uniphier_get_ddrmphy_param(); if (!param) { - printf("unsupported SoC\n"); + pr_err("unsupported SoC\n"); return CMD_RET_FAILURE; }
diff --git a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c index a71f704..0283eda 100644 --- a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c +++ b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c @@ -7,7 +7,9 @@ */
#include <common.h> +#include <stdio.h> #include <linux/io.h> +#include <linux/printk.h> #include <linux/sizes.h>
#include "../soc-info.h" @@ -267,7 +269,7 @@ static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
param = uniphier_get_ddrphy_param(); if (!param) { - printf("unsupported SoC\n"); + pr_err("unsupported SoC\n"); return CMD_RET_FAILURE; }
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ld4.c b/arch/arm/mach-uniphier/dram/ddrphy-ld4.c index c20730d..ba3d314 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ld4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ld4.c @@ -5,9 +5,10 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#include <common.h> +#include <linux/bitops.h> #include <linux/errno.h> #include <linux/io.h> +#include <linux/printk.h>
#include "ddrphy-init.h" #include "ddrphy-regs.h" @@ -41,7 +42,7 @@ int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus) freq_e = DRAM_FREQ_1600M; break; default: - printf("unsupported DRAM frequency %d MHz\n", freq); + pr_err("unsupported DRAM frequency %d MHz\n", freq); return -EINVAL; }
diff --git a/arch/arm/mach-uniphier/dram/umc-pxs2.c b/arch/arm/mach-uniphier/dram/umc-pxs2.c index 8068ef1..fccdb98 100644 --- a/arch/arm/mach-uniphier/dram/umc-pxs2.c +++ b/arch/arm/mach-uniphier/dram/umc-pxs2.c @@ -8,11 +8,13 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#include <common.h> +#include <linux/delay.h> #include <linux/errno.h> #include <linux/io.h> +#include <linux/printk.h> #include <linux/sizes.h> #include <asm/processor.h> +#include <time.h>
#include "../init.h" #include "../soc-info.h" @@ -134,7 +136,7 @@ static int ddrphy_get_system_latency(void __iomem *phy_base, int width) }
if (dgsl_min != dgsl_max) - printf("DQS Gateing System Latencies are not all leveled.\n"); + pr_warn("DQS Gateing System Latencies are not all leveled.\n");
return dgsl_max; } @@ -149,7 +151,7 @@ static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width,
nr_dx = width / 8;
- writel(MPHY_PIR_ZCALBYP, phy_base + MPHY_PIR); + writel(MPHY_PIR_ZCALBYP, phy_base + MPHY_PIR); /* * Disable RGLVT bit (Read DQS Gating LCDL Delay VT Compensation) * to avoid read error issue. @@ -315,8 +317,10 @@ static int __ddrphy_training(void __iomem *phy_base, u32 init_flag = MPHY_PIR_INIT; u32 done_flag = MPHY_PGSR0_IDONE; int timeout = 50000; /* 50 msec is long enough */ -#ifdef DISPLAY_ELAPSED_TIME - ulong start = get_timer(0); + unsigned long start = 0; + +#ifdef DEBUG + start = get_timer(0); #endif
for (s = seq; s->description; s++) { @@ -344,9 +348,7 @@ static int __ddrphy_training(void __iomem *phy_base, } }
-#ifdef DISPLAY_ELAPSED_TIME - printf("%s: info: elapsed time %ld msec\n", get_timer(start)); -#endif + pr_debug("DDRPHY training: elapsed time %ld msec\n", get_timer(start));
return 0; } diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 2213685..e9672d2 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -10,7 +10,10 @@ #include <fdt_support.h> #include <fdtdec.h> #include <linux/errno.h> +#include <linux/kernel.h> +#include <linux/printk.h> #include <linux/sizes.h> +#include <asm/global_data.h>
#include "sg-regs.h" #include "soc-info.h" @@ -264,8 +267,8 @@ int ft_board_setup(void *fdt, bd_t *bd) if (ret) return -ENOSPC;
- printf(" Reserved memory region for DRAM PHY training: addr=%lx size=%lx\n", - rsv_addr, rsv_size); + pr_notice(" Reserved memory region for DRAM PHY training: addr=%lx size=%lx\n", + rsv_addr, rsv_size); }
return 0;
Including <common.h> pulls in a lot of bloat. What this driver needs is BIT(), so replace it with <linux/bitops.h>
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
drivers/usb/dwc3/dwc3-uniphier.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/dwc3-uniphier.c b/drivers/usb/dwc3/dwc3-uniphier.c index 0d13770..25b17a8 100644 --- a/drivers/usb/dwc3/dwc3-uniphier.c +++ b/drivers/usb/dwc3/dwc3-uniphier.c @@ -7,8 +7,8 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#include <common.h> #include <dm.h> +#include <linux/bitops.h> #include <linux/errno.h> #include <linux/io.h> #include <linux/sizes.h>
On 10/13/2017 12:21 PM, Masahiro Yamada wrote:
Including <common.h> pulls in a lot of bloat. What this driver needs is BIT(), so replace it with <linux/bitops.h>
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com
Doesn't common.h also pull in the config macros ? Maybe they are not needed here though ...
drivers/usb/dwc3/dwc3-uniphier.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/dwc3-uniphier.c b/drivers/usb/dwc3/dwc3-uniphier.c index 0d13770..25b17a8 100644 --- a/drivers/usb/dwc3/dwc3-uniphier.c +++ b/drivers/usb/dwc3/dwc3-uniphier.c @@ -7,8 +7,8 @@
- SPDX-License-Identifier: GPL-2.0+
*/
-#include <common.h> #include <dm.h> +#include <linux/bitops.h> #include <linux/errno.h> #include <linux/io.h> #include <linux/sizes.h>
Hi Marek,
2017-10-13 19:40 GMT+09:00 Marek Vasut marex@denx.de:
On 10/13/2017 12:21 PM, Masahiro Yamada wrote:
Including <common.h> pulls in a lot of bloat. What this driver needs is BIT(), so replace it with <linux/bitops.h>
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com
Doesn't common.h also pull in the config macros ? Maybe they are not needed here though ...
If you need legacy CONFIG from include/configs/<board>.h, yes, you need to include <common.h> (or <config.h> at least)
Recent CONFIG options from Kconfig are automatically provided via -include $(srctree)/include/linux/kconfig.h
On 10/13/2017 01:01 PM, Masahiro Yamada wrote:
Hi Marek,
2017-10-13 19:40 GMT+09:00 Marek Vasut marex@denx.de:
On 10/13/2017 12:21 PM, Masahiro Yamada wrote:
Including <common.h> pulls in a lot of bloat. What this driver needs is BIT(), so replace it with <linux/bitops.h>
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com
Doesn't common.h also pull in the config macros ? Maybe they are not needed here though ...
If you need legacy CONFIG from include/configs/<board>.h, yes, you need to include <common.h> (or <config.h> at least)
Recent CONFIG options from Kconfig are automatically provided via -include $(srctree)/include/linux/kconfig.h
OK, so not needed , perfect, thanks.
Acked-by: Marek Vasut marex@denx.de
Use dev_dbg() functions. It will be helpful to prefix log messages with the corresponding device name when the core framework is ready.
While I am here, I renamed "dev", which was actually private data, into "priv" because dev->dev looks confusing.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
drivers/i2c/i2c-uniphier.c | 63 ++++++++++++++++++++++++---------------------- 1 file changed, 33 insertions(+), 30 deletions(-)
diff --git a/drivers/i2c/i2c-uniphier.c b/drivers/i2c/i2c-uniphier.c index 3412e2a..0f2734e 100644 --- a/drivers/i2c/i2c-uniphier.c +++ b/drivers/i2c/i2c-uniphier.c @@ -6,14 +6,14 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#include <common.h> -#include <dm.h> -#include <linux/types.h> +#include <linux/delay.h> +#include <linux/errno.h> #include <linux/io.h> #include <linux/sizes.h> -#include <linux/errno.h> -#include <i2c.h> +#include <linux/types.h> +#include <dm.h> #include <fdtdec.h> +#include <i2c.h>
struct uniphier_i2c_regs { u32 dtrm; /* data transmission */ @@ -38,7 +38,8 @@ struct uniphier_i2c_regs {
#define IOBUS_FREQ 100000000
-struct uniphier_i2c_dev { +struct uniphier_i2c_priv { + struct udevice *dev; struct uniphier_i2c_regs __iomem *regs; /* register base */ unsigned long input_clk; /* master clock (Hz) */ unsigned long wait_us; /* wait for every byte transfer (us) */ @@ -47,7 +48,7 @@ struct uniphier_i2c_dev { static int uniphier_i2c_probe(struct udevice *dev) { fdt_addr_t addr; - struct uniphier_i2c_dev *priv = dev_get_priv(dev); + struct uniphier_i2c_priv *priv = dev_get_priv(dev);
addr = devfdt_get_addr(dev); if (addr == FDT_ADDR_T_NONE) @@ -59,15 +60,17 @@ static int uniphier_i2c_probe(struct udevice *dev)
priv->input_clk = IOBUS_FREQ;
+ priv->dev = dev; + /* deassert reset */ writel(0x3, &priv->regs->brst);
return 0; }
-static int send_and_recv_byte(struct uniphier_i2c_dev *dev, u32 dtrm) +static int send_and_recv_byte(struct uniphier_i2c_priv *priv, u32 dtrm) { - writel(dtrm, &dev->regs->dtrm); + writel(dtrm, &priv->regs->dtrm);
/* * This controller only provides interruption to inform the completion @@ -75,72 +78,72 @@ static int send_and_recv_byte(struct uniphier_i2c_dev *dev, u32 dtrm) * Unfortunately, U-Boot does not have a good support of interrupt. * Wait for a while. */ - udelay(dev->wait_us); + udelay(priv->wait_us);
- return readl(&dev->regs->drec); + return readl(&priv->regs->drec); }
-static int send_byte(struct uniphier_i2c_dev *dev, u32 dtrm, bool *stop) +static int send_byte(struct uniphier_i2c_priv *priv, u32 dtrm, bool *stop) { int ret = 0; u32 drec;
- drec = send_and_recv_byte(dev, dtrm); + drec = send_and_recv_byte(priv, dtrm);
if (drec & I2C_DREC_LAB) { - debug("uniphier_i2c: bus arbitration failed\n"); + dev_dbg(priv->dev, "uniphier_i2c: bus arbitration failed\n"); *stop = false; ret = -EREMOTEIO; } if (drec & I2C_DREC_LRB) { - debug("uniphier_i2c: slave did not return ACK\n"); + dev_dbg(priv->dev, "uniphier_i2c: slave did not return ACK\n"); ret = -EREMOTEIO; } return ret; }
-static int uniphier_i2c_transmit(struct uniphier_i2c_dev *dev, uint addr, +static int uniphier_i2c_transmit(struct uniphier_i2c_priv *priv, uint addr, uint len, const u8 *buf, bool *stop) { int ret;
- debug("%s: addr = %x, len = %d\n", __func__, addr, len); + dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);
- ret = send_byte(dev, I2C_DTRM_STA | I2C_DTRM_NACK | addr << 1, stop); + ret = send_byte(priv, I2C_DTRM_STA | I2C_DTRM_NACK | addr << 1, stop); if (ret < 0) goto fail;
while (len--) { - ret = send_byte(dev, I2C_DTRM_NACK | *buf++, stop); + ret = send_byte(priv, I2C_DTRM_NACK | *buf++, stop); if (ret < 0) goto fail; }
fail: if (*stop) - writel(I2C_DTRM_STO | I2C_DTRM_NACK, &dev->regs->dtrm); + writel(I2C_DTRM_STO | I2C_DTRM_NACK, &priv->regs->dtrm);
return ret; }
-static int uniphier_i2c_receive(struct uniphier_i2c_dev *dev, uint addr, +static int uniphier_i2c_receive(struct uniphier_i2c_priv *priv, uint addr, uint len, u8 *buf, bool *stop) { int ret;
- debug("%s: addr = %x, len = %d\n", __func__, addr, len); + dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);
- ret = send_byte(dev, I2C_DTRM_STA | I2C_DTRM_NACK | + ret = send_byte(priv, I2C_DTRM_STA | I2C_DTRM_NACK | I2C_DTRM_RD | addr << 1, stop); if (ret < 0) goto fail;
while (len--) - *buf++ = send_and_recv_byte(dev, len ? 0 : I2C_DTRM_NACK); + *buf++ = send_and_recv_byte(priv, len ? 0 : I2C_DTRM_NACK);
fail: if (*stop) - writel(I2C_DTRM_STO | I2C_DTRM_NACK, &dev->regs->dtrm); + writel(I2C_DTRM_STO | I2C_DTRM_NACK, &priv->regs->dtrm);
return ret; } @@ -149,7 +152,7 @@ static int uniphier_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) { int ret = 0; - struct uniphier_i2c_dev *dev = dev_get_priv(bus); + struct uniphier_i2c_priv *priv = dev_get_priv(bus); bool stop;
for (; nmsgs > 0; nmsgs--, msg++) { @@ -157,10 +160,10 @@ static int uniphier_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true;
if (msg->flags & I2C_M_RD) - ret = uniphier_i2c_receive(dev, msg->addr, msg->len, + ret = uniphier_i2c_receive(priv, msg->addr, msg->len, msg->buf, &stop); else - ret = uniphier_i2c_transmit(dev, msg->addr, msg->len, + ret = uniphier_i2c_transmit(priv, msg->addr, msg->len, msg->buf, &stop);
if (ret < 0) @@ -172,7 +175,7 @@ static int uniphier_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
static int uniphier_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) { - struct uniphier_i2c_dev *priv = dev_get_priv(bus); + struct uniphier_i2c_priv *priv = dev_get_priv(bus);
/* max supported frequency is 400 kHz */ if (speed > 400000) @@ -211,6 +214,6 @@ U_BOOT_DRIVER(uniphier_i2c) = { .id = UCLASS_I2C, .of_match = uniphier_i2c_of_match, .probe = uniphier_i2c_probe, - .priv_auto_alloc_size = sizeof(struct uniphier_i2c_dev), + .priv_auto_alloc_size = sizeof(struct uniphier_i2c_priv), .ops = &uniphier_i2c_ops, };
Hello Masahiro,
Am 13.10.2017 um 12:21 schrieb Masahiro Yamada:
Use dev_dbg() functions. It will be helpful to prefix log messages with the corresponding device name when the core framework is ready.
While I am here, I renamed "dev", which was actually private data, into "priv" because dev->dev looks confusing.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com
drivers/i2c/i2c-uniphier.c | 63 ++++++++++++++++++++++++---------------------- 1 file changed, 33 insertions(+), 30 deletions(-)
Reviewed-by: Heiko Schocher hs@denx.de
bye, Heiko
Use dev_dbg() functions. It will be helpful to prefix log messages with the corresponding device name when the core framework is ready.
While I am here, I renamed "dev", which was actually private data, into "priv" because dev->dev looks confusing.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
drivers/i2c/i2c-uniphier-f.c | 114 ++++++++++++++++++++----------------------- 1 file changed, 52 insertions(+), 62 deletions(-)
diff --git a/drivers/i2c/i2c-uniphier-f.c b/drivers/i2c/i2c-uniphier-f.c index e51537b..eb6c9f3 100644 --- a/drivers/i2c/i2c-uniphier-f.c +++ b/drivers/i2c/i2c-uniphier-f.c @@ -6,13 +6,12 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#include <common.h> -#include <dm.h> -#include <linux/types.h> +#include <linux/errno.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/sizes.h> -#include <linux/errno.h> +#include <linux/types.h> +#include <dm.h> #include <i2c.h> #include <fdtdec.h>
@@ -64,35 +63,27 @@ struct uniphier_fi2c_regs {
#define FIOCLK 50000000
-struct uniphier_fi2c_dev { +struct uniphier_fi2c_priv { + struct udevice *dev; struct uniphier_fi2c_regs __iomem *regs; /* register base */ unsigned long fioclk; /* internal operation clock */ unsigned long timeout; /* time out (us) */ };
-static int reset_bus(struct uniphier_fi2c_regs __iomem *regs) +static void uniphier_fi2c_reset(struct uniphier_fi2c_priv *priv) { - u32 val; - int ret; - - /* bus forcible reset */ - writel(I2C_RST_RST, ®s->rst); - ret = readl_poll_timeout(®s->rst, val, !(val & I2C_RST_RST), 1); - if (ret < 0) - debug("error: fail to reset I2C controller\n"); - - return ret; + writel(I2C_RST_RST, &priv->regs->rst); }
-static int check_device_busy(struct uniphier_fi2c_regs __iomem *regs) +static int uniphier_fi2c_check_bus_busy(struct uniphier_fi2c_priv *priv) { u32 val; int ret;
- ret = readl_poll_timeout(®s->sr, val, !(val & I2C_SR_DB), 100); + ret = readl_poll_timeout(&priv->regs->sr, val, !(val & I2C_SR_DB), 100); if (ret < 0) { - debug("error: device busy too long. reset...\n"); - ret = reset_bus(regs); + dev_dbg(priv->dev, "error: device busy too long. reset...\n"); + uniphier_fi2c_reset(priv); }
return ret; @@ -101,8 +92,7 @@ static int check_device_busy(struct uniphier_fi2c_regs __iomem *regs) static int uniphier_fi2c_probe(struct udevice *dev) { fdt_addr_t addr; - struct uniphier_fi2c_dev *priv = dev_get_priv(dev); - int ret; + struct uniphier_fi2c_priv *priv = dev_get_priv(dev);
addr = devfdt_get_addr(dev); if (addr == FDT_ADDR_T_NONE) @@ -114,85 +104,85 @@ static int uniphier_fi2c_probe(struct udevice *dev)
priv->fioclk = FIOCLK;
+ priv->dev = dev; + /* bus forcible reset */ - ret = reset_bus(priv->regs); - if (ret < 0) - return ret; + uniphier_fi2c_reset(priv);
writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &priv->regs->brst);
return 0; }
-static int wait_for_irq(struct uniphier_fi2c_dev *dev, u32 flags, +static int wait_for_irq(struct uniphier_fi2c_priv *priv, u32 flags, bool *stop) { u32 irq; int ret;
- ret = readl_poll_timeout(&dev->regs->intr, irq, irq & flags, - dev->timeout); + ret = readl_poll_timeout(&priv->regs->intr, irq, irq & flags, + priv->timeout); if (ret < 0) { - debug("error: time out\n"); + dev_dbg(priv->dev, "error: time out\n"); return ret; }
if (irq & I2C_INT_AL) { - debug("error: arbitration lost\n"); + dev_dbg(priv->dev, "error: arbitration lost\n"); *stop = false; return ret; }
if (irq & I2C_INT_NA) { - debug("error: no answer\n"); + dev_dbg(priv->dev, "error: no answer\n"); return ret; }
return 0; }
-static int issue_stop(struct uniphier_fi2c_dev *dev, int old_ret) +static int issue_stop(struct uniphier_fi2c_priv *priv, int old_ret) { int ret;
- debug("stop condition\n"); - writel(I2C_CR_MST | I2C_CR_STO, &dev->regs->cr); + dev_dbg(priv->dev, "stop condition\n"); + writel(I2C_CR_MST | I2C_CR_STO, &priv->regs->cr);
- ret = check_device_busy(dev->regs); + ret = uniphier_fi2c_check_bus_busy(priv); if (ret < 0) - debug("error: device busy after operation\n"); + dev_dbg(priv->dev, "error: device busy after operation\n");
return old_ret ? old_ret : ret; }
-static int uniphier_fi2c_transmit(struct uniphier_fi2c_dev *dev, uint addr, +static int uniphier_fi2c_transmit(struct uniphier_fi2c_priv *priv, uint addr, uint len, const u8 *buf, bool *stop) { int ret; const u32 irq_flags = I2C_INT_TE | I2C_INT_NA | I2C_INT_AL; - struct uniphier_fi2c_regs __iomem *regs = dev->regs; + struct uniphier_fi2c_regs __iomem *regs = priv->regs;
- debug("%s: addr = %x, len = %d\n", __func__, addr, len); + dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);
writel(I2C_DTTX_CMD | addr << 1, ®s->dttx);
writel(irq_flags, ®s->ie); writel(irq_flags, ®s->ic);
- debug("start condition\n"); + dev_dbg(priv->dev, "start condition\n"); writel(I2C_CR_MST | I2C_CR_STA, ®s->cr);
- ret = wait_for_irq(dev, irq_flags, stop); + ret = wait_for_irq(priv, irq_flags, stop); if (ret < 0) goto error;
while (len--) { - debug("sending %x\n", *buf); + dev_dbg(priv->dev, "sending %x\n", *buf); writel(*buf++, ®s->dttx);
writel(irq_flags, ®s->ic);
- ret = wait_for_irq(dev, irq_flags, stop); + ret = wait_for_irq(priv, irq_flags, stop); if (ret < 0) goto error; } @@ -201,26 +191,26 @@ error: writel(irq_flags, ®s->ic);
if (*stop) - ret = issue_stop(dev, ret); + ret = issue_stop(priv, ret);
return ret; }
-static int uniphier_fi2c_receive(struct uniphier_fi2c_dev *dev, uint addr, +static int uniphier_fi2c_receive(struct uniphier_fi2c_priv *priv, uint addr, uint len, u8 *buf, bool *stop) { int ret = 0; const u32 irq_flags = I2C_INT_RB | I2C_INT_NA | I2C_INT_AL; - struct uniphier_fi2c_regs __iomem *regs = dev->regs; + struct uniphier_fi2c_regs __iomem *regs = priv->regs;
- debug("%s: addr = %x, len = %d\n", __func__, addr, len); + dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);
/* * In case 'len == 0', only the slave address should be sent * for probing, which is covered by the transmit function. */ if (len == 0) - return uniphier_fi2c_transmit(dev, addr, len, buf, stop); + return uniphier_fi2c_transmit(priv, addr, len, buf, stop);
writel(I2C_DTTX_CMD | I2C_DTTX_RD | addr << 1, ®s->dttx);
@@ -228,17 +218,17 @@ static int uniphier_fi2c_receive(struct uniphier_fi2c_dev *dev, uint addr, writel(irq_flags, ®s->ie); writel(irq_flags, ®s->ic);
- debug("start condition\n"); + dev_dbg(priv->dev, "start condition\n"); writel(I2C_CR_MST | I2C_CR_STA | (len == 1 ? I2C_CR_NACK : 0), ®s->cr);
while (len--) { - ret = wait_for_irq(dev, irq_flags, stop); + ret = wait_for_irq(priv, irq_flags, stop); if (ret < 0) goto error;
*buf++ = readl(®s->dtrx); - debug("received %x\n", *(buf - 1)); + dev_dbg(priv->dev, "received %x\n", *(buf - 1));
if (len == 1) writel(I2C_CR_MST | I2C_CR_NACK, ®s->cr); @@ -250,7 +240,7 @@ error: writel(irq_flags, ®s->ic);
if (*stop) - ret = issue_stop(dev, ret); + ret = issue_stop(priv, ret);
return ret; } @@ -259,10 +249,10 @@ static int uniphier_fi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) { int ret; - struct uniphier_fi2c_dev *dev = dev_get_priv(bus); + struct uniphier_fi2c_priv *priv = dev_get_priv(bus); bool stop;
- ret = check_device_busy(dev->regs); + ret = uniphier_fi2c_check_bus_busy(priv); if (ret < 0) return ret;
@@ -271,10 +261,10 @@ static int uniphier_fi2c_xfer(struct udevice *bus, struct i2c_msg *msg, stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true;
if (msg->flags & I2C_M_RD) - ret = uniphier_fi2c_receive(dev, msg->addr, msg->len, + ret = uniphier_fi2c_receive(priv, msg->addr, msg->len, msg->buf, &stop); else - ret = uniphier_fi2c_transmit(dev, msg->addr, msg->len, + ret = uniphier_fi2c_transmit(priv, msg->addr, msg->len, msg->buf, &stop);
if (ret < 0) @@ -288,21 +278,21 @@ static int uniphier_fi2c_set_bus_speed(struct udevice *bus, unsigned int speed) { int ret; unsigned int clk_count; - struct uniphier_fi2c_dev *dev = dev_get_priv(bus); - struct uniphier_fi2c_regs __iomem *regs = dev->regs; + struct uniphier_fi2c_priv *priv = dev_get_priv(bus); + struct uniphier_fi2c_regs __iomem *regs = priv->regs;
/* max supported frequency is 400 kHz */ if (speed > 400000) return -EINVAL;
- ret = check_device_busy(dev->regs); + ret = uniphier_fi2c_check_bus_busy(priv); if (ret < 0) return ret;
/* make sure the bus is idle when changing the frequency */ writel(I2C_BRST_RSCLO, ®s->brst);
- clk_count = dev->fioclk / speed; + clk_count = priv->fioclk / speed;
writel(clk_count, ®s->cyc); writel(clk_count / 2, ®s->lctl); @@ -316,7 +306,7 @@ static int uniphier_fi2c_set_bus_speed(struct udevice *bus, unsigned int speed) * 1000000 * 9 / speed usec. * This time out value is long enough. */ - dev->timeout = 100000000L / speed; + priv->timeout = 100000000L / speed;
return 0; } @@ -336,6 +326,6 @@ U_BOOT_DRIVER(uniphier_fi2c) = { .id = UCLASS_I2C, .of_match = uniphier_fi2c_of_match, .probe = uniphier_fi2c_probe, - .priv_auto_alloc_size = sizeof(struct uniphier_fi2c_dev), + .priv_auto_alloc_size = sizeof(struct uniphier_fi2c_priv), .ops = &uniphier_fi2c_ops, };
Hello Masahiro,
Am 13.10.2017 um 12:21 schrieb Masahiro Yamada:
Use dev_dbg() functions. It will be helpful to prefix log messages with the corresponding device name when the core framework is ready.
While I am here, I renamed "dev", which was actually private data, into "priv" because dev->dev looks confusing.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com
drivers/i2c/i2c-uniphier-f.c | 114 ++++++++++++++++++++----------------------- 1 file changed, 52 insertions(+), 62 deletions(-)
Reviewed-by: Heiko Schocher hs@denx.de
bye, Heiko
U-Boot does not support fancy clock tree structures like the Linux common clock framework. Implement a simple clock tree model at the driver level. With this, the clock data will be simplified.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
drivers/clk/uniphier/clk-uniphier-core.c | 267 ++++++++++++++++++++++--------- drivers/clk/uniphier/clk-uniphier-mio.c | 118 +++++++------- drivers/clk/uniphier/clk-uniphier-sys.c | 42 +++-- drivers/clk/uniphier/clk-uniphier.h | 79 +++++---- 4 files changed, 323 insertions(+), 183 deletions(-)
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index 722cd6b..3d1d411 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Socionext Inc. + * Copyright (C) 2016-2017 Socionext Inc. * Author: Masahiro Yamada yamada.masahiro@socionext.com * * SPDX-License-Identifier: GPL-2.0+ @@ -21,104 +21,224 @@ * @data: SoC specific data */ struct uniphier_clk_priv { + struct udevice *dev; void __iomem *base; const struct uniphier_clk_data *data; };
-static int uniphier_clk_enable(struct clk *clk) +static void uniphier_clk_gate_enable(struct uniphier_clk_priv *priv, + const struct uniphier_clk_gate_data *gate) { - struct uniphier_clk_priv *priv = dev_get_priv(clk->dev); - unsigned long id = clk->id; - const struct uniphier_clk_gate_data *p; + u32 val;
- for (p = priv->data->gate; p->id != UNIPHIER_CLK_ID_END; p++) { - u32 val; + val = readl(priv->base + gate->reg); + val |= BIT(gate->bit); + writel(val, priv->base + gate->reg); +}
- if (p->id != id) - continue; +static void uniphier_clk_mux_set_parent(struct uniphier_clk_priv *priv, + const struct uniphier_clk_mux_data *mux, + u8 id) +{ + u32 val; + int i;
- val = readl(priv->base + p->reg); - val |= BIT(p->bit); - writel(val, priv->base + p->reg); + for (i = 0; i < mux->num_parents; i++) { + if (mux->parent_ids[i] != id) + continue;
- return 0; + val = readl(priv->base + mux->reg); + val &= ~mux->masks[i]; + val |= mux->vals[i]; + writel(val, priv->base + mux->reg); + return; }
- dev_err(priv->dev, "clk_id=%lu was not handled\n", id); - return -EINVAL; + WARN_ON(1); }
-static const struct uniphier_clk_mux_data * -uniphier_clk_get_mux_data(struct uniphier_clk_priv *priv, unsigned long id) +static u8 uniphier_clk_mux_get_parent(struct uniphier_clk_priv *priv, + const struct uniphier_clk_mux_data *mux) { - const struct uniphier_clk_mux_data *p; + u32 val; + int i;
- for (p = priv->data->mux; p->id != UNIPHIER_CLK_ID_END; p++) { - if (p->id == id) - return p; - } + val = readl(priv->base + mux->reg); + + for (i = 0; i < mux->num_parents; i++) + if ((mux->masks[i] & val) == mux->vals[i]) + return mux->parent_ids[i]; + + dev_err(priv->dev, "invalid mux setting\n"); + + return UNIPHIER_CLK_ID_INVALID; +} + +static const struct uniphier_clk_data *uniphier_clk_get_data( + struct uniphier_clk_priv *priv, u8 id) +{ + const struct uniphier_clk_data *data; + + for (data = priv->data; data->type != UNIPHIER_CLK_TYPE_END; data++) + if (data->id == id) + return data; + + dev_err(priv->dev, "id=%u not found\n", id);
return NULL; }
-static ulong uniphier_clk_get_rate(struct clk *clk) +static const struct uniphier_clk_data *uniphier_clk_get_parent_data( + struct uniphier_clk_priv *priv, + const struct uniphier_clk_data *data) { - struct uniphier_clk_priv *priv = dev_get_priv(clk->dev); - const struct uniphier_clk_mux_data *mux; - u32 val; - int i; + const struct uniphier_clk_data *parent_data; + u8 parent_id = UNIPHIER_CLK_ID_INVALID; + + switch (data->type) { + case UNIPHIER_CLK_TYPE_GATE: + parent_id = data->data.gate.parent_id; + break; + case UNIPHIER_CLK_TYPE_MUX: + parent_id = uniphier_clk_mux_get_parent(priv, &data->data.mux); + break; + default: + break; + }
- mux = uniphier_clk_get_mux_data(priv, clk->id); - if (!mux) - return 0; + if (parent_id == UNIPHIER_CLK_ID_INVALID) + return NULL;
- if (!mux->nr_muxs) /* fixed-rate */ - return mux->rates[0]; + parent_data = uniphier_clk_get_data(priv, parent_id);
- val = readl(priv->base + mux->reg); + WARN_ON(!parent_data);
- for (i = 0; i < mux->nr_muxs; i++) - if ((mux->masks[i] & val) == mux->vals[i]) - return mux->rates[i]; + return parent_data; +} + +static void __uniphier_clk_enable(struct uniphier_clk_priv *priv, + const struct uniphier_clk_data *data) +{ + const struct uniphier_clk_data *parent_data;
- return -EINVAL; + if (data->type == UNIPHIER_CLK_TYPE_GATE) + uniphier_clk_gate_enable(priv, &data->data.gate); + + parent_data = uniphier_clk_get_parent_data(priv, data); + if (!parent_data) + return; + + return __uniphier_clk_enable(priv, parent_data); }
-static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate) +static int uniphier_clk_enable(struct clk *clk) { struct uniphier_clk_priv *priv = dev_get_priv(clk->dev); - const struct uniphier_clk_mux_data *mux; - u32 val; - int i, best_rate_id = -1; - ulong best_rate = 0; + const struct uniphier_clk_data *data; + + data = uniphier_clk_get_data(priv, clk->id); + if (!data) + return -ENODEV; + + __uniphier_clk_enable(priv, data); + + return 0; +} + +static unsigned long __uniphier_clk_get_rate( + struct uniphier_clk_priv *priv, + const struct uniphier_clk_data *data) +{ + const struct uniphier_clk_data *parent_data;
- mux = uniphier_clk_get_mux_data(priv, clk->id); - if (!mux) + if (data->type == UNIPHIER_CLK_TYPE_FIXED_RATE) + return data->data.rate.fixed_rate; + + parent_data = uniphier_clk_get_parent_data(priv, data); + if (!parent_data) return 0;
- if (!mux->nr_muxs) /* fixed-rate */ - return mux->rates[0]; + return __uniphier_clk_get_rate(priv, parent_data); +}
- /* first, decide the best match rate */ - for (i = 0; i < mux->nr_muxs; i++) { - if (mux->rates[i] > best_rate && mux->rates[i] <= rate) { - best_rate = mux->rates[i]; - best_rate_id = i; +static unsigned long uniphier_clk_get_rate(struct clk *clk) +{ + struct uniphier_clk_priv *priv = dev_get_priv(clk->dev); + const struct uniphier_clk_data *data; + + data = uniphier_clk_get_data(priv, clk->id); + if (!data) + return -ENODEV; + + return __uniphier_clk_get_rate(priv, data); +} + +static unsigned long __uniphier_clk_set_rate( + struct uniphier_clk_priv *priv, + const struct uniphier_clk_data *data, + unsigned long rate, bool set) +{ + const struct uniphier_clk_data *best_parent_data = NULL; + const struct uniphier_clk_data *parent_data; + unsigned long best_rate = 0; + unsigned long parent_rate; + u8 parent_id; + int i; + + if (data->type == UNIPHIER_CLK_TYPE_FIXED_RATE) + return data->data.rate.fixed_rate; + + if (data->type == UNIPHIER_CLK_TYPE_GATE) { + parent_data = uniphier_clk_get_parent_data(priv, data); + if (!parent_data) + return 0; + + return __uniphier_clk_set_rate(priv, parent_data, rate, set); + } + + if (WARN_ON(data->type != UNIPHIER_CLK_TYPE_MUX)) + return -EINVAL; + + for (i = 0; i < data->data.mux.num_parents; i++) { + parent_id = data->data.mux.parent_ids[i]; + parent_data = uniphier_clk_get_data(priv, parent_id); + if (WARN_ON(!parent_data)) + return -EINVAL; + + parent_rate = __uniphier_clk_set_rate(priv, parent_data, rate, + false); + + if (parent_rate <= rate && best_rate < parent_rate) { + best_rate = parent_rate; + best_parent_data = parent_data; } }
- if (best_rate_id < 0) + dev_dbg(priv->dev, "id=%u, best_rate=%lu\n", data->id, best_rate); + + if (!best_parent_data) return -EINVAL;
- val = readl(priv->base + mux->reg); - val &= ~mux->masks[best_rate_id]; - val |= mux->vals[best_rate_id]; - writel(val, priv->base + mux->reg); + if (!set) + return best_rate; + + uniphier_clk_mux_set_parent(priv, &data->data.mux, + best_parent_data->id); + + return best_rate = __uniphier_clk_set_rate(priv, best_parent_data, + rate, true); +} + +static unsigned long uniphier_clk_set_rate(struct clk *clk, ulong rate) +{ + struct uniphier_clk_priv *priv = dev_get_priv(clk->dev); + const struct uniphier_clk_data *data;
- debug("%s: requested rate = %lu, set rate = %lu\n", __func__, - rate, best_rate); + data = uniphier_clk_get_data(priv, clk->id); + if (!data) + return -ENODEV;
- return best_rate; + return __uniphier_clk_set_rate(priv, data, rate, true); }
static const struct clk_ops uniphier_clk_ops = { @@ -140,6 +260,7 @@ static int uniphier_clk_probe(struct udevice *dev) if (!priv->base) return -ENOMEM;
+ priv->dev = dev; priv->data = (void *)dev_get_driver_data(dev);
return 0; @@ -149,60 +270,60 @@ static const struct udevice_id uniphier_clk_match[] = { /* System clock */ { .compatible = "socionext,uniphier-ld4-clock", - .data = (ulong)&uniphier_pxs2_sys_clk_data, + .data = (ulong)uniphier_pxs2_sys_clk_data, }, { .compatible = "socionext,uniphier-pro4-clock", - .data = (ulong)&uniphier_pxs2_sys_clk_data, + .data = (ulong)uniphier_pxs2_sys_clk_data, }, { .compatible = "socionext,uniphier-sld8-clock", - .data = (ulong)&uniphier_pxs2_sys_clk_data, + .data = (ulong)uniphier_pxs2_sys_clk_data, }, { .compatible = "socionext,uniphier-pro5-clock", - .data = (ulong)&uniphier_pxs2_sys_clk_data, + .data = (ulong)uniphier_pxs2_sys_clk_data, }, { .compatible = "socionext,uniphier-pxs2-clock", - .data = (ulong)&uniphier_pxs2_sys_clk_data, + .data = (ulong)uniphier_pxs2_sys_clk_data, }, { .compatible = "socionext,uniphier-ld11-clock", - .data = (ulong)&uniphier_ld20_sys_clk_data, + .data = (ulong)uniphier_ld20_sys_clk_data, }, { .compatible = "socionext,uniphier-ld20-clock", - .data = (ulong)&uniphier_ld20_sys_clk_data, + .data = (ulong)uniphier_ld20_sys_clk_data, }, /* Media I/O clock */ { .compatible = "socionext,uniphier-ld4-mio-clock", - .data = (ulong)&uniphier_mio_clk_data, + .data = (ulong)uniphier_mio_clk_data, }, { .compatible = "socionext,uniphier-pro4-mio-clock", - .data = (ulong)&uniphier_mio_clk_data, + .data = (ulong)uniphier_mio_clk_data, }, { .compatible = "socionext,uniphier-sld8-mio-clock", - .data = (ulong)&uniphier_mio_clk_data, + .data = (ulong)uniphier_mio_clk_data, }, { .compatible = "socionext,uniphier-pro5-sd-clock", - .data = (ulong)&uniphier_mio_clk_data, + .data = (ulong)uniphier_mio_clk_data, }, { .compatible = "socionext,uniphier-pxs2-sd-clock", - .data = (ulong)&uniphier_mio_clk_data, + .data = (ulong)uniphier_mio_clk_data, }, { .compatible = "socionext,uniphier-ld11-mio-clock", - .data = (ulong)&uniphier_mio_clk_data, + .data = (ulong)uniphier_mio_clk_data, }, { .compatible = "socionext,uniphier-ld20-sd-clock", - .data = (ulong)&uniphier_mio_clk_data, + .data = (ulong)uniphier_mio_clk_data, }, { /* sentinel */ } }; diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c index 9c13dcd..5c73848 100644 --- a/drivers/clk/uniphier/clk-uniphier-mio.c +++ b/drivers/clk/uniphier/clk-uniphier-mio.c @@ -7,59 +7,71 @@
#include "clk-uniphier.h"
-#define UNIPHIER_MIO_CLK_SD_GATE(id, ch) \ - UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 8) +#define UNIPHIER_MIO_CLK_SD_FIXED \ + UNIPHIER_CLK_RATE(128, 44444444), \ + UNIPHIER_CLK_RATE(129, 33333333), \ + UNIPHIER_CLK_RATE(130, 50000000), \ + UNIPHIER_CLK_RATE(131, 66666667), \ + UNIPHIER_CLK_RATE(132, 100000000), \ + UNIPHIER_CLK_RATE(133, 40000000), \ + UNIPHIER_CLK_RATE(134, 25000000), \ + UNIPHIER_CLK_RATE(135, 22222222) + +#define UNIPHIER_MIO_CLK_SD(_id, ch) \ + { \ + .type = UNIPHIER_CLK_TYPE_MUX, \ + .id = (_id) + 32, \ + .data.mux = { \ + .parent_ids = { \ + 128, \ + 129, \ + 130, \ + 131, \ + 132, \ + 133, \ + 134, \ + 135, \ + }, \ + .num_parents = 8, \ + .reg = 0x30 + 0x200 * (ch), \ + .masks = { \ + 0x00031000, \ + 0x00031000, \ + 0x00031000, \ + 0x00031000, \ + 0x00001300, \ + 0x00001300, \ + 0x00001300, \ + 0x00001300, \ + }, \ + .vals = { \ + 0x00000000, \ + 0x00010000, \ + 0x00020000, \ + 0x00030000, \ + 0x00001000, \ + 0x00001100, \ + 0x00001200, \ + 0x00001300, \ + }, \ + }, \ + }, \ + UNIPHIER_CLK_GATE((_id), (_id) + 32, 0x20 + 0x200 * (ch), 8)
#define UNIPHIER_MIO_CLK_USB2(id, ch) \ - UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 28) + UNIPHIER_CLK_GATE_SIMPLE((id), 0x20 + 0x200 * (ch), 28)
#define UNIPHIER_MIO_CLK_USB2_PHY(id, ch) \ - UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 29) + UNIPHIER_CLK_GATE_SIMPLE((id), 0x20 + 0x200 * (ch), 29)
#define UNIPHIER_MIO_CLK_DMAC(id) \ - UNIPHIER_CLK_GATE((id), 0x20, 25) - -#define UNIPHIER_MIO_CLK_SD_MUX(_id, ch) \ - { \ - .id = (_id), \ - .nr_muxs = 8, \ - .reg = 0x30 + 0x200 * (ch), \ - .masks = { \ - 0x00031000, \ - 0x00031000, \ - 0x00031000, \ - 0x00031000, \ - 0x00001300, \ - 0x00001300, \ - 0x00001300, \ - 0x00001300, \ - }, \ - .vals = { \ - 0x00000000, \ - 0x00010000, \ - 0x00020000, \ - 0x00030000, \ - 0x00001000, \ - 0x00001100, \ - 0x00001200, \ - 0x00001300, \ - }, \ - .rates = { \ - 44444444, \ - 33333333, \ - 50000000, \ - 66666666, \ - 100000000, \ - 40000000, \ - 25000000, \ - 22222222, \ - }, \ - } + UNIPHIER_CLK_GATE_SIMPLE((id), 0x20, 25)
-static const struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = { - UNIPHIER_MIO_CLK_SD_GATE(0, 0), - UNIPHIER_MIO_CLK_SD_GATE(1, 1), - UNIPHIER_MIO_CLK_SD_GATE(2, 2), /* for PH1-Pro4 only */ +const struct uniphier_clk_data uniphier_mio_clk_data[] = { + UNIPHIER_MIO_CLK_SD_FIXED, + UNIPHIER_MIO_CLK_SD(0, 0), + UNIPHIER_MIO_CLK_SD(1, 1), + UNIPHIER_MIO_CLK_SD(2, 2), UNIPHIER_MIO_CLK_DMAC(7), UNIPHIER_MIO_CLK_USB2(8, 0), UNIPHIER_MIO_CLK_USB2(9, 1), @@ -67,17 +79,5 @@ static const struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = { UNIPHIER_MIO_CLK_USB2_PHY(12, 0), UNIPHIER_MIO_CLK_USB2_PHY(13, 1), UNIPHIER_MIO_CLK_USB2_PHY(14, 2), - UNIPHIER_CLK_END -}; - -static const struct uniphier_clk_mux_data uniphier_mio_clk_mux[] = { - UNIPHIER_MIO_CLK_SD_MUX(0, 0), - UNIPHIER_MIO_CLK_SD_MUX(1, 1), - UNIPHIER_MIO_CLK_SD_MUX(2, 2), /* for PH1-Pro4 only */ - UNIPHIER_CLK_END -}; - -const struct uniphier_clk_data uniphier_mio_clk_data = { - .gate = uniphier_mio_clk_gate, - .mux = uniphier_mio_clk_mux, + { /* sentinel */ } }; diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index 709fa50..e9df885 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -7,28 +7,26 @@
#include "clk-uniphier.h"
-const struct uniphier_clk_gate_data uniphier_pxs2_sys_clk_gate[] = { - UNIPHIER_CLK_GATE(8, 0x2104, 10), /* stdmac */ - UNIPHIER_CLK_GATE(12, 0x2104, 6), /* gio (Pro4, Pro5) */ - UNIPHIER_CLK_GATE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */ - UNIPHIER_CLK_GATE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */ - UNIPHIER_CLK_GATE(16, 0x2104, 19), /* usb30-phy (PXs2) */ - UNIPHIER_CLK_GATE(20, 0x2104, 20), /* usb31-phy (PXs2) */ - UNIPHIER_CLK_END +const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { +#if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_SLD8) ||\ + defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\ + defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B) + UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */ + UNIPHIER_CLK_GATE_SIMPLE(12, 0x2104, 6), /* gio (Pro4, Pro5) */ + UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */ + UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */ + UNIPHIER_CLK_GATE_SIMPLE(16, 0x2104, 19), /* usb30-phy (PXs2) */ + UNIPHIER_CLK_GATE_SIMPLE(20, 0x2104, 20), /* usb31-phy (PXs2) */ + { /* sentinel */ } +#endif };
-const struct uniphier_clk_data uniphier_pxs2_sys_clk_data = { - .gate = uniphier_pxs2_sys_clk_gate, -}; - -const struct uniphier_clk_gate_data uniphier_ld20_sys_clk_gate[] = { - UNIPHIER_CLK_GATE(8, 0x210c, 8), /* stdmac */ - UNIPHIER_CLK_GATE(14, 0x210c, 14), /* usb30 (LD20) */ - UNIPHIER_CLK_GATE(16, 0x210c, 12), /* usb30-phy0 (LD20) */ - UNIPHIER_CLK_GATE(17, 0x210c, 13), /* usb30-phy1 (LD20) */ - UNIPHIER_CLK_END -}; - -const struct uniphier_clk_data uniphier_ld20_sys_clk_data = { - .gate = uniphier_ld20_sys_clk_gate, +const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { +#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) + UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */ + UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */ + UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12), /* usb30-phy0 (LD20) */ + UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 13), /* usb30-phy1 (LD20) */ + { /* sentinel */ } +#endif }; diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h index 770a322..9b6c94f 100644 --- a/drivers/clk/uniphier/clk-uniphier.h +++ b/drivers/clk/uniphier/clk-uniphier.h @@ -9,49 +9,70 @@ #define __CLK_UNIPHIER_H__
#include <linux/kernel.h> +#include <linux/types.h>
-#define UNIPHIER_CLK_MAX_NR_MUXS 8 +#define UNIPHIER_CLK_MUX_MAX_PARENTS 8 + +#define UNIPHIER_CLK_TYPE_END 0 +#define UNIPHIER_CLK_TYPE_FIXED_RATE 2 +#define UNIPHIER_CLK_TYPE_GATE 3 +#define UNIPHIER_CLK_TYPE_MUX 4 + +#define UNIPHIER_CLK_ID_INVALID (U8_MAX) + +struct uniphier_clk_fixed_rate_data { + unsigned long fixed_rate; +};
struct uniphier_clk_gate_data { - unsigned int id; - unsigned int reg; - unsigned int bit; + u8 parent_id; + u16 reg; + u8 bit; };
struct uniphier_clk_mux_data { - unsigned int id; - unsigned int nr_muxs; - unsigned int reg; - unsigned int masks[UNIPHIER_CLK_MAX_NR_MUXS]; - unsigned int vals[UNIPHIER_CLK_MAX_NR_MUXS]; - unsigned long rates[UNIPHIER_CLK_MAX_NR_MUXS]; + u8 parent_ids[UNIPHIER_CLK_MUX_MAX_PARENTS]; + u8 num_parents; + u16 reg; + u32 masks[UNIPHIER_CLK_MUX_MAX_PARENTS]; + u32 vals[UNIPHIER_CLK_MUX_MAX_PARENTS]; };
struct uniphier_clk_data { - const struct uniphier_clk_gate_data *gate; - const struct uniphier_clk_mux_data *mux; + u8 type; + u8 id; + union { + struct uniphier_clk_fixed_rate_data rate; + struct uniphier_clk_gate_data gate; + struct uniphier_clk_mux_data mux; + } data; };
-#define UNIPHIER_CLK_ID_END (unsigned int)(-1) - -#define UNIPHIER_CLK_END \ - { .id = UNIPHIER_CLK_ID_END } - -#define UNIPHIER_CLK_GATE(_id, _reg, _bit) \ - { \ - .id = (_id), \ - .reg = (_reg), \ - .bit = (_bit), \ +#define UNIPHIER_CLK_RATE(_id, _rate) \ + { \ + .type = UNIPHIER_CLK_TYPE_FIXED_RATE, \ + .id = (_id), \ + .data.rate = { \ + .fixed_rate = (_rate), \ + }, \ }
-#define UNIPHIER_CLK_FIXED_RATE(_id, _rate) \ - { \ - .id = (_id), \ - .rates = {(_reg),}, \ +#define UNIPHIER_CLK_GATE(_id, _parent, _reg, _bit) \ + { \ + .type = UNIPHIER_CLK_TYPE_GATE, \ + .id = (_id), \ + .data.gate = { \ + .parent_id = (_parent), \ + .reg = (_reg), \ + .bit = (_bit), \ + }, \ }
-extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data; -extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data; -extern const struct uniphier_clk_data uniphier_mio_clk_data; +#define UNIPHIER_CLK_GATE_SIMPLE(_id, _reg, _bit) \ + UNIPHIER_CLK_GATE(_id, UNIPHIER_CLK_ID_INVALID, _reg, _bit) + +extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[]; +extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[]; +extern const struct uniphier_clk_data uniphier_mio_clk_data[];
#endif /* __CLK_UNIPHIER_H__ */
Add basic clock data for Socionext's new SoC PXs3.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
drivers/clk/uniphier/clk-uniphier-core.c | 8 ++++++++ drivers/clk/uniphier/clk-uniphier-sys.c | 14 ++++++++++++++ drivers/clk/uniphier/clk-uniphier.h | 1 + 3 files changed, 23 insertions(+)
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index 3d1d411..9a7d03a 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -296,6 +296,10 @@ static const struct udevice_id uniphier_clk_match[] = { .compatible = "socionext,uniphier-ld20-clock", .data = (ulong)uniphier_ld20_sys_clk_data, }, + { + .compatible = "socionext,uniphier-pxs3-clock", + .data = (ulong)uniphier_pxs3_sys_clk_data, + }, /* Media I/O clock */ { .compatible = "socionext,uniphier-ld4-mio-clock", @@ -325,6 +329,10 @@ static const struct udevice_id uniphier_clk_match[] = { .compatible = "socionext,uniphier-ld20-sd-clock", .data = (ulong)uniphier_mio_clk_data, }, + { + .compatible = "socionext,uniphier-pxs3-sd-clock", + .data = (ulong)uniphier_mio_clk_data, + }, { /* sentinel */ } };
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index e9df885..f8cf6da 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -30,3 +30,17 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { { /* sentinel */ } #endif }; + +const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { +#if defined(CONFIG_ARCH_UNIPHIER_PXS3) + UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */ + UNIPHIER_CLK_GATE_SIMPLE(13, 0x210c, 5), /* usb31-0 (gio1) */ + UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 6), /* usb31-1 (gio1-1) */ + UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 16), /* usb30-phy0 */ + UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 18), /* usb30-phy1 */ + UNIPHIER_CLK_GATE_SIMPLE(18, 0x210c, 20), /* usb30-phy2 */ + UNIPHIER_CLK_GATE_SIMPLE(20, 0x210c, 17), /* usb31-phy0 */ + UNIPHIER_CLK_GATE_SIMPLE(21, 0x210c, 19), /* usb31-phy1 */ + { /* sentinel */ } +#endif +}; diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h index 9b6c94f..77ebae1 100644 --- a/drivers/clk/uniphier/clk-uniphier.h +++ b/drivers/clk/uniphier/clk-uniphier.h @@ -73,6 +73,7 @@ struct uniphier_clk_data {
extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[]; extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[]; +extern const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[]; extern const struct uniphier_clk_data uniphier_mio_clk_data[];
#endif /* __CLK_UNIPHIER_H__ */
Add peripheral clock data for all SoCs.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
drivers/clk/uniphier/Makefile | 2 + drivers/clk/uniphier/clk-uniphier-core.c | 33 +++++++++ drivers/clk/uniphier/clk-uniphier-peri.c | 113 +++++++++++++++++++++++++++++++ drivers/clk/uniphier/clk-uniphier.h | 5 ++ 4 files changed, 153 insertions(+) create mode 100644 drivers/clk/uniphier/clk-uniphier-peri.c
diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile index 54c7e09..d132cf7 100644 --- a/drivers/clk/uniphier/Makefile +++ b/drivers/clk/uniphier/Makefile @@ -1,3 +1,5 @@ obj-y += clk-uniphier-core.o + obj-y += clk-uniphier-sys.o obj-y += clk-uniphier-mio.o +obj-y += clk-uniphier-peri.o diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index 9a7d03a..ed5acbd 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -333,6 +333,39 @@ static const struct udevice_id uniphier_clk_match[] = { .compatible = "socionext,uniphier-pxs3-sd-clock", .data = (ulong)uniphier_mio_clk_data, }, + /* Peripheral clock */ + { + .compatible = "socionext,uniphier-ld4-peri-clock", + .data = (ulong)uniphier_ld4_peri_clk_data, + }, + { + .compatible = "socionext,uniphier-pro4-peri-clock", + .data = (ulong)uniphier_pro4_peri_clk_data, + }, + { + .compatible = "socionext,uniphier-sld8-peri-clock", + .data = (ulong)uniphier_sld8_peri_clk_data, + }, + { + .compatible = "socionext,uniphier-pro5-peri-clock", + .data = (ulong)uniphier_pro4_peri_clk_data, + }, + { + .compatible = "socionext,uniphier-pxs2-peri-clock", + .data = (ulong)uniphier_pxs2_peri_clk_data, + }, + { + .compatible = "socionext,uniphier-ld11-peri-clock", + .data = (ulong)uniphier_ld11_peri_clk_data, + }, + { + .compatible = "socionext,uniphier-ld20-peri-clock", + .data = (ulong)uniphier_ld11_peri_clk_data, + }, + { + .compatible = "socionext,uniphier-pxs3-peri-clock", + .data = (ulong)uniphier_ld11_peri_clk_data, + }, { /* sentinel */ } };
diff --git a/drivers/clk/uniphier/clk-uniphier-peri.c b/drivers/clk/uniphier/clk-uniphier-peri.c new file mode 100644 index 0000000..51edcab --- /dev/null +++ b/drivers/clk/uniphier/clk-uniphier-peri.c @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2016-2017 Socionext Inc. + * Author: Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "clk-uniphier.h" + +#define UNIPHIER_PERI_CLK_UART(id, ch) \ + UNIPHIER_CLK_GATE(id, 128, 0x24, 19 + (ch)) + +#define UNIPHIER_PERI_CLK_I2C(id, ch) \ + UNIPHIER_CLK_GATE(id, 129, 0x24, 5 + (ch)) + +#define UNIPHIER_PERI_CLK_FI2C(id, ch) \ + UNIPHIER_CLK_GATE(id, 129, 0x24, 24 + (ch)) + +const struct uniphier_clk_data uniphier_ld4_peri_clk_data[] = { +#ifdef CONFIG_ARCH_UNIPHIER_LD4 + UNIPHIER_CLK_RATE(128, 36864000), + UNIPHIER_CLK_RATE(129, 99840000), + UNIPHIER_PERI_CLK_UART(0, 0), + UNIPHIER_PERI_CLK_UART(1, 1), + UNIPHIER_PERI_CLK_UART(2, 2), + UNIPHIER_PERI_CLK_UART(3, 3), + UNIPHIER_PERI_CLK_I2C(4, 0), + UNIPHIER_PERI_CLK_I2C(5, 1), + UNIPHIER_PERI_CLK_I2C(6, 2), + UNIPHIER_PERI_CLK_I2C(7, 3), + UNIPHIER_PERI_CLK_I2C(8, 4), + UNIPHIER_PERI_CLK_I2C(9, 5), + UNIPHIER_PERI_CLK_I2C(10, 6), + { /* sentinel */ } +#endif +}; + +const struct uniphier_clk_data uniphier_sld8_peri_clk_data[] = { +#ifdef CONFIG_ARCH_UNIPHIER_SLD8 + UNIPHIER_CLK_RATE(128, 80000000), + UNIPHIER_CLK_RATE(129, 100000000), + UNIPHIER_PERI_CLK_UART(0, 0), + UNIPHIER_PERI_CLK_UART(1, 1), + UNIPHIER_PERI_CLK_UART(2, 2), + UNIPHIER_PERI_CLK_UART(3, 3), + UNIPHIER_PERI_CLK_I2C(4, 0), + UNIPHIER_PERI_CLK_I2C(5, 1), + UNIPHIER_PERI_CLK_I2C(6, 2), + UNIPHIER_PERI_CLK_I2C(7, 3), + UNIPHIER_PERI_CLK_I2C(8, 4), + UNIPHIER_PERI_CLK_I2C(9, 5), + UNIPHIER_PERI_CLK_I2C(10, 6), + { /* sentinel */ } +#endif +}; + +const struct uniphier_clk_data uniphier_pro4_peri_clk_data[] = { +#if defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) + UNIPHIER_CLK_RATE(128, 73728000), + UNIPHIER_CLK_RATE(129, 50000000), + UNIPHIER_PERI_CLK_UART(0, 0), + UNIPHIER_PERI_CLK_UART(1, 1), + UNIPHIER_PERI_CLK_UART(2, 2), + UNIPHIER_PERI_CLK_UART(3, 3), + UNIPHIER_PERI_CLK_FI2C(4, 0), + UNIPHIER_PERI_CLK_FI2C(5, 1), + UNIPHIER_PERI_CLK_FI2C(6, 2), + UNIPHIER_PERI_CLK_FI2C(7, 3), + UNIPHIER_PERI_CLK_FI2C(8, 4), + UNIPHIER_PERI_CLK_FI2C(9, 5), + UNIPHIER_PERI_CLK_FI2C(10, 6), + { /* sentinel */ } +#endif +}; + +const struct uniphier_clk_data uniphier_pxs2_peri_clk_data[] = { +#if defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B) + UNIPHIER_CLK_RATE(128, 88888889), + UNIPHIER_CLK_RATE(129, 50000000), + UNIPHIER_PERI_CLK_UART(0, 0), + UNIPHIER_PERI_CLK_UART(1, 1), + UNIPHIER_PERI_CLK_UART(2, 2), + UNIPHIER_PERI_CLK_UART(3, 3), + UNIPHIER_PERI_CLK_FI2C(4, 0), + UNIPHIER_PERI_CLK_FI2C(5, 1), + UNIPHIER_PERI_CLK_FI2C(6, 2), + UNIPHIER_PERI_CLK_FI2C(7, 3), + UNIPHIER_PERI_CLK_FI2C(8, 4), + UNIPHIER_PERI_CLK_FI2C(9, 5), + UNIPHIER_PERI_CLK_FI2C(10, 6), + { /* sentinel */ } +#endif +}; + +const struct uniphier_clk_data uniphier_ld11_peri_clk_data[] = { +#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) ||\ + defined(CONFIG_ARCH_UNIPHIER_PXS3) + UNIPHIER_CLK_RATE(128, 58823529), + UNIPHIER_CLK_RATE(129, 50000000), + UNIPHIER_PERI_CLK_UART(0, 0), + UNIPHIER_PERI_CLK_UART(1, 1), + UNIPHIER_PERI_CLK_UART(2, 2), + UNIPHIER_PERI_CLK_UART(3, 3), + UNIPHIER_PERI_CLK_FI2C(4, 0), + UNIPHIER_PERI_CLK_FI2C(5, 1), + UNIPHIER_PERI_CLK_FI2C(6, 2), + UNIPHIER_PERI_CLK_FI2C(7, 3), + UNIPHIER_PERI_CLK_FI2C(8, 4), + UNIPHIER_PERI_CLK_FI2C(9, 5), + UNIPHIER_PERI_CLK_FI2C(10, 6), + { /* sentinel */ } +#endif +}; diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h index 77ebae1..5706db5 100644 --- a/drivers/clk/uniphier/clk-uniphier.h +++ b/drivers/clk/uniphier/clk-uniphier.h @@ -75,5 +75,10 @@ extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[]; extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[]; extern const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[]; extern const struct uniphier_clk_data uniphier_mio_clk_data[]; +extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[]; +extern const struct uniphier_clk_data uniphier_sld8_peri_clk_data[]; +extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[]; +extern const struct uniphier_clk_data uniphier_pxs2_peri_clk_data[]; +extern const struct uniphier_clk_data uniphier_ld11_peri_clk_data[];
#endif /* __CLK_UNIPHIER_H__ */
priv->dev does not exist. Pass the correct pointer to udevice.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
drivers/reset/reset-uniphier.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index c74d16f..a40cea5 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c @@ -210,7 +210,8 @@ static int uniphier_reset_update(struct reset_ctl *reset_ctl, int assert) return 0; }
- dev_err(priv->dev, "reset_id=%lu was not handled\n", id); + dev_err(reset_ctl->dev, "reset_id=%lu was not handled\n", id); + return -EINVAL; }
Get clock rate from the clock driver instead of hard-coding it.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
drivers/i2c/i2c-uniphier.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/i2c-uniphier.c b/drivers/i2c/i2c-uniphier.c index 0f2734e..9100129 100644 --- a/drivers/i2c/i2c-uniphier.c +++ b/drivers/i2c/i2c-uniphier.c @@ -11,6 +11,7 @@ #include <linux/io.h> #include <linux/sizes.h> #include <linux/types.h> +#include <clk.h> #include <dm.h> #include <fdtdec.h> #include <i2c.h> @@ -36,8 +37,6 @@ struct uniphier_i2c_regs { u32 setup; /* setup time control */ };
-#define IOBUS_FREQ 100000000 - struct uniphier_i2c_priv { struct udevice *dev; struct uniphier_i2c_regs __iomem *regs; /* register base */ @@ -49,6 +48,8 @@ static int uniphier_i2c_probe(struct udevice *dev) { fdt_addr_t addr; struct uniphier_i2c_priv *priv = dev_get_priv(dev); + struct clk clk; + int ret;
addr = devfdt_get_addr(dev); if (addr == FDT_ADDR_T_NONE) @@ -58,7 +59,19 @@ static int uniphier_i2c_probe(struct udevice *dev) if (!priv->regs) return -ENOMEM;
- priv->input_clk = IOBUS_FREQ; + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + dev_err(dev, "failed to get clock\n"); + return ret; + } + + ret = clk_enable(&clk); + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + + priv->input_clk = clk_get_rate(&clk);
priv->dev = dev;
Hello Masahiro,
Am 13.10.2017 um 12:22 schrieb Masahiro Yamada:
Get clock rate from the clock driver instead of hard-coding it.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com
drivers/i2c/i2c-uniphier.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-)
Reviewed-by: Heiko Schocher hs@denx.de
bye, Heiko
Get clock rate from the clock driver instead of hard-coding it.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
drivers/i2c/i2c-uniphier-f.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/i2c-uniphier-f.c b/drivers/i2c/i2c-uniphier-f.c index eb6c9f3..6f45cc5 100644 --- a/drivers/i2c/i2c-uniphier-f.c +++ b/drivers/i2c/i2c-uniphier-f.c @@ -11,6 +11,7 @@ #include <linux/iopoll.h> #include <linux/sizes.h> #include <linux/types.h> +#include <clk.h> #include <dm.h> #include <i2c.h> #include <fdtdec.h> @@ -61,8 +62,6 @@ struct uniphier_fi2c_regs { #define I2C_BRST_RSCLO (1 << 0) /* release SCL low fixing */ };
-#define FIOCLK 50000000 - struct uniphier_fi2c_priv { struct udevice *dev; struct uniphier_fi2c_regs __iomem *regs; /* register base */ @@ -93,6 +92,8 @@ static int uniphier_fi2c_probe(struct udevice *dev) { fdt_addr_t addr; struct uniphier_fi2c_priv *priv = dev_get_priv(dev); + struct clk clk; + int ret;
addr = devfdt_get_addr(dev); if (addr == FDT_ADDR_T_NONE) @@ -102,7 +103,19 @@ static int uniphier_fi2c_probe(struct udevice *dev) if (!priv->regs) return -ENOMEM;
- priv->fioclk = FIOCLK; + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + dev_err(dev, "failed to get clock\n"); + return ret; + } + + ret = clk_enable(&clk); + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + + priv->fioclk = clk_get_rate(&clk);
priv->dev = dev;
Hello Masahiro,
Am 13.10.2017 um 12:22 schrieb Masahiro Yamada:
Get clock rate from the clock driver instead of hard-coding it.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com
drivers/i2c/i2c-uniphier-f.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-)
Reviewed-by: Heiko Schocher hs@denx.de
bye, Heiko
UniPhier 32-bit SoCs use CONFIG_SPL_OF_CONTROL. So, many nodes must be marked as dm-pre-reloc to prevent fdtgrep from stripping them off.
Sprinkling U-Boot specific properties all over the place is painful because DT files are synced with Linux from time to time.
Split u-boot,dm-pre-reloc out to uniphier-v7-u-boot.dtsi, which is appended to UniPhier V7 DTS before the build.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/dts/uniphier-ld4-ref.dts | 9 ------ arch/arm/dts/uniphier-ld4.dtsi | 3 -- arch/arm/dts/uniphier-ld6b-ref.dts | 9 ------ arch/arm/dts/uniphier-pro4-ace.dts | 9 ------ arch/arm/dts/uniphier-pro4-ref.dts | 9 ------ arch/arm/dts/uniphier-pro4-sanji.dts | 21 ------------ arch/arm/dts/uniphier-pro4.dtsi | 4 --- arch/arm/dts/uniphier-pro5-4kbox.dts | 9 ------ arch/arm/dts/uniphier-pro5.dtsi | 4 --- arch/arm/dts/uniphier-pxs2-gentil.dts | 21 ------------ arch/arm/dts/uniphier-pxs2-vodka.dts | 21 ------------ arch/arm/dts/uniphier-pxs2.dtsi | 4 --- arch/arm/dts/uniphier-sld8-ref.dts | 9 ------ arch/arm/dts/uniphier-sld8.dtsi | 3 -- arch/arm/dts/uniphier-v7-u-boot.dtsi | 61 +++++++++++++++++++++++++++++++++++ arch/arm/mach-uniphier/Kconfig | 3 ++ 16 files changed, 64 insertions(+), 135 deletions(-) create mode 100644 arch/arm/dts/uniphier-v7-u-boot.dtsi
diff --git a/arch/arm/dts/uniphier-ld4-ref.dts b/arch/arm/dts/uniphier-ld4-ref.dts index 0f50acb..0fd66e7 100644 --- a/arch/arm/dts/uniphier-ld4-ref.dts +++ b/arch/arm/dts/uniphier-ld4-ref.dts @@ -68,12 +68,3 @@ &usb1 { status = "okay"; }; - -/* for U-Boot only */ -&serial0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi index b816038..158beae 100644 --- a/arch/arm/dts/uniphier-ld4.dtsi +++ b/arch/arm/dts/uniphier-ld4.dtsi @@ -50,7 +50,6 @@ #size-cells = <1>; ranges; interrupt-parent = <&intc>; - u-boot,dm-pre-reloc;
l2: l2-cache@500c0000 { compatible = "socionext,uniphier-system-cache"; @@ -295,11 +294,9 @@ compatible = "socionext,uniphier-ld4-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; - u-boot,dm-pre-reloc;
pinctrl: pinctrl { compatible = "socionext,uniphier-ld4-pinctrl"; - u-boot,dm-pre-reloc; }; };
diff --git a/arch/arm/dts/uniphier-ld6b-ref.dts b/arch/arm/dts/uniphier-ld6b-ref.dts index bdb7f50..926d37e 100644 --- a/arch/arm/dts/uniphier-ld6b-ref.dts +++ b/arch/arm/dts/uniphier-ld6b-ref.dts @@ -70,12 +70,3 @@ &usb1 { status = "okay"; }; - -/* for U-Boot only */ -&serial0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-pro4-ace.dts b/arch/arm/dts/uniphier-pro4-ace.dts index 8161ba8..60a8c33 100644 --- a/arch/arm/dts/uniphier-pro4-ace.dts +++ b/arch/arm/dts/uniphier-pro4-ace.dts @@ -90,12 +90,3 @@ &usb3 { status = "okay"; }; - -/* for U-Boot only */ -&serial0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-pro4-ref.dts b/arch/arm/dts/uniphier-pro4-ref.dts index 360b31d..1b22f80 100644 --- a/arch/arm/dts/uniphier-pro4-ref.dts +++ b/arch/arm/dts/uniphier-pro4-ref.dts @@ -83,12 +83,3 @@ &usb1 { status = "okay"; }; - -/* for U-Boot only */ -&serial0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-pro4-sanji.dts b/arch/arm/dts/uniphier-pro4-sanji.dts index 778e2bb..950f47a 100644 --- a/arch/arm/dts/uniphier-pro4-sanji.dts +++ b/arch/arm/dts/uniphier-pro4-sanji.dts @@ -85,24 +85,3 @@ &usb3 { status = "okay"; }; - -/* for U-Boot only */ -&serial0 { - u-boot,dm-pre-reloc; -}; - -&mio_clk { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_emmc { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi index 5f39972..ea97e26 100644 --- a/arch/arm/dts/uniphier-pro4.dtsi +++ b/arch/arm/dts/uniphier-pro4.dtsi @@ -58,7 +58,6 @@ #size-cells = <1>; ranges; interrupt-parent = <&intc>; - u-boot,dm-pre-reloc;
l2: l2-cache@500c0000 { compatible = "socionext,uniphier-system-cache"; @@ -224,7 +223,6 @@ compatible = "socionext,uniphier-pro4-mioctrl", "simple-mfd", "syscon"; reg = <0x59810000 0x800>; - u-boot,dm-pre-reloc;
mio_clk: clock { compatible = "socionext,uniphier-pro4-mio-clock"; @@ -333,11 +331,9 @@ compatible = "socionext,uniphier-pro4-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; - u-boot,dm-pre-reloc;
pinctrl: pinctrl { compatible = "socionext,uniphier-pro4-pinctrl"; - u-boot,dm-pre-reloc; }; };
diff --git a/arch/arm/dts/uniphier-pro5-4kbox.dts b/arch/arm/dts/uniphier-pro5-4kbox.dts index 05597d3..1986a0b 100644 --- a/arch/arm/dts/uniphier-pro5-4kbox.dts +++ b/arch/arm/dts/uniphier-pro5-4kbox.dts @@ -55,12 +55,3 @@ &sd { status = "okay"; }; - -/* for U-Boot only */ -&serial1 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart1 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi index 950b02c..3be3acf 100644 --- a/arch/arm/dts/uniphier-pro5.dtsi +++ b/arch/arm/dts/uniphier-pro5.dtsi @@ -132,7 +132,6 @@ #size-cells = <1>; ranges; interrupt-parent = <&intc>; - u-boot,dm-pre-reloc;
l2: l2-cache@500c0000 { compatible = "socionext,uniphier-system-cache"; @@ -311,7 +310,6 @@ compatible = "socionext,uniphier-pro5-sdctrl", "simple-mfd", "syscon"; reg = <0x59810000 0x400>; - u-boot,dm-pre-reloc;
sd_clk: clock { compatible = "socionext,uniphier-pro5-sd-clock"; @@ -344,11 +342,9 @@ compatible = "socionext,uniphier-pro5-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; - u-boot,dm-pre-reloc;
pinctrl: pinctrl { compatible = "socionext,uniphier-pro5-pinctrl"; - u-boot,dm-pre-reloc; }; };
diff --git a/arch/arm/dts/uniphier-pxs2-gentil.dts b/arch/arm/dts/uniphier-pxs2-gentil.dts index 7f0f972..4397714 100644 --- a/arch/arm/dts/uniphier-pxs2-gentil.dts +++ b/arch/arm/dts/uniphier-pxs2-gentil.dts @@ -66,24 +66,3 @@ &usb1 { status = "okay"; }; - -/* for U-Boot only */ -&serial2 { - u-boot,dm-pre-reloc; -}; - -&sd_clk { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart2 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_emmc { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-pxs2-vodka.dts b/arch/arm/dts/uniphier-pxs2-vodka.dts index ec9ffb7..d29096f 100644 --- a/arch/arm/dts/uniphier-pxs2-vodka.dts +++ b/arch/arm/dts/uniphier-pxs2-vodka.dts @@ -49,24 +49,3 @@ &usb0 { status = "okay"; }; - -/* for U-Boot only */ -&serial2 { - u-boot,dm-pre-reloc; -}; - -&sd_clk { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart2 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_emmc { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi index ac84d15..dcb2515 100644 --- a/arch/arm/dts/uniphier-pxs2.dtsi +++ b/arch/arm/dts/uniphier-pxs2.dtsi @@ -120,7 +120,6 @@ #size-cells = <1>; ranges; interrupt-parent = <&intc>; - u-boot,dm-pre-reloc;
l2: l2-cache@500c0000 { compatible = "socionext,uniphier-system-cache"; @@ -297,7 +296,6 @@ compatible = "socionext,uniphier-pxs2-sdctrl", "simple-mfd", "syscon"; reg = <0x59810000 0x400>; - u-boot,dm-pre-reloc;
sd_clk: clock { compatible = "socionext,uniphier-pxs2-sd-clock"; @@ -365,11 +363,9 @@ compatible = "socionext,uniphier-pxs2-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; - u-boot,dm-pre-reloc;
pinctrl: pinctrl { compatible = "socionext,uniphier-pxs2-pinctrl"; - u-boot,dm-pre-reloc; }; };
diff --git a/arch/arm/dts/uniphier-sld8-ref.dts b/arch/arm/dts/uniphier-sld8-ref.dts index 3557bb7..478ee0a 100644 --- a/arch/arm/dts/uniphier-sld8-ref.dts +++ b/arch/arm/dts/uniphier-sld8-ref.dts @@ -72,12 +72,3 @@ &usb2 { status = "okay"; }; - -/* for U-Boot only */ -&serial0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi index 70a5ea4..a3693b0 100644 --- a/arch/arm/dts/uniphier-sld8.dtsi +++ b/arch/arm/dts/uniphier-sld8.dtsi @@ -50,7 +50,6 @@ #size-cells = <1>; ranges; interrupt-parent = <&intc>; - u-boot,dm-pre-reloc;
l2: l2-cache@500c0000 { compatible = "socionext,uniphier-system-cache"; @@ -299,11 +298,9 @@ compatible = "socionext,uniphier-sld8-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; - u-boot,dm-pre-reloc;
pinctrl: pinctrl { compatible = "socionext,uniphier-sld8-pinctrl"; - u-boot,dm-pre-reloc; }; };
diff --git a/arch/arm/dts/uniphier-v7-u-boot.dtsi b/arch/arm/dts/uniphier-v7-u-boot.dtsi new file mode 100644 index 0000000..4a0c9c0 --- /dev/null +++ b/arch/arm/dts/uniphier-v7-u-boot.dtsi @@ -0,0 +1,61 @@ +/ { + soc { + u-boot,dm-pre-reloc; + + serial@54006800 { + u-boot,dm-pre-reloc; + }; + + serial@54006900 { + u-boot,dm-pre-reloc; + }; + + serial@54006a00 { + u-boot,dm-pre-reloc; + }; + + mioctrl@59810000 { + u-boot,dm-pre-reloc; + + clock { + u-boot,dm-pre-reloc; + }; + }; + + sdctrl@59810000 { + u-boot,dm-pre-reloc; + + clock { + u-boot,dm-pre-reloc; + }; + }; + + soc-glue@5f800000 { + u-boot,dm-pre-reloc; + + pinctrl { + u-boot,dm-pre-reloc; + + emmc_grp { + u-boot,dm-pre-reloc; + }; + + uart0_grp { + u-boot,dm-pre-reloc; + }; + + uart1_grp { + u-boot,dm-pre-reloc; + }; + + uart2_grp { + u-boot,dm-pre-reloc; + }; + }; + }; + }; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index c8b5ab4..6512d42 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -117,4 +117,7 @@ config CMD_DDRMPHY_DUMP The command "ddrmphy" shows the resulting parameters of DDR Multi PHY training; it is useful for the evaluation of DDR Multi PHY training.
+config SYS_SOC + default "uniphier-v7" if ARCH_UNIPHIER_LD4_SLD8 || ARCH_UNIPHIER_V7_MULTI + default "uniphier-v8" if ARCH_UNIPHIER_V8_MULTI endif
The serial driver is probed by SPL and/or board_init_f. To get the clock from the serial driver, the clock node must be marked as u-boot,dm-pre-reloc.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/dts/uniphier-v7-u-boot.dtsi | 8 ++++++++ arch/arm/dts/uniphier-v8-u-boot.dtsi | 13 +++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 arch/arm/dts/uniphier-v8-u-boot.dtsi
diff --git a/arch/arm/dts/uniphier-v7-u-boot.dtsi b/arch/arm/dts/uniphier-v7-u-boot.dtsi index 4a0c9c0..e3854fa 100644 --- a/arch/arm/dts/uniphier-v7-u-boot.dtsi +++ b/arch/arm/dts/uniphier-v7-u-boot.dtsi @@ -30,6 +30,14 @@ }; };
+ perictrl@59820000 { + u-boot,dm-pre-reloc; + + clock { + u-boot,dm-pre-reloc; + }; + }; + soc-glue@5f800000 { u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/uniphier-v8-u-boot.dtsi b/arch/arm/dts/uniphier-v8-u-boot.dtsi new file mode 100644 index 0000000..3d83e62 --- /dev/null +++ b/arch/arm/dts/uniphier-v8-u-boot.dtsi @@ -0,0 +1,13 @@ +/ { + soc@0 { + u-boot,dm-pre-reloc; + + perictrl@59820000 { + u-boot,dm-pre-reloc; + + clock { + u-boot,dm-pre-reloc; + }; + }; + }; +};
Get clock rate from the clock driver to drop U-Boot specific property "clock-frequency".
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
drivers/serial/serial_uniphier.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c index 68895bd..a9d8b5c 100644 --- a/drivers/serial/serial_uniphier.c +++ b/drivers/serial/serial_uniphier.c @@ -6,7 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#include <common.h> +#include <clk.h> #include <dm.h> #include <linux/io.h> #include <linux/serial_reg.h> @@ -90,11 +90,12 @@ static int uniphier_serial_pending(struct udevice *dev, bool input)
static int uniphier_serial_probe(struct udevice *dev) { - DECLARE_GLOBAL_DATA_PTR; struct uniphier_serial_private_data *priv = dev_get_priv(dev); struct uniphier_serial __iomem *port; + struct clk clk; fdt_addr_t base; u32 tmp; + int ret;
base = devfdt_get_addr(dev); if (base == FDT_ADDR_T_NONE) @@ -106,8 +107,15 @@ static int uniphier_serial_probe(struct udevice *dev)
priv->membase = port;
- priv->uartclk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "clock-frequency", 0); + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + + priv->uartclk = clk_get_rate(&clk);
tmp = readl(&port->lcr_mcr); tmp &= ~LCR_MASK;
Sync with Linux 4.14-rc4. (Include some DT updates queued up for Linux 4.15.)
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/dts/uniphier-ld11.dtsi | 15 ++++-- arch/arm/dts/uniphier-ld20.dtsi | 97 ++++++++++++++++++++++++++++++++++++-- arch/arm/dts/uniphier-ld4-ref.dts | 4 ++ arch/arm/dts/uniphier-ld4.dtsi | 4 -- arch/arm/dts/uniphier-ld6b-ref.dts | 4 ++ arch/arm/dts/uniphier-pinctrl.dtsi | 15 ++++++ arch/arm/dts/uniphier-pro4.dtsi | 4 -- arch/arm/dts/uniphier-pro5.dtsi | 4 -- arch/arm/dts/uniphier-pxs2.dtsi | 51 ++++++++++++++++---- arch/arm/dts/uniphier-pxs3.dtsi | 4 -- arch/arm/dts/uniphier-sld8-ref.dts | 4 ++ arch/arm/dts/uniphier-sld8.dtsi | 4 -- 12 files changed, 174 insertions(+), 36 deletions(-)
diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi index 0cc6fd7..2ac1bfc 100644 --- a/arch/arm/dts/uniphier-ld11.dtsi +++ b/arch/arm/dts/uniphier-ld11.dtsi @@ -118,7 +118,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; - clock-frequency = <58820000>; };
serial1: serial@54006900 { @@ -129,7 +128,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; - clock-frequency = <58820000>; };
serial2: serial@54006a00 { @@ -140,7 +138,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; - clock-frequency = <58820000>; };
serial3: serial@54006b00 { @@ -151,7 +148,17 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; - clock-frequency = <58820000>; + }; + + adamv@57920000 { + compatible = "socionext,uniphier-ld11-adamv", + "simple-mfd", "syscon"; + reg = <0x57920000 0x1000>; + + adamv_rst: reset { + compatible = "socionext,uniphier-ld11-adamv-reset"; + #reset-cells = <1>; + }; };
gpio: gpio@55000000 { diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi index a7fdaa7..b74efb9 100644 --- a/arch/arm/dts/uniphier-ld20.dtsi +++ b/arch/arm/dts/uniphier-ld20.dtsi @@ -7,6 +7,8 @@ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+#include <dt-bindings/thermal/thermal.h> + /memreserve/ 0x80000000 0x02000000;
/ { @@ -46,6 +48,7 @@ clocks = <&sys_clk 32>; enable-method = "psci"; operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; };
cpu1: cpu@1 { @@ -64,6 +67,7 @@ clocks = <&sys_clk 33>; enable-method = "psci"; operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; };
cpu3: cpu@101 { @@ -173,6 +177,40 @@ <1 10 4>; };
+ thermal-zones { + cpu_thermal { + polling-delay-passive = <250>; /* 250ms */ + polling-delay = <1000>; /* 1000ms */ + thermal-sensors = <&pvtctl>; + + trips { + cpu_crit: cpu_crit { + temperature = <110000>; /* 110C */ + hysteresis = <2000>; + type = "critical"; + }; + cpu_alert: cpu_alert { + temperature = <100000>; /* 100C */ + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = <&cpu0 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert>; + cooling-device = <&cpu2 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; @@ -187,7 +225,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; - clock-frequency = <58820000>; };
serial1: serial@54006900 { @@ -198,7 +235,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; - clock-frequency = <58820000>; };
serial2: serial@54006a00 { @@ -209,7 +245,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; - clock-frequency = <58820000>; };
serial3: serial@54006b00 { @@ -220,7 +255,36 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; - clock-frequency = <58820000>; + }; + + adamv@57920000 { + compatible = "socionext,uniphier-ld20-adamv", + "simple-mfd", "syscon"; + reg = <0x57920000 0x1000>; + + adamv_rst: reset { + compatible = "socionext,uniphier-ld20-adamv-reset"; + #reset-cells = <1>; + }; + }; + + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>, + <&pinctrl 96 0 0>, + <&pinctrl 160 0 0>; + gpio-ranges-group-names = "gpio_range0", + "gpio_range1", + "gpio_range2"; + ngpios = <205>; + socionext,interrupt-ranges = <0 48 16>, <16 154 5>, + <21 217 3>; };
i2c0: i2c@58780000 { @@ -383,6 +447,24 @@ }; };
+ soc-glue@5f900000 { + compatible = "socionext,uniphier-ld20-soc-glue-debug", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + + efuse@200 { + compatible = "socionext,uniphier-efuse"; + reg = <0x200 0x68>; + }; + }; + aidet: aidet@5fc20000 { compatible = "socionext,uniphier-ld20-aidet"; reg = <0x5fc20000 0x200>; @@ -417,6 +499,13 @@ watchdog { compatible = "socionext,uniphier-wdt"; }; + + pvtctl: pvtctl { + compatible = "socionext,uniphier-ld20-thermal"; + interrupts = <0 3 4>; + #thermal-sensor-cells = <0>; + socionext,tmod-calibration = <0x0f22 0x68ee>; + }; };
usb: usb@65b00000 { diff --git a/arch/arm/dts/uniphier-ld4-ref.dts b/arch/arm/dts/uniphier-ld4-ref.dts index 0fd66e7..fb94df4 100644 --- a/arch/arm/dts/uniphier-ld4-ref.dts +++ b/arch/arm/dts/uniphier-ld4-ref.dts @@ -68,3 +68,7 @@ &usb1 { status = "okay"; }; + +&nand { + status = "okay"; +}; diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi index 158beae..49fd25b 100644 --- a/arch/arm/dts/uniphier-ld4.dtsi +++ b/arch/arm/dts/uniphier-ld4.dtsi @@ -71,7 +71,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; - clock-frequency = <36864000>; };
serial1: serial@54006900 { @@ -82,7 +81,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; - clock-frequency = <36864000>; };
serial2: serial@54006a00 { @@ -93,7 +91,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; - clock-frequency = <36864000>; };
serial3: serial@54006b00 { @@ -104,7 +101,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; - clock-frequency = <36864000>; };
gpio: gpio@55000000 { diff --git a/arch/arm/dts/uniphier-ld6b-ref.dts b/arch/arm/dts/uniphier-ld6b-ref.dts index 926d37e..9b136b8 100644 --- a/arch/arm/dts/uniphier-ld6b-ref.dts +++ b/arch/arm/dts/uniphier-ld6b-ref.dts @@ -70,3 +70,7 @@ &usb1 { status = "okay"; }; + +&nand { + status = "okay"; +}; diff --git a/arch/arm/dts/uniphier-pinctrl.dtsi b/arch/arm/dts/uniphier-pinctrl.dtsi index d5e8aaf..a1b9a6c 100644 --- a/arch/arm/dts/uniphier-pinctrl.dtsi +++ b/arch/arm/dts/uniphier-pinctrl.dtsi @@ -23,6 +23,21 @@ function = "emmc"; };
+ pinctrl_ether_mii: ether_mii_grp { + groups = "ether_mii"; + function = "ether_mii"; + }; + + pinctrl_ether_rgmii: ether_rgmii_grp { + groups = "ether_rgmii"; + function = "ether_rgmii"; + }; + + pinctrl_ether_rmii: ether_rmii_grp { + groups = "ether_rmii"; + function = "ether_rmii"; + }; + pinctrl_i2c0: i2c0_grp { groups = "i2c0"; function = "i2c0"; diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi index ea97e26..9b82903 100644 --- a/arch/arm/dts/uniphier-pro4.dtsi +++ b/arch/arm/dts/uniphier-pro4.dtsi @@ -79,7 +79,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; - clock-frequency = <73728000>; };
serial1: serial@54006900 { @@ -90,7 +89,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; - clock-frequency = <73728000>; };
serial2: serial@54006a00 { @@ -101,7 +99,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; - clock-frequency = <73728000>; };
serial3: serial@54006b00 { @@ -112,7 +109,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; - clock-frequency = <73728000>; };
gpio: gpio@55000000 { diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi index 3be3acf..ac235ff 100644 --- a/arch/arm/dts/uniphier-pro5.dtsi +++ b/arch/arm/dts/uniphier-pro5.dtsi @@ -166,7 +166,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; - clock-frequency = <73728000>; };
serial1: serial@54006900 { @@ -177,7 +176,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; - clock-frequency = <73728000>; };
serial2: serial@54006a00 { @@ -188,7 +186,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; - clock-frequency = <73728000>; };
serial3: serial@54006b00 { @@ -199,7 +196,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; - clock-frequency = <73728000>; };
gpio: gpio@55000000 { diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi index dcb2515..a05df41 100644 --- a/arch/arm/dts/uniphier-pxs2.dtsi +++ b/arch/arm/dts/uniphier-pxs2.dtsi @@ -7,6 +7,8 @@ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+#include <dt-bindings/thermal/thermal.h> + / { compatible = "socionext,uniphier-pxs2"; #address-cells = <1>; @@ -16,7 +18,7 @@ #address-cells = <1>; #size-cells = <0>;
- cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; @@ -24,9 +26,10 @@ enable-method = "psci"; next-level-cache = <&l2>; operating-points-v2 = <&cpu_opp>; + #cooling-cells = <2>; };
- cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; @@ -36,7 +39,7 @@ operating-points-v2 = <&cpu_opp>; };
- cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; @@ -46,7 +49,7 @@ operating-points-v2 = <&cpu_opp>; };
- cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; @@ -114,6 +117,35 @@ }; };
+ thermal-zones { + cpu_thermal { + polling-delay-passive = <250>; /* 250ms */ + polling-delay = <1000>; /* 1000ms */ + thermal-sensors = <&pvtctl>; + + trips { + cpu_crit: cpu_crit { + temperature = <95000>; /* 95C */ + hysteresis = <2000>; + type = "critical"; + }; + cpu_alert: cpu_alert { + temperature = <85000>; /* 85C */ + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + map { + trip = <&cpu_alert>; + cooling-device = <&cpu0 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -141,7 +173,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; - clock-frequency = <88900000>; };
serial1: serial@54006900 { @@ -152,7 +183,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; - clock-frequency = <88900000>; };
serial2: serial@54006a00 { @@ -163,7 +193,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; - clock-frequency = <88900000>; };
serial3: serial@54006b00 { @@ -174,7 +203,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; - clock-frequency = <88900000>; };
gpio: gpio@55000000 { @@ -412,6 +440,13 @@ compatible = "socionext,uniphier-pxs2-reset"; #reset-cells = <1>; }; + + pvtctl: pvtctl { + compatible = "socionext,uniphier-pxs2-thermal"; + interrupts = <0 3 4>; + #thermal-sensor-cells = <0>; + socionext,tmod-calibration = <0x0f86 0x6844>; + }; };
usb0: usb@65b00000 { diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi index a004bd1..cbab00b 100644 --- a/arch/arm/dts/uniphier-pxs3.dtsi +++ b/arch/arm/dts/uniphier-pxs3.dtsi @@ -146,7 +146,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; - clock-frequency = <58820000>; };
serial1: serial@54006900 { @@ -157,7 +156,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; - clock-frequency = <58820000>; };
serial2: serial@54006a00 { @@ -168,7 +166,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; - clock-frequency = <58820000>; };
serial3: serial@54006b00 { @@ -179,7 +176,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; - clock-frequency = <58820000>; };
gpio: gpio@55000000 { diff --git a/arch/arm/dts/uniphier-sld8-ref.dts b/arch/arm/dts/uniphier-sld8-ref.dts index 478ee0a..c94f0af 100644 --- a/arch/arm/dts/uniphier-sld8-ref.dts +++ b/arch/arm/dts/uniphier-sld8-ref.dts @@ -72,3 +72,7 @@ &usb2 { status = "okay"; }; + +&nand { + status = "okay"; +}; diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi index a3693b0..f61d2ec 100644 --- a/arch/arm/dts/uniphier-sld8.dtsi +++ b/arch/arm/dts/uniphier-sld8.dtsi @@ -71,7 +71,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; - clock-frequency = <80000000>; };
serial1: serial@54006900 { @@ -82,7 +81,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; - clock-frequency = <80000000>; };
serial2: serial@54006a00 { @@ -93,7 +91,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; - clock-frequency = <80000000>; };
serial3: serial@54006b00 { @@ -104,7 +101,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; - clock-frequency = <80000000>; };
gpio: gpio@55000000 {
ARCH_UNIPHIER_V8_MULTI depends on !SPL, so the default may be hidden. Use a clearer default.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/mach-uniphier/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 6512d42..0d48e04 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -12,7 +12,7 @@ config ARCH_UNIPHIER_32BIT
choice prompt "UniPhier SoC select" - default ARCH_UNIPHIER_V8_MULTI + default ARCH_UNIPHIER_V7_MULTI
config ARCH_UNIPHIER_LD4_SLD8 bool "UniPhier LD4/sLD8 SoCs"
2017-10-13 19:21 GMT+09:00 Masahiro Yamada yamada.masahiro@socionext.com:
- Reactor of GPIO, clk, reset drivers.
- Clean up SOC code
- Sync DT
- Use more clock drivers
- Split U-Boot specific DT property
Masahiro Yamada (20): ARM: uniphier: switch to CONFIG_ENV_IS_NOWHERE gpio: uniphier: rework single device node model ARM: dts: uniphier: update GPIO nodes pinctrl: uniphier: set PUPD_SIMPLE cap flag for PXs3 pinctrl: uniphier: simplify input enable and delete pin arrays ARM: uniphier: use pr_() instead of printf() where appropriate usb: dwc3-uniphier: replace <common.h> with <linux/bitops.h> i2c: uniphier: replace debug() with dev_dbg() i2c: uniphier-f: replace debug() with dev_dbg() clk: uniphier: rework for better clock tree structure clk: uniphier: add PXs3 clock data clk: uniphier: add peripheral clock data reset: uniphier: fix the first argument passed to dev_err() i2c: uniphier: use clk for enable and get_rate i2c: uniphier-f: use clk for enable and get_rate ARM: uniphier: split u-boot,dm-pre-reloc out to uniphier-v7-u-boot.dtsi ARM: dts: uniphier: prepare to use clock for serial serial: uniphier: use clk for enable and get_rate ARM: dts: uniphier: sync DT with Linux 4.14-rc4 ARM: uniphier: change the default of SoC select to UNIPHIER_V7_MULTI
1-11, 13, 20 applied to u-boot-uniphier.
The others have been deferred because I found the SPL size exceeds the limit depending on compiler.
participants (3)
-
Heiko Schocher -
Marek Vasut -
Masahiro Yamada