[U-Boot] [PATCH v3 1/2] armv8: ls1028a: enable workaround for USB erratum A-008997
This is supplement for patch which would handle A-008997
Compared to other Layerscape SoCs, ls1028a has moved register PCSTXSWINGFULL from SCFG to DSCR.
Signed-off-by: Ran Wang ran.wang_1@nxp.com --- Change in v3: - Add more explaination to commit message.
Change in v2: - Update commit subject to make it clearer
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 + arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 ++++ arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++ 3 files changed, 7 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 8ecd095c76..fc4e866f1e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -48,6 +48,7 @@ config ARCH_LS1028A select SYS_I2C_MXC_I2C6 select SYS_I2C_MXC_I2C7 select SYS_I2C_MXC_I2C8 + select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A008514 if !TFABOOT select SYS_FSL_ERRATUM_A009663 if !TFABOOT diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 06f3edb302..f2392f0ebf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -126,6 +126,10 @@ static void erratum_a008997(void) set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2); set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3); #endif +#elif defined(CONFIG_ARCH_LS1028A) + clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1, + 0x7F << 11, + DCSR_USB_PCSTXSWINGFULL << 11); #endif #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index dbf3215cb6..dd73de4a9a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -214,6 +214,8 @@ #define USB_PHY_RX_EQ_VAL_2 0x0080 #define USB_PHY_RX_EQ_VAL_3 0x0380 #define USB_PHY_RX_EQ_VAL_4 0x0b80 +#define DCSR_USB_IOCR1 0x108004 +#define DCSR_USB_PCSTXSWINGFULL 0x71
#define TP_ITYP_AV 0x00000001 /* Initiator available */ #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
From: Yinbo Zhu yinbo.zhu@nxp.com
Rx Compliance tests may fail intermittently at high jitter frequencies using default register values.
Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass.
Signed-off-by: Yinbo Zhu yinbo.zhu@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com --- Change in v3: - Update commit subject to remove redundant message
Change in v2: - Update commit subject to make it clearer
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index f2392f0ebf..af2d86bb9d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -143,7 +143,8 @@ static void erratum_a008997(void) out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \ out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
-#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) +#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \ + defined(CONFIG_ARCH_LS1028A)
#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ @@ -167,7 +168,8 @@ static void erratum_a009007(void) usb_phy = (void __iomem *)SCFG_USB_PHY3; PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); #endif -#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) +#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \ + defined(CONFIG_ARCH_LS1028A) void __iomem *dcsr = (void __iomem *)DCSR_BASE;
PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
-----Original Message----- From: Ran Wang ran.wang_1@nxp.com Sent: Tuesday, May 14, 2019 3:05 PM To: Albert Aribaud albert.u.boot@aribaud.net; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Cc: Yinbo Zhu yinbo.zhu@nxp.com; u-boot@lists.denx.de; Ran Wang ran.wang_1@nxp.com Subject: [PATCH v3 2/2] armv8: ls1028a: enable workaround for USB errarum A- 009007
From: Yinbo Zhu yinbo.zhu@nxp.com
Rx Compliance tests may fail intermittently at high jitter frequencies using default register values.
Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass.
Signed-off-by: Yinbo Zhu yinbo.zhu@nxp.com Signed-off-by: Ran Wang ran.wang_1@nxp.com
Change in v3:
- Update commit subject to remove redundant message
Change in v2:
- Update commit subject to make it clearer
This patch has been applied to fsl-qoriq master, awaiting upstream.
--pk
-----Original Message----- From: Ran Wang ran.wang_1@nxp.com Sent: Tuesday, May 14, 2019 3:05 PM To: Albert Aribaud albert.u.boot@aribaud.net; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Cc: Yinbo Zhu yinbo.zhu@nxp.com; u-boot@lists.denx.de; Ran Wang ran.wang_1@nxp.com Subject: [PATCH v3 1/2] armv8: ls1028a: enable workaround for USB erratum A- 008997
This is supplement for patch which would handle A-008997
Compared to other Layerscape SoCs, ls1028a has moved register PCSTXSWINGFULL from SCFG to DSCR.
Signed-off-by: Ran Wang ran.wang_1@nxp.com
Change in v3:
- Add more explaination to commit message.
Change in v2:
- Update commit subject to make it clearer
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 + arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 ++++ arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++ 3 files changed, 7 insertions(+)
This patch has been applied to fsl-qoriq master after modification in description, awaiting upstream.
--pk
participants (2)
-
Prabhakar Kushwaha -
Ran Wang