Hi Fabio,

On 08/29/2016 10:56 AM, Fabio Estevam wrote:

From: Fabio Estevam fabio.estevam@nxp.com

To be in the safe side we need to enable the CCGR clocks prior to calling arch_cpu_init().

Inspired by Tim Harvey's commit d783c2744f9 ("imx: ventana: fix boot to SD").

Signed-off-by: Fabio Estevam fabio.estevam@nxp.com

Changes since v1:

• Newly introduced in this version

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index b13f0e2..fe81042 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -842,11 +842,11 @@ static void spl_dram_init(void)

void board_init_f(ulong dummy) {

• ccgr_init();
• /* setup AIPS and disable watchdog */ arch_cpu_init();

• ccgr_init();
• /* iomux and setup of i2c */ board_early_init_f();

Reviewed-by: Eric Nelson eric@nelint.com Tested-by: Eric Nelson eric@nelint.com

Hi Fabio,

On 08/29/2016 11:48 AM, Eric Nelson wrote:

Hi Fabio,

On 08/29/2016 10:56 AM, Fabio Estevam wrote:

...

From: Fabio Estevam fabio.estevam@nxp.com

When running a NXP 4.1 kernel with U-Boot mainline we observe a hang when going into the lowest operational point of cpufreq.

After comparing the SPL DDR initialization against the DCD table from NXP U-Boot, the key difference that causes the hang is the MDREF register setting.

In all the DDR3 MX6UL boards we have the following configuration for MDREF:

I think this commit message needs work.

"we have" seems to mean that the NXP U-Boot fork has this setting, but this isn't an explanation of why.

After reviewing the manual, I think I understand why this is needed and something like this is probably better:

The i.MX6UL kernel uses a 32kHz clock for to drive refresh in low power mode. Configure the MMDC to use it as the input for refresh in MMDC_MDREF.

...

DATA 4 0x021B0020 0x00000800

,which means:

REF_SEL = 0 -->Periodic refresh cycle: 64kHz REFR = 1 ---> Refresh Rate - 2 refreshes

So adjust the MDREF initialization for MX6UL to fix the kernel hang issue.

Reported-by: Eric Nelson eric@nelint.com Signed-off-by: Fabio Estevam fabio.estevam@nxp.com

---

Changes since v1:

• Newly introduced in this version

arch/arm/cpu/armv7/mx6/ddr.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index f151eec..56d3e65 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -1183,7 +1183,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, volatile struct mmdc_p_regs *mmdc0; volatile struct mmdc_p_regs *mmdc1; u32 val;

• u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;

• u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd, refr, refsel; u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl; u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */ u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;

@@ -1472,9 +1472,15 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, MMDC1(mpzqhwctrl, val);

/* Step 12: Configure and activate periodic refresh */

• mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */

•        (7 << 11);  /* REFR: Refresh Rate - 8 refreshes */
  

I'm not understanding why this is CPU specific. Is the issue

...

• if (!is_mx6ul()) {

Table 44-15 of the 6DQ reference manual says that this will generate tREFI at 3.9uS (256kHz).

Never mind. Your comment is about the input clock, not the refresh cycle.

I do wonder if both of these settings don't over-refresh the DDR3 though.

...

• refsel = 1; /* REF_SEL: Periodic refresh cycle: 32kHz */
  

• refr = 7;   /* REFR: Refresh Rate - 8 refreshes */
  

• } else {

Table 33-15 of the 6UL manual says 7.8us (128 kHz).

...

• refsel = 0; /* REF_SEL: Periodic refresh cycle: 64kHz */
  

• refr = 1;   /* REFR: Refresh Rate - 2 refreshes */
  

• }

• mmdc0->mdref = (refsel << 14) | (refr << 11); /* Step 13: Deassert config request - init complete */ mmdc0->mdscr = 0x00000000;

I did test this patch though, and I can confirm that the problem I experienced (hang with low bus frequency) goes away with just this change, so

Tested-by: Eric Nelson eric@nelint.com