From: Peng Fan peng.fan@nxp.com

This is NXP internal validation board, no longer support it.

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/Kconfig | 14 - arch/arm/cpu/armv8/Kconfig | 2 +- .../cpu/armv8/fsl-layerscape/doc/README.qspi | 1 - board/freescale/ls1012aqds/Kconfig | 80 ----- board/freescale/ls1012aqds/MAINTAINERS | 9 - board/freescale/ls1012aqds/Makefile | 8 - board/freescale/ls1012aqds/README | 59 ---- board/freescale/ls1012aqds/eth.c | 309 ------------------ board/freescale/ls1012aqds/ls1012aqds.c | 293 ----------------- board/freescale/ls1012aqds/ls1012aqds_pfe.h | 44 --- board/freescale/ls1012aqds/ls1012aqds_qixis.h | 34 -- configs/ls1012aqds_qspi_defconfig | 95 ------ configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 87 ----- configs/ls1012aqds_tfa_defconfig | 94 ------ include/configs/ls1012aqds.h | 109 ------ 15 files changed, 1 insertion(+), 1237 deletions(-) delete mode 100644 board/freescale/ls1012aqds/Kconfig delete mode 100644 board/freescale/ls1012aqds/MAINTAINERS delete mode 100644 board/freescale/ls1012aqds/Makefile delete mode 100644 board/freescale/ls1012aqds/README delete mode 100644 board/freescale/ls1012aqds/eth.c delete mode 100644 board/freescale/ls1012aqds/ls1012aqds.c delete mode 100644 board/freescale/ls1012aqds/ls1012aqds_pfe.h delete mode 100644 board/freescale/ls1012aqds/ls1012aqds_qixis.h delete mode 100644 configs/ls1012aqds_qspi_defconfig delete mode 100644 configs/ls1012aqds_tfa_SECURE_BOOT_defconfig delete mode 100644 configs/ls1012aqds_tfa_defconfig delete mode 100644 include/configs/ls1012aqds.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index bd7fffcce0b..752e379e3c1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1482,19 +1482,6 @@ config TARGET_POPLAR making it capable of running any commercial set-top solution based on Linux or Android.

-config TARGET_LS1012AQDS - bool "Support ls1012aqds" - select ARCH_LS1012A - select ARM64 - select ARCH_SUPPORT_TFABOOT - select BOARD_LATE_INIT - select GPIO_EXTRA_HEADER - help - Support for Freescale LS1012AQDS platform. - The LS1012A Development System (QDS) is a high-performance - development platform that supports the QorIQ LS1012A - Layerscape Architecture processor. - config TARGET_LS1012ARDB bool "Support ls1012ardb" select ARCH_LS1012A @@ -2283,7 +2270,6 @@ source "board/freescale/ls1046aqds/Kconfig" source "board/freescale/ls1043ardb/Kconfig" source "board/freescale/ls1046ardb/Kconfig" source "board/freescale/ls1046afrwy/Kconfig" -source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/ls1012ardb/Kconfig" source "board/freescale/ls1012afrdm/Kconfig" source "board/freescale/lx2160a/Kconfig" diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 1305238c9d2..74fd13b95f8 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -116,7 +116,7 @@ config PSCI_RESET !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \ !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \ !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \ - !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \ + !TARGET_LS1012A2G5RDB && \ !TARGET_LS1012AFRWY && \ !TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \ !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.qspi b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.qspi index de86f4b3079..563e73023ca 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.qspi +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.qspi @@ -5,7 +5,6 @@ QSPI Boot source support Overview 2. LS2080A LS2080AQDS 3. LS1012A - LS1012AQDS LS1012ARDB 4. LS1046A LS1046AQDS diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig deleted file mode 100644 index 991ba6044db..00000000000 --- a/board/freescale/ls1012aqds/Kconfig +++ /dev/null @@ -1,80 +0,0 @@ -if TARGET_LS1012AQDS - -config SYS_BOARD - default "ls1012aqds" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls1012aqds" - -config SYS_LS_PPA_FW_ADDR - hex "PPA Firmware Addr" - default 0x40400000 - -if CHAIN_OF_TRUST -config SYS_LS_PPA_ESBC_ADDR - hex "PPA Firmware HDR Addr" - default 0x40680000 - -config SYS_LS_PFE_ESBC_ADDR - hex "PFE Firmware HDR Addr" - default 0x40700000 - -config SYS_LS_PFE_ESBC_LENGTH - hex "length of PFE Firmware HDR" - default 0xc00 -endif - -if FSL_PFE - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select PHYLIB - imply PHY_VITESSE - imply PHY_REALTEK - imply PHY_AQUANTIA - imply PHYLIB_10G - -config PFE_RGMII_RESET_WA - def_bool y - -config SYS_LS_PFE_FW_ADDR - hex "Flash address of PFE firmware" - default 0x40a00000 - -config SYS_LS_PFE_FW_LENGTH - hex "length of PFE firmware" - default 0x300000 - -config DDR_PFE_PHYS_BASEADDR - hex "PFE DDR physical base address" - default 0x03800000 - -config DDR_PFE_BASEADDR - hex "PFE DDR base address" - default 0x83800000 - -config PFE_EMAC1_PHY_ADDR - hex "PFE DDR base address" - default 0x1e - -config PFE_EMAC2_PHY_ADDR - hex "PFE DDR base address" - default 0x1 - -config PFE_SGMII_2500_PHY1_ADDR - hex "PFE DDR base address" - default 0x1 - -config PFE_SGMII_2500_PHY2_ADDR - hex "PFE DDR base address" - default 0x2 - -endif - -endif diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS deleted file mode 100644 index c1bb8d51508..00000000000 --- a/board/freescale/ls1012aqds/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -LS1012AQDS BOARD -M: Rajesh Bhagat rajesh.bhagat@nxp.com -M: Pramod Kumar pramod.kumar_1@nxp.com -S: Maintained -F: board/freescale/ls1012aqds/ -F: include/configs/ls1012aqds.h -F: configs/ls1012aqds_qspi_defconfig -F: configs/ls1012aqds_tfa_defconfig -F: configs/ls1012aqds_tfa_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile deleted file mode 100644 index 5aba9caf927..00000000000 --- a/board/freescale/ls1012aqds/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2016 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += ls1012aqds.o -obj-$(CONFIG_FSL_PFE) += eth.o diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README deleted file mode 100644 index c1956f9fd78..00000000000 --- a/board/freescale/ls1012aqds/README +++ /dev/null @@ -1,59 +0,0 @@ -Overview --------- -QorIQ LS1012A Development System (LS1012AQDS) is a high-performance -development platform, with a complete debugging environment. -The LS1012AQDS board supports the QorIQ LS1012A processor and is -optimized to support the high-bandwidth DDR3L memory and -a full complement of high-speed SerDes ports. - -LS1012A SoC Overview --------------------- -Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A -SoC overview. - -LS1012AQDS board Overview ------------------------ - - SERDES Connections, 4 lanes supporting: - - PCI Express - 3.0 - - SGMII, SGMII 2.5 - - SATA 3.0 - - DDR Controller - - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s - - QSPI Controller - - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select - signals to QSPI NOR flash memory (2 virtual banks) and the QSPI - emulator - - USB 3.0 - - One USB 3.0 controller with integrated PHY - - One high-speed USB 3.0 port - - USB 2.0 - - One USB 2.0 controller with ULPI interface - - Two enhanced secure digital host controllers: - - SDHC1 controller can be connected to onboard SDHC connector - - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices - - 2 I2C controllers - - One SATA onboard connectors - - UART - - 5 SAI - - One SAI port with audio codec SGTL5000: - • Provides MIC bias - • Provides headphone and line output - - One SAI port terminated at 2x6 header - - Three SAI Tx/Rx ports terminated at 2x3 headers - - ARM JTAG support - -Booting Options ---------------- -a) QSPI Flash Emu Boot -b) QSPI Flash 1 -c) QSPI Flash 2 - -QSPI flash map --------------- -Images | Size |QSPI Flash Address ------------------------------------------- -RCW + PBI | 1MB | 0x4000_0000 -U-boot | 1MB | 0x4010_0000 -U-boot Env | 1MB | 0x4020_0000 -PPA FIT image | 2MB | 0x4050_0000 -Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c deleted file mode 100644 index 38267acedde..00000000000 --- a/board/freescale/ls1012aqds/eth.c +++ /dev/null @@ -1,309 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - */ - -#include <common.h> -#include <dm.h> -#include <asm/io.h> -#include <netdev.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <malloc.h> -#include <asm/types.h> -#include <fsl_dtsec.h> -#include <asm/arch/soc.h> -#include <asm/arch-fsl-layerscape/config.h> -#include <asm/arch-fsl-layerscape/immap_lsch2.h> -#include <asm/arch/fsl_serdes.h> -#include <linux/delay.h> -#include "../common/qixis.h" -#include <net/pfe_eth/pfe_eth.h> -#include <dm/platform_data/pfe_dm_eth.h> -#include "ls1012aqds_qixis.h" - -#define EMI_NONE 0xFF -#define EMI1_RGMII 1 -#define EMI1_SLOT1 2 -#define EMI1_SLOT2 3 - -#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO" -#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1" - -static const char * const mdio_names[] = { - "NULL", - "LS1012AQDS_MDIO_RGMII", - "LS1012AQDS_MDIO_SLOT1", - "LS1012AQDS_MDIO_SLOT2", - "NULL", -}; - -static const char *ls1012aqds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct ls1012aqds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static void ls1012aqds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - - if (muxval < 7) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int ls1012aqds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct ls1012aqds_mdio *priv = bus->priv; - - ls1012aqds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int ls1012aqds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct ls1012aqds_mdio *priv = bus->priv; - - ls1012aqds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int ls1012aqds_mdio_reset(struct mii_dev *bus) -{ - struct ls1012aqds_mdio *priv = bus->priv; - - if (priv->realbus->reset) - return priv->realbus->reset(priv->realbus); - else - return -1; -} - -static int ls1012aqds_mdio_init(char *realbusname, u8 muxval) -{ - struct ls1012aqds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate ls1012aqds MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate ls1012aqds private data\n"); - free(bus); - return -1; - } - - bus->read = ls1012aqds_mdio_read; - bus->write = ls1012aqds_mdio_write; - bus->reset = ls1012aqds_mdio_reset; - sprintf(bus->name, ls1012aqds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - return mdio_register(bus); -} - -int pfe_eth_board_init(struct udevice *dev) -{ - static int init_done; - struct mii_dev *bus; - static const char *mdio_name; - struct pfe_mdio_info mac_mdio_info; - struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; - u8 data8; - struct pfe_eth_dev *priv = dev_get_priv(dev); - - int srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - ls1012aqds_mux_mdio(EMI1_SLOT1); - - if (!init_done) { - mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR; - mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME; - - bus = pfe_mdio_init(&mac_mdio_info); - if (!bus) { - printf("Failed to register mdio\n"); - return -1; - } - init_done = 1; - } - - if (priv->gemac_port) { - mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR; - mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME; - - bus = pfe_mdio_init(&mac_mdio_info); - if (!bus) { - printf("Failed to register mdio\n"); - return -1; - } - } - - switch (srds_s1) { - case 0x3508: - printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1); -#ifdef CONFIG_PFE_RGMII_RESET_WA - /* - * Work around for FPGA registers initialization - * This is needed for RGMII to work. - */ - printf("Reset RGMII WA....\n"); - data8 = QIXIS_READ(rst_frc[0]); - data8 |= 0x2; - QIXIS_WRITE(rst_frc[0], data8); - data8 = QIXIS_READ(rst_frc[0]); - - data8 = QIXIS_READ(res8[6]); - data8 |= 0xff; - QIXIS_WRITE(res8[6], data8); - data8 = QIXIS_READ(res8[6]); -#endif - if (priv->gemac_port) { - mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII); - if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_RGMII) - < 0) { - printf("Failed to register mdio for %s\n", mdio_name); - } - - /* MAC2 */ - mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII); - bus = miiphy_get_dev_by_name(mdio_name); - pfe_set_mdio(priv->gemac_port, bus); - pfe_set_phy_address_mode(priv->gemac_port, - CONFIG_PFE_EMAC2_PHY_ADDR, - PHY_INTERFACE_MODE_RGMII); - - } else { - mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1); - if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1) - < 0) { - printf("Failed to register mdio for %s\n", mdio_name); - } - - /* MAC1 */ - mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1); - bus = miiphy_get_dev_by_name(mdio_name); - pfe_set_mdio(priv->gemac_port, bus); - pfe_set_phy_address_mode(priv->gemac_port, - CONFIG_PFE_EMAC1_PHY_ADDR, - PHY_INTERFACE_MODE_SGMII); - } - - break; - - case 0x2205: - printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1); - /* - * Work around for FPGA registers initialization - * This is needed for RGMII to work. - */ - printf("Reset SLOT1 SLOT2....\n"); - data8 = QIXIS_READ(rst_frc[2]); - data8 |= 0xc0; - QIXIS_WRITE(rst_frc[2], data8); - mdelay(100); - data8 = QIXIS_READ(rst_frc[2]); - data8 &= 0x3f; - QIXIS_WRITE(rst_frc[2], data8); - - if (priv->gemac_port) { - mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2); - if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT2) - < 0) { - printf("Failed to register mdio for %s\n", mdio_name); - } - /* MAC2 */ - mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2); - bus = miiphy_get_dev_by_name(mdio_name); - pfe_set_mdio(1, bus); - pfe_set_phy_address_mode(1, CONFIG_PFE_SGMII_2500_PHY2_ADDR, - PHY_INTERFACE_MODE_2500BASEX); - - data8 = QIXIS_READ(brdcfg[12]); - data8 |= 0x20; - QIXIS_WRITE(brdcfg[12], data8); - - } else { - mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1); - if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1) - < 0) { - printf("Failed to register mdio for %s\n", mdio_name); - } - - /* MAC1 */ - mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1); - bus = miiphy_get_dev_by_name(mdio_name); - pfe_set_mdio(0, bus); - pfe_set_phy_address_mode(0, - CONFIG_PFE_SGMII_2500_PHY1_ADDR, - PHY_INTERFACE_MODE_2500BASEX); - } - break; - - default: - printf("ls1012aqds:unsupported SerDes PRCTL= %d\n", srds_s1); - break; - } - return 0; -} - -static struct pfe_eth_pdata pfe_pdata0 = { - .pfe_eth_pdata_mac = { - .iobase = (phys_addr_t)EMAC1_BASE_ADDR, - .phy_interface = 0, - }, - - .pfe_ddr_addr = { - .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, - .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, - }, -}; - -static struct pfe_eth_pdata pfe_pdata1 = { - .pfe_eth_pdata_mac = { - .iobase = (phys_addr_t)EMAC2_BASE_ADDR, - .phy_interface = 1, - }, - - .pfe_ddr_addr = { - .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, - .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, - }, -}; - -U_BOOT_DRVINFO(ls1012a_pfe0) = { - .name = "pfe_eth", - .plat = &pfe_pdata0, -}; - -U_BOOT_DRVINFO(ls1012a_pfe1) = { - .name = "pfe_eth", - .plat = &pfe_pdata1, -}; diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c deleted file mode 100644 index 194b5d27295..00000000000 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ /dev/null @@ -1,293 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2021 NXP - */ - -#include <common.h> -#include <i2c.h> -#include <fdt_support.h> -#include <asm/cache.h> -#include <init.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/fsl_serdes.h> -#ifdef CONFIG_FSL_LS_PPA -#include <asm/arch/ppa.h> -#endif -#include <asm/arch/fdt.h> -#include <asm/arch/mmu.h> -#include <asm/arch/soc.h> -#include <ahci.h> -#include <hwconfig.h> -#include <mmc.h> -#include <env_internal.h> -#include <scsi.h> -#include <fm_eth.h> -#include <fsl_esdhc.h> -#include <fsl_mmdc.h> -#include <spl.h> -#include <netdev.h> -#include "../common/qixis.h" -#include "ls1012aqds_qixis.h" -#include "ls1012aqds_pfe.h" -#include <net/pfe_eth/pfe/pfe_hw.h> - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - char buf[64]; - u8 sw; - - sw = QIXIS_READ(arch); - printf("Board Arch: V%d, ", sw >> 4); - printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); - - sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]); - - if (sw & QIXIS_LBMAP_ALTBANK) - printf("flash: 2\n"); - else - printf("flash: 1\n"); - - printf("FPGA: v%d (%s), build %d", - (int)QIXIS_READ(scver), qixis_read_tag(buf), - (int)qixis_read_minor()); - - /* the timestamp string contains "\n" at the end */ - printf(" on %s", qixis_read_time(buf)); - return 0; -} - -#ifdef CONFIG_TFABOOT -int dram_init(void) -{ - gd->ram_size = tfa_get_dram_size(); - if (!gd->ram_size) - gd->ram_size = CFG_SYS_SDRAM_SIZE; - - return 0; -} -#else -int dram_init(void) -{ - static const struct fsl_mmdc_info mparam = { - 0x05180000, /* mdctl */ - 0x00030035, /* mdpdc */ - 0x12554000, /* mdotc */ - 0xbabf7954, /* mdcfg0 */ - 0xdb328f64, /* mdcfg1 */ - 0x01ff00db, /* mdcfg2 */ - 0x00001680, /* mdmisc */ - 0x0f3c8000, /* mdref */ - 0x00002000, /* mdrwd */ - 0x00bf1023, /* mdor */ - 0x0000003f, /* mdasp */ - 0x0000022a, /* mpodtctrl */ - 0xa1390003, /* mpzqhwctrl */ - }; - - mmdc_init(&mparam); - gd->ram_size = CFG_SYS_SDRAM_SIZE; -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) - /* This will break-before-make MMU for DDR */ - update_early_mmu_table(); -#endif - - return 0; -} -#endif - -int board_early_init_f(void) -{ - fsl_lsch2_early_init_f(); - - return 0; -} - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ - u8 mux_sdhc_cd = 0x80; - int bus_num = 0; - -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - int ret; - - ret = i2c_get_chip_for_busnum(bus_num, CFG_SYS_I2C_FPGA_ADDR, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - dm_i2c_write(dev, 0x5a, &mux_sdhc_cd, 1); -#else - i2c_set_bus_num(bus_num); - - i2c_write(CFG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); -#endif - - return 0; -} -#endif - -int board_init(void) -{ - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + - CONFIG_SYS_CCI400_OFFSET); - - /* Set CCI-400 control override register to enable barrier - * transaction */ - if (current_el() == 3) - out_le32(&cci->ctrl_ord, - CCI400_CTRLORD_EN_BARRIER); - -#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 - erratum_a010315(); -#endif - -#ifdef CONFIG_FSL_LS_PPA - ppa_init(); -#endif - return 0; -} - -#ifdef CONFIG_FSL_PFE -void board_quiesce_devices(void) -{ - pfe_command_stop(0, NULL); -} -#endif - -int esdhc_status_fixup(void *blob, const char *compat) -{ - char esdhc0_path[] = "/soc/esdhc@1560000"; - char esdhc1_path[] = "/soc/esdhc@1580000"; - u8 card_id; - - do_fixup_by_path(blob, esdhc0_path, "status", "okay", - sizeof("okay"), 1); - - /* - * The Presence Detect 2 register detects the installation - * of cards in various PCI Express or SGMII slots. - * - * STAT_PRS2[7:5]: Specifies the type of card installed in the - * SDHC2 Adapter slot. 0b111 indicates no adapter is installed. - */ - card_id = (QIXIS_READ(present2) & 0xe0) >> 5; - - /* If no adapter is installed in SDHC2, disable SDHC2 */ - if (card_id == 0x7) - do_fixup_by_path(blob, esdhc1_path, "status", "disabled", - sizeof("disabled"), 1); - else - do_fixup_by_path(blob, esdhc1_path, "status", "okay", - sizeof("okay"), 1); - return 0; -} - -static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val, - char *enet_path, char *mdio_path) -{ - do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id", - &prop_val.busid, PFE_PROP_LEN, 1); - do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id", - &prop_val.phyid, PFE_PROP_LEN, 1); - do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val", - &prop_val.mux_val, PFE_PROP_LEN, 1); - do_fixup_by_path(set_blob, enet_path, "phy-mode", - prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1); - do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask", - &prop_val.phy_mask, PFE_PROP_LEN, 1); - return 0; -} - -static void fdt_fsl_fixup_of_pfe(void *blob) -{ - int i = 0; - struct pfe_prop_val prop_val; - void *l_blob = blob; - - struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; - unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - for (i = 0; i < NUM_ETH_NODE; i++) { - switch (srds_s1) { - case SERDES_1_G_PROTOCOL: - if (i == 0) { - prop_val.busid = cpu_to_fdt32( - ETH_1_1G_BUS_ID); - prop_val.phyid = cpu_to_fdt32( - ETH_1_1G_PHY_ID); - prop_val.mux_val = cpu_to_fdt32( - ETH_1_1G_MDIO_MUX); - prop_val.phy_mask = cpu_to_fdt32( - ETH_1G_MDIO_PHY_MASK); - prop_val.phy_mode = "sgmii"; - pfe_set_properties(l_blob, prop_val, ETH_1_PATH, - ETH_1_MDIO); - } else { - prop_val.busid = cpu_to_fdt32( - ETH_2_1G_BUS_ID); - prop_val.phyid = cpu_to_fdt32( - ETH_2_1G_PHY_ID); - prop_val.mux_val = cpu_to_fdt32( - ETH_2_1G_MDIO_MUX); - prop_val.phy_mask = cpu_to_fdt32( - ETH_1G_MDIO_PHY_MASK); - prop_val.phy_mode = "rgmii"; - pfe_set_properties(l_blob, prop_val, ETH_2_PATH, - ETH_2_MDIO); - } - break; - case SERDES_2_5_G_PROTOCOL: - if (i == 0) { - prop_val.busid = cpu_to_fdt32( - ETH_1_2_5G_BUS_ID); - prop_val.phyid = cpu_to_fdt32( - ETH_1_2_5G_PHY_ID); - prop_val.mux_val = cpu_to_fdt32( - ETH_1_2_5G_MDIO_MUX); - prop_val.phy_mask = cpu_to_fdt32( - ETH_2_5G_MDIO_PHY_MASK); - prop_val.phy_mode = "2500base-x"; - pfe_set_properties(l_blob, prop_val, ETH_1_PATH, - ETH_1_MDIO); - } else { - prop_val.busid = cpu_to_fdt32( - ETH_2_2_5G_BUS_ID); - prop_val.phyid = cpu_to_fdt32( - ETH_2_2_5G_PHY_ID); - prop_val.mux_val = cpu_to_fdt32( - ETH_2_2_5G_MDIO_MUX); - prop_val.phy_mask = cpu_to_fdt32( - ETH_2_5G_MDIO_PHY_MASK); - prop_val.phy_mode = "2500base-x"; - pfe_set_properties(l_blob, prop_val, ETH_2_PATH, - ETH_2_MDIO); - } - break; - default: - printf("serdes:[%d]\n", srds_s1); - } - } -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, struct bd_info *bd) -{ - arch_fixup_fdt(blob); - - ft_cpu_setup(blob, bd); - fdt_fsl_fixup_of_pfe(blob); - - return 0; -} -#endif diff --git a/board/freescale/ls1012aqds/ls1012aqds_pfe.h b/board/freescale/ls1012aqds/ls1012aqds_pfe.h deleted file mode 100644 index 5ab283ce8d5..00000000000 --- a/board/freescale/ls1012aqds/ls1012aqds_pfe.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017 NXP - */ - -#define ETH_1_1G_BUS_ID 0x1 -#define ETH_1_1G_PHY_ID 0x1e -#define ETH_1_1G_MDIO_MUX 0x2 -#define ETH_1G_MDIO_PHY_MASK 0xBFFFFFFD -#define ETH_1_1G_PHY_MODE "sgmii" -#define ETH_2_1G_BUS_ID 0x1 -#define ETH_2_1G_PHY_ID 0x1 -#define ETH_2_1G_MDIO_MUX 0x1 -#define ETH_2_1G_PHY_MODE "rgmii" - -#define ETH_1_2_5G_BUS_ID 0x0 -#define ETH_1_2_5G_PHY_ID 0x1 -#define ETH_1_2_5G_MDIO_MUX 0x2 -#define ETH_2_5G_MDIO_PHY_MASK 0xFFFFFFF9 -#define ETH_2_5G_PHY_MODE "2500base-x" -#define ETH_2_2_5G_BUS_ID 0x1 -#define ETH_2_2_5G_PHY_ID 0x2 -#define ETH_2_2_5G_MDIO_MUX 0x3 - -#define SERDES_1_G_PROTOCOL 0x3508 -#define SERDES_2_5_G_PROTOCOL 0x2205 - -#define PFE_PROP_LEN 4 - -#define ETH_1_PATH "/pfe@04000000/ethernet@0" -#define ETH_1_MDIO ETH_1_PATH "/mdio@0" - -#define ETH_2_PATH "/pfe@04000000/ethernet@1" -#define ETH_2_MDIO ETH_2_PATH "/mdio@0" - -#define NUM_ETH_NODE 2 - -struct pfe_prop_val { - int busid; - int phyid; - int mux_val; - int phy_mask; - char *phy_mode; -}; diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h deleted file mode 100644 index 19f522d9eaa..00000000000 --- a/board/freescale/ls1012aqds/ls1012aqds_qixis.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __LS1043AQDS_QIXIS_H__ -#define __LS1043AQDS_QIXIS_H__ - -/* Definitions of QIXIS Registers for LS1043AQDS */ - -/* BRDCFG4[4:7] select EC1 and EC2 as a pair */ -#define BRDCFG4_EMISEL_MASK 0xe0 -#define BRDCFG4_EMISEL_SHIFT 6 - -/* SYSCLK */ -#define QIXIS_SYSCLK_66 0x0 -#define QIXIS_SYSCLK_83 0x1 -#define QIXIS_SYSCLK_100 0x2 -#define QIXIS_SYSCLK_125 0x3 -#define QIXIS_SYSCLK_133 0x4 - -/* DDRCLK */ -#define QIXIS_DDRCLK_66 0x0 -#define QIXIS_DDRCLK_100 0x1 -#define QIXIS_DDRCLK_125 0x2 -#define QIXIS_DDRCLK_133 0x3 - -/* BRDCFG2 - SD clock*/ -#define QIXIS_SDCLK1_100 0x0 -#define QIXIS_SDCLK1_125 0x1 -#define QIXIS_SDCLK1_165 0x2 -#define QIXIS_SDCLK1_100_SP 0x3 - -#endif diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig deleted file mode 100644 index fcef5e5d5bb..00000000000 --- a/configs/ls1012aqds_qspi_defconfig +++ /dev/null @@ -1,95 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=25000000 -CONFIG_TARGET_LS1012AQDS=y -CONFIG_TEXT_BASE=0x40100000 -CONFIG_SYS_MALLOC_LEN=0x500000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x300000 -CONFIG_ENV_SECT_SIZE=0x40000 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" -CONFIG_FSL_LS_PPA=y -CONFIG_QSPI_AHB_INIT=y -CONFIG_AHCI=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_FSL_QIXIS=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff -CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_QSPI_BOOT=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" -CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;" -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SPI=y -CONFIG_DEFAULT_SPI_BUS=1 -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_SPI_BUS=0 -CONFIG_ENV_SPI_MAX_HZ=1000000 -CONFIG_ENV_SPI_MODE=0x03 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SATA=y -CONFIG_SCSI_AHCI=y -CONFIG_SATA_CEVA=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SF_DEFAULT_SPEED=10000000 -# CONFIG_SPI_FLASH_BAR is not set -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_FSL_PFE=y -CONFIG_E1000=y -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_DM_RTC=y -CONFIG_RTC_PCF8563=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_DSPI=y -CONFIG_FSL_QSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig deleted file mode 100644 index c2996a1372e..00000000000 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ /dev/null @@ -1,87 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=25000000 -CONFIG_TARGET_LS1012AQDS=y -CONFIG_TFABOOT=y -CONFIG_TEXT_BASE=0x82000000 -CONFIG_SYS_MALLOC_LEN=0x500000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x2000 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" -CONFIG_QSPI_AHB_INIT=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_NXP_ESBC=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_FSL_QIXIS=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff -CONFIG_DISTRO_DEFAULTS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" -# CONFIG_USE_BOOTCOMMAND is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SPI=y -CONFIG_DEFAULT_SPI_BUS=1 -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_FSL_SEC_MON_BE=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SF_DEFAULT_SPEED=10000000 -# CONFIG_SPI_FLASH_BAR is not set -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_FSL_PFE=y -CONFIG_E1000=y -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_DM_RTC=y -CONFIG_RTC_PCF8563=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_DSPI=y -CONFIG_FSL_QSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig deleted file mode 100644 index a1709f4525b..00000000000 --- a/configs/ls1012aqds_tfa_defconfig +++ /dev/null @@ -1,94 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=25000000 -CONFIG_TARGET_LS1012AQDS=y -CONFIG_TFABOOT=y -CONFIG_TEXT_BASE=0x82000000 -CONFIG_SYS_MALLOC_LEN=0x500000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x500000 -CONFIG_ENV_SECT_SIZE=0x40000 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" -CONFIG_QSPI_AHB_INIT=y -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_AHCI=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_FSL_QIXIS=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff -CONFIG_DISTRO_DEFAULTS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" -# CONFIG_USE_BOOTCOMMAND is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_MISC_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SPI=y -CONFIG_DEFAULT_SPI_BUS=1 -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_SPI_BUS=0 -CONFIG_ENV_SPI_MAX_HZ=1000000 -CONFIG_ENV_SPI_MODE=0x03 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SATA=y -CONFIG_SCSI_AHCI=y -CONFIG_SATA_CEVA=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SF_DEFAULT_SPEED=10000000 -# CONFIG_SPI_FLASH_BAR is not set -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_FSL_PFE=y -CONFIG_E1000=y -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_DM_RTC=y -CONFIG_RTC_PCF8563=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_DSPI=y -CONFIG_FSL_QSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h deleted file mode 100644 index 35e8ff05798..00000000000 --- a/include/configs/ls1012aqds.h +++ /dev/null @@ -1,109 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2021 NXP - */ - -#ifndef __LS1012AQDS_H__ -#define __LS1012AQDS_H__ - -#include "ls1012a_common.h" - -/* DDR */ -#define CFG_SYS_SDRAM_SIZE 0x40000000 - -/* - * QIXIS Definitions - */ - -#ifdef CONFIG_FSL_QIXIS -#define CFG_SYS_I2C_FPGA_ADDR 0x66 -#define QIXIS_LBMAP_BRDCFG_REG 0x04 -#define QIXIS_LBMAP_SWITCH 6 -#define QIXIS_LBMAP_MASK 0x08 -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x08 -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#endif - -/* - * I2C bus multiplexer - */ -#define I2C_MUX_PCA_ADDR_PRI 0x77 -#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ -#define I2C_RETIMER_ADDR 0x18 -#define I2C_MUX_CH_DEFAULT 0x8 -#define I2C_MUX_CH_CH7301 0xC -#define I2C_MUX_CH5 0xD -#define I2C_MUX_CH7 0xF - -#define I2C_MUX_CH_VOL_MONITOR 0xa - -/* -* RTC configuration -*/ -#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ - - -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_ADDR 0x40 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 - -#undef CFG_EXTRA_ENV_SETTINGS -#define CFG_EXTRA_ENV_SETTINGS \ - "verify=no\0" \ - "kernel_addr=0x01000000\0" \ - "kernelheader_addr=0x600000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "kernel_addr_r=0x96000000\0" \ - "fdt_addr_r=0x90000000\0" \ - "load_addr=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "kernelheader_size=0x40000\0" \ - "console=ttyS0,115200\0" \ - BOOTENV \ - "boot_scripts=ls1012aqds_boot.scr\0" \ - "boot_script_hdr=hdr_ls1012aqds_bs.out\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ - "env exists secureboot " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" \ - "qspi_bootcmd=echo Trying load from qspi..;" \ - "sf probe 0:0 && sf read $load_addr " \ - "$kernel_addr $kernel_size; env exists secureboot " \ - "&& sf read $kernelheader_addr_r $kernelheader_addr " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ - "bootm $load_addr#$board\0" - -#ifdef CONFIG_TFABOOT -#undef QSPI_NOR_BOOTCOMMAND -#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\ - "env exists secureboot && esbc_halt;" -#endif - -#include <asm/fsl_secure_boot.h> -#endif /* __LS1012AQDS_H__ */

From: Peng Fan peng.fan@nxp.com

This is NXP internal validation board, no longer support it.

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/Kconfig | 19 - board/freescale/ls1043aqds/Kconfig | 31 - board/freescale/ls1043aqds/MAINTAINERS | 15 - board/freescale/ls1043aqds/Makefile | 11 - board/freescale/ls1043aqds/README | 64 -- board/freescale/ls1043aqds/ddr.c | 146 ----- board/freescale/ls1043aqds/ddr.h | 61 -- board/freescale/ls1043aqds/eth.c | 501 --------------- board/freescale/ls1043aqds/ls1043aqds.c | 601 ------------------ board/freescale/ls1043aqds/ls1043aqds_pbi.cfg | 14 - board/freescale/ls1043aqds/ls1043aqds_qixis.h | 38 -- .../ls1043aqds/ls1043aqds_rcw_nand.cfg | 7 - .../ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg | 8 - .../ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg | 8 - configs/ls1043aqds_defconfig | 107 ---- configs/ls1043aqds_lpuart_defconfig | 109 ---- configs/ls1043aqds_nand_defconfig | 138 ---- configs/ls1043aqds_nor_ddr3_defconfig | 108 ---- configs/ls1043aqds_qspi_defconfig | 98 --- configs/ls1043aqds_sdcard_ifc_defconfig | 135 ---- configs/ls1043aqds_sdcard_qspi_defconfig | 124 ---- configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 109 ---- configs/ls1043aqds_tfa_defconfig | 116 ---- configs/ls1043ardb_SECURE_BOOT_defconfig | 97 --- configs/ls1043ardb_defconfig | 98 --- configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 122 ---- configs/ls1043ardb_nand_defconfig | 127 ---- .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 122 ---- configs/ls1043ardb_sdcard_defconfig | 125 ---- configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 95 --- configs/ls1043ardb_tfa_defconfig | 99 --- 31 files changed, 3453 deletions(-) delete mode 100644 board/freescale/ls1043aqds/Kconfig delete mode 100644 board/freescale/ls1043aqds/MAINTAINERS delete mode 100644 board/freescale/ls1043aqds/Makefile delete mode 100644 board/freescale/ls1043aqds/README delete mode 100644 board/freescale/ls1043aqds/ddr.c delete mode 100644 board/freescale/ls1043aqds/ddr.h delete mode 100644 board/freescale/ls1043aqds/eth.c delete mode 100644 board/freescale/ls1043aqds/ls1043aqds.c delete mode 100644 board/freescale/ls1043aqds/ls1043aqds_pbi.cfg delete mode 100644 board/freescale/ls1043aqds/ls1043aqds_qixis.h delete mode 100644 board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg delete mode 100644 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg delete mode 100644 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg delete mode 100644 configs/ls1043aqds_defconfig delete mode 100644 configs/ls1043aqds_lpuart_defconfig delete mode 100644 configs/ls1043aqds_nand_defconfig delete mode 100644 configs/ls1043aqds_nor_ddr3_defconfig delete mode 100644 configs/ls1043aqds_qspi_defconfig delete mode 100644 configs/ls1043aqds_sdcard_ifc_defconfig delete mode 100644 configs/ls1043aqds_sdcard_qspi_defconfig delete mode 100644 configs/ls1043aqds_tfa_SECURE_BOOT_defconfig delete mode 100644 configs/ls1043aqds_tfa_defconfig delete mode 100644 configs/ls1043ardb_SECURE_BOOT_defconfig delete mode 100644 configs/ls1043ardb_defconfig delete mode 100644 configs/ls1043ardb_nand_SECURE_BOOT_defconfig delete mode 100644 configs/ls1043ardb_nand_defconfig delete mode 100644 configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig delete mode 100644 configs/ls1043ardb_sdcard_defconfig delete mode 100644 configs/ls1043ardb_tfa_SECURE_BOOT_defconfig delete mode 100644 configs/ls1043ardb_tfa_defconfig

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c004e9256da..adc1b9d6e30 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1668,24 +1668,6 @@ config TARGET_LS1021AIOT development platform that supports the QorIQ LS1021A Layerscape Architecture processor.

-config TARGET_LS1043AQDS - bool "Support ls1043aqds" - select ARCH_LS1043A - select ARM64 - select ARMV8_MULTIENTRY - select ARCH_SUPPORT_TFABOOT - select BOARD_EARLY_INIT_F - select BOARD_LATE_INIT - select SUPPORT_SPL - select FSL_DDR_INTERACTIVE if !SPL - select FSL_DSPI if !SPL_NO_DSPI - select DM_SPI_FLASH if FSL_DSPI - select GPIO_EXTRA_HEADER - imply SCSI - imply SCSI_AHCI - help - Support for Freescale LS1043AQDS platform. - config TARGET_LS1043ARDB bool "Support ls1043ardb" select ARCH_LS1043A @@ -2242,7 +2224,6 @@ source "board/freescale/ls2080aqds/Kconfig" source "board/freescale/ls2080ardb/Kconfig" source "board/freescale/ls1088a/Kconfig" source "board/freescale/ls1028a/Kconfig" -source "board/freescale/ls1043aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" source "board/freescale/ls1021atsn/Kconfig" source "board/freescale/ls1021aiot/Kconfig" diff --git a/board/freescale/ls1043aqds/Kconfig b/board/freescale/ls1043aqds/Kconfig deleted file mode 100644 index 4be445e8c8f..00000000000 --- a/board/freescale/ls1043aqds/Kconfig +++ /dev/null @@ -1,31 +0,0 @@ -if TARGET_LS1043AQDS - -config SYS_BOARD - default "ls1043aqds" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls1043aqds" - -if FSL_LS_PPA -config SYS_LS_PPA_FW_ADDR - hex "PPA Firmware Addr" - default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT - default 0x60400000 if SYS_LS_PPA_FW_IN_XIP - default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND - -if CHAIN_OF_TRUST -config SYS_LS_PPA_ESBC_ADDR - hex "PPA Firmware HDR Addr" - default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT - default 0x60680000 if SYS_LS_PPA_FW_IN_XIP - default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND -endif -endif - -endif diff --git a/board/freescale/ls1043aqds/MAINTAINERS b/board/freescale/ls1043aqds/MAINTAINERS deleted file mode 100644 index 9fb6cc85cd0..00000000000 --- a/board/freescale/ls1043aqds/MAINTAINERS +++ /dev/null @@ -1,15 +0,0 @@ -LS1043AQDS BOARD -M: Mingkai Hu mingkai.hu@nxp.com -M: Rajesh Bhagat rajesh.bhagat@nxp.com -S: Maintained -F: board/freescale/ls1043aqds/ -F: include/configs/ls1043aqds.h -F: configs/ls1043aqds_defconfig -F: configs/ls1043aqds_nor_ddr3_defconfig -F: configs/ls1043aqds_nand_defconfig -F: configs/ls1043aqds_sdcard_ifc_defconfig -F: configs/ls1043aqds_sdcard_qspi_defconfig -F: configs/ls1043aqds_qspi_defconfig -F: configs/ls1043aqds_lpuart_defconfig -F: configs/ls1043aqds_tfa_defconfig -F: configs/ls1043aqds_tfa_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1043aqds/Makefile b/board/freescale/ls1043aqds/Makefile deleted file mode 100644 index 49d8d7d9b96..00000000000 --- a/board/freescale/ls1043aqds/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright 2015 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += ddr.o -ifndef CONFIG_SPL_BUILD -obj-y += eth.o -endif -obj-y += ls1043aqds.o diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README deleted file mode 100644 index f5aa51da87e..00000000000 --- a/board/freescale/ls1043aqds/README +++ /dev/null @@ -1,64 +0,0 @@ -Overview --------- -The LS1043A Development System (QDS) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS1043A -LayerScape Architecture processor. The LS1043AQDS provides SW development -platform for the Freescale LS1043A processor series, with a complete -debugging environment. - -LS1043A SoC Overview --------------------- -Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A -SoC overview. - - LS1043AQDS board Overview - ----------------------- - - SERDES Connections, 4 lanes supporting: - - PCI Express - 3.0 - - SGMII, SGMII 2.5 - - QSGMII - - SATA 3.0 - - 10GBase-R - - DDR Controller - - 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s - -IFC/Local Bus - - One in-socket 128 MB NOR flash 16-bit data bus - - One 512 MB NAND flash with ECC support - - PromJet Port - - FPGA connection - - USB 3.0 - - Three high speed USB 3.0 ports - - First USB 3.0 port configured as Host with Type-A connector - - The other two USB 3.0 ports configured as OTG with micro-AB connector - - SDHC port connects directly to an adapter card slot, featuring: - - Optional clock feedback paths, and optional high-speed voltage translation assistance - - SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC - - eMMC memory devices - - DSPI: Onboard support for three SPI flash memory devices - - 4 I2C controllers - - One SATA onboard connectors - - UART - - Two 4-pin serial ports at up to 115.2 Kbit/s - - Two DB9 D-Type connectors supporting one Serial port each - - ARM JTAG support - -Memory map from core's view ----------------------------- -Start Address End Address Description Size -0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB -0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB -0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB -0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB -0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB -0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB -0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB -0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB -0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB - -Booting Options ---------------- -a) Promjet Boot -b) NOR boot -c) NAND boot -d) SD boot -e) QSPI boot diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c deleted file mode 100644 index 23947bdb84c..00000000000 --- a/board/freescale/ls1043aqds/ddr.c +++ /dev/null @@ -1,146 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> -#ifdef CONFIG_FSL_DEEP_SLEEP -#include <fsl_sleep.h> -#endif -#include <log.h> -#include <asm/arch/clock.h> -#include <asm/global_data.h> -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 3) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - pbsp = udimms[0]; - - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->cpo_override = pbsp->cpo_override; - popts->write_data_delay = - pbsp->write_data_delay; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found for %lu MT/s\n", - ddr_freq); - printf("Trying to use the highest speed (%u) parameters\n", - pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); - - /* force DDR bus width to 32 bits */ - popts->data_bus_width = 1; - popts->otf_burst_chop_en = 0; - popts->burst_length = DDR_BL8; - popts->bstopre = 0; /* enable auto precharge */ - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 1; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - -#ifdef CONFIG_SYS_FSL_DDR4 - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | - DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ - - /* optimize cpo for erratum A-009942 */ - popts->cpo_sample = 0x59; -#else - popts->cswl_override = DDR_CSWL_CS0; - - /* DHC_EN =1, ODT = 75 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); -#endif -} - -#ifdef CONFIG_TFABOOT -int fsl_initdram(void) -{ - gd->ram_size = tfa_get_dram_size(); - if (!gd->ram_size) - gd->ram_size = fsl_ddr_sdram_size(); - - return 0; -} -#else -int fsl_initdram(void) -{ - phys_size_t dram_size; - -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) - gd->ram_size = fsl_ddr_sdram_size(); - - return 0; -#else - puts("Initializing DDR....using SPD\n"); - - dram_size = fsl_ddr_sdram(); -#endif - erratum_a008850_post(); - -#ifdef CONFIG_FSL_DEEP_SLEEP - fsl_dp_ddr_restore(); -#endif - - gd->ram_size = dram_size; - - return 0; -} -#endif diff --git a/board/freescale/ls1043aqds/ddr.h b/board/freescale/ls1043aqds/ddr.h deleted file mode 100644 index 65b0250d370..00000000000 --- a/board/freescale/ls1043aqds/ddr.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __DDR_H__ -#define __DDR_H__ - -extern void erratum_a008850_post(void); - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; - u32 cpo_override; - u32 write_data_delay; - u32 force_2t; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | - */ -#ifdef CONFIG_SYS_FSL_DDR4 - {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, - {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E0A,}, - {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, - {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,}, -#elif defined(CONFIG_SYS_FSL_DDR3) - {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, - {2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, -#else -#error DDR type not defined -#endif - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; - -#endif diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c deleted file mode 100644 index cd1f83e3d06..00000000000 --- a/board/freescale/ls1043aqds/eth.c +++ /dev/null @@ -1,501 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * Copyright 2019 NXP - */ - -#include <common.h> -#include <log.h> -#include <net.h> -#include <asm/io.h> -#include <netdev.h> -#include <fdt_support.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <fsl_dtsec.h> -#include <linux/libfdt.h> -#include <malloc.h> -#include <asm/arch/fsl_serdes.h> - -#include "../common/qixis.h" -#include "../common/fman.h" -#include "ls1043aqds_qixis.h" - -#define EMI_NONE 0xFF -#define EMI1_RGMII1 0 -#define EMI1_RGMII2 1 -#define EMI1_SLOT1 2 -#define EMI1_SLOT2 3 -#define EMI1_SLOT3 4 -#define EMI1_SLOT4 5 -#define EMI2 6 - -static const char * const mdio_names[] = { - "LS1043AQDS_MDIO_RGMII1", - "LS1043AQDS_MDIO_RGMII2", - "LS1043AQDS_MDIO_SLOT1", - "LS1043AQDS_MDIO_SLOT2", - "LS1043AQDS_MDIO_SLOT3", - "LS1043AQDS_MDIO_SLOT4", - "NULL", -}; - -/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */ -#ifdef CONFIG_FMAN_ENET -static int mdio_mux[NUM_FM_PORTS]; - -static u8 lane_to_slot[] = {1, 2, 3, 4}; -#endif - -static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u8 muxval) -{ - struct mii_dev *bus; - const char *name; - - if (muxval > EMI2) - return NULL; - - name = ls1043aqds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -#ifdef CONFIG_FMAN_ENET -struct ls1043aqds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static void ls1043aqds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - - if (muxval < 7) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct ls1043aqds_mdio *priv = bus->priv; - - ls1043aqds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct ls1043aqds_mdio *priv = bus->priv; - - ls1043aqds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, - regnum, value); -} - -static int ls1043aqds_mdio_reset(struct mii_dev *bus) -{ - struct ls1043aqds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int ls1043aqds_mdio_init(char *realbusname, u8 muxval) -{ - struct ls1043aqds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate ls1043aqds MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate ls1043aqds private data\n"); - free(bus); - return -1; - } - - bus->read = ls1043aqds_mdio_read; - bus->write = ls1043aqds_mdio_write; - bus->reset = ls1043aqds_mdio_reset; - strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - struct fixed_link f_link; - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - if (port == FM1_DTSEC9) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s1-p1"); - } else if (port == FM1_DTSEC2) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s2-p1"); - } else if (port == FM1_DTSEC5) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s3-p1"); - } else if (port == FM1_DTSEC6) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s4-p1"); - } - } else if (fm_info_get_enet_if(port) == - PHY_INTERFACE_MODE_2500BASEX) { - /* 2.5G SGMII interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(1000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 2.5G SGMII */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "2500base-x"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { - switch (mdio_mux[port]) { - case EMI1_SLOT1: - switch (port) { - case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p1"); - break; - case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p2"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p3"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p4"); - break; - default: - break; - } - break; - case EMI1_SLOT2: - switch (port) { - case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p1"); - break; - case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p2"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p3"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p4"); - break; - default: - break; - } - break; - default: - break; - } - fdt_delprop(fdt, offset, "phy-connection-type"); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "qsgmii"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && - port == FM1_10GEC1) { - /* 10GBase-R interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(10000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 10GBase-R */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - int i; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_QSGMII: - switch (mdio_mux[i]) { - case EMI1_SLOT1: - fdt_status_okay_by_alias(fdt, "emi1-slot1"); - break; - case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, "emi1-slot2"); - break; - case EMI1_SLOT3: - fdt_status_okay_by_alias(fdt, "emi1-slot3"); - break; - case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1-slot4"); - break; - default: - break; - } - break; - case PHY_INTERFACE_MODE_XGMII: - break; - default: - break; - } - } -} - -int board_eth_init(struct bd_info *bis) -{ - int i, idx, lane, slot, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Register the muxing front-ends to the MDIO buses */ - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); - ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - switch (srds_s1) { - case 0x2555: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - break; - case 0x4555: - case 0x4558: - /* QSGMII on lane A, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT1_PHY_ADDR_S1); - fm_info_set_phy_address(FM1_DTSEC2, - QSGMII_CARD_PORT2_PHY_ADDR_S1); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT3_PHY_ADDR_S1); - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT4_PHY_ADDR_S1); - break; - case 0x1355: - /* SGMII on lane B, MAC 2*/ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x2355: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - /* SGMII on lane B, MAC 2*/ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x3335: - /* SGMII on lane C, MAC 5 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); - case 0x3355: - case 0x3358: - /* SGMII on lane B, MAC 2 */ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - case 0x3555: - case 0x3558: - /* SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x1455: - /* QSGMII on lane B, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT1_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC2, - QSGMII_CARD_PORT2_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT3_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT4_PHY_ADDR_S2); - break; - case 0x2455: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - /* QSGMII on lane B, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT1_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC2, - QSGMII_CARD_PORT2_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT3_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT4_PHY_ADDR_S2); - break; - case 0x2255: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - /* 2.5G SGMII on lane B, MAC 2 */ - fm_info_set_phy_address(FM1_DTSEC2, 2); - break; - case 0x3333: - /* SGMII on lane A/B/C/D, MAC 9/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC9, - SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, - SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC5, - SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, - SGMII_CARD_PORT1_PHY_ADDR); - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n", - srds_s1); - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - idx = i - FM1_DTSEC1; - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_2500BASEX: - case PHY_INTERFACE_MODE_QSGMII: - if (interface == PHY_INTERFACE_MODE_SGMII) { - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1 + idx); - } else if (interface == PHY_INTERFACE_MODE_2500BASEX) { - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_2500_FM1_DTSEC1 + idx); - } else { - lane = serdes_get_first_lane(FSL_SRDS_1, - QSGMII_FM1_A); - } - - if (lane < 0) - break; - - slot = lane_to_slot[lane]; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - - switch (slot) { - case 1: - mdio_mux[i] = EMI1_SLOT1; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 2: - mdio_mux[i] = EMI1_SLOT2; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - default: - break; - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - if (i == FM1_DTSEC3) - mdio_mux[i] = EMI1_RGMII1; - else if (i == FM1_DTSEC4) - mdio_mux[i] = EMI1_RGMII2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - cpu_eth_init(bis); - - return pci_eth_init(bis); -} -#endif /* CONFIG_FMAN_ENET */ diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c deleted file mode 100644 index 841d8b59bb4..00000000000 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ /dev/null @@ -1,601 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * Copyright 2019-2020 NXP - */ - -#include <common.h> -#include <clock_legacy.h> -#include <i2c.h> -#include <fdt_support.h> -#include <fsl_ddr_sdram.h> -#include <init.h> -#include <log.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/fsl_serdes.h> -#include <asm/arch/ppa.h> -#include <asm/arch/fdt.h> -#include <asm/arch/mmu.h> -#include <asm/arch/cpu.h> -#include <asm/arch/soc.h> -#include <asm/arch-fsl-layerscape/fsl_icid.h> -#include <ahci.h> -#include <hwconfig.h> -#include <mmc.h> -#include <scsi.h> -#include <fm_eth.h> -#include <fsl_esdhc.h> -#include <fsl_ifc.h> -#include <spl.h> -#include "../common/i2c_mux.h" - -#include "../common/qixis.h" -#include "ls1043aqds_qixis.h" - -DECLARE_GLOBAL_DATA_PTR; - -enum { - MUX_TYPE_GPIO, -}; - -/* LS1043AQDS serdes mux */ -#define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */ -#define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */ -#define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */ -#define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */ -#define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */ -#define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */ -#define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */ -#define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */ -#define CFG_UART_MUX_MASK 0x6 -#define CFG_UART_MUX_SHIFT 1 -#define CFG_LPUART_EN 0x1 - -#ifdef CONFIG_TFABOOT -struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { - { - "nor0", - CFG_SYS_NOR0_CSPR, - CFG_SYS_NOR0_CSPR_EXT, - CFG_SYS_NOR_AMASK, - CFG_SYS_NOR_CSOR, - { - CFG_SYS_NOR_FTIM0, - CFG_SYS_NOR_FTIM1, - CFG_SYS_NOR_FTIM2, - CFG_SYS_NOR_FTIM3 - }, - - }, - { - "nor1", - CFG_SYS_NOR1_CSPR, - CFG_SYS_NOR1_CSPR_EXT, - CFG_SYS_NOR_AMASK, - CFG_SYS_NOR_CSOR, - { - CFG_SYS_NOR_FTIM0, - CFG_SYS_NOR_FTIM1, - CFG_SYS_NOR_FTIM2, - CFG_SYS_NOR_FTIM3 - }, - }, - { - "nand", - CFG_SYS_NAND_CSPR, - CFG_SYS_NAND_CSPR_EXT, - CFG_SYS_NAND_AMASK, - CFG_SYS_NAND_CSOR, - { - CFG_SYS_NAND_FTIM0, - CFG_SYS_NAND_FTIM1, - CFG_SYS_NAND_FTIM2, - CFG_SYS_NAND_FTIM3 - }, - }, - { - "fpga", - CFG_SYS_FPGA_CSPR, - CFG_SYS_FPGA_CSPR_EXT, - CFG_SYS_FPGA_AMASK, - CFG_SYS_FPGA_CSOR, - { - CFG_SYS_FPGA_FTIM0, - CFG_SYS_FPGA_FTIM1, - CFG_SYS_FPGA_FTIM2, - CFG_SYS_FPGA_FTIM3 - }, - } -}; - -struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { - { - "nand", - CFG_SYS_NAND_CSPR, - CFG_SYS_NAND_CSPR_EXT, - CFG_SYS_NAND_AMASK, - CFG_SYS_NAND_CSOR, - { - CFG_SYS_NAND_FTIM0, - CFG_SYS_NAND_FTIM1, - CFG_SYS_NAND_FTIM2, - CFG_SYS_NAND_FTIM3 - }, - }, - { - "nor0", - CFG_SYS_NOR0_CSPR, - CFG_SYS_NOR0_CSPR_EXT, - CFG_SYS_NOR_AMASK, - CFG_SYS_NOR_CSOR, - { - CFG_SYS_NOR_FTIM0, - CFG_SYS_NOR_FTIM1, - CFG_SYS_NOR_FTIM2, - CFG_SYS_NOR_FTIM3 - }, - }, - { - "nor1", - CFG_SYS_NOR1_CSPR, - CFG_SYS_NOR1_CSPR_EXT, - CFG_SYS_NOR_AMASK, - CFG_SYS_NOR_CSOR, - { - CFG_SYS_NOR_FTIM0, - CFG_SYS_NOR_FTIM1, - CFG_SYS_NOR_FTIM2, - CFG_SYS_NOR_FTIM3 - }, - }, - { - "fpga", - CFG_SYS_FPGA_CSPR, - CFG_SYS_FPGA_CSPR_EXT, - CFG_SYS_FPGA_AMASK, - CFG_SYS_FPGA_CSOR, - { - CFG_SYS_FPGA_FTIM0, - CFG_SYS_FPGA_FTIM1, - CFG_SYS_FPGA_FTIM2, - CFG_SYS_FPGA_FTIM3 - }, - } -}; - -void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) -{ - enum boot_src src = get_boot_src(); - - if (src == BOOT_SOURCE_IFC_NAND) - regs_info->regs = ifc_cfg_nand_boot; - else - regs_info->regs = ifc_cfg_nor_boot; - regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; -} -#endif - -int checkboard(void) -{ -#ifdef CONFIG_TFABOOT - enum boot_src src = get_boot_src(); -#endif - char buf[64]; -#ifndef CONFIG_SD_BOOT - u8 sw; -#endif - - puts("Board: LS1043AQDS, boot from "); - -#ifdef CONFIG_TFABOOT - if (src == BOOT_SOURCE_SD_MMC) - puts("SD\n"); - else { -#endif - -#ifdef CONFIG_SD_BOOT - puts("SD\n"); -#else - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - printf("vBank: %d\n", sw); - else if (sw == 0x8) - puts("PromJet\n"); - else if (sw == 0x9) - puts("NAND\n"); - else if (sw == 0xF) - printf("QSPI\n"); - else - printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); -#endif - -#ifdef CONFIG_TFABOOT - } -#endif - printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", - QIXIS_READ(id), QIXIS_READ(arch)); - - printf("FPGA: v%d (%s), build %d\n", - (int)QIXIS_READ(scver), qixis_read_tag(buf), - (int)qixis_read_minor()); - - return 0; -} - -bool if_board_diff_clk(void) -{ - u8 diff_conf = QIXIS_READ(brdcfg[11]); - - return diff_conf & 0x40; -} - -unsigned long get_board_sys_clk(void) -{ - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); - - switch (sysclk_conf & 0x0f) { - case QIXIS_SYSCLK_64: - return 64000000; - case QIXIS_SYSCLK_83: - return 83333333; - case QIXIS_SYSCLK_100: - return 100000000; - case QIXIS_SYSCLK_125: - return 125000000; - case QIXIS_SYSCLK_133: - return 133333333; - case QIXIS_SYSCLK_150: - return 150000000; - case QIXIS_SYSCLK_160: - return 160000000; - case QIXIS_SYSCLK_166: - return 166666666; - } - - return 66666666; -} - -unsigned long get_board_ddr_clk(void) -{ - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); - - if (if_board_diff_clk()) - return get_board_sys_clk(); - switch ((ddrclk_conf & 0x30) >> 4) { - case QIXIS_DDRCLK_100: - return 100000000; - case QIXIS_DDRCLK_125: - return 125000000; - case QIXIS_DDRCLK_133: - return 133333333; - } - - return 66666666; -} - -int dram_init(void) -{ - /* - * When resuming from deep sleep, the I2C channel may not be - * in the default channel. So, switch to the default channel - * before accessing DDR SPD. - * - * PCA9547 mount on I2C1 bus - */ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - fsl_initdram(); -#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ - defined(CONFIG_SPL_BUILD) - /* This will break-before-make MMU for DDR */ - update_early_mmu_table(); -#endif - - return 0; -} - -int i2c_multiplexer_select_vid_channel(u8 channel) -{ - return select_i2c_ch_pca9547(channel, 0); -} - -void board_retimer_init(void) -{ - u8 reg; - int bus_num = 0; - - /* Retimer is connected to I2C1_CH7_CH5 */ - select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num); - reg = I2C_MUX_CH5; -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - int ret; - - ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return; - } - dm_i2c_write(dev, 0, &reg, 1); - - /* Access to Control/Shared register */ - ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return; - } - - reg = 0x0; - dm_i2c_write(dev, 0xff, &reg, 1); - - /* Read device revision and ID */ - dm_i2c_read(dev, 1, &reg, 1); - debug("Retimer version id = 0x%x\n", reg); - - /* Enable Broadcast. All writes target all channel register sets */ - reg = 0x0c; - dm_i2c_write(dev, 0xff, &reg, 1); - - /* Reset Channel Registers */ - dm_i2c_read(dev, 0, &reg, 1); - reg |= 0x4; - dm_i2c_write(dev, 0, &reg, 1); - - /* Enable override divider select and Enable Override Output Mux */ - dm_i2c_read(dev, 9, &reg, 1); - reg |= 0x24; - dm_i2c_write(dev, 9, &reg, 1); - - /* Select VCO Divider to full rate (000) */ - dm_i2c_read(dev, 0x18, &reg, 1); - reg &= 0x8f; - dm_i2c_write(dev, 0x18, &reg, 1); - - /* Selects active PFD MUX Input as Re-timed Data (001) */ - dm_i2c_read(dev, 0x1e, &reg, 1); - reg &= 0x3f; - reg |= 0x20; - dm_i2c_write(dev, 0x1e, &reg, 1); - - /* Set data rate as 10.3125 Gbps */ - reg = 0x0; - dm_i2c_write(dev, 0x60, &reg, 1); - reg = 0xb2; - dm_i2c_write(dev, 0x61, &reg, 1); - reg = 0x90; - dm_i2c_write(dev, 0x62, &reg, 1); - reg = 0xb3; - dm_i2c_write(dev, 0x63, &reg, 1); - reg = 0xcd; - dm_i2c_write(dev, 0x64, &reg, 1); -#else - i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1); - - /* Access to Control/Shared register */ - reg = 0x0; - i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1); - - /* Read device revision and ID */ - i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1); - debug("Retimer version id = 0x%x\n", reg); - - /* Enable Broadcast. All writes target all channel register sets */ - reg = 0x0c; - i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1); - - /* Reset Channel Registers */ - i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1); - reg |= 0x4; - i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1); - - /* Enable override divider select and Enable Override Output Mux */ - i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1); - reg |= 0x24; - i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1); - - /* Select VCO Divider to full rate (000) */ - i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1); - reg &= 0x8f; - i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1); - - /* Selects active PFD MUX Input as Re-timed Data (001) */ - i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1); - reg &= 0x3f; - reg |= 0x20; - i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1); - - /* Set data rate as 10.3125 Gbps */ - reg = 0x0; - i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1); - reg = 0xb2; - i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1); - reg = 0x90; - i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1); - reg = 0xb3; - i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1); - reg = 0xcd; - i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1); -#endif - - /* Return the default channel */ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num); -} - -int board_early_init_f(void) -{ - u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR; -#ifdef CONFIG_HAS_FSL_XHCI_USB - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; - u32 usb_pwrfault; -#endif -#ifdef CONFIG_LPUART - u8 uart; -#endif - - /* - * Enable secure system counter for timer - */ - out_le32(cntcr, 0x1); - -#if defined(CONFIG_SYS_I2C_EARLY_INIT) - i2c_early_init_f(); -#endif - fsl_lsch2_early_init_f(); - -#ifdef CONFIG_HAS_FSL_XHCI_USB - out_be32(&scfg->rcwpmuxcr0, 0x3333); - out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); - usb_pwrfault = - (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) | - (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) | - (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT); - out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); -#endif - -#ifdef CONFIG_LPUART - /* We use lpuart0 as system console */ - uart = QIXIS_READ(brdcfg[14]); - uart &= ~CFG_UART_MUX_MASK; - uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; - QIXIS_WRITE(brdcfg[14], uart); -#endif - - return 0; -} - -#ifdef CONFIG_FSL_DEEP_SLEEP -/* determine if it is a warm boot */ -bool is_warm_boot(void) -{ -#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) - struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; - - if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) - return 1; - - return 0; -} -#endif - -int config_board_mux(int ctrl_type) -{ - u8 reg14; - - reg14 = QIXIS_READ(brdcfg[14]); - - switch (ctrl_type) { - case MUX_TYPE_GPIO: - reg14 = (reg14 & (~0x30)) | 0x20; - break; - default: - puts("Unsupported mux interface type\n"); - return -1; - } - - QIXIS_WRITE(brdcfg[14], reg14); - - return 0; -} - -int config_serdes_mux(void) -{ - return 0; -} - - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ - if (hwconfig("gpio")) - config_board_mux(MUX_TYPE_GPIO); - - return 0; -} -#endif - -int board_init(void) -{ -#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 - erratum_a010315(); -#endif - - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - board_retimer_init(); - -#ifdef CFG_SYS_FSL_SERDES - config_serdes_mux(); -#endif - -#ifdef CONFIG_FSL_LS_PPA - ppa_init(); -#endif - - return 0; -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, struct bd_info *bd) -{ - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; - u8 reg; - - /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; - - fdt_fixup_memory_banks(blob, base, size, 2); - ft_cpu_setup(blob, bd); - -#ifdef CONFIG_FMAN_ENET - fdt_fixup_board_enet(blob); -#endif - - fdt_fixup_icid(blob); - - reg = QIXIS_READ(brdcfg[0]); - reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - /* Disable IFC if QSPI is enabled */ - if (reg == 0xF) - do_fixup_by_compat(blob, "fsl,ifc", - "status", "disabled", 8 + 1, 1); - - return 0; -} -#endif - -u8 flash_read8(void *addr) -{ - return __raw_readb(addr + 1); -} - -void flash_write16(u16 val, void *addr) -{ - u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); - - __raw_writew(shftval, addr); -} - -u16 flash_read16(void *addr) -{ - u16 val = __raw_readw(addr); - - return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); -} - -#if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) -void *env_sf_get_env_addr(void) -{ - return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); -} -#endif diff --git a/board/freescale/ls1043aqds/ls1043aqds_pbi.cfg b/board/freescale/ls1043aqds/ls1043aqds_pbi.cfg deleted file mode 100644 index f072274f474..00000000000 --- a/board/freescale/ls1043aqds/ls1043aqds_pbi.cfg +++ /dev/null @@ -1,14 +0,0 @@ -#Configure Scratch register -09570600 00000000 -09570604 10000000 -#Alt base register -09570158 00001000 -#Disable CCI barrier tranaction -09570178 0000e010 -09180000 00000008 -#USB PHY frequency sel -09570418 0000009e -0957041c 0000009e -09570420 0000009e -#flush PBI data -096100c0 000fffff diff --git a/board/freescale/ls1043aqds/ls1043aqds_qixis.h b/board/freescale/ls1043aqds/ls1043aqds_qixis.h deleted file mode 100644 index bba494ae413..00000000000 --- a/board/freescale/ls1043aqds/ls1043aqds_qixis.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __LS1043AQDS_QIXIS_H__ -#define __LS1043AQDS_QIXIS_H__ - -/* Definitions of QIXIS Registers for LS1043AQDS */ - -/* BRDCFG4[4:7] select EC1 and EC2 as a pair */ -#define BRDCFG4_EMISEL_MASK 0xe0 -#define BRDCFG4_EMISEL_SHIFT 5 - -/* SYSCLK */ -#define QIXIS_SYSCLK_66 0x0 -#define QIXIS_SYSCLK_83 0x1 -#define QIXIS_SYSCLK_100 0x2 -#define QIXIS_SYSCLK_125 0x3 -#define QIXIS_SYSCLK_133 0x4 -#define QIXIS_SYSCLK_150 0x5 -#define QIXIS_SYSCLK_160 0x6 -#define QIXIS_SYSCLK_166 0x7 -#define QIXIS_SYSCLK_64 0x8 - -/* DDRCLK */ -#define QIXIS_DDRCLK_66 0x0 -#define QIXIS_DDRCLK_100 0x1 -#define QIXIS_DDRCLK_125 0x2 -#define QIXIS_DDRCLK_133 0x3 - -/* BRDCFG2 - SD clock*/ -#define QIXIS_SDCLK1_100 0x0 -#define QIXIS_SDCLK1_125 0x1 -#define QIXIS_SDCLK1_165 0x2 -#define QIXIS_SDCLK1_100_SP 0x3 - -#endif diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg b/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg deleted file mode 100644 index d87058b7efe..00000000000 --- a/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 -# serdes protocol -08100010 0a000000 00000000 00000000 -14550002 80004012 e0106000 c1002000 -00000000 00000000 00000000 00038800 -00000000 00001100 00000096 00000001 diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg deleted file mode 100644 index b6b5e0b1018..00000000000 --- a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg +++ /dev/null @@ -1,8 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 -# RCW -# Enable IFC; disable QSPI -08100010 0a000000 00000000 00000000 -14550002 80004012 60040000 c1002000 -00000000 00000000 00000000 00038800 -00000000 00001100 00000096 00000001 diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg deleted file mode 100644 index 7783521b95b..00000000000 --- a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg +++ /dev/null @@ -1,8 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 -# RCW -# Enable QSPI; disable IFC -08100010 0a000000 00000000 00000000 -14550002 80004012 60040000 c1002000 -00000000 00000000 00000000 00038800 -20124000 00001100 00000096 00000001 diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig deleted file mode 100644 index a7e9583c735..00000000000 --- a/configs/ls1043aqds_defconfig +++ /dev/null @@ -1,107 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=25000000 -CONFIG_TARGET_LS1043AQDS=y -CONFIG_TEXT_BASE=0x60100000 -CONFIG_SYS_MALLOC_LEN=0x120000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x60300000 -CONFIG_AHCI=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" -CONFIG_VOL_MONITOR_INA220=y -CONFIG_VOL_MONITOR_IR36021_SET=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff -CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 -CONFIG_REMAKE_ELF=y -CONFIG_MP=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_MISC_INIT_R=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SATA=y -CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y -CONFIG_DYNAMIC_DDR_CLK_FREQ=y -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_FSL_IFC=y -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_VITESSE=y -CONFIG_E1000=y -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig deleted file mode 100644 index 7334d31e834..00000000000 --- a/configs/ls1043aqds_lpuart_defconfig +++ /dev/null @@ -1,109 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=25000000 -CONFIG_TARGET_LS1043AQDS=y -CONFIG_TEXT_BASE=0x60100000 -CONFIG_SYS_MALLOC_LEN=0x120000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart" -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x60300000 -CONFIG_AHCI=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" -CONFIG_VOL_MONITOR_INA220=y -CONFIG_VOL_MONITOR_IR36021_SET=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff -CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 -CONFIG_REMAKE_ELF=y -CONFIG_MP=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_MISC_INIT_R=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SATA=y -CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y -CONFIG_DYNAMIC_DDR_CLK_FREQ=y -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_FSL_IFC=y -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_VITESSE=y -CONFIG_E1000=y -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_DM_SCSI=y -CONFIG_DM_SERIAL=y -CONFIG_FSL_LPUART=y -CONFIG_LPUART=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig deleted file mode 100644 index 774d41308ba..00000000000 --- a/configs/ls1043aqds_nand_defconfig +++ /dev/null @@ -1,138 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=25000000 -CONFIG_TARGET_LS1043AQDS=y -CONFIG_TEXT_BASE=0x82000000 -CONFIG_SYS_MALLOC_LEN=0x102000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x300000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" -CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_AHCI=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" -CONFIG_VOL_MONITOR_INA220=y -CONFIG_VOL_MONITOR_IR36021_SET=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff -CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 -CONFIG_REMAKE_ELF=y -CONFIG_SYS_MONITOR_LEN=1048576 -CONFIG_MP=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg" -CONFIG_NAND_BOOT=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_MISC_INIT_R=y -CONFIG_SPL_MAX_SIZE=0x1a000 -CONFIG_SPL_PAD_TO=0x20000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80100000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 -CONFIG_SPL_FSL_PBL=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x1001d000 -CONFIG_SYS_SPL_MALLOC=y -CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y -CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80200000 -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_WATCHDOG=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SATA=y -CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y -CONFIG_DYNAMIC_DDR_CLK_FREQ=y -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_NAND_FSL_IFC=y -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y -CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 -CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_VITESSE=y -CONFIG_E1000=y -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig deleted file mode 100644 index f759baf36db..00000000000 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ /dev/null @@ -1,108 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=25000000 -CONFIG_TARGET_LS1043AQDS=y -CONFIG_TEXT_BASE=0x60100000 -CONFIG_SYS_MALLOC_LEN=0x120000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x60300000 -CONFIG_AHCI=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" -CONFIG_VOL_MONITOR_INA220=y -CONFIG_VOL_MONITOR_IR36021_SET=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff -CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 -CONFIG_REMAKE_ELF=y -CONFIG_MP=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_MISC_INIT_R=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SATA=y -CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y -CONFIG_DYNAMIC_DDR_CLK_FREQ=y -CONFIG_SYS_FSL_DDR3=y -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_FSL_IFC=y -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_VITESSE=y -CONFIG_E1000=y -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig deleted file mode 100644 index e7dbf41b972..00000000000 --- a/configs/ls1043aqds_qspi_defconfig +++ /dev/null @@ -1,98 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=25000000 -CONFIG_TARGET_LS1043AQDS=y -CONFIG_TEXT_BASE=0x40100000 -CONFIG_SYS_MALLOC_LEN=0x102000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x300000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x40300000 -CONFIG_AHCI=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" -CONFIG_VOL_MONITOR_INA220=y -CONFIG_VOL_MONITOR_IR36021_SET=y -CONFIG_FSL_QIXIS=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff -CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 -CONFIG_REMAKE_ELF=y -CONFIG_MP=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_QSPI_BOOT=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_MISC_INIT_R=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GREPENV=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SATA=y -CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y -CONFIG_DYNAMIC_DDR_CLK_FREQ=y -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_EARLY_INIT=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -# CONFIG_SPI_FLASH_BAR is not set -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_VITESSE=y -CONFIG_E1000=y -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_QSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig deleted file mode 100644 index 627abc81c9c..00000000000 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ /dev/null @@ -1,135 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=25000000 -CONFIG_TARGET_LS1043AQDS=y -CONFIG_TEXT_BASE=0x82000000 -CONFIG_SYS_MALLOC_LEN=0x102000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x300000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" -CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_AHCI=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" -CONFIG_VOL_MONITOR_INA220=y -CONFIG_VOL_MONITOR_IR36021_SET=y -CONFIG_FSL_QIXIS=y -# CONFIG_QIXIS_I2C_ACCESS is not set -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff -CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 -CONFIG_REMAKE_ELF=y -CONFIG_SYS_MONITOR_LEN=1048576 -CONFIG_MP=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg" -CONFIG_SD_BOOT=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_MISC_INIT_R=y -CONFIG_SPL_MAX_SIZE=0x17000 -CONFIG_SPL_PAD_TO=0x1d000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x8f000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 -CONFIG_SPL_FSL_PBL=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x1001e000 -CONFIG_SYS_SPL_MALLOC=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR=y -CONFIG_SPL_WATCHDOG=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SATA=y -CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y -CONFIG_DYNAMIC_DDR_CLK_FREQ=y -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_FSL_IFC=y -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_VITESSE=y -CONFIG_E1000=y -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig deleted file mode 100644 index f4dcbd4a926..00000000000 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ /dev/null @@ -1,124 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=25000000 -CONFIG_TARGET_LS1043AQDS=y -CONFIG_TEXT_BASE=0x82000000 -CONFIG_SYS_MALLOC_LEN=0x102000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x300000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" -CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_AHCI=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" -CONFIG_VOL_MONITOR_INA220=y -CONFIG_VOL_MONITOR_IR36021_SET=y -CONFIG_FSL_QIXIS=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff -CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 -CONFIG_REMAKE_ELF=y -CONFIG_SYS_MONITOR_LEN=1048576 -CONFIG_MP=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg" -CONFIG_SD_BOOT=y -CONFIG_SD_BOOT_QSPI=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_MISC_INIT_R=y -CONFIG_SPL_MAX_SIZE=0x17000 -CONFIG_SPL_PAD_TO=0x1d000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x8f000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 -CONFIG_SPL_FSL_PBL=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x1001e000 -CONFIG_SYS_SPL_MALLOC=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR=y -CONFIG_SPL_WATCHDOG=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GREPENV=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SATA=y -CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y -CONFIG_DYNAMIC_DDR_CLK_FREQ=y -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_EARLY_INIT=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -# CONFIG_SPI_FLASH_BAR is not set -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_VITESSE=y -CONFIG_E1000=y -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_QSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig deleted file mode 100644 index 307fbfcbb7d..00000000000 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ /dev/null @@ -1,109 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=25000000 -CONFIG_TARGET_LS1043AQDS=y -CONFIG_TFABOOT=y -CONFIG_TEXT_BASE=0x82000000 -CONFIG_SYS_MALLOC_LEN=0x102000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x2000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_AHCI=y -CONFIG_NXP_ESBC=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" -CONFIG_VOL_MONITOR_INA220=y -CONFIG_VOL_MONITOR_IR36021_SET=y -CONFIG_FSL_QIXIS=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff -CONFIG_DISTRO_DEFAULTS=y -CONFIG_REMAKE_ELF=y -CONFIG_MP=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_MISC_INIT_R=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SATA=y -CONFIG_SATA_CEVA=y -CONFIG_DYNAMIC_DDR_CLK_FREQ=y -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_EARLY_INIT=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_FSL_SEC_MON_BE=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_FSL_IFC=y -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SF_DEFAULT_BUS=1 -# CONFIG_SPI_FLASH_BAR is not set -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_VITESSE=y -CONFIG_E1000=y -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_QSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig deleted file mode 100644 index 667fc2123a2..00000000000 --- a/configs/ls1043aqds_tfa_defconfig +++ /dev/null @@ -1,116 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=25000000 -CONFIG_TARGET_LS1043AQDS=y -CONFIG_TFABOOT=y -CONFIG_TEXT_BASE=0x82000000 -CONFIG_SYS_MALLOC_LEN=0x102000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x500000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_ENV_ADDR=0x60500000 -CONFIG_AHCI=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_FSL_USE_PCA9547_MUX=y -CONFIG_VID=y -CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv" -CONFIG_VOL_MONITOR_INA220=y -CONFIG_VOL_MONITOR_IR36021_SET=y -CONFIG_FSL_QIXIS=y -CONFIG_SYS_MEMTEST_START=0x80000000 -CONFIG_SYS_MEMTEST_END=0x9fffffff -CONFIG_DISTRO_DEFAULTS=y -CONFIG_REMAKE_ELF=y -CONFIG_MP=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_MISC_INIT_R=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_SPI_BUS=0 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SATA=y -CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y -CONFIG_DYNAMIC_DDR_CLK_FREQ=y -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_EARLY_INIT=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_FSL_IFC=y -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SF_DEFAULT_BUS=1 -# CONFIG_SPI_FLASH_BAR is not set -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_VITESSE=y -CONFIG_E1000=y -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_QSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig deleted file mode 100644 index 7d980c3c469..00000000000 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ /dev/null @@ -1,97 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=25000000 -CONFIG_TARGET_LS1043ARDB=y -CONFIG_TEXT_BASE=0x60100000 -CONFIG_SYS_MALLOC_LEN=0x120000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x20000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" -CONFIG_FSL_LS_PPA=y -CONFIG_OF_BOARD_FIXUP=y -CONFIG_NXP_ESBC=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 -CONFIG_REMAKE_ELF=y -CONFIG_MP=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;" -CONFIG_MISC_INIT_R=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_IMLS=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_DM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC3" -# CONFIG_DDR_SPD is not set -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_DDR_RAW_TIMING=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_FSL_SEC_MON_BE=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x53 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_FSL_IFC=y -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_VITESSE=y -CONFIG_DM_MDIO=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0x60900000 -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_QE_FW_ADDR=0x60940000 -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig deleted file mode 100644 index b345d13caa0..00000000000 --- a/configs/ls1043ardb_defconfig +++ /dev/null @@ -1,98 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=25000000 -CONFIG_TARGET_LS1043ARDB=y -CONFIG_TEXT_BASE=0x60100000 -CONFIG_SYS_MALLOC_LEN=0x120000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" -CONFIG_FSL_LS_PPA=y -CONFIG_ENV_ADDR=0x60300000 -CONFIG_OF_BOARD_FIXUP=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 -CONFIG_REMAKE_ELF=y -CONFIG_MP=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_BOOTCOMMAND="run distro_bootcmd; run nor_bootcmd; env exists secureboot && esbc_halt;" -CONFIG_ARCH_MISC_INIT=y -CONFIG_MISC_INIT_R=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_IMLS=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_DM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC3" -CONFIG_FSL_CAAM=y -# CONFIG_DDR_SPD is not set -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_DDR_RAW_TIMING=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x53 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_FSL_IFC=y -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHY_AQUANTIA=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_VITESSE=y -CONFIG_DM_MDIO=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0x60900000 -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_QE_FW_ADDR=0x60940000 -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig deleted file mode 100644 index d4546348bbd..00000000000 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ /dev/null @@ -1,122 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=25000000 -CONFIG_TARGET_LS1043ARDB=y -CONFIG_TEXT_BASE=0x82000000 -CONFIG_SYS_MALLOC_LEN=0x102000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x2000 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" -CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_OF_BOARD_FIXUP=y -CONFIG_NXP_ESBC=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 -CONFIG_REMAKE_ELF=y -CONFIG_SYS_MONITOR_LEN=1064960 -CONFIG_MP=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg" -CONFIG_NAND_BOOT=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_MISC_INIT_R=y -CONFIG_SPL_MAX_SIZE=0x1a000 -CONFIG_SPL_PAD_TO=0x20000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80100000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 -CONFIG_SPL_FSL_PBL=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x1001d000 -CONFIG_SYS_SPL_MALLOC=y -CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y -CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80200000 -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_WATCHDOG=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_IMLS=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_DM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC3" -CONFIG_SPL_DM=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_FSL_SEC_MON_BE=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x53 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_NAND_FSL_IFC=y -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y -CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 -CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHY_AQUANTIA=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_VITESSE=y -CONFIG_DM_MDIO=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -# CONFIG_SPL_USE_TINY_PRINTF is not set -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig deleted file mode 100644 index f0f8cbf34e0..00000000000 --- a/configs/ls1043ardb_nand_defconfig +++ /dev/null @@ -1,127 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=25000000 -CONFIG_TARGET_LS1043ARDB=y -CONFIG_TEXT_BASE=0x82000000 -CONFIG_SYS_MALLOC_LEN=0x102000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x300000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" -CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_OF_BOARD_FIXUP=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 -CONFIG_REMAKE_ELF=y -CONFIG_SYS_MONITOR_LEN=1048576 -CONFIG_MP=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg" -CONFIG_NAND_BOOT=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_MISC_INIT_R=y -CONFIG_SPL_MAX_SIZE=0x1a000 -CONFIG_SPL_PAD_TO=0x20000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80100000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 -CONFIG_SPL_FSL_PBL=y -CONFIG_SPL_BOARD_INIT=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x1001d000 -CONFIG_SYS_SPL_MALLOC=y -CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y -CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80200000 -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C=y -CONFIG_SPL_MPC8XXX_INIT_DDR=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_WATCHDOG=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_IMLS=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_DM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC3" -CONFIG_FSL_CAAM=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x53 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_NAND_FSL_IFC=y -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y -CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 -CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHY_AQUANTIA=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_VITESSE=y -CONFIG_DM_MDIO=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -# CONFIG_SPL_USE_TINY_PRINTF is not set -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig deleted file mode 100644 index 529cd93bd24..00000000000 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ /dev/null @@ -1,122 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=25000000 -CONFIG_TARGET_LS1043ARDB=y -CONFIG_TEXT_BASE=0x82000000 -CONFIG_SYS_MALLOC_LEN=0x102000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x2000 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" -CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_OF_BOARD_FIXUP=y -CONFIG_NXP_ESBC=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 -CONFIG_REMAKE_ELF=y -CONFIG_SYS_MONITOR_LEN=1064960 -CONFIG_MP=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg" -CONFIG_SD_BOOT=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;" -CONFIG_MISC_INIT_R=y -CONFIG_SPL_MAX_SIZE=0x17000 -CONFIG_SPL_PAD_TO=0x1d000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x8f000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 -CONFIG_SPL_FSL_PBL=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x1001e000 -CONFIG_SYS_SPL_MALLOC=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR=y -CONFIG_SPL_WATCHDOG=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_IMLS=y -CONFIG_CMD_SPL=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_DM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC3" -CONFIG_SPL_DM=y -# CONFIG_SPL_BLK is not set -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_FSL_SEC_MON_BE=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x53 -# CONFIG_SPL_DM_MMC is not set -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_FSL_IFC=y -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_VITESSE=y -CONFIG_DM_MDIO=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_PCI=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_QE_FW_ADDR=0x940000 -CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -# CONFIG_SPL_USE_TINY_PRINTF is not set -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig deleted file mode 100644 index bfe9260d1b7..00000000000 --- a/configs/ls1043ardb_sdcard_defconfig +++ /dev/null @@ -1,125 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=25000000 -CONFIG_TARGET_LS1043ARDB=y -CONFIG_TEXT_BASE=0x82000000 -CONFIG_SYS_MALLOC_LEN=0x102000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x300000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" -CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_FSL_LS_PPA=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL=y -CONFIG_OF_BOARD_FIXUP=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 -CONFIG_REMAKE_ELF=y -CONFIG_SYS_MONITOR_LEN=1048576 -CONFIG_MP=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043ardb/ls1043ardb_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg" -CONFIG_SD_BOOT=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;" -CONFIG_ARCH_MISC_INIT=y -CONFIG_MISC_INIT_R=y -CONFIG_SPL_MAX_SIZE=0x17000 -CONFIG_SPL_PAD_TO=0x1d000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x8f000000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 -CONFIG_SPL_FSL_PBL=y -CONFIG_SPL_BOARD_INIT=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x1001e000 -CONFIG_SYS_SPL_MALLOC=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR=y -CONFIG_SPL_WATCHDOG=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_IMLS=y -CONFIG_CMD_SPL=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_DM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC3" -CONFIG_FSL_CAAM=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x53 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_FSL_IFC=y -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHY_AQUANTIA=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_VITESSE=y -CONFIG_DM_MDIO=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_QE_FW_ADDR=0x940000 -CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -# CONFIG_SPL_USE_TINY_PRINTF is not set -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig deleted file mode 100644 index 391e95a48d5..00000000000 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ /dev/null @@ -1,95 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=25000000 -CONFIG_TARGET_LS1043ARDB=y -CONFIG_TFABOOT=y -CONFIG_TEXT_BASE=0x82000000 -CONFIG_SYS_MALLOC_LEN=0x102000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x2000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_OF_BOARD_FIXUP=y -CONFIG_NXP_ESBC=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_REMAKE_ELF=y -CONFIG_MP=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_MISC_INIT_R=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_IMLS=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_DM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC3" -# CONFIG_DDR_SPD is not set -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_DDR_RAW_TIMING=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_FSL_SEC_MON_BE=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x53 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_FSL_IFC=y -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_VITESSE=y -CONFIG_DM_MDIO=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_QE_FW_ADDR=0x940000 -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig deleted file mode 100644 index 2ebde25bd93..00000000000 --- a/configs/ls1043ardb_tfa_defconfig +++ /dev/null @@ -1,99 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=25000000 -CONFIG_TARGET_LS1043ARDB=y -CONFIG_TFABOOT=y -CONFIG_TEXT_BASE=0x82000000 -CONFIG_SYS_MALLOC_LEN=0x102000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x500000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y -CONFIG_ENV_ADDR=0x60500000 -CONFIG_OF_BOARD_FIXUP=y -CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_REMAKE_ELF=y -CONFIG_MP=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_ARCH_MISC_INIT=y -CONFIG_MISC_INIT_R=y -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=532 -CONFIG_CMD_IMLS=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -CONFIG_CMD_DM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -CONFIG_CMD_CACHE=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC3" -CONFIG_FSL_CAAM=y -# CONFIG_DDR_SPD is not set -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_DDR_RAW_TIMING=y -CONFIG_MPC8XXX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x53 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_FSL_IFC=y -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHY_AQUANTIA=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_VITESSE=y -CONFIG_DM_MDIO=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0x900000 -CONFIG_NVME_PCI=y -CONFIG_PCI=y -CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_QE_FW_ADDR=0x940000 -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

From: Peng Fan peng.fan@nxp.com

This is NXP internal validation board, no longer support it.

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/Kconfig | 20 - board/freescale/ls2080aqds/Kconfig | 32 - board/freescale/ls2080aqds/MAINTAINERS | 14 - board/freescale/ls2080aqds/Makefile | 7 - board/freescale/ls2080aqds/README | 215 ---- board/freescale/ls2080aqds/ddr.c | 183 --- board/freescale/ls2080aqds/ddr.h | 91 -- board/freescale/ls2080aqds/eth.c | 1089 ----------------- board/freescale/ls2080aqds/ls2080aqds.c | 353 ------ board/freescale/ls2080aqds/ls2080aqds_qixis.h | 29 - 10 files changed, 2033 deletions(-) delete mode 100644 board/freescale/ls2080aqds/Kconfig delete mode 100644 board/freescale/ls2080aqds/MAINTAINERS delete mode 100644 board/freescale/ls2080aqds/Makefile delete mode 100644 board/freescale/ls2080aqds/README delete mode 100644 board/freescale/ls2080aqds/ddr.c delete mode 100644 board/freescale/ls2080aqds/ddr.h delete mode 100644 board/freescale/ls2080aqds/eth.c delete mode 100644 board/freescale/ls2080aqds/ls2080aqds.c delete mode 100644 board/freescale/ls2080aqds/ls2080aqds_qixis.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8e75f1dd22a..990bdc356a1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1346,25 +1346,6 @@ config TARGET_LS1088AQDS development platform that supports the QorIQ LS1088A Layerscape Architecture processor.

-config TARGET_LS2080AQDS - bool "Support ls2080aqds" - select ARCH_LS2080A - select ARM64 - select ARMV8_MULTIENTRY - select ARCH_SUPPORT_TFABOOT - select BOARD_LATE_INIT - select GPIO_EXTRA_HEADER - select SUPPORT_SPL - imply SCSI - imply SCSI_AHCI - select FSL_DDR_BIST - select FSL_DDR_INTERACTIVE if !SPL - help - Support for Freescale LS2080AQDS platform. - The LS2080A Development System (QDS) is a high-performance - development platform that supports the QorIQ LS2080A - Layerscape Architecture processor. - config TARGET_LS2080ARDB bool "Support ls2080ardb" select ARCH_LS2080A @@ -2199,7 +2180,6 @@ source "board/broadcom/bcmns3/Kconfig" source "board/cavium/thunderx/Kconfig" source "board/eets/pdu001/Kconfig" source "board/emulation/qemu-arm/Kconfig" -source "board/freescale/ls2080aqds/Kconfig" source "board/freescale/ls2080ardb/Kconfig" source "board/freescale/ls1088a/Kconfig" source "board/freescale/ls1028a/Kconfig" diff --git a/board/freescale/ls2080aqds/Kconfig b/board/freescale/ls2080aqds/Kconfig deleted file mode 100644 index 1036f33c61f..00000000000 --- a/board/freescale/ls2080aqds/Kconfig +++ /dev/null @@ -1,32 +0,0 @@ - -if TARGET_LS2080AQDS - -config SYS_BOARD - default "ls2080aqds" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls2080aqds" - -if FSL_LS_PPA -config SYS_LS_PPA_FW_ADDR - hex "PPA Firmware Addr" - default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT - default 0x580400000 if SYS_LS_PPA_FW_IN_XIP - default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND - -if CHAIN_OF_TRUST -config SYS_LS_PPA_ESBC_ADDR - hex "PPA Firmware HDR Addr" - default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT - default 0x580680000 if SYS_LS_PPA_FW_IN_XIP - default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND -endif -endif - -endif diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS deleted file mode 100644 index 39d02ae3f46..00000000000 --- a/board/freescale/ls2080aqds/MAINTAINERS +++ /dev/null @@ -1,14 +0,0 @@ -LS2080A BOARD -M: Priyanka Jain priyanka.jain@nxp.com -M: Rajesh Bhagat rajesh.bhagat@nxp.com -M: Wasim Khan wasim.khan@nxp.com -S: Maintained -F: board/freescale/ls2080aqds/ -F: board/freescale/ls2080a/ls2080aqds.c -F: include/configs/ls2080aqds.h -F: configs/ls2080aqds_defconfig -F: configs/ls2080aqds_nand_defconfig -F: configs/ls2080aqds_qspi_defconfig -F: configs/ls2080aqds_sdcard_defconfig -F: configs/ls2088aqds_tfa_defconfig -F: configs/ls2080aqds_SECURE_BOOT_defconfig diff --git a/board/freescale/ls2080aqds/Makefile b/board/freescale/ls2080aqds/Makefile deleted file mode 100644 index efc51b4a34d..00000000000 --- a/board/freescale/ls2080aqds/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2015 Freescale Semiconductor - -obj-y += ls2080aqds.o -obj-y += ddr.o -obj-y += eth.o diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README deleted file mode 100644 index a4cb1a6cac4..00000000000 --- a/board/freescale/ls2080aqds/README +++ /dev/null @@ -1,215 +0,0 @@ -Overview --------- -The LS2080A Development System (QDS) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS2080A -and LS2088A Layerscape Architecture processor. The LS2080AQDS provides -validation and SW development platform for the Freescale LS2080A, LS2088A -processor series, with a complete debugging environment. - -LS2080A, LS2088A SoC Overview --------------------- -Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A, -LS2088A SoC overview. - - LS2080AQDS board Overview - ----------------------- - - SERDES Connections, 16 lanes supporting: - - PCI Express - 3.0 - - SGMII, SGMII 2.5 - - QSGMII - - SATA 3.0 - - XAUI - - 10GBase-R - - DDR Controller - - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four - chip-selects and two DIMM connectors. Support is up to 2133MT/s. - - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects - and two DIMM connectors. Support is up to 1600MT/s. - -IFC/Local Bus - - IFC rev. 2.0 implementation supporting Little Endian connection scheme. - - One in-socket 128 MB NOR flash 16-bit data bus - - One 512 MB NAND flash with ECC support - - IFC Test Port - - PromJet Port - - FPGA connection - - USB 3.0 - - Two high speed USB 3.0 ports - - First USB 3.0 port configured as Host with Type-A connector - - Second USB 3.0 port configured as OTG with micro-AB connector - - SDHC: PCIe x1 Right Angle connector for supporting following cards - - 1/4-/8-bit SD/MMC Legacy CARD supporting 3.3V devices only - - 1-/4-/8-bit SD/MMC Card supporting 1.8V devices only - - 4-bit eMMC Card Rev 4.4 (1.8V only) - - 8-bit eMMC Card Rev 4.5 (1.8V only) - - SD Card Rev 2.0 and Rev 3.0 - - DSPI: 3 high-speed flash Memory for storage - - 16 MB high-speed flash Memory for boot code and storage (up to 108MHz) - - 8 MB high-speed flash Memory (up to 104 MHz) - - 512 MB low-speed flash Memory (up to 40 MHz) - - QSPI: via NAND/QSPI Card - - 4 I2C controllers - - Two SATA onboard connectors - - UART - - Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s - - Two DB9 D-Type connectors supporting one Serial port each - - ARM JTAG support - -Memory map from core's view ----------------------------- -0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom -0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR -0x00_1800_0000 .. 0x00_181F_FFFF OCRAM -0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1 -0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1 -0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 -0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2 - -Other addresses are either reserved, or not used directly by U-Boot. -This list should be updated when more addresses are used. - -IFC region map from core's view -------------------------------- -During boot i.e. IFC Region #1:- - 0x30000000 - 0x37ffffff : 128MB : NOR flash - 0x38000000 - 0x3BFFFFFF : 64MB : Promjet - 0x3C000000 - 0x40000000 : 64MB : FPGA etc - -After relocate to DDR i.e. IFC Region #2:- - 0x5_1000_0000..0x5_1fff_ffff Memory Hole - 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) - 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB - 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) - 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) - -Booting Options ---------------- -a) Promjet Boot -b) NOR boot -c) NAND boot -d) SD boot -e) QSPI boot - -Memory map for NOR boot -------------------------- -Image Flash Offset -RCW+PBI 0x00000000 -Boot firmware (U-Boot) 0x00100000 -Boot firmware Environment 0x00300000 -PPA firmware 0x00400000 -Secure Headers 0x00600000 -DPAA2 MC 0x00A00000 -DPAA2 DPL 0x00D00000 -DPAA2 DPC 0x00E00000 -Kernel.itb 0x01000000 - -Memory map for SD boot -------------------------- -Image Flash Offset SD Card - Start Block No. -RCW+PBI 0x00000000 0x00008 -Boot firmware (U-Boot) 0x00100000 0x00800 -Boot firmware Environment 0x00300000 0x01800 -PPA firmware 0x00400000 0x02000 -DPAA2 MC 0x00A00000 0x05000 -DPAA2 DPL 0x00D00000 0x06800 -DPAA2 DPC 0x00E00000 0x07000 -Kernel.itb 0x01000000 0x08000 - -Environment Variables ---------------------- -- mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined - the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. - -- mcmemsize: MC DRAM block size. If this variable is not defined - the value CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. - -Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) -------------------------------------------------------------------- -One needs to use appropriate bootargs to boot Linux flavors which do -not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown -below: - -=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram - earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m - hugepages=16 mem=2048M' - - -X-QSGMII-16PORT riser card ----------------------------- -The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes -interfaces implemented in PCIe form factor board. -It supports following: - - Card can operate with up to 4 QSGMII lane simultaneously - - Card can operate with up to 8 SGMII lane simultaneously - -Supported card configuration - - CSEL : ON ON ON ON - - MSEL1 : ON ON ON ON OFF OFF OFF OFF - - MSEL2 : OFF OFF OFF OFF ON ON ON ON - -To enable this card: modify hwconfig to add "xqsgmii" variable. - -Supported PHY addresses during SGMII: -#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 -#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 -#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 -#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 -#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 -#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa -#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc -#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe - -Mapping DPMACx to PHY during SGMII -DPMAC1 -> PHY1-P0 -DPMAC2 -> PHY2-P0 -DPMAC3 -> PHY3-P0 -DPMAC4 -> PHY4-P0 -DPMAC5 -> PHY3-P2 -DPMAC6 -> PHY1-P2 -DPMAC7 -> PHY4-P1 -DPMAC8 -> PHY2-P2 -DPMAC9 -> PHY1-P0 -DPMAC10 -> PHY2-P0 -DPMAC11 -> PHY3-P0 -DPMAC12 -> PHY4-P0 -DPMAC13 -> PHY3-P2 -DPMAC14 -> PHY1-P2 -DPMAC15 -> PHY4-P1 -DPMAC16 -> PHY2-P2 - - -Supported PHY address during QSGMII -#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 -#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 -#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 -#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 -#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 -#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 -#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 -#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 -#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 -#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 -#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa -#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb -#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc -#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd -#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe -#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf - -Mapping DPMACx to PHY during QSGMII -DPMAC1 -> PHY1-P3 -DPMAC2 -> PHY1-P2 -DPMAC3 -> PHY1-P1 -DPMAC4 -> PHY1-P0 -DPMAC5 -> PHY2-P3 -DPMAC6 -> PHY2-P2 -DPMAC7 -> PHY2-P1 -DPMAC8 -> PHY2-P0 -DPMAC9 -> PHY3-P0 -DPMAC10 -> PHY3-P1 -DPMAC11 -> PHY3-P2 -DPMAC12 -> PHY3-P3 -DPMAC13 -> PHY4-P0 -DPMAC14 -> PHY4-P1 -DPMAC15 -> PHY4-P2 -DPMAC16 -> PHY4-P3 diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c deleted file mode 100644 index 2767d058cc9..00000000000 --- a/board/freescale/ls2080aqds/ddr.c +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> -#include <log.h> -#include <asm/arch/soc.h> -#include <asm/arch/clock.h> -#include <asm/global_data.h> -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR - u8 dq_mapping_0, dq_mapping_2, dq_mapping_3; -#endif - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - int slot; - - if (ctrl_num > 2) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - - for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) { - if (pdimm[slot].n_ranks) - break; - } - - if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR) - return; - - /* - * we use identical timing for all slots. If needed, change the code - * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; - */ - if (popts->registered_dimm_en) - pbsp = rdimms[ctrl_num]; - else - pbsp = udimms[ctrl_num]; - - - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(ctrl_num) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm[slot].n_ranks && - (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found for data rate %lu MT/s\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" - "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, - pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, - pbsp->wrlvl_ctl_3); -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (ctrl_num == CONFIG_DP_DDR_CTRL) { - /* force DDR bus width to 32 bits */ - popts->data_bus_width = 1; - popts->otf_burst_chop_en = 0; - popts->burst_length = DDR_BL8; - popts->bstopre = 0; /* enable auto precharge */ - /* - * Layout optimization results byte mapping - * Byte 0 -> Byte ECC - * Byte 1 -> Byte 3 - * Byte 2 -> Byte 2 - * Byte 3 -> Byte 1 - * Byte ECC -> Byte 0 - */ - dq_mapping_0 = pdimm[slot].dq_mapping[0]; - dq_mapping_2 = pdimm[slot].dq_mapping[2]; - dq_mapping_3 = pdimm[slot].dq_mapping[3]; - pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8]; - pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9]; - pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6]; - pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7]; - pdimm[slot].dq_mapping[6] = dq_mapping_2; - pdimm[slot].dq_mapping[7] = dq_mapping_3; - pdimm[slot].dq_mapping[8] = dq_mapping_0; - pdimm[slot].dq_mapping[9] = 0; - pdimm[slot].dq_mapping[10] = 0; - pdimm[slot].dq_mapping[11] = 0; - pdimm[slot].dq_mapping[12] = 0; - pdimm[slot].dq_mapping[13] = 0; - pdimm[slot].dq_mapping[14] = 0; - pdimm[slot].dq_mapping[15] = 0; - pdimm[slot].dq_mapping[16] = 0; - pdimm[slot].dq_mapping[17] = 0; - } -#endif - /* To work at higher than 1333MT/s */ - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0x0; /* 32 clocks */ - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - if (ddr_freq < 2350) { - if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) { - /* four chip-selects */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | - DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm); - popts->twot_en = 1; /* enable 2T timing */ - } else { - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | - DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | - DDR_CDR2_VREF_RANGE_2; - } - } else { - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | - DDR_CDR1_ODT(DDR_CDR_ODT_100ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) | - DDR_CDR2_VREF_RANGE_2; - } -} - -#ifdef CONFIG_TFABOOT -int fsl_initdram(void) -{ - gd->ram_size = tfa_get_dram_size(); - - if (!gd->ram_size) - gd->ram_size = fsl_ddr_sdram_size(); - - return 0; -} -#else -int fsl_initdram(void) -{ -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) - gd->ram_size = fsl_ddr_sdram_size(); -#else - puts("Initializing DDR....using SPD\n"); - - gd->ram_size = fsl_ddr_sdram(); -#endif - - return 0; -} -#endif /* CONFIG_TFABOOT */ diff --git a/board/freescale/ls2080aqds/ddr.h b/board/freescale/ls2080aqds/ddr.h deleted file mode 100644 index b5d790a4a05..00000000000 --- a/board/freescale/ls2080aqds/ddr.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __DDR_H__ -#define __DDR_H__ -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ - -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, - {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2300, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, - {} -}; - -/* DP-DDR DIMM */ -static const struct board_specific_parameters udimm2[] = { - /* - * memory controller 2 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, - {2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, - {2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, - {2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, - {} -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, - {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, - {} -}; - -/* DP-DDR DIMM */ -static const struct board_specific_parameters rdimm2[] = { - /* - * memory controller 2 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 8, 7, 0x0B0A090C, 0x0D0F100B,}, - {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, - udimm0, - udimm2, -}; - -static const struct board_specific_parameters *rdimms[] = { - rdimm0, - rdimm0, - rdimm2, -}; - - -#endif diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c deleted file mode 100644 index 6da6e5c8415..00000000000 --- a/board/freescale/ls2080aqds/eth.c +++ /dev/null @@ -1,1089 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <env.h> -#include <log.h> -#include <net.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/arch/fsl_serdes.h> -#include <hwconfig.h> -#include <fsl_mdio.h> -#include <malloc.h> -#include <fm_eth.h> -#include <i2c.h> -#include <miiphy.h> -#include <fsl-mc/fsl_mc.h> -#include <fsl-mc/ldpaa_wriop.h> -#include <linux/delay.h> - -#include "../common/qixis.h" - -#include "ls2080aqds_qixis.h" - -#define MC_BOOT_ENV_VAR "mcinitcmd" - -#ifndef CONFIG_DM_ETH - -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) - /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks. - * Bank 1 -> Lanes A, B, C, D, E, F, G, H - * Bank 2 -> Lanes A,B, C, D, E, F, G, H - */ - - /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here - * means that the mapping must be determined dynamically, or that the lane - * maps to something other than a board slot. - */ - -static u8 lane_to_slot_fsm1[] = { - 0, 0, 0, 0, 0, 0, 0, 0 -}; - -static u8 lane_to_slot_fsm2[] = { - 0, 0, 0, 0, 0, 0, 0, 0 -}; - -/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs - * housed. - */ - -static int xqsgii_riser_phy_addr[] = { - XQSGMII_CARD_PHY1_PORT0_ADDR, - XQSGMII_CARD_PHY2_PORT0_ADDR, - XQSGMII_CARD_PHY3_PORT0_ADDR, - XQSGMII_CARD_PHY4_PORT0_ADDR, - XQSGMII_CARD_PHY3_PORT2_ADDR, - XQSGMII_CARD_PHY1_PORT2_ADDR, - XQSGMII_CARD_PHY4_PORT2_ADDR, - XQSGMII_CARD_PHY2_PORT2_ADDR, -}; - -static int sgmii_riser_phy_addr[] = { - SGMII_CARD_PORT1_PHY_ADDR, - SGMII_CARD_PORT2_PHY_ADDR, - SGMII_CARD_PORT3_PHY_ADDR, - SGMII_CARD_PORT4_PHY_ADDR, -}; - -/* Slot2 does not have EMI connections */ -#define EMI_NONE 0xFF -#define EMI1_SLOT1 0 -#define EMI1_SLOT2 1 -#define EMI1_SLOT3 2 -#define EMI1_SLOT4 3 -#define EMI1_SLOT5 4 -#define EMI1_SLOT6 5 -#define EMI2 6 -#define SFP_TX 0 - -static const char * const mdio_names[] = { - "LS2080A_QDS_MDIO0", - "LS2080A_QDS_MDIO1", - "LS2080A_QDS_MDIO2", - "LS2080A_QDS_MDIO3", - "LS2080A_QDS_MDIO4", - "LS2080A_QDS_MDIO5", - DEFAULT_WRIOP_MDIO2_NAME, -}; - -struct ls2080a_qds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -struct reg_pair { - uint addr; - u8 *val; -}; - -static void sgmii_configure_repeater(int serdes_port) -{ - struct mii_dev *bus; - uint8_t a = 0xf; - int i, j, k, ret; - int dpmac_id = 0, dpmac, mii_bus = 0; - unsigned short value; - char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"}; - uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60}; - - uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7}; - uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84}; - uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; - uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; - - u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20}; - struct reg_pair reg_pair[10] = { - {6, &reg_val[0]}, {4, &reg_val[1]}, - {8, &reg_val[2]}, {0xf, NULL}, - {0x11, NULL}, {0x16, NULL}, - {0x18, NULL}, {0x23, &reg_val[3]}, - {0x2d, &reg_val[4]}, {4, &reg_val[5]}, - }; - - int *riser_phy_addr = &xqsgii_riser_phy_addr[0]; -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *udev; -#endif - - /* Set I2c to Slot 1 */ -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_write(0x77, 0, 0, &a, 1); -#else - ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev); - if (!ret) - ret = dm_i2c_write(udev, 0, &a, 1); -#endif - if (ret) - goto error; - - for (dpmac = 0; dpmac < 8; dpmac++) { - /* Check the PHY status */ - switch (serdes_port) { - case 1: - mii_bus = 0; - dpmac_id = dpmac + 1; - break; - case 2: - mii_bus = 1; - dpmac_id = dpmac + 9; - a = 0xb; -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_write(0x76, 0, 0, &a, 1); -#else - ret = i2c_get_chip_for_busnum(0, 0x76, 1, &udev); - if (!ret) - ret = dm_i2c_write(udev, 0, &a, 1); -#endif - if (ret) - goto error; - break; - } - - ret = miiphy_set_current_dev(dev[mii_bus]); - if (ret > 0) - goto error; - - bus = mdio_get_current_dev(); - debug("Reading from bus %s\n", bus->name); - - ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f, - 3); - if (ret > 0) - goto error; - - mdelay(10); - ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11, - &value); - if (ret > 0) - goto error; - - mdelay(10); - - if ((value & 0xfff) == 0x401) { - printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id); - miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], - 0x1f, 0); - continue; - } - - for (i = 0; i < 4; i++) { - for (j = 0; j < 4; j++) { - reg_pair[3].val = &ch_a_eq[i]; - reg_pair[4].val = &ch_a_ctl2[j]; - reg_pair[5].val = &ch_b_eq[i]; - reg_pair[6].val = &ch_b_ctl2[j]; - - for (k = 0; k < 10; k++) { -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_write(i2c_addr[dpmac], - reg_pair[k].addr, - 1, reg_pair[k].val, 1); -#else - ret = i2c_get_chip_for_busnum(0, - i2c_addr[dpmac], - 1, &udev); - if (!ret) - ret = dm_i2c_write(udev, - reg_pair[k].addr, - reg_pair[k].val, 1); -#endif - if (ret) - goto error; - } - - mdelay(100); - ret = miiphy_read(dev[mii_bus], - riser_phy_addr[dpmac], - 0x11, &value); - if (ret > 0) - goto error; - - mdelay(100); - ret = miiphy_read(dev[mii_bus], - riser_phy_addr[dpmac], - 0x11, &value); - if (ret > 0) - goto error; - - if ((value & 0xfff) == 0x401) { - printf("DPMAC %d :PHY is configured ", - dpmac_id); - printf("after setting repeater 0x%x\n", - value); - i = 5; - j = 5; - } else { - printf("DPMAC %d :PHY is failed to ", - dpmac_id); - printf("configure the repeater 0x%x\n", - value); - } - } - } - miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f, 0); - } -error: - if (ret) - printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id); - return; -} - -static void qsgmii_configure_repeater(int dpmac) -{ - uint8_t a = 0xf; - int i, j, k; - int i2c_phy_addr = 0; - int phy_addr = 0; - int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b}; - - uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7}; - uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84}; - uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; - uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; - - u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20}; - struct reg_pair reg_pair[10] = { - {6, &reg_val[0]}, {4, &reg_val[1]}, - {8, &reg_val[2]}, {0xf, NULL}, - {0x11, NULL}, {0x16, NULL}, - {0x18, NULL}, {0x23, &reg_val[3]}, - {0x2d, &reg_val[4]}, {4, &reg_val[5]}, - }; - - const char *dev = "LS2080A_QDS_MDIO0"; - int ret = 0; - unsigned short value; -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *udev; -#endif - - /* Set I2c to Slot 1 */ -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_write(0x77, 0, 0, &a, 1); -#else - ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev); - if (!ret) - ret = dm_i2c_write(udev, 0, &a, 1); -#endif - if (ret) - goto error; - - switch (dpmac) { - case 1: - case 2: - case 3: - case 4: - i2c_phy_addr = i2c_addr[0]; - phy_addr = 0; - break; - - case 5: - case 6: - case 7: - case 8: - i2c_phy_addr = i2c_addr[1]; - phy_addr = 4; - break; - - case 9: - case 10: - case 11: - case 12: - i2c_phy_addr = i2c_addr[2]; - phy_addr = 8; - break; - - case 13: - case 14: - case 15: - case 16: - i2c_phy_addr = i2c_addr[3]; - phy_addr = 0xc; - break; - } - - /* Check the PHY status */ - ret = miiphy_set_current_dev(dev); - ret = miiphy_write(dev, phy_addr, 0x1f, 3); - mdelay(10); - ret = miiphy_read(dev, phy_addr, 0x11, &value); - mdelay(10); - ret = miiphy_read(dev, phy_addr, 0x11, &value); - mdelay(10); - if ((value & 0xf) == 0xf) { - printf("DPMAC %d :PHY is ..... Configured\n", dpmac); - return; - } - - for (i = 0; i < 4; i++) { - for (j = 0; j < 4; j++) { - reg_pair[3].val = &ch_a_eq[i]; - reg_pair[4].val = &ch_a_ctl2[j]; - reg_pair[5].val = &ch_b_eq[i]; - reg_pair[6].val = &ch_b_ctl2[j]; - - for (k = 0; k < 10; k++) { -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_write(i2c_phy_addr, - reg_pair[k].addr, - 1, reg_pair[k].val, 1); -#else - ret = i2c_get_chip_for_busnum(0, - i2c_phy_addr, - 1, &udev); - if (!ret) - ret = dm_i2c_write(udev, - reg_pair[k].addr, - reg_pair[k].val, 1); -#endif - if (ret) - goto error; - } - - mdelay(100); - ret = miiphy_read(dev, phy_addr, 0x11, &value); - if (ret > 0) - goto error; - mdelay(1); - ret = miiphy_read(dev, phy_addr, 0x11, &value); - if (ret > 0) - goto error; - mdelay(10); - if ((value & 0xf) == 0xf) { - printf("DPMAC %d :PHY is ..... Configured\n", - dpmac); - return; - } - } - } -error: - printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac); - return; -} - -static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u8 muxval) -{ - struct mii_dev *bus; - const char *name = ls2080a_qds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -static void ls2080a_qds_enable_SFP_TX(u8 muxval) -{ - u8 brdcfg9; - - brdcfg9 = QIXIS_READ(brdcfg[9]); - brdcfg9 &= ~BRDCFG9_SFPTX_MASK; - brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT); - QIXIS_WRITE(brdcfg[9], brdcfg9); -} - -static void ls2080a_qds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - - if (muxval <= 5) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr, - int devad, int regnum) -{ - struct ls2080a_qds_mdio *priv = bus->priv; - - ls2080a_qds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct ls2080a_qds_mdio *priv = bus->priv; - - ls2080a_qds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int ls2080a_qds_mdio_reset(struct mii_dev *bus) -{ - struct ls2080a_qds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval) -{ - struct ls2080a_qds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate ls2080a_qds MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate ls2080a_qds private data\n"); - free(bus); - return -1; - } - - bus->read = ls2080a_qds_mdio_read; - bus->write = ls2080a_qds_mdio_write; - bus->reset = ls2080a_qds_mdio_reset; - strcpy(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - - return mdio_register(bus); -} - -/* - * Initialize the dpmac_info array. - * - */ -static void initialize_dpmac_to_slot(void) -{ - struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; - int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & - FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) - >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; - int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) & - FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK) - >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; - - char *env_hwconfig; - env_hwconfig = env_get("hwconfig"); - - switch (serdes1_prtcl) { - case 0x07: - case 0x09: - case 0x33: - printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", - serdes1_prtcl); - lane_to_slot_fsm1[0] = EMI1_SLOT1; - lane_to_slot_fsm1[1] = EMI1_SLOT1; - lane_to_slot_fsm1[2] = EMI1_SLOT1; - lane_to_slot_fsm1[3] = EMI1_SLOT1; - if (hwconfig_f("xqsgmii", env_hwconfig)) { - lane_to_slot_fsm1[4] = EMI1_SLOT1; - lane_to_slot_fsm1[5] = EMI1_SLOT1; - lane_to_slot_fsm1[6] = EMI1_SLOT1; - lane_to_slot_fsm1[7] = EMI1_SLOT1; - } else { - lane_to_slot_fsm1[4] = EMI1_SLOT2; - lane_to_slot_fsm1[5] = EMI1_SLOT2; - lane_to_slot_fsm1[6] = EMI1_SLOT2; - lane_to_slot_fsm1[7] = EMI1_SLOT2; - } - break; - - case 0x39: - printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", - serdes1_prtcl); - if (hwconfig_f("xqsgmii", env_hwconfig)) { - lane_to_slot_fsm1[0] = EMI1_SLOT3; - lane_to_slot_fsm1[1] = EMI1_SLOT3; - lane_to_slot_fsm1[2] = EMI1_SLOT3; - lane_to_slot_fsm1[3] = EMI_NONE; - } else { - lane_to_slot_fsm1[0] = EMI_NONE; - lane_to_slot_fsm1[1] = EMI_NONE; - lane_to_slot_fsm1[2] = EMI_NONE; - lane_to_slot_fsm1[3] = EMI_NONE; - } - lane_to_slot_fsm1[4] = EMI1_SLOT3; - lane_to_slot_fsm1[5] = EMI1_SLOT3; - lane_to_slot_fsm1[6] = EMI1_SLOT3; - lane_to_slot_fsm1[7] = EMI_NONE; - break; - - case 0x4D: - printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", - serdes1_prtcl); - if (hwconfig_f("xqsgmii", env_hwconfig)) { - lane_to_slot_fsm1[0] = EMI1_SLOT3; - lane_to_slot_fsm1[1] = EMI1_SLOT3; - lane_to_slot_fsm1[2] = EMI_NONE; - lane_to_slot_fsm1[3] = EMI_NONE; - } else { - lane_to_slot_fsm1[0] = EMI_NONE; - lane_to_slot_fsm1[1] = EMI_NONE; - lane_to_slot_fsm1[2] = EMI_NONE; - lane_to_slot_fsm1[3] = EMI_NONE; - } - lane_to_slot_fsm1[4] = EMI1_SLOT3; - lane_to_slot_fsm1[5] = EMI1_SLOT3; - lane_to_slot_fsm1[6] = EMI_NONE; - lane_to_slot_fsm1[7] = EMI_NONE; - break; - - case 0x2A: - case 0x4B: - case 0x4C: - printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", - serdes1_prtcl); - break; - default: - printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n", - __func__, serdes1_prtcl); - break; - } - - switch (serdes2_prtcl) { - case 0x07: - case 0x08: - case 0x09: - case 0x49: - printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n", - serdes2_prtcl); - lane_to_slot_fsm2[0] = EMI1_SLOT4; - lane_to_slot_fsm2[1] = EMI1_SLOT4; - lane_to_slot_fsm2[2] = EMI1_SLOT4; - lane_to_slot_fsm2[3] = EMI1_SLOT4; - - if (hwconfig_f("xqsgmii", env_hwconfig)) { - lane_to_slot_fsm2[4] = EMI1_SLOT4; - lane_to_slot_fsm2[5] = EMI1_SLOT4; - lane_to_slot_fsm2[6] = EMI1_SLOT4; - lane_to_slot_fsm2[7] = EMI1_SLOT4; - } else { - /* No MDIO physical connection */ - lane_to_slot_fsm2[4] = EMI1_SLOT6; - lane_to_slot_fsm2[5] = EMI1_SLOT6; - lane_to_slot_fsm2[6] = EMI1_SLOT6; - lane_to_slot_fsm2[7] = EMI1_SLOT6; - } - break; - - case 0x47: - printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n", - serdes2_prtcl); - lane_to_slot_fsm2[0] = EMI_NONE; - lane_to_slot_fsm2[1] = EMI1_SLOT5; - lane_to_slot_fsm2[2] = EMI1_SLOT5; - lane_to_slot_fsm2[3] = EMI1_SLOT5; - - if (hwconfig_f("xqsgmii", env_hwconfig)) { - lane_to_slot_fsm2[4] = EMI_NONE; - lane_to_slot_fsm2[5] = EMI1_SLOT5; - lane_to_slot_fsm2[6] = EMI1_SLOT5; - lane_to_slot_fsm2[7] = EMI1_SLOT5; - } - break; - - case 0x57: - printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n", - serdes2_prtcl); - if (hwconfig_f("xqsgmii", env_hwconfig)) { - lane_to_slot_fsm2[0] = EMI_NONE; - lane_to_slot_fsm2[1] = EMI_NONE; - lane_to_slot_fsm2[2] = EMI_NONE; - lane_to_slot_fsm2[3] = EMI_NONE; - } - lane_to_slot_fsm2[4] = EMI_NONE; - lane_to_slot_fsm2[5] = EMI_NONE; - lane_to_slot_fsm2[6] = EMI1_SLOT5; - lane_to_slot_fsm2[7] = EMI1_SLOT5; - break; - - default: - printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n", - __func__ , serdes2_prtcl); - break; - } -} - -void ls2080a_handle_phy_interface_sgmii(int dpmac_id) -{ - int lane, slot; - struct mii_dev *bus; - struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; - int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & - FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) - >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; - int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) & - FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK) - >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; - - int *riser_phy_addr; - char *env_hwconfig = env_get("hwconfig"); - - if (hwconfig_f("xqsgmii", env_hwconfig)) - riser_phy_addr = &xqsgii_riser_phy_addr[0]; - else - riser_phy_addr = &sgmii_riser_phy_addr[0]; - - if (dpmac_id > WRIOP1_DPMAC9) - goto serdes2; - - switch (serdes1_prtcl) { - case 0x07: - case 0x39: - case 0x4D: - lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id - 1); - - slot = lane_to_slot_fsm1[lane]; - - switch (++slot) { - case 1: - /* Slot housing a SGMII riser card? */ - wriop_set_phy_address(dpmac_id, 0, - riser_phy_addr[dpmac_id - 1]); - dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; - bus = mii_dev_for_muxval(EMI1_SLOT1); - wriop_set_mdio(dpmac_id, bus); - break; - case 2: - /* Slot housing a SGMII riser card? */ - wriop_set_phy_address(dpmac_id, 0, - riser_phy_addr[dpmac_id - 1]); - dpmac_info[dpmac_id].board_mux = EMI1_SLOT2; - bus = mii_dev_for_muxval(EMI1_SLOT2); - wriop_set_mdio(dpmac_id, bus); - break; - case 3: - if (slot == EMI_NONE) - return; - if (serdes1_prtcl == 0x39) { - wriop_set_phy_address(dpmac_id, 0, - riser_phy_addr[dpmac_id - 2]); - if (dpmac_id >= 6 && hwconfig_f("xqsgmii", - env_hwconfig)) - wriop_set_phy_address(dpmac_id, 0, - riser_phy_addr[dpmac_id - 3]); - } else { - wriop_set_phy_address(dpmac_id, 0, - riser_phy_addr[dpmac_id - 2]); - if (dpmac_id >= 7 && hwconfig_f("xqsgmii", - env_hwconfig)) - wriop_set_phy_address(dpmac_id, 0, - riser_phy_addr[dpmac_id - 3]); - } - dpmac_info[dpmac_id].board_mux = EMI1_SLOT3; - bus = mii_dev_for_muxval(EMI1_SLOT3); - wriop_set_mdio(dpmac_id, bus); - break; - case 4: - break; - case 5: - break; - case 6: - break; - } - break; - default: - printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n", - __func__ , serdes1_prtcl); - break; - } - -serdes2: - switch (serdes2_prtcl) { - case 0x07: - case 0x08: - case 0x49: - case 0x47: - case 0x57: - lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 + - (dpmac_id - 9)); - slot = lane_to_slot_fsm2[lane]; - - switch (++slot) { - case 1: - break; - case 3: - break; - case 4: - /* Slot housing a SGMII riser card? */ - wriop_set_phy_address(dpmac_id, 0, - riser_phy_addr[dpmac_id - 9]); - dpmac_info[dpmac_id].board_mux = EMI1_SLOT4; - bus = mii_dev_for_muxval(EMI1_SLOT4); - wriop_set_mdio(dpmac_id, bus); - break; - case 5: - if (slot == EMI_NONE) - return; - if (serdes2_prtcl == 0x47) { - wriop_set_phy_address(dpmac_id, 0, - riser_phy_addr[dpmac_id - 10]); - if (dpmac_id >= 14 && hwconfig_f("xqsgmii", - env_hwconfig)) - wriop_set_phy_address(dpmac_id, 0, - riser_phy_addr[dpmac_id - 11]); - } else { - wriop_set_phy_address(dpmac_id, 0, - riser_phy_addr[dpmac_id - 11]); - } - dpmac_info[dpmac_id].board_mux = EMI1_SLOT5; - bus = mii_dev_for_muxval(EMI1_SLOT5); - wriop_set_mdio(dpmac_id, bus); - break; - case 6: - /* Slot housing a SGMII riser card? */ - wriop_set_phy_address(dpmac_id, 0, - riser_phy_addr[dpmac_id - 13]); - dpmac_info[dpmac_id].board_mux = EMI1_SLOT6; - bus = mii_dev_for_muxval(EMI1_SLOT6); - wriop_set_mdio(dpmac_id, bus); - break; - } - break; - default: - printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n", - __func__, serdes2_prtcl); - break; - } -} - -void ls2080a_handle_phy_interface_qsgmii(int dpmac_id) -{ - int lane = 0, slot; - struct mii_dev *bus; - struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; - int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & - FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) - >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; - - switch (serdes1_prtcl) { - case 0x33: - switch (dpmac_id) { - case 1: - case 2: - case 3: - case 4: - lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A); - break; - case 5: - case 6: - case 7: - case 8: - lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B); - break; - case 9: - case 10: - case 11: - case 12: - lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C); - break; - case 13: - case 14: - case 15: - case 16: - lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D); - break; - } - - slot = lane_to_slot_fsm1[lane]; - - switch (++slot) { - case 1: - /* Slot housing a QSGMII riser card? */ - wriop_set_phy_address(dpmac_id, 0, dpmac_id - 1); - dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; - bus = mii_dev_for_muxval(EMI1_SLOT1); - wriop_set_mdio(dpmac_id, bus); - break; - case 3: - break; - case 4: - break; - case 5: - break; - case 6: - break; - } - break; - default: - printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n", - serdes1_prtcl); - break; - } - - qsgmii_configure_repeater(dpmac_id); -} - -void ls2080a_handle_phy_interface_xsgmii(int i) -{ - struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; - int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & - FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) - >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; - - switch (serdes1_prtcl) { - case 0x2A: - case 0x4B: - case 0x4C: - /* - * 10GBase-R does not need a PHY to work, but to avoid U-Boot - * use default PHY address which is zero to a MAC when it found - * a MAC has no PHY address, we give a PHY address to 10GBase-R - * MAC, and should not use a real XAUI PHY address, since MDIO - * can access it successfully, and then MDIO thinks the XAUI - * card is used for the 10GBase-R MAC, which will cause error. - */ - wriop_set_phy_address(i, 0, i + 4); - ls2080a_qds_enable_SFP_TX(SFP_TX); - - break; - default: - printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n", - serdes1_prtcl); - break; - } -} -#endif -#endif // !CONFIG_DM_ETH - -int board_eth_init(struct bd_info *bis) -{ -#ifndef CONFIG_DM_ETH -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) - struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; - int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & - FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) - >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; - int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) & - FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK) - >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; - - struct memac_mdio_info *memac_mdio0_info; - struct memac_mdio_info *memac_mdio1_info; - unsigned int i; - char *env_hwconfig; - int error; - - env_hwconfig = env_get("hwconfig"); - - initialize_dpmac_to_slot(); - - memac_mdio0_info = (struct memac_mdio_info *)malloc( - sizeof(struct memac_mdio_info)); - memac_mdio0_info->regs = - (struct memac_mdio_controller *) - CFG_SYS_FSL_WRIOP1_MDIO1; - memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME; - - /* Register the real MDIO1 bus */ - fm_memac_mdio_init(bis, memac_mdio0_info); - - memac_mdio1_info = (struct memac_mdio_info *)malloc( - sizeof(struct memac_mdio_info)); - memac_mdio1_info->regs = - (struct memac_mdio_controller *) - CFG_SYS_FSL_WRIOP1_MDIO2; - memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME; - - /* Register the real MDIO2 bus */ - fm_memac_mdio_init(bis, memac_mdio1_info); - - /* Register the muxing front-ends to the MDIO buses */ - ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1); - ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2); - ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3); - ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4); - ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5); - ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6); - - ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2); - - for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { - switch (wriop_get_enet_if(i)) { - case PHY_INTERFACE_MODE_QSGMII: - ls2080a_handle_phy_interface_qsgmii(i); - break; - case PHY_INTERFACE_MODE_SGMII: - ls2080a_handle_phy_interface_sgmii(i); - break; - case PHY_INTERFACE_MODE_XGMII: - ls2080a_handle_phy_interface_xsgmii(i); - break; - default: - break; - - if (i == 16) - i = NUM_WRIOP_PORTS; - } - } - - error = cpu_eth_init(bis); - - if (hwconfig_f("xqsgmii", env_hwconfig)) { - if (serdes1_prtcl == 0x7) - sgmii_configure_repeater(1); - if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 || - serdes2_prtcl == 0x49) - sgmii_configure_repeater(2); - } -#endif -#endif // !CONFIG_DM_ETH - -#ifdef CONFIG_DM_ETH - return 0; -#else - return pci_eth_init(bis); -#endif -} - -#if defined(CONFIG_RESET_PHY_R) -void reset_phy(void) -{ - mc_env_boot(); -} -#endif /* CONFIG_RESET_PHY_R */ - -#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT) - -/* Structure to hold SERDES protocols supported in case of - * CONFIG_DM_ETH enabled (network interfaces are described in the DTS). - * - * @serdes_block: the index of the SERDES block - * @serdes_protocol: the decimal value of the protocol supported - * @dts_needed: DTS notes describing the current configuration are needed - * - * When dts_needed is true, the board_fit_config_name_match() function - * will try to exactly match the current configuration of the block with a DTS - * name provided. - */ -static struct serdes_configuration { - u8 serdes_block; - u32 serdes_protocol; - bool dts_needed; -} supported_protocols[] = { - /* Serdes block #1 */ - {1, 42, true}, - - /* Serdes block #2 */ - {2, 65, false}, -}; - -#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) - -static bool protocol_supported(u8 serdes_block, u32 protocol) -{ - struct serdes_configuration serdes_conf; - int i; - - for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { - serdes_conf = supported_protocols[i]; - if (serdes_conf.serdes_block == serdes_block && - serdes_conf.serdes_protocol == protocol) - return true; - } - - return false; -} - -static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) -{ - struct serdes_configuration serdes_conf; - int i; - - for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { - serdes_conf = supported_protocols[i]; - if (serdes_conf.serdes_block == serdes_block && - serdes_conf.serdes_protocol == protocol) { - if (serdes_conf.dts_needed == true) - sprintf(str, "%u", protocol); - else - sprintf(str, "x"); - return; - } - } -} - -int board_fit_config_name_match(const char *name) -{ - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 rcw_status = in_le32(&gur->rcwsr[28]); - char srds_s1_str[2], srds_s2_str[2]; - u32 srds_s1, srds_s2; - char expected_dts[100]; - - srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; - - srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; - srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; - - /* Check for supported protocols. The default DTS will be used - * in this case - */ - if (!protocol_supported(1, srds_s1) || - !protocol_supported(2, srds_s2)) - return -1; - - get_str_protocol(1, srds_s1, srds_s1_str); - get_str_protocol(2, srds_s2, srds_s2_str); - - printf("expected_dts %s\n", expected_dts); - sprintf(expected_dts, "fsl-ls2080a-qds-%s-%s", - srds_s1_str, srds_s2_str); - - if (!strcmp(name, expected_dts)) - return 0; - - printf("this is not!\n"); - return -1; -} - -#endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c deleted file mode 100644 index 91db618227d..00000000000 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ /dev/null @@ -1,353 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor - * Copyright 2021 NXP - */ -#include <common.h> -#include <clock_legacy.h> -#include <display_options.h> -#include <env.h> -#include <init.h> -#include <malloc.h> -#include <errno.h> -#include <netdev.h> -#include <fsl_ifc.h> -#include <fsl_ddr.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <fdt_support.h> -#include <linux/libfdt.h> -#include <fsl-mc/fsl_mc.h> -#include <env_internal.h> -#include <i2c.h> -#include <rtc.h> -#include <asm/arch/soc.h> -#include <hwconfig.h> -#include <asm/arch/ppa.h> -#include <asm/arch-fsl-layerscape/fsl_icid.h> -#include "../common/i2c_mux.h" - -#include "../common/qixis.h" -#include "ls2080aqds_qixis.h" -#include "../common/vid.h" - -#define PIN_MUX_SEL_SDHC 0x00 -#define PIN_MUX_SEL_DSPI 0x0a -#define SCFG_QSPICLKCTRL_DIV_20 (5 << 27) - -#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value) - -DECLARE_GLOBAL_DATA_PTR; - -enum { - MUX_TYPE_SDHC, - MUX_TYPE_DSPI, -}; - -unsigned long long get_qixis_addr(void) -{ - unsigned long long addr; - - if (gd->flags & GD_FLG_RELOC) - addr = QIXIS_BASE_PHYS; - else - addr = QIXIS_BASE_PHYS_EARLY; - - /* - * IFC address under 256MB is mapped to 0x30000000, any address above - * is mapped to 0x5_10000000 up to 4GB. - */ - addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; - - return addr; -} - -int checkboard(void) -{ - char buf[64]; - u8 sw; - static const char *const freq[] = {"100", "125", "156.25", - "100 separate SSCG"}; - int clock; - - cpu_name(buf); - printf("Board: %s-QDS, ", buf); - - sw = QIXIS_READ(arch); - printf("Board Arch: V%d, ", sw >> 4); - printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); - - memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); - - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - printf("vBank: %d\n", sw); - else if (sw == 0x8) - puts("PromJet\n"); - else if (sw == 0x9) - puts("NAND\n"); - else if (sw == 0xf) - puts("QSPI\n"); - else if (sw == 0x15) - printf("IFCCard\n"); - else - printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); - - printf("FPGA: v%d (%s), build %d", - (int)QIXIS_READ(scver), qixis_read_tag(buf), - (int)qixis_read_minor()); - /* the timestamp string contains "\n" at the end */ - printf(" on %s", qixis_read_time(buf)); - - /* - * Display the actual SERDES reference clocks as configured by the - * dip switches on the board. Note that the SWx registers could - * technically be set to force the reference clocks to match the - * values that the SERDES expects (or vice versa). For now, however, - * we just display both values and hope the user notices when they - * don't match. - */ - puts("SERDES1 Reference : "); - sw = QIXIS_READ(brdcfg[2]); - clock = (sw >> 6) & 3; - printf("Clock1 = %sMHz ", freq[clock]); - clock = (sw >> 4) & 3; - printf("Clock2 = %sMHz", freq[clock]); - - puts("\nSERDES2 Reference : "); - clock = (sw >> 2) & 3; - printf("Clock1 = %sMHz ", freq[clock]); - clock = (sw >> 0) & 3; - printf("Clock2 = %sMHz\n", freq[clock]); - - return 0; -} - -unsigned long get_board_sys_clk(void) -{ - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); - - switch (sysclk_conf & 0x0F) { - case QIXIS_SYSCLK_83: - return 83333333; - case QIXIS_SYSCLK_100: - return 100000000; - case QIXIS_SYSCLK_125: - return 125000000; - case QIXIS_SYSCLK_133: - return 133333333; - case QIXIS_SYSCLK_150: - return 150000000; - case QIXIS_SYSCLK_160: - return 160000000; - case QIXIS_SYSCLK_166: - return 166666666; - } - return 66666666; -} - -unsigned long get_board_ddr_clk(void) -{ - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); - - switch ((ddrclk_conf & 0x30) >> 4) { - case QIXIS_DDRCLK_100: - return 100000000; - case QIXIS_DDRCLK_125: - return 125000000; - case QIXIS_DDRCLK_133: - return 133333333; - } - return 66666666; -} - -int config_board_mux(int ctrl_type) -{ - u8 reg5; - - reg5 = QIXIS_READ(brdcfg[5]); - - switch (ctrl_type) { - case MUX_TYPE_SDHC: - reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); - break; - case MUX_TYPE_DSPI: - reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); - break; - default: - printf("Wrong mux interface type\n"); - return -1; - } - - QIXIS_WRITE(brdcfg[5], reg5); - - return 0; -} - -int board_init(void) -{ - char *env_hwconfig; - u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; - u32 val; - - init_final_memctl_regs(); - - val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); - - env_hwconfig = env_get("hwconfig"); - - if (hwconfig_f("dspi", env_hwconfig) && - DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) - config_board_mux(MUX_TYPE_DSPI); - else - config_board_mux(MUX_TYPE_SDHC); - -#if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_FSL_QSPI) - val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4); - - if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3)) - QIXIS_WRITE(brdcfg[9], - (QIXIS_READ(brdcfg[9]) & 0xf8) | - FSL_QIXIS_BRDCFG9_QSPI); -#endif - - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - -#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT -#if CONFIG_IS_ENABLED(DM_I2C) - rtc_enable_32khz_output(0, CFG_SYS_I2C_RTC_ADDR); -#else - rtc_enable_32khz_output(); -#endif -#endif - -#ifdef CONFIG_FSL_LS_PPA - ppa_init(); -#endif - -#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) - pci_init(); -#endif - - return 0; -} - -int board_early_init_f(void) -{ -#if defined(CONFIG_SYS_I2C_EARLY_INIT) - i2c_early_init_f(); -#endif - fsl_lsch3_early_init_f(); -#ifdef CONFIG_FSL_QSPI - /* input clk: 1/2 platform clk, output: input/20 */ - out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20); -#endif - return 0; -} - -int misc_init_r(void) -{ - if (adjust_vdd(0)) - printf("Warning: Adjusting core voltage failed.\n"); - - return 0; -} - -void detail_board_ddr_info(void) -{ - puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); - print_ddr_info(0); -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { - puts("\nDP-DDR "); - print_size(gd->bd->bi_dram[2].size, ""); - print_ddr_info(CONFIG_DP_DDR_CTRL); - } -#endif -} - -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) -void fdt_fixup_board_enet(void *fdt) -{ - int offset; - - offset = fdt_path_offset(fdt, "/soc/fsl-mc"); - - if (offset < 0) - offset = fdt_path_offset(fdt, "/fsl-mc"); - - if (offset < 0) { - printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", - __func__, offset); - return; - } - - if (get_mc_boot_status() == 0 && - (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) - fdt_status_okay(fdt, offset); - else - fdt_status_fail(fdt, offset); -} - -void board_quiesce_devices(void) -{ - fsl_mc_ldpaa_exit(gd->bd); -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, struct bd_info *bd) -{ - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; - - ft_cpu_setup(blob, bd); - - /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; - -#ifdef CONFIG_RESV_RAM - /* reduce size if reserved memory is within this bank */ - if (gd->arch.resv_ram >= base[0] && - gd->arch.resv_ram < base[0] + size[0]) - size[0] = gd->arch.resv_ram - base[0]; - else if (gd->arch.resv_ram >= base[1] && - gd->arch.resv_ram < base[1] + size[1]) - size[1] = gd->arch.resv_ram - base[1]; -#endif - - fdt_fixup_memory_banks(blob, base, size, 2); - - fdt_fsl_mc_fixup_iommu_map_entry(blob); - - fsl_fdt_fixup_dr_usb(blob, bd); - -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) - fdt_fixup_board_enet(blob); -#endif - - fdt_fixup_icid(blob); - - return 0; -} -#endif - -void qixis_dump_switch(void) -{ - int i, nr_of_cfgsw; - - QIXIS_WRITE(cms[0], 0x00); - nr_of_cfgsw = QIXIS_READ(cms[1]); - - puts("DIP switch settings dump:\n"); - for (i = 1; i <= nr_of_cfgsw; i++) { - QIXIS_WRITE(cms[0], i); - printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); - } -} diff --git a/board/freescale/ls2080aqds/ls2080aqds_qixis.h b/board/freescale/ls2080aqds/ls2080aqds_qixis.h deleted file mode 100644 index 7b2607b8daa..00000000000 --- a/board/freescale/ls2080aqds/ls2080aqds_qixis.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __LS2_QDS_QIXIS_H__ -#define __LS2_QDS_QIXIS_H__ - -/* SYSCLK */ -#define QIXIS_SYSCLK_66 0x0 -#define QIXIS_SYSCLK_83 0x1 -#define QIXIS_SYSCLK_100 0x2 -#define QIXIS_SYSCLK_125 0x3 -#define QIXIS_SYSCLK_133 0x4 -#define QIXIS_SYSCLK_150 0x5 -#define QIXIS_SYSCLK_160 0x6 -#define QIXIS_SYSCLK_166 0x7 - -/* DDRCLK */ -#define QIXIS_DDRCLK_66 0x0 -#define QIXIS_DDRCLK_100 0x1 -#define QIXIS_DDRCLK_125 0x2 -#define QIXIS_DDRCLK_133 0x3 - -#define BRDCFG4_EMISEL_MASK 0xE0 -#define BRDCFG4_EMISEL_SHIFT 5 -#define BRDCFG9_SFPTX_MASK 0x10 -#define BRDCFG9_SFPTX_SHIFT 4 -#endif /*__LS2_QDS_QIXIS_H__*/