[PATCH v2 0/3] arm: socfpga: arria10: Add save_boot_params()
This patchset add support save reset status value from bootrom for Arria 10.
v2: - Add macro for BOOTROM_SHARED_MEM_SIZE. - Change to use SOCFPGA_PHYS_OCRAM_SIZE macro. - Change to static for rst_mgr_status.
History: v1: https://patchwork.ozlabs.org/patch/1245681/
Ley Foon Tan (3): arm: socfpga: Add onchip RAM size macro configs: socfpga: Change to use SOCFPGA_PHYS_OCRAM_SIZE macro arm: socfpga: arria10: Add save_boot_params()
.../mach-socfpga/include/mach/base_addr_a10.h | 2 ++ .../mach-socfpga/include/mach/base_addr_ac5.h | 2 ++ arch/arm/mach-socfpga/spl_a10.c | 32 +++++++++++++++++++ include/configs/socfpga_common.h | 5 +-- 4 files changed, 39 insertions(+), 2 deletions(-)
Add OCRAM size macro for Gen5 and Arria 10.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 2 ++ arch/arm/mach-socfpga/include/mach/base_addr_ac5.h | 2 ++ 2 files changed, 4 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h index 929c413e0392..b947cc07291c 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h @@ -47,4 +47,6 @@ #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS 0xffd13400 #define SOCFPGA_NOC_FW_H2F_SCR_OFST 0xffd13500
+#define SOCFPGA_PHYS_OCRAM_SIZE 0x40000 + #endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h index 2725e9fcc345..da966fb45836 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h @@ -59,4 +59,6 @@ #define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000 #define SOCFPGA_DMASECURE_ADDRESS 0xffe01000
+#define SOCFPGA_PHYS_OCRAM_SIZE 0x10000 + #endif /* _SOCFPGA_BASE_ADDRS_H_ */
Change to use SOCFPGA_PHYS_OCRAM_SIZE macro for onchip RAM size.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- include/configs/socfpga_common.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index ec4184369539..410ec80618f5 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -21,14 +21,15 @@ #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE #if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 /* SPL memory allocation configuration, this is for FAT implementation */ #ifndef CONFIG_SYS_SPL_MALLOC_SIZE #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000 #endif -#define CONFIG_SYS_INIT_RAM_SIZE (0x40000 - CONFIG_SYS_SPL_MALLOC_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ + CONFIG_SYS_SPL_MALLOC_SIZE) #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE) #endif
Add save_boot_params() to save reset status value from bootrom.
Bootrom will clear the status register in reset manager and stores the reset status value in shared memory. Bootrom stores shared data at last 2KB of onchip RAM.
This function save reset status provided by bootrom to rst_mgr_status. More information about reset status register value can be found in reset manager register description.
When running in debugger without bootrom, r0 to r3 are random values. So, skip save the value when r0 is not bootrom shared data address.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
--- v2: - Add macro for BOOTROM_SHARED_MEM_SIZE. - Change to use SOCFPGA_PHYS_OCRAM_SIZE macro. - Change to static for rst_mgr_status. --- arch/arm/mach-socfpga/spl_a10.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index d9ef851054d8..b10be3326803 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -33,6 +33,38 @@
DECLARE_GLOBAL_DATA_PTR;
+#define BOOTROM_SHARED_MEM_SIZE 0x800 /* 2KB */ +#define BOOTROM_SHARED_MEM_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + SOCFPGA_PHYS_OCRAM_SIZE - \ + BOOTROM_SHARED_MEM_SIZE) +#define RST_STATUS_SHARED_ADDR (BOOTROM_SHARED_MEM_ADDR + 0x438) +static u32 rst_mgr_status __section(.data); + +/* + * Bootrom will clear the status register in reset manager and stores the + * reset status value in shared memory. Bootrom stores shared data at last + * 2KB of onchip RAM. + * This function save reset status provided by BootROM to rst_mgr_status. + * More information about reset status register value can be found in reset + * manager register description. + * When running in debugger without Bootrom, r0 to r3 are random values. + * So, skip save the value when r0 is not BootROM shared data address. + * + * r0 - Contains the pointer to the shared memory block. The shared + * memory block is located in the top 2 KB of on-chip RAM. + * r1 - contains the length of the shared memory. + * r2 - unused and set to 0x0. + * r3 - points to the version block. + */ +void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, + unsigned long r3) +{ + if (r0 == BOOTROM_SHARED_MEM_ADDR) + rst_mgr_status = readl(RST_STATUS_SHARED_ADDR); + + save_boot_params_ret(); +} + u32 spl_boot_device(void) { const u32 bsel = readl(socfpga_get_sysmgr_addr() + SYSMGR_A10_BOOTINFO);
participants (2)
-
Ley Foon Tan -
Marek Vasut