[U-Boot] [PATCH 0/2] i.MX6 LPDDR2 fixes
Hey all,
The following two patches fix JEDEC violations that were observed when I was working on a board similar to the MX6SL EVK. Based on talking with Micron and reading up on what the code here is (and isn't) doing, I'm certain these issues exist on the reference platforms here. I'm publishing these for correctness. I'm also not updating the the SPL code as I haven't tested that (and only could for EVK anyhow) but would suggest it's worth a follow-up from tha maintainers.
Having had a similar board and memory part under logic analyzer, a tINIT3 violation was measured. The fix was involved keeping tXPR and SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC value for LPDDR2.
Cc: Jason Liu jason.hui.liu@nxp.com Cc: Ye Li ye.li@nxp.com Signed-off-by: Tom Rini trini@konsulko.com --- board/freescale/mx6qarm2/imximage_mx6dl.cfg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6qarm2/imximage_mx6dl.cfg b/board/freescale/mx6qarm2/imximage_mx6dl.cfg index ae8dcc6..1f5a0a5 100644 --- a/board/freescale/mx6qarm2/imximage_mx6dl.cfg +++ b/board/freescale/mx6qarm2/imximage_mx6dl.cfg @@ -234,7 +234,7 @@ DATA 4 0x021b0018 0x0000174C /* MMDC0_MDRWD;*/ DATA 4 0x021b002c 0x0f9f26d2 /* MMDC0_MDOR */ -DATA 4 0x021b0030 0x0000020e +DATA 4 0x021b0030 0x009f0e10 /* MMDC0_MDCFG3LP */ DATA 4 0x021b0038 0x00190778 /* MMDC0_MDOTC */ @@ -263,7 +263,7 @@ DATA 4 0x021b4018 0x0000174C /* MMDC1_MDRWD;*/ DATA 4 0x021b402c 0x0f9f26d2 /* MMDC1_MDOR */ -DATA 4 0x021b4030 0x0000020e +DATA 4 0x021b4030 0x009f0e10 /* MMDC1_MDCFG3LP */ DATA 4 0x021b4038 0x00190778 /* MMDC1_MDOTC */
On 01/04/2016 23:54, Tom Rini wrote:
Having had a similar board and memory part under logic analyzer, a tINIT3 violation was measured. The fix was involved keeping tXPR and SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC value for LPDDR2.
Cc: Jason Liu jason.hui.liu@nxp.com Cc: Ye Li ye.li@nxp.com Signed-off-by: Tom Rini trini@konsulko.com
board/freescale/mx6qarm2/imximage_mx6dl.cfg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6qarm2/imximage_mx6dl.cfg b/board/freescale/mx6qarm2/imximage_mx6dl.cfg index ae8dcc6..1f5a0a5 100644 --- a/board/freescale/mx6qarm2/imximage_mx6dl.cfg +++ b/board/freescale/mx6qarm2/imximage_mx6dl.cfg @@ -234,7 +234,7 @@ DATA 4 0x021b0018 0x0000174C /* MMDC0_MDRWD;*/ DATA 4 0x021b002c 0x0f9f26d2 /* MMDC0_MDOR */ -DATA 4 0x021b0030 0x0000020e +DATA 4 0x021b0030 0x009f0e10 /* MMDC0_MDCFG3LP */ DATA 4 0x021b0038 0x00190778 /* MMDC0_MDOTC */ @@ -263,7 +263,7 @@ DATA 4 0x021b4018 0x0000174C /* MMDC1_MDRWD;*/ DATA 4 0x021b402c 0x0f9f26d2 /* MMDC1_MDOR */ -DATA 4 0x021b4030 0x0000020e +DATA 4 0x021b4030 0x009f0e10 /* MMDC1_MDCFG3LP */ DATA 4 0x021b4038 0x00190778 /* MMDC1_MDOTC */
Applied to u-boot-imx, thanks !
Best regards, Stefano Babic
Having had a similar board and memory part under logic analyzer, a tINIT3 violation was measured. The fix was involved keeping tXPR and SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC value for LPDDR2. There was also a tIH-CA violation and this was resolved by writing the default value in rather than what the script here uses.
Cc: Fabio Estevam fabio.estevam@nxp.com Cc: Peng Fan peng.fan@nxp.com Signed-off-by: Tom Rini trini@konsulko.com --- board/freescale/mx6slevk/imximage.cfg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6slevk/imximage.cfg b/board/freescale/mx6slevk/imximage.cfg index 16ea597..c77bbde 100644 --- a/board/freescale/mx6slevk/imximage.cfg +++ b/board/freescale/mx6slevk/imximage.cfg @@ -70,7 +70,7 @@ DATA 4 0x020e05d0 0x00080000 DATA 4 0x021b001c 0x00008000 DATA 4 0x021b085c 0x1b4700c7 DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b0890 0x00300000 +DATA 4 0x021b0890 0x00400000 DATA 4 0x021b08b8 0x00000800 DATA 4 0x021b081c 0x33333333 DATA 4 0x021b0820 0x33333333 @@ -92,7 +92,7 @@ DATA 4 0x021b0010 0x00100A82 DATA 4 0x021b0014 0x00000093 DATA 4 0x021b0018 0x00001688 DATA 4 0x021b002c 0x0f9f26d2 -DATA 4 0x021b0030 0x0000020e +DATA 4 0x021b0030 0x009f0e10 DATA 4 0x021b0038 0x00190778 DATA 4 0x021b0008 0x00000000 DATA 4 0x021b0040 0x0000004f
On Fri, Apr 1, 2016 at 6:54 PM, Tom Rini trini@konsulko.com wrote:
Having had a similar board and memory part under logic analyzer, a tINIT3 violation was measured. The fix was involved keeping tXPR and SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC value for LPDDR2. There was also a tIH-CA violation and this was resolved by writing the default value in rather than what the script here uses.
Cc: Fabio Estevam fabio.estevam@nxp.com Cc: Peng Fan peng.fan@nxp.com Signed-off-by: Tom Rini trini@konsulko.com
Good fix!
Reviewed-by: Fabio Estevam fabio.estevam@nxp.com
On 01/04/2016 23:54, Tom Rini wrote:
Having had a similar board and memory part under logic analyzer, a tINIT3 violation was measured. The fix was involved keeping tXPR and SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC value for LPDDR2. There was also a tIH-CA violation and this was resolved by writing the default value in rather than what the script here uses.
Cc: Fabio Estevam fabio.estevam@nxp.com Cc: Peng Fan peng.fan@nxp.com Signed-off-by: Tom Rini trini@konsulko.com
board/freescale/mx6slevk/imximage.cfg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6slevk/imximage.cfg b/board/freescale/mx6slevk/imximage.cfg index 16ea597..c77bbde 100644 --- a/board/freescale/mx6slevk/imximage.cfg +++ b/board/freescale/mx6slevk/imximage.cfg @@ -70,7 +70,7 @@ DATA 4 0x020e05d0 0x00080000 DATA 4 0x021b001c 0x00008000 DATA 4 0x021b085c 0x1b4700c7 DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b0890 0x00300000 +DATA 4 0x021b0890 0x00400000 DATA 4 0x021b08b8 0x00000800 DATA 4 0x021b081c 0x33333333 DATA 4 0x021b0820 0x33333333 @@ -92,7 +92,7 @@ DATA 4 0x021b0010 0x00100A82 DATA 4 0x021b0014 0x00000093 DATA 4 0x021b0018 0x00001688 DATA 4 0x021b002c 0x0f9f26d2 -DATA 4 0x021b0030 0x0000020e +DATA 4 0x021b0030 0x009f0e10 DATA 4 0x021b0038 0x00190778 DATA 4 0x021b0008 0x00000000 DATA 4 0x021b0040 0x0000004f
Applied to u-boot-imx, thanks !
Best regards, Stefano Babic
On Sun, Apr 03, 2016 at 07:22:30PM +0200, Stefano Babic wrote:
On 01/04/2016 23:54, Tom Rini wrote:
Having had a similar board and memory part under logic analyzer, a tINIT3 violation was measured. The fix was involved keeping tXPR and SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC value for LPDDR2. There was also a tIH-CA violation and this was resolved by writing the default value in rather than what the script here uses.
Cc: Fabio Estevam fabio.estevam@nxp.com Cc: Peng Fan peng.fan@nxp.com Signed-off-by: Tom Rini trini@konsulko.com
board/freescale/mx6slevk/imximage.cfg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6slevk/imximage.cfg b/board/freescale/mx6slevk/imximage.cfg index 16ea597..c77bbde 100644 --- a/board/freescale/mx6slevk/imximage.cfg +++ b/board/freescale/mx6slevk/imximage.cfg @@ -70,7 +70,7 @@ DATA 4 0x020e05d0 0x00080000 DATA 4 0x021b001c 0x00008000 DATA 4 0x021b085c 0x1b4700c7 DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b0890 0x00300000 +DATA 4 0x021b0890 0x00400000 DATA 4 0x021b08b8 0x00000800 DATA 4 0x021b081c 0x33333333 DATA 4 0x021b0820 0x33333333 @@ -92,7 +92,7 @@ DATA 4 0x021b0010 0x00100A82 DATA 4 0x021b0014 0x00000093 DATA 4 0x021b0018 0x00001688 DATA 4 0x021b002c 0x0f9f26d2 -DATA 4 0x021b0030 0x0000020e +DATA 4 0x021b0030 0x009f0e10 DATA 4 0x021b0038 0x00190778 DATA 4 0x021b0008 0x00000000 DATA 4 0x021b0040 0x0000004f
Applied to u-boot-imx, thanks !
OK. But per 0/2 the SPL versions are out of sync and someone should take care of that :)
Hi Tom,
I know this already merged to i.mx tree. I still have a question for the tIH-CA violation.
In my side, the value is ok. clk is 400MHz. (0x30 * 256.0) * (1000000000000.0/400000000.0) = 468.75ps. And according to spec, to 800M date rate, the minimum tIH value is 290ps.
So I wonder how in your side it is tIH-CA violation.
Regards, Peng.
On Sun, Apr 03, 2016 at 02:06:05PM -0400, Tom Rini wrote:
On Sun, Apr 03, 2016 at 07:22:30PM +0200, Stefano Babic wrote:
On 01/04/2016 23:54, Tom Rini wrote:
Having had a similar board and memory part under logic analyzer, a tINIT3 violation was measured. The fix was involved keeping tXPR and SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC value for LPDDR2. There was also a tIH-CA violation and this was resolved by writing the default value in rather than what the script here uses.
Cc: Fabio Estevam fabio.estevam@nxp.com Cc: Peng Fan peng.fan@nxp.com Signed-off-by: Tom Rini trini@konsulko.com
board/freescale/mx6slevk/imximage.cfg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6slevk/imximage.cfg b/board/freescale/mx6slevk/imximage.cfg index 16ea597..c77bbde 100644 --- a/board/freescale/mx6slevk/imximage.cfg +++ b/board/freescale/mx6slevk/imximage.cfg @@ -70,7 +70,7 @@ DATA 4 0x020e05d0 0x00080000 DATA 4 0x021b001c 0x00008000 DATA 4 0x021b085c 0x1b4700c7 DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b0890 0x00300000 +DATA 4 0x021b0890 0x00400000 DATA 4 0x021b08b8 0x00000800 DATA 4 0x021b081c 0x33333333 DATA 4 0x021b0820 0x33333333 @@ -92,7 +92,7 @@ DATA 4 0x021b0010 0x00100A82 DATA 4 0x021b0014 0x00000093 DATA 4 0x021b0018 0x00001688 DATA 4 0x021b002c 0x0f9f26d2 -DATA 4 0x021b0030 0x0000020e +DATA 4 0x021b0030 0x009f0e10 DATA 4 0x021b0038 0x00190778 DATA 4 0x021b0008 0x00000000 DATA 4 0x021b0040 0x0000004f
Applied to u-boot-imx, thanks !
OK. But per 0/2 the SPL versions are out of sync and someone should take care of that :)
-- Tom
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
On Tue, Apr 05, 2016 at 04:53:28PM +0800, Peng Fan wrote:
Hi Tom,
I know this already merged to i.mx tree. I still have a question for the tIH-CA violation.
It's not in mainline 'tho so it can always come out :)
In my side, the value is ok. clk is 400MHz. (0x30 * 256.0) * (1000000000000.0/400000000.0) = 468.75ps. And according to spec, to 800M date rate, the minimum tIH value is 290ps.
So I wonder how in your side it is tIH-CA violation.
The board we measured this on is based on the mx6slevk and this particular part of the board (layout, etc) is unchanged. Micron put the board under analysis and measured these violations (along with that we don't issue a reset before configuring CS1, I still might try and push that change up for the EVK at least, not armadillo tho).
On 05/04/2016 15:43, Tom Rini wrote:
On Tue, Apr 05, 2016 at 04:53:28PM +0800, Peng Fan wrote:
Hi Tom,
I know this already merged to i.mx tree. I still have a question for the tIH-CA violation.
It's not in mainline 'tho so it can always come out :)
Right - it is still in u-boot-imx, and I can revert it before my PR.
In my side, the value is ok. clk is 400MHz. (0x30 * 256.0) * (1000000000000.0/400000000.0) = 468.75ps. And according to spec, to 800M date rate, the minimum tIH value is 290ps.
So I wonder how in your side it is tIH-CA violation.
The board we measured this on is based on the mx6slevk and this particular part of the board (layout, etc) is unchanged. Micron put the board under analysis and measured these violations (along with that we don't issue a reset before configuring CS1, I still might try and push that change up for the EVK at least, not armadillo tho).
Stefano
Hi Tom,
On Tue, Apr 05, 2016 at 09:43:11AM -0400, Tom Rini wrote:
On Tue, Apr 05, 2016 at 04:53:28PM +0800, Peng Fan wrote:
Hi Tom,
I know this already merged to i.mx tree. I still have a question for the tIH-CA violation.
It's not in mainline 'tho so it can always come out :)
In my side, the value is ok. clk is 400MHz. (0x30 * 256.0) * (1000000000000.0/400000000.0) = 468.75ps. And according to spec, to 800M date rate, the minimum tIH value is 290ps.
So I wonder how in your side it is tIH-CA violation.
The board we measured this on is based on the mx6slevk and this particular part of the board (layout, etc) is unchanged. Micron put the board under analysis and measured these violations (along with that we don't issue a reset before configuring CS1, I still might try and push that change up for the EVK at least, not armadillo tho).
I have no way to measure the signals (:. So just formula computing: If setting the value to 0x40, then tIH is (0x40 / 256.0) * (1000000000000.0/400000000.0) = 625ps. If setting the value to 0x30, then tIH is (0x30 / 256.0) * (1000000000000.0/400000000.0) = 468.75ps.
Both value does not violate the LPDDR2 spec, bigger that 290ps which 800M date rate requires the minimum value.
I can not say which value is better. Anyway different board may have different value.
since you measured the signals, and value 0x30 is not good, I am ok with your change.
Regards, Peng.
-- Tom
participants (4)
-
Fabio Estevam -
Peng Fan -
Stefano Babic -
Tom Rini