[U-Boot] [PATCH v2 1/4] macb: initial support for Cadence GEM
The Cadence GEM is based on the MACB Ethernet controller but has a few small changes with regards to register and bitfield placement. This patch detects the presence of a GEM by reading the module ID register and setting a flag appropriately.
This handles the new HW address, USRIO and hash register base register locations in GEM.
Signed-off-by: Dave Aldridge fovsoft@gmail.com --- Changes for v2: - Cleaned up issues reported by checkpatch
drivers/net/macb.c | 18 +++++++++++----- drivers/net/macb.h | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+), 6 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c index c63eea9..89491c8 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -88,6 +88,7 @@ struct macb_dma_desc {
struct macb_device { void *regs; + int is_gem;
unsigned int rx_tail; unsigned int tx_head; @@ -473,18 +474,19 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \ defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \ defined(CONFIG_AT91SAM9XE) - macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); + macb_or_gem_writel(macb, USRIO, (MACB_BIT(RMII) | + MACB_BIT(CLKEN))); #else - macb_writel(macb, USRIO, 0); + macb_or_gem_writel(macb, USRIO, 0); #endif #else #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \ defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \ defined(CONFIG_AT91SAM9XE) - macb_writel(macb, USRIO, MACB_BIT(CLKEN)); + macb_or_gem_writel(macb, USRIO, MACB_BIT(CLKEN)); #else - macb_writel(macb, USRIO, MACB_BIT(MII)); + macb_or_gem_writel(macb, USRIO, MACB_BIT(MII)); #endif #endif /* CONFIG_RMII */
@@ -524,9 +526,9 @@ static int macb_write_hwaddr(struct eth_device *dev) /* set hardware address */ hwaddr_bottom = dev->enetaddr[0] | dev->enetaddr[1] << 8 | dev->enetaddr[2] << 16 | dev->enetaddr[3] << 24; - macb_writel(macb, SA1B, hwaddr_bottom); + macb_or_gem_writel(macb, SA1B, hwaddr_bottom); hwaddr_top = dev->enetaddr[4] | dev->enetaddr[5] << 8; - macb_writel(macb, SA1T, hwaddr_top); + macb_or_gem_writel(macb, SA1T, hwaddr_top); return 0; }
@@ -581,6 +583,10 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
macb_writel(macb, NCFGR, ncfgr);
+ /* Cadence GEM has a module ID of 2. */ + if (MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2) + macb->is_gem = 1; + eth_register(netdev);
#if defined(CONFIG_CMD_MII) diff --git a/drivers/net/macb.h b/drivers/net/macb.h index f92a20c..a2913f2 100644 --- a/drivers/net/macb.h +++ b/drivers/net/macb.h @@ -71,6 +71,15 @@ #define MACB_TPQ 0x00bc #define MACB_USRIO 0x00c0 #define MACB_WOL 0x00c4 +#define MACB_MID 0x00fc + +/* GEM register offsets. */ +#define GEM_NCFGR 0x0004 +#define GEM_USRIO 0x000c +#define GEM_HRB 0x0080 +#define GEM_HRT 0x0084 +#define GEM_SA1B 0x0088 +#define GEM_SA1T 0x008C
/* Bitfields in NCR */ #define MACB_LB_OFFSET 0 @@ -240,6 +249,12 @@ #define MACB_WOL_MTI_OFFSET 19 #define MACB_WOL_MTI_SIZE 1
+/* Bitfields in MID */ +#define MACB_IDNUM_OFFSET 16 +#define MACB_IDNUM_SIZE 16 +#define MACB_REV_OFFSET 0 +#define MACB_REV_SIZE 16 + /* Constants for CLK */ #define MACB_CLK_DIV8 0 #define MACB_CLK_DIV16 1 @@ -266,10 +281,50 @@ << MACB_##name##_OFFSET)) \ | MACB_BF(name,value))
+#define GEM_BIT(name) \ + (1 << GEM_##name##_OFFSET) +#define GEM_BF(name, value) \ + (((value) & ((1 << GEM_##name##_SIZE) - 1)) \ + << GEM_##name##_OFFSET) +#define GEM_BFEXT(name, value)\ + (((value) >> GEM_##name##_OFFSET) \ + & ((1 << GEM_##name##_SIZE) - 1)) +#define GEM_BFINS(name, value, old) \ + (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \ + << GEM_##name##_OFFSET)) \ + | GEM_BF(name, value)) + /* Register access macros */ #define macb_readl(port,reg) \ readl((port)->regs + MACB_##reg) #define macb_writel(port,reg,value) \ writel((value), (port)->regs + MACB_##reg) +#define gem_readl(port, reg) \ + __raw_readl((port)->regs + GEM_##reg) +#define gem_writel(port, reg, value) \ + __raw_writel((value), (port)->regs + GEM_##reg) + +/* + * Conditional GEM/MACB macros. These perform the operation to the correct + * register dependent on whether the device is a GEM or a MACB. For registers + * and bitfields that are common across both devices, use macb_{read,write}l + * to avoid the cost of the conditional. + */ +#define macb_or_gem_writel(__macb, __reg, __value) \ + ({ \ + if ((__macb)->is_gem) \ + gem_writel((__macb), __reg, __value); \ + else \ + macb_writel((__macb), __reg, __value); \ + })
+#define macb_or_gem_readl(__macb, __reg) \ + ({ \ + u32 __v; \ + if ((__macb)->is_gem) \ + __v = gem_readl((__macb), __reg); \ + else \ + __v = macb_readl((__macb), __reg); \ + __v; \ + }) #endif /* __DRIVERS_MACB_H__ */
GEM devices support larger clock divisors and have a different range of divisors. Program the MDIO clock divisors based on the device type.
Signed-off-by: Dave Aldridge fovsoft@gmail.com --- drivers/net/macb.c | 63 ++++++++++++++++++++++++++++++++++++++-------------- drivers/net/macb.h | 12 ++++++++++ 2 files changed, 58 insertions(+), 17 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 89491c8..07d1ba8 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -532,11 +532,52 @@ static int macb_write_hwaddr(struct eth_device *dev) return 0; }
+static u32 gem_mdc_clk_div(int id) +{ + u32 ncfgr; + unsigned long pclk_hz = get_macb_pclk_rate(id); + + if (pclk_hz <= 20000000) + ncfgr = GEM_BF(CLK, GEM_CLK_DIV8); + else if (pclk_hz <= 40000000) + ncfgr = GEM_BF(CLK, GEM_CLK_DIV16); + else if (pclk_hz <= 80000000) + ncfgr = GEM_BF(CLK, GEM_CLK_DIV32); + else if (pclk_hz <= 120000000) + ncfgr = GEM_BF(CLK, GEM_CLK_DIV48); + else if (pclk_hz <= 160000000) + ncfgr = GEM_BF(CLK, GEM_CLK_DIV64); + else + ncfgr = GEM_BF(CLK, GEM_CLK_DIV96); + + return ncfgr; +} + +static u32 macb_mdc_clk_div(struct macb_device *macb, int id) +{ + u32 ncfgr; + unsigned long pclk_hz; + + if (macb->is_gem) + return gem_mdc_clk_div(id); + + pclk_hz = get_macb_pclk_rate(id); + if (pclk_hz <= 20000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); + else if (pclk_hz <= 40000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); + else if (pclk_hz <= 80000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); + else + ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); + + return ncfgr; +} + int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) { struct macb_device *macb; struct eth_device *netdev; - unsigned long macb_hz; u32 ncfgr;
macb = malloc(sizeof(struct macb_device)); @@ -567,26 +608,14 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) netdev->recv = macb_recv; netdev->write_hwaddr = macb_write_hwaddr;
- /* - * Do some basic initialization so that we at least can talk - * to the PHY - */ - macb_hz = get_macb_pclk_rate(id); - if (macb_hz < 20000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); - else if (macb_hz < 40000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); - else if (macb_hz < 80000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); - else - ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); - - macb_writel(macb, NCFGR, ncfgr); - /* Cadence GEM has a module ID of 2. */ if (MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2) macb->is_gem = 1;
+ /* Set MII management clock divider */ + ncfgr = macb_mdc_clk_div(macb, id); + macb_writel(macb, NCFGR, ncfgr); + eth_register(netdev);
#if defined(CONFIG_CMD_MII) diff --git a/drivers/net/macb.h b/drivers/net/macb.h index a2913f2..b08a057 100644 --- a/drivers/net/macb.h +++ b/drivers/net/macb.h @@ -147,6 +147,10 @@ #define MACB_IRXFCS_OFFSET 19 #define MACB_IRXFCS_SIZE 1
+/* GEM specific NCFGR bitfields. */ +#define GEM_CLK_OFFSET 18 +#define GEM_CLK_SIZE 3 + /* Bitfields in NSR */ #define MACB_NSR_LINK_OFFSET 0 #define MACB_NSR_LINK_SIZE 1 @@ -261,6 +265,14 @@ #define MACB_CLK_DIV32 2 #define MACB_CLK_DIV64 3
+/* GEM specific constants for CLK. */ +#define GEM_CLK_DIV8 0 +#define GEM_CLK_DIV16 1 +#define GEM_CLK_DIV32 2 +#define GEM_CLK_DIV48 3 +#define GEM_CLK_DIV64 4 +#define GEM_CLK_DIV96 5 + /* Constants for MAN register */ #define MACB_MAN_SOF 1 #define MACB_MAN_WRITE 1
Dear Dave Aldridge,
In message 1318251753-23604-2-git-send-email-fovsoft@gmail.com you wrote:
GEM devices support larger clock divisors and have a different range of divisors. Program the MDIO clock divisors based on the device type.
Signed-off-by: Dave Aldridge fovsoft@gmail.com
drivers/net/macb.c | 63 ++++++++++++++++++++++++++++++++++++++-------------- drivers/net/macb.h | 12 ++++++++++ 2 files changed, 58 insertions(+), 17 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
Dear Dave Aldridge,
In message 1318251753-23604-2-git-send-email-fovsoft@gmail.com you wrote:
GEM devices support larger clock divisors and have a different range of divisors. Program the MDIO clock divisors based on the device type.
Signed-off-by: Dave Aldridge fovsoft@gmail.com
drivers/net/macb.c | 63 ++++++++++++++++++++++++++++++++++++++-------------- drivers/net/macb.h | 12 ++++++++++ 2 files changed, 58 insertions(+), 17 deletions(-)
No, not applied - doesn't apply:
Description: [U-Boot,2/4] macb: support higher rate GEM MDIO clock divisors Applying: macb: support higher rate GEM MDIO clock divisors fatal: sha1 information is lacking or useless (drivers/net/macb.c). Repository lacks necessary blobs to fall back on 3-way merge. Cannot fall back to three-way merge. Patch failed at 0001 macb: support higher rate GEM MDIO clock divisors
Please fix / rebase and resubmit.
Best regards,
Wolfgang Denk
Some GEM implementations may support DMA bus widths up to 128 bits. We can get the maximum supported DMA bus width from the design configuration register so use that to program the device up.
Signed-off-by: Dave Aldridge fovsoft@gmail.com --- drivers/net/macb.c | 25 +++++++++++++++++++++++++ drivers/net/macb.h | 18 ++++++++++++++++++ 2 files changed, 43 insertions(+), 0 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 07d1ba8..36f0a0f 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -574,6 +574,27 @@ static u32 macb_mdc_clk_div(struct macb_device *macb, int id) return ncfgr; }
+/* + * Get the DMA bus width field of the network configuration register that we + * should program. We find the width from decoding the design configuration + * register to find the maximum supported data bus width. + */ +static u32 macb_dbw(struct macb_device *macb) +{ + if (!macb->is_gem) + return 0; + + switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) { + case 4: + return GEM_BF(DBW, GEM_DBW128); + case 2: + return GEM_BF(DBW, GEM_DBW64); + case 1: + default: + return GEM_BF(DBW, GEM_DBW32); + } +} + int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) { struct macb_device *macb; @@ -614,6 +635,10 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
/* Set MII management clock divider */ ncfgr = macb_mdc_clk_div(macb, id); + + /* Set up the DMA bus width */ + ncfgr |= macb_dbw(macb); + macb_writel(macb, NCFGR, ncfgr);
eth_register(netdev); diff --git a/drivers/net/macb.h b/drivers/net/macb.h index b08a057..c0759cf 100644 --- a/drivers/net/macb.h +++ b/drivers/net/macb.h @@ -80,6 +80,13 @@ #define GEM_HRT 0x0084 #define GEM_SA1B 0x0088 #define GEM_SA1T 0x008C +#define GEM_DCFG1 0x0280 +#define GEM_DCFG2 0x0284 +#define GEM_DCFG3 0x0288 +#define GEM_DCFG4 0x028c +#define GEM_DCFG5 0x0290 +#define GEM_DCFG6 0x0294 +#define GEM_DCFG7 0x0298
/* Bitfields in NCR */ #define MACB_LB_OFFSET 0 @@ -150,6 +157,13 @@ /* GEM specific NCFGR bitfields. */ #define GEM_CLK_OFFSET 18 #define GEM_CLK_SIZE 3 +#define GEM_DBW_OFFSET 21 +#define GEM_DBW_SIZE 2 + +/* Constants for data bus width. */ +#define GEM_DBW32 0 +#define GEM_DBW64 1 +#define GEM_DBW128 2
/* Bitfields in NSR */ #define MACB_NSR_LINK_OFFSET 0 @@ -259,6 +273,10 @@ #define MACB_REV_OFFSET 0 #define MACB_REV_SIZE 16
+/* Bitfields in DCFG1. */ +#define GEM_DBWDEF_OFFSET 25 +#define GEM_DBWDEF_SIZE 3 + /* Constants for CLK */ #define MACB_CLK_DIV8 0 #define MACB_CLK_DIV16 1
GEM has configurable receive buffer sizes so requires this to be programmed up.
Signed-off-by: Dave Aldridge fovsoft@gmail.com --- drivers/net/macb.c | 19 +++++++++++++++++++ drivers/net/macb.h | 5 +++++ 2 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 36f0a0f..de52c09 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -436,6 +436,23 @@ static int macb_phy_init(struct macb_device *macb) } }
+/* + * Configure the receive DMA engine to use the correct receive buffer size. + * This is a configurable parameter for GEM. + */ +static void macb_configure_dma(struct macb_device *macb) +{ + u32 dmacfg; + u32 rx_ring_buf_size = CONFIG_SYS_MACB_RX_BUFFER_SIZE / + CONFIG_SYS_MACB_RX_RING_SIZE; + + if (macb->is_gem) { + dmacfg = gem_readl(macb, DMACFG) & ~GEM_BF(RXBS, -1L); + dmacfg |= GEM_BF(RXBS, rx_ring_buf_size / 64); + gem_writel(macb, DMACFG, dmacfg); + } +} + static int macb_init(struct eth_device *netdev, bd_t *bd) { struct macb_device *macb = to_macb(netdev); @@ -465,6 +482,8 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) } macb->rx_tail = macb->tx_head = macb->tx_tail = 0;
+ macb_configure_dma(macb); + macb_writel(macb, RBQP, macb->rx_ring_dma); macb_writel(macb, TBQP, macb->tx_ring_dma);
diff --git a/drivers/net/macb.h b/drivers/net/macb.h index c0759cf..e0fbd46 100644 --- a/drivers/net/macb.h +++ b/drivers/net/macb.h @@ -76,6 +76,7 @@ /* GEM register offsets. */ #define GEM_NCFGR 0x0004 #define GEM_USRIO 0x000c +#define GEM_DMACFG 0x0010 #define GEM_HRB 0x0080 #define GEM_HRT 0x0084 #define GEM_SA1B 0x0088 @@ -165,6 +166,10 @@ #define GEM_DBW64 1 #define GEM_DBW128 2
+/* Bitfields in DMACFG. */ +#define GEM_RXBS_OFFSET 16 +#define GEM_RXBS_SIZE 8 + /* Bitfields in NSR */ #define MACB_NSR_LINK_OFFSET 0 #define MACB_NSR_LINK_SIZE 1
Dear Dave Aldridge,
In message 1318251753-23604-1-git-send-email-fovsoft@gmail.com you wrote:
The Cadence GEM is based on the MACB Ethernet controller but has a few small changes with regards to register and bitfield placement. This patch detects the presence of a GEM by reading the module ID register and setting a flag appropriately.
This handles the new HW address, USRIO and hash register base register locations in GEM.
Signed-off-by: Dave Aldridge fovsoft@gmail.com
...
--- a/drivers/net/macb.h +++ b/drivers/net/macb.h @@ -71,6 +71,15 @@ #define MACB_TPQ 0x00bc #define MACB_USRIO 0x00c0 #define MACB_WOL 0x00c4 +#define MACB_MID 0x00fc
+/* GEM register offsets. */ +#define GEM_NCFGR 0x0004 +#define GEM_USRIO 0x000c +#define GEM_HRB 0x0080 +#define GEM_HRT 0x0084 +#define GEM_SA1B 0x0088 +#define GEM_SA1T 0x008C
NAK.
/* Register access macros */ #define macb_readl(port,reg) \ readl((port)->regs + MACB_##reg) #define macb_writel(port,reg,value) \ writel((value), (port)->regs + MACB_##reg) +#define gem_readl(port, reg) \
- __raw_readl((port)->regs + GEM_##reg)
+#define gem_writel(port, reg, value) \
- __raw_writel((value), (port)->regs + GEM_##reg)
NAK. We don't allow regoister accesses through base address + offset notation any more.
Please use a C struct instead.
Best regards,
Wolfgang Denk
participants (2)
-
Dave Aldridge -
Wolfgang Denk