[U-Boot] [PATCH] vf610twr: Tune DDR initialization settings
Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual.
Changed register settings to comply with JEDEC required values.
Changed timing parameters because they included full clock periods that were doing nothing.
Signed-off-by: Anthony Felice tony.felice@timesys.com --- arch/arm/include/asm/arch-vf610/imx-regs.h | 50 +++++++++++--- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 44 +++++++------ arch/arm/include/asm/imx-common/iomux-v3.h | 2 + board/freescale/vf610twr/vf610twr.c | 93 +++++++++++++++++---------- 4 files changed, 128 insertions(+), 61 deletions(-)
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index c2f9761..a11b419 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -100,9 +100,11 @@ /* DDRMC */ #define DDRMC_PHY_DQ_TIMING 0x00002613 #define DDRMC_PHY_DQS_TIMING 0x00002615 -#define DDRMC_PHY_CTRL 0x01210080 +#define DDRMC_PHY_CTRL 0x00210000 #define DDRMC_PHY_MASTER_CTRL 0x0001012a -#define DDRMC_PHY_SLAVE_CTRL 0x00012020 +#define DDRMC_PHY_SLAVE_CTRL 0x00002000 +#define DDRMC_PHY_OFF 0x00000000 +#define DDRMC_PHY_PROC_PAD_ODT 0x00010101
#define DDRMC_PHY50_DDR3_MODE (1 << 12) #define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8) @@ -135,7 +137,7 @@ #define DDRMC_CR21_CCMAP_EN 1 #define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16) #define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24) -#define DDRMC_CR23_TDLL(v) ((v) & 0xff) +#define DDRMC_CR23_TDLL(v) ((v) & 0xffff) #define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f) #define DDRMC_CR25_TREF_EN (1 << 16) #define DDRMC_CR26_TREF(v) (((v) & 0xffff) << 16) @@ -148,7 +150,7 @@ #define DDRMC_CR33_EN_QK_SREF (1 << 16) #define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16) #define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8) -#define DDRMC_CR38_FREQ_CHG_EN (1 << 8) +#define DDRMC_CR38_FREQ_CHG_EN(v) (((v) & 0x1) << 8) #define DDRMC_CR39_PHY_INI_COM(v) (((v) & 0xffff) << 16) #define DDRMC_CR39_PHY_INI_STA(v) (((v) & 0xff) << 8) #define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) & 0x3) @@ -160,7 +162,7 @@ #define DDRMC_CR67_ZQCS(v) ((v) & 0xfff) #define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8) #define DDRMC_CR70_REF_PER_ZQ(v) (v) -#define DDRMC_CR72_ZQCS_ROTATE (1 << 24) +#define DDRMC_CR72_ZQCS_ROTATE(v) (((v) & 0x1) << 24) #define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24) #define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << 16) #define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << 8) @@ -179,9 +181,10 @@ #define DDRMC_CR77_CS_MAP (1 << 24) #define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8) #define DDRMC_CR77_SWAP_EN 1 +#define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24) #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf) -#define DDRMC_CR79_CTLUPD_AREF (1 << 24) -#define DDRMC_CR82_INT_MASK 0x1fffffff +#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24) +#define DDRMC_CR82_INT_MASK 0x10000000 #define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24) #define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16) #define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16) @@ -189,9 +192,17 @@ #define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16) #define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8) #define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f) +#define DDRMC_CR97_WRLVL_EN (1 << 24) +#define DDRMC_CR98_WRLVL_DL_0 (0) +#define DDRMC_CR99_WRLVL_DL_1 (0) +#define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16) +#define DDRMC_CR102_RDLVL_REG_EN (1 << 8) #define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8) +#define DDRMC_CR106_RDLVL_GTDL_0(v) ((v) & 0xff) #define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff) +#define DDRMC_CR110_RDLVL_GTDL_1(v) (((v) & 0xff) << 16) #define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8) +#define DDRMC_CR115_RDLVL_GTDL_2(v) ((v) & 0xff) #define DDRMC_CR117_AXI0_W_PRI(v) (((v) & 0x3) << 8) #define DDRMC_CR117_AXI0_R_PRI(v) ((v) & 0x3) #define DDRMC_CR118_AXI1_W_PRI(v) (((v) & 0x3) << 24) @@ -205,19 +216,42 @@ #define DDRMC_CR122_AXI0_PRIRLX(v) ((v) & 0x3ff) #define DDRMC_CR123_AXI1_PRI3_RPRI(v) (((v) & 0xf) << 8) #define DDRMC_CR123_AXI1_PRI2_RPRI(v) ((v) & 0xf) +#define DDRMC_CR123_AXI1_P_ODR_EN (1 << 16) #define DDRMC_CR124_AXI1_PRIRLX(v) ((v) & 0x3ff) #define DDRMC_CR126_PHY_RDLAT(v) (((v) & 0x3f) << 8) #define DDRMC_CR132_WRLAT_ADJ(v) (((v) & 0x1f) << 8) #define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f) +#define DDRMC_CR137_PHYCTL_DL(v) (((v) & 0xf) << 16) +#define DDRMC_CR138_PHY_WRLV_MXDL(v) (((v) & 0xffff) << 16) +#define DDRMC_CR138_PHYDRAM_CK_EN(v) (((v) & 0x8) << 8) #define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24) #define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16) #define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8) #define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff) +#define DDRMC_CR140_PHY_WRLV_WW(v) ((v) & 0x3ff) +#define DDRMC_CR143_RDLV_GAT_MXDL(v) (((v) & 0xffff) << 16) +#define DDRMC_CR143_RDLV_MXDL(v) ((v) & 0xffff) +#define DDRMC_CR144_PHY_RDLVL_RES(v) (((v) & 0xff) << 24) +#define DDRMC_CR144_PHY_RDLV_LOAD(v) (((v) & 0xff) << 16) +#define DDRMC_CR144_PHY_RDLV_DLL(v) (((v) & 0xff) << 8) +#define DDRMC_CR144_PHY_RDLV_EN(v) ((v) & 0xff) +#define DDRMC_CR145_PHY_RDLV_RR(v) ((v) & 0x3ff) +#define DDRMC_CR146_PHY_RDLVL_RESP(v) (v) +#define DDRMC_CR147_RDLV_RESP_MASK(v) ((v) & 0xfffff) +#define DDRMC_CR148_RDLV_GATE_RESP_MASK(v) ((v) & 0xfffff) +#define DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(v) (((v) & 0xf) << 8) +#define DDRMC_CR151_RDLVL_DQ_ZERO_CNT(v) ((v) & 0xf) #define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27) #define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21) +#define DDRMC_CR154_DDR_SEL_PAD_CONTR(v) (((v) & 0x3) << 18) +#define DDRMC_CR154_PAD_ZQ_HW_FOR(v) (((v) & 0x1) << 14) #define DDRMC_CR155_AXI0_AWCACHE (1 << 10) -#define DDRMC_CR155_PAD_ODT_BYTE1(v) ((v) & 0x7) +#define DDRMC_CR155_PAD_ODT_BYTE1(v) (((v) & 0x7) << 3) +#define DDRMC_CR155_PAD_ODT_BYTE0(v) ((v) & 0x7) #define DDRMC_CR158_TWR(v) ((v) & 0x3f) +#define DDRMC_CR161_ODT_EN(v) (((v) & 0x1) << 16) +#define DDRMC_CR161_TODTH_RD(v) (((v) & 0xf) << 8) +#define DDRMC_CR161_TODTH_WR(v) ((v) & 0xf)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index 88807d8..20b0dc4 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -17,6 +17,8 @@ #define VF610_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ PAD_CTL_OBE_IBE_ENABLE) #define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm +#define VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_25ohm | \ + PAD_CTL_INPUT_DIFFERENTIAL) #define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
@@ -53,6 +55,7 @@ enum { VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL), VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL), + VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL), @@ -68,6 +71,7 @@ enum { VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, 0x025c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL), @@ -75,26 +79,26 @@ enum { VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index dec11a1..bad4537 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -115,6 +115,8 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_MUX_MODE_SHIFT 20
+#define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16) + #define PAD_CTL_SPEED_MED (1 << 12) #define PAD_CTL_SPEED_HIGH (3 << 12)
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c index 4ee74c0..11670cf 100644 --- a/board/freescale/vf610twr/vf610twr.c +++ b/board/freescale/vf610twr/vf610twr.c @@ -45,6 +45,7 @@ void setup_iomux_ddr(void) VF610_PAD_DDR_A3__DDR_A_3, VF610_PAD_DDR_A2__DDR_A_2, VF610_PAD_DDR_A1__DDR_A_1, + VF610_PAD_DDR_A0__DDR_A_0, VF610_PAD_DDR_BA2__DDR_BA_2, VF610_PAD_DDR_BA1__DDR_BA_1, VF610_PAD_DDR_BA0__DDR_BA_0, @@ -76,6 +77,7 @@ void setup_iomux_ddr(void) VF610_PAD_DDR_WE__DDR_WE_B, VF610_PAD_DDR_ODT1__DDR_ODT_0, VF610_PAD_DDR_ODT0__DDR_ODT_1, + VF610_PAD_DDR_RESETB, };
imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads)); @@ -88,30 +90,30 @@ void ddr_phy_init(void) writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]); writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]); writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]); - writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]);
writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]); writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]); - writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]); - writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]);
writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]); writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]); writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]); - writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]);
writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]); writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]); writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]); - writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]);
writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]); writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]); writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]); - writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]); + + /* LPDDR2 only parameter */ + writel(DDRMC_PHY_OFF, &ddrmr->phy[49]);
writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, &ddrmr->phy[50]); + + /* Processor Pad ODT settings */ + writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]); }
void ddr_ctrl_init(void) @@ -120,12 +122,12 @@ void ddr_ctrl_init(void)
writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]); writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]); - writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]); + writel(DDRMC_CR10_TRST_PWRON(80000), &ddrmr->cr[10]);
- writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]); + writel(DDRMC_CR11_CKE_INACTIVE(200000), &ddrmr->cr[11]); writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]); - writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) | - DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]); + writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4), + &ddrmr->cr[13]); writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) | DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]); writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]); @@ -134,24 +136,23 @@ void ddr_ctrl_init(void) writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]);
writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]); - writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT | - DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]); + writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
- writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]); + writel(DDRMC_CR22_TDAL(12), &ddrmr->cr[22]); writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]); writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]);
writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]); - writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]); - writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]); + writel(DDRMC_CR26_TREF(3120) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]); + writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]); writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]);
writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]); - writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]); + writel(DDRMC_CR31_TXSNR(48) | DDRMC_CR31_TXSR(468), &ddrmr->cr[31]); writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]); writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]);
- writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]); + writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]); writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) | DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
@@ -164,37 +165,45 @@ void ddr_ctrl_init(void) writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]); - writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]); + writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]);
writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) | DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]); writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN | - DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255), + DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64), &ddrmr->cr[74]); writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN | DDRMC_CR75_PLEN, &ddrmr->cr[75]); writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) | - DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]); + DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]); writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE | DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]); - writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]); - writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]); + writel(DDRMC_CR78_Q_FULLNESS(7) | DDRMC_CR78_BUR_ON_FLY_BIT(12), + &ddrmr->cr[78]); + writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
- writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0, - &ddrmr->cr[87]); + writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]); writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]); writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]); writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]); + writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]); + writel(DDRMC_CR98_WRLVL_DL_0, &ddrmr->cr[98]); + writel(DDRMC_CR99_WRLVL_DL_1, &ddrmr->cr[99]); + + writel(DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, + &ddrmr->cr[102]);
- writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]); - writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]); - writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]); + writel(DDRMC_CR105_RDLVL_DL_0(0), &ddrmr->cr[105]); + writel(DDRMC_CR106_RDLVL_GTDL_0(4), &ddrmr->cr[106]); + writel(DDRMC_CR110_RDLVL_GTDL_1(4), &ddrmr->cr[110]); + writel(DDRMC_CR114_RDLVL_GTDL_2(0), &ddrmr->cr[114]); + writel(DDRMC_CR115_RDLVL_GTDL_2(0), &ddrmr->cr[115]);
- writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), + writel(DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), &ddrmr->cr[117]); writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), &ddrmr->cr[118]); @@ -205,22 +214,40 @@ void ddr_ctrl_init(void) &ddrmr->cr[121]); writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]); - writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1), - &ddrmr->cr[123]); + writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) | + DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]); writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
- writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]); + writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]); writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), &ddrmr->cr[132]); + writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]); + writel(DDRMC_CR138_PHY_WRLV_MXDL(256) | DDRMC_CR138_PHYDRAM_CK_EN(1), + &ddrmr->cr[138]); writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3), &ddrmr->cr[139]); + writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]); + writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) | DDRMC_CR143_RDLV_MXDL(128), + &ddrmr->cr[143]); + writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) | + DDRMC_CR144_PHY_RDLV_DLL(3) | DDRMC_CR144_PHY_RDLV_EN(3), + &ddrmr->cr[144]); + writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]); + writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]); + writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]); + writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]); + writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) | + DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]);
writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | - DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]); - writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2), + DDRMC_CR154_PAD_ZQ_MODE(1) | DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | + DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]); + writel(DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), &ddrmr->cr[155]); writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]); + writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) | + DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]);
ddr_phy_init();
Hi Anthony,
On Wed, 14 May 2014 17:29:48 -0400, Anthony Felice tony.felice@timesys.com wrote:
Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual.
Changed register settings to comply with JEDEC required values.
Is this just a compliance fix, or a bug fix?
Changed timing parameters because they included full clock periods that were doing nothing.
Signed-off-by: Anthony Felice tony.felice@timesys.com
Amicalement,
Hi Albert,
On Mon, 9 Jun 2014 10:11:28 +0200, Albert ARIBAUD albert.u.boot@aribaud.net wrote:
Hi Anthony,
On Wed, 14 May 2014 17:29:48 -0400, Anthony Felice tony.felice@timesys.com wrote:
Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual.
Changed register settings to comply with JEDEC required values.
Is this just a compliance fix, or a bug fix?
Ping.
Amicalement,
Am 2014-05-14 23:29, schrieb Anthony Felice:
Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual.
Changed register settings to comply with JEDEC required values.
Changed timing parameters because they included full clock periods that were doing nothing.
Signed-off-by: Anthony Felice tony.felice@timesys.com
arch/arm/include/asm/arch-vf610/imx-regs.h | 50 +++++++++++--- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 44 +++++++------ arch/arm/include/asm/imx-common/iomux-v3.h | 2 + board/freescale/vf610twr/vf610twr.c | 93 +++++++++++++++++---------- 4 files changed, 128 insertions(+), 61 deletions(-)
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index c2f9761..a11b419 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -100,9 +100,11 @@ /* DDRMC */ #define DDRMC_PHY_DQ_TIMING 0x00002613 #define DDRMC_PHY_DQS_TIMING 0x00002615 -#define DDRMC_PHY_CTRL 0x01210080 +#define DDRMC_PHY_CTRL 0x00210000 #define DDRMC_PHY_MASTER_CTRL 0x0001012a -#define DDRMC_PHY_SLAVE_CTRL 0x00012020 +#define DDRMC_PHY_SLAVE_CTRL 0x00002000 +#define DDRMC_PHY_OFF 0x00000000 +#define DDRMC_PHY_PROC_PAD_ODT 0x00010101
#define DDRMC_PHY50_DDR3_MODE (1 << 12) #define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8) @@ -135,7 +137,7 @@ #define DDRMC_CR21_CCMAP_EN 1 #define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16) #define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24) -#define DDRMC_CR23_TDLL(v) ((v) & 0xff) +#define DDRMC_CR23_TDLL(v) ((v) & 0xffff) #define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f) #define DDRMC_CR25_TREF_EN (1 << 16) #define DDRMC_CR26_TREF(v) (((v) & 0xffff) << 16) @@ -148,7 +150,7 @@ #define DDRMC_CR33_EN_QK_SREF (1 << 16) #define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16) #define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8) -#define DDRMC_CR38_FREQ_CHG_EN (1 << 8) +#define DDRMC_CR38_FREQ_CHG_EN(v) (((v) & 0x1) << 8) #define DDRMC_CR39_PHY_INI_COM(v) (((v) & 0xffff) << 16) #define DDRMC_CR39_PHY_INI_STA(v) (((v) & 0xff) << 8) #define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) & 0x3) @@ -160,7 +162,7 @@ #define DDRMC_CR67_ZQCS(v) ((v) & 0xfff) #define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8) #define DDRMC_CR70_REF_PER_ZQ(v) (v) -#define DDRMC_CR72_ZQCS_ROTATE (1 << 24) +#define DDRMC_CR72_ZQCS_ROTATE(v) (((v) & 0x1) << 24) #define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24) #define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << 16) #define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << 8) @@ -179,9 +181,10 @@ #define DDRMC_CR77_CS_MAP (1 << 24) #define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8) #define DDRMC_CR77_SWAP_EN 1 +#define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24) #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf) -#define DDRMC_CR79_CTLUPD_AREF (1 << 24) -#define DDRMC_CR82_INT_MASK 0x1fffffff +#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24) +#define DDRMC_CR82_INT_MASK 0x10000000 #define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24) #define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16) #define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16) @@ -189,9 +192,17 @@ #define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16) #define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8) #define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f) +#define DDRMC_CR97_WRLVL_EN (1 << 24) +#define DDRMC_CR98_WRLVL_DL_0 (0) +#define DDRMC_CR99_WRLVL_DL_1 (0) +#define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16) +#define DDRMC_CR102_RDLVL_REG_EN (1 << 8) #define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8) +#define DDRMC_CR106_RDLVL_GTDL_0(v) ((v) & 0xff) #define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff) +#define DDRMC_CR110_RDLVL_GTDL_1(v) (((v) & 0xff) << 16) #define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8) +#define DDRMC_CR115_RDLVL_GTDL_2(v) ((v) & 0xff) #define DDRMC_CR117_AXI0_W_PRI(v) (((v) & 0x3) << 8) #define DDRMC_CR117_AXI0_R_PRI(v) ((v) & 0x3) #define DDRMC_CR118_AXI1_W_PRI(v) (((v) & 0x3) << 24) @@ -205,19 +216,42 @@ #define DDRMC_CR122_AXI0_PRIRLX(v) ((v) & 0x3ff) #define DDRMC_CR123_AXI1_PRI3_RPRI(v) (((v) & 0xf) << 8) #define DDRMC_CR123_AXI1_PRI2_RPRI(v) ((v) & 0xf) +#define DDRMC_CR123_AXI1_P_ODR_EN (1 << 16) #define DDRMC_CR124_AXI1_PRIRLX(v) ((v) & 0x3ff) #define DDRMC_CR126_PHY_RDLAT(v) (((v) & 0x3f) << 8) #define DDRMC_CR132_WRLAT_ADJ(v) (((v) & 0x1f) << 8) #define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f) +#define DDRMC_CR137_PHYCTL_DL(v) (((v) & 0xf) << 16) +#define DDRMC_CR138_PHY_WRLV_MXDL(v) (((v) & 0xffff) << 16) +#define DDRMC_CR138_PHYDRAM_CK_EN(v) (((v) & 0x8) << 8) #define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24) #define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16) #define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8) #define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff) +#define DDRMC_CR140_PHY_WRLV_WW(v) ((v) & 0x3ff) +#define DDRMC_CR143_RDLV_GAT_MXDL(v) (((v) & 0xffff) << 16) +#define DDRMC_CR143_RDLV_MXDL(v) ((v) & 0xffff) +#define DDRMC_CR144_PHY_RDLVL_RES(v) (((v) & 0xff) << 24) +#define DDRMC_CR144_PHY_RDLV_LOAD(v) (((v) & 0xff) << 16) +#define DDRMC_CR144_PHY_RDLV_DLL(v) (((v) & 0xff) << 8) +#define DDRMC_CR144_PHY_RDLV_EN(v) ((v) & 0xff) +#define DDRMC_CR145_PHY_RDLV_RR(v) ((v) & 0x3ff) +#define DDRMC_CR146_PHY_RDLVL_RESP(v) (v) +#define DDRMC_CR147_RDLV_RESP_MASK(v) ((v) & 0xfffff) +#define DDRMC_CR148_RDLV_GATE_RESP_MASK(v) ((v) & 0xfffff) +#define DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(v) (((v) & 0xf) << 8) +#define DDRMC_CR151_RDLVL_DQ_ZERO_CNT(v) ((v) & 0xf) #define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27) #define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21) +#define DDRMC_CR154_DDR_SEL_PAD_CONTR(v) (((v) & 0x3) << 18) +#define DDRMC_CR154_PAD_ZQ_HW_FOR(v) (((v) & 0x1) << 14) #define DDRMC_CR155_AXI0_AWCACHE (1 << 10) -#define DDRMC_CR155_PAD_ODT_BYTE1(v) ((v) & 0x7) +#define DDRMC_CR155_PAD_ODT_BYTE1(v) (((v) & 0x7) << 3) +#define DDRMC_CR155_PAD_ODT_BYTE0(v) ((v) & 0x7) #define DDRMC_CR158_TWR(v) ((v) & 0x3f) +#define DDRMC_CR161_ODT_EN(v) (((v) & 0x1) << 16) +#define DDRMC_CR161_TODTH_RD(v) (((v) & 0xf) << 8) +#define DDRMC_CR161_TODTH_WR(v) ((v) & 0xf)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index 88807d8..20b0dc4 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -17,6 +17,8 @@ #define VF610_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ PAD_CTL_OBE_IBE_ENABLE) #define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm +#define VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_25ohm | \
PAD_CTL_INPUT_DIFFERENTIAL)#define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
@@ -53,6 +55,7 @@ enum { VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL), VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL),
- VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0,
VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL), @@ -68,6 +71,7 @@ enum { VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, 0x025c, 0, __NA_, 0,
VF610_DDR_PAD_CTRL), VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL), @@ -75,26 +79,26 @@ enum { VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_,
0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_,
0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_,
0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_,
0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_,
0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_,
0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0,
VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0,
VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0,
VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0,
VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0,
VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0,
VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0,
VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0,
VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0,
VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0,
VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_,
0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_,
0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_,
0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_,
0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_,
0, VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_,
0, VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_,
0, VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_,
0, VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_,
0, VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_,
0, VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0,
VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0,
VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0,
VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0,
VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0,
VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0,
VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0,
VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0,
VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0,
VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0,
VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_,
0, VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_,
0, VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_,
0, VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_,
0, VF610_DDR_PAD_CTRL_1), VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index dec11a1..bad4537 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -115,6 +115,8 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_MUX_MODE_SHIFT 20
+#define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16)
#define PAD_CTL_SPEED_MED (1 << 12) #define PAD_CTL_SPEED_HIGH (3 << 12)
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c index 4ee74c0..11670cf 100644 --- a/board/freescale/vf610twr/vf610twr.c +++ b/board/freescale/vf610twr/vf610twr.c @@ -45,6 +45,7 @@ void setup_iomux_ddr(void) VF610_PAD_DDR_A3__DDR_A_3, VF610_PAD_DDR_A2__DDR_A_2, VF610_PAD_DDR_A1__DDR_A_1,
VF610_PAD_DDR_A0__DDR_A_0,@@ -76,6 +77,7 @@ void setup_iomux_ddr(void) VF610_PAD_DDR_WE__DDR_WE_B, VF610_PAD_DDR_ODT1__DDR_ODT_0, VF610_PAD_DDR_ODT0__DDR_ODT_1,
VF610_PAD_DDR_RESETB,};
imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
@@ -88,30 +90,30 @@ void ddr_phy_init(void) writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]); writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]); writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]);
writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]); writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]);
writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]);
writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]); writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]); writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]);
writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]); writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]); writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]);
writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]); writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]); writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]);
/* LPDDR2 only parameter */
writel(DDRMC_PHY_OFF, &ddrmr->phy[49]);
writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, &ddrmr->phy[50]);
/* Processor Pad ODT settings */
writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]);
}
void ddr_ctrl_init(void) @@ -120,12 +122,12 @@ void ddr_ctrl_init(void)
writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]); writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]);
- writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]);
- writel(DDRMC_CR10_TRST_PWRON(80000), &ddrmr->cr[10]);
- writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]);
- writel(DDRMC_CR11_CKE_INACTIVE(200000), &ddrmr->cr[11]); writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]);
- writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) |
DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]);
- writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4),
&ddrmr->cr[13]);@@ -134,24 +136,23 @@ void ddr_ctrl_init(void) writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]);
writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
- writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT |
DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
- writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
- writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]);
writel(DDRMC_CR22_TDAL(12), &ddrmr->cr[22]); writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]); writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]);
writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
- writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
- writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]);
writel(DDRMC_CR26_TREF(3120) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]); writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]);
writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]);
- writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]);
- writel(DDRMC_CR31_TXSNR(48) | DDRMC_CR31_TXSR(468), &ddrmr->cr[31]); writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]); writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]);
- writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]);
- writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]); writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) | DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
These registers are somewhat confusing, according to the RM they are read-only. However, in a different register (CR124) the RM refers to CR39... However, I tried to remove these registers, which made the system not work anymore, hence they seem to be required...
@@ -164,37 +165,45 @@ void ddr_ctrl_init(void) writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]);
- writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]);
writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]);
writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) | DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]); writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255),
DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64),
DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]);
DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
- writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
- writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]);
writel(DDRMC_CR78_Q_FULLNESS(7) | DDRMC_CR78_BUR_ON_FLY_BIT(12),
&ddrmr->cr[78]);writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
- writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0,
&ddrmr->cr[87]);
- writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]);
Why is this not enabled for read anymore (DDRMC_CR87_ODT_RD_MAPCS0)?
writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]); writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]); writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]);
- writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]);
- writel(DDRMC_CR98_WRLVL_DL_0, &ddrmr->cr[98]);
- writel(DDRMC_CR99_WRLVL_DL_1, &ddrmr->cr[99]);
- writel(DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN,
&ddrmr->cr[102]);
- writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]);
- writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]);
- writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]);
- writel(DDRMC_CR105_RDLVL_DL_0(0), &ddrmr->cr[105]);
- writel(DDRMC_CR106_RDLVL_GTDL_0(4), &ddrmr->cr[106]);
- writel(DDRMC_CR110_RDLVL_GTDL_1(4), &ddrmr->cr[110]);
- writel(DDRMC_CR114_RDLVL_GTDL_2(0), &ddrmr->cr[114]);
- writel(DDRMC_CR115_RDLVL_GTDL_2(0), &ddrmr->cr[115]);
- writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1),
- writel(DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), &ddrmr->cr[117]); writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), &ddrmr->cr[118]);
@@ -205,22 +214,40 @@ void ddr_ctrl_init(void) &ddrmr->cr[121]); writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
- writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1),
&ddrmr->cr[123]);
- writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]);
- writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]);
writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]); writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), &ddrmr->cr[132]);
writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]);
writel(DDRMC_CR138_PHY_WRLV_MXDL(256) | DDRMC_CR138_PHYDRAM_CK_EN(1),
&ddrmr->cr[138]);writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3), &ddrmr->cr[139]);
writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]);
writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) | DDRMC_CR143_RDLV_MXDL(128),
&ddrmr->cr[143]);writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
DDRMC_CR144_PHY_RDLV_DLL(3) | DDRMC_CR144_PHY_RDLV_EN(3),&ddrmr->cr[144]);writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]);
writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]);
writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]);
writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]);
writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]);writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]);- writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2),
DDRMC_CR154_PAD_ZQ_MODE(1) | DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]);
The DDRMC_CR154_PAD_ZQ_HW_FOR enables a pad calibration. According to the data sheet we should wait until the pad calibration is done (see DDR_CR 156[PAD_ZQ_HW_IN_PROG]).
writel(DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), &ddrmr->cr[155]); writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]);ddr_phy_init();
Due to my patch recently which added the DDRMC_CR154_DDR_SEL_PAD_CONTR(3) flag (which essentially enabled DDR3 for newer SoC revisions) this patch currently does not apply cleanly. However, the merge is rather trivial.
I successfully tested that code on our Colibri VF61 and did some performance measurements using memtester (http://pyropus.ca/software/memtester/).
Old settings: real 8m25.427s user 8m19.730s sys 0m0.530s
New settings: real 8m47.152s user 8m40.720s sys 0m0.760s
So memory seems to be slightly slower now, I tried to isolate the change but was not successful so far. I run that test for both settings (old/new) multiple times, the measured time were always in the same range.
All in all there seem to be quite a lot unused/wrong writes before. The cleanup improves the situation a lot and makes the code aligned to the RM.
-- Stefan
Am 2014-07-22 00:42, schrieb Stefan Agner:
Am 2014-05-14 23:29, schrieb Anthony Felice:
Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual.
Changed register settings to comply with JEDEC required values.
Changed timing parameters because they included full clock periods that were doing nothing.
Signed-off-by: Anthony Felice tony.felice@timesys.com
arch/arm/include/asm/arch-vf610/imx-regs.h | 50 +++++++++++--- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 44 +++++++------ arch/arm/include/asm/imx-common/iomux-v3.h | 2 + board/freescale/vf610twr/vf610twr.c | 93 +++++++++++++++++---------- 4 files changed, 128 insertions(+), 61 deletions(-)
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index c2f9761..a11b419 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -100,9 +100,11 @@ /* DDRMC */ #define DDRMC_PHY_DQ_TIMING 0x00002613 #define DDRMC_PHY_DQS_TIMING 0x00002615 -#define DDRMC_PHY_CTRL 0x01210080 +#define DDRMC_PHY_CTRL 0x00210000 #define DDRMC_PHY_MASTER_CTRL 0x0001012a -#define DDRMC_PHY_SLAVE_CTRL 0x00012020 +#define DDRMC_PHY_SLAVE_CTRL 0x00002000 +#define DDRMC_PHY_OFF 0x00000000 +#define DDRMC_PHY_PROC_PAD_ODT 0x00010101
#define DDRMC_PHY50_DDR3_MODE (1 << 12) #define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8) @@ -135,7 +137,7 @@ #define DDRMC_CR21_CCMAP_EN 1 #define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16) #define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24) -#define DDRMC_CR23_TDLL(v) ((v) & 0xff) +#define DDRMC_CR23_TDLL(v) ((v) & 0xffff) #define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f) #define DDRMC_CR25_TREF_EN (1 << 16) #define DDRMC_CR26_TREF(v) (((v) & 0xffff) << 16) @@ -148,7 +150,7 @@ #define DDRMC_CR33_EN_QK_SREF (1 << 16) #define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16) #define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8) -#define DDRMC_CR38_FREQ_CHG_EN (1 << 8) +#define DDRMC_CR38_FREQ_CHG_EN(v) (((v) & 0x1) << 8) #define DDRMC_CR39_PHY_INI_COM(v) (((v) & 0xffff) << 16) #define DDRMC_CR39_PHY_INI_STA(v) (((v) & 0xff) << 8) #define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) & 0x3) @@ -160,7 +162,7 @@ #define DDRMC_CR67_ZQCS(v) ((v) & 0xfff) #define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8) #define DDRMC_CR70_REF_PER_ZQ(v) (v) -#define DDRMC_CR72_ZQCS_ROTATE (1 << 24) +#define DDRMC_CR72_ZQCS_ROTATE(v) (((v) & 0x1) << 24) #define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24) #define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << 16) #define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << 8) @@ -179,9 +181,10 @@ #define DDRMC_CR77_CS_MAP (1 << 24) #define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8) #define DDRMC_CR77_SWAP_EN 1 +#define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24) #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf) -#define DDRMC_CR79_CTLUPD_AREF (1 << 24) -#define DDRMC_CR82_INT_MASK 0x1fffffff +#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24) +#define DDRMC_CR82_INT_MASK 0x10000000 #define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24) #define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16) #define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16) @@ -189,9 +192,17 @@ #define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16) #define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8) #define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f) +#define DDRMC_CR97_WRLVL_EN (1 << 24) +#define DDRMC_CR98_WRLVL_DL_0 (0) +#define DDRMC_CR99_WRLVL_DL_1 (0) +#define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16) +#define DDRMC_CR102_RDLVL_REG_EN (1 << 8) #define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8) +#define DDRMC_CR106_RDLVL_GTDL_0(v) ((v) & 0xff) #define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff) +#define DDRMC_CR110_RDLVL_GTDL_1(v) (((v) & 0xff) << 16) #define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8) +#define DDRMC_CR115_RDLVL_GTDL_2(v) ((v) & 0xff) #define DDRMC_CR117_AXI0_W_PRI(v) (((v) & 0x3) << 8) #define DDRMC_CR117_AXI0_R_PRI(v) ((v) & 0x3) #define DDRMC_CR118_AXI1_W_PRI(v) (((v) & 0x3) << 24) @@ -205,19 +216,42 @@ #define DDRMC_CR122_AXI0_PRIRLX(v) ((v) & 0x3ff) #define DDRMC_CR123_AXI1_PRI3_RPRI(v) (((v) & 0xf) << 8) #define DDRMC_CR123_AXI1_PRI2_RPRI(v) ((v) & 0xf) +#define DDRMC_CR123_AXI1_P_ODR_EN (1 << 16) #define DDRMC_CR124_AXI1_PRIRLX(v) ((v) & 0x3ff) #define DDRMC_CR126_PHY_RDLAT(v) (((v) & 0x3f) << 8) #define DDRMC_CR132_WRLAT_ADJ(v) (((v) & 0x1f) << 8) #define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f) +#define DDRMC_CR137_PHYCTL_DL(v) (((v) & 0xf) << 16) +#define DDRMC_CR138_PHY_WRLV_MXDL(v) (((v) & 0xffff) << 16) +#define DDRMC_CR138_PHYDRAM_CK_EN(v) (((v) & 0x8) << 8) #define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24) #define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16) #define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8) #define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff) +#define DDRMC_CR140_PHY_WRLV_WW(v) ((v) & 0x3ff) +#define DDRMC_CR143_RDLV_GAT_MXDL(v) (((v) & 0xffff) << 16) +#define DDRMC_CR143_RDLV_MXDL(v) ((v) & 0xffff) +#define DDRMC_CR144_PHY_RDLVL_RES(v) (((v) & 0xff) << 24) +#define DDRMC_CR144_PHY_RDLV_LOAD(v) (((v) & 0xff) << 16) +#define DDRMC_CR144_PHY_RDLV_DLL(v) (((v) & 0xff) << 8) +#define DDRMC_CR144_PHY_RDLV_EN(v) ((v) & 0xff) +#define DDRMC_CR145_PHY_RDLV_RR(v) ((v) & 0x3ff) +#define DDRMC_CR146_PHY_RDLVL_RESP(v) (v) +#define DDRMC_CR147_RDLV_RESP_MASK(v) ((v) & 0xfffff) +#define DDRMC_CR148_RDLV_GATE_RESP_MASK(v) ((v) & 0xfffff) +#define DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(v) (((v) & 0xf) << 8) +#define DDRMC_CR151_RDLVL_DQ_ZERO_CNT(v) ((v) & 0xf) #define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27) #define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21) +#define DDRMC_CR154_DDR_SEL_PAD_CONTR(v) (((v) & 0x3) << 18) +#define DDRMC_CR154_PAD_ZQ_HW_FOR(v) (((v) & 0x1) << 14) #define DDRMC_CR155_AXI0_AWCACHE (1 << 10) -#define DDRMC_CR155_PAD_ODT_BYTE1(v) ((v) & 0x7) +#define DDRMC_CR155_PAD_ODT_BYTE1(v) (((v) & 0x7) << 3) +#define DDRMC_CR155_PAD_ODT_BYTE0(v) ((v) & 0x7) #define DDRMC_CR158_TWR(v) ((v) & 0x3f) +#define DDRMC_CR161_ODT_EN(v) (((v) & 0x1) << 16) +#define DDRMC_CR161_TODTH_RD(v) (((v) & 0xf) << 8) +#define DDRMC_CR161_TODTH_WR(v) ((v) & 0xf)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index 88807d8..20b0dc4 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -17,6 +17,8 @@ #define VF610_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ PAD_CTL_OBE_IBE_ENABLE) #define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm +#define VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_25ohm | \
PAD_CTL_INPUT_DIFFERENTIAL)#define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
@@ -53,6 +55,7 @@ enum { VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL), VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL),
- VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0,
VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL), @@ -68,6 +71,7 @@ enum { VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, 0x025c, 0, __NA_, 0,
VF610_DDR_PAD_CTRL), VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL), @@ -75,26 +79,26 @@ enum { VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_,
0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_,
0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_,
0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_,
0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_,
0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_,
0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0,
VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0,
VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0,
VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0,
VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0,
VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0,
VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0,
VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0,
VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0,
VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0,
VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_,
0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_,
0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_,
0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_,
0, VF610_DDR_PAD_CTRL),
- VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_,
0, VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_,
0, VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_,
0, VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_,
0, VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_,
0, VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_,
0, VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0,
VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0,
VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0,
VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0,
VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0,
VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0,
VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0,
VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0,
VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0,
VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0,
VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_,
0, VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_,
0, VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_,
0, VF610_DDR_PAD_CTRL_1),
- VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_,
0, VF610_DDR_PAD_CTRL_1), VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index dec11a1..bad4537 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -115,6 +115,8 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_MUX_MODE_SHIFT 20
+#define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16)
#define PAD_CTL_SPEED_MED (1 << 12) #define PAD_CTL_SPEED_HIGH (3 << 12)
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c index 4ee74c0..11670cf 100644 --- a/board/freescale/vf610twr/vf610twr.c +++ b/board/freescale/vf610twr/vf610twr.c @@ -45,6 +45,7 @@ void setup_iomux_ddr(void) VF610_PAD_DDR_A3__DDR_A_3, VF610_PAD_DDR_A2__DDR_A_2, VF610_PAD_DDR_A1__DDR_A_1,
VF610_PAD_DDR_A0__DDR_A_0,@@ -76,6 +77,7 @@ void setup_iomux_ddr(void) VF610_PAD_DDR_WE__DDR_WE_B, VF610_PAD_DDR_ODT1__DDR_ODT_0, VF610_PAD_DDR_ODT0__DDR_ODT_1,
VF610_PAD_DDR_RESETB,};
imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
@@ -88,30 +90,30 @@ void ddr_phy_init(void) writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]); writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]); writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]);
writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]); writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]);
writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]);
writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]); writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]); writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]);
writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]); writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]); writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]);
writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]); writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]); writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]);
/* LPDDR2 only parameter */
writel(DDRMC_PHY_OFF, &ddrmr->phy[49]);
writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, &ddrmr->phy[50]);
/* Processor Pad ODT settings */
writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]);
}
void ddr_ctrl_init(void) @@ -120,12 +122,12 @@ void ddr_ctrl_init(void)
writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]); writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]);
- writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]);
- writel(DDRMC_CR10_TRST_PWRON(80000), &ddrmr->cr[10]);
- writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]);
- writel(DDRMC_CR11_CKE_INACTIVE(200000), &ddrmr->cr[11]); writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]);
- writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) |
DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]);
- writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4),
&ddrmr->cr[13]);@@ -134,24 +136,23 @@ void ddr_ctrl_init(void) writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]);
writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
- writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT |
DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
- writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
- writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]);
writel(DDRMC_CR22_TDAL(12), &ddrmr->cr[22]); writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]); writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]);
writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
- writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
- writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]);
writel(DDRMC_CR26_TREF(3120) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]); writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]);
writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]);
- writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]);
- writel(DDRMC_CR31_TXSNR(48) | DDRMC_CR31_TXSR(468), &ddrmr->cr[31]); writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]); writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]);
- writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]);
- writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]); writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) | DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
These registers are somewhat confusing, according to the RM they are read-only. However, in a different register (CR124) the RM refers to CR39... However, I tried to remove these registers, which made the system not work anymore, hence they seem to be required...
@@ -164,37 +165,45 @@ void ddr_ctrl_init(void) writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]);
- writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]);
writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]);
writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) | DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]); writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255),
DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64),
DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]);
DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
- writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
- writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]);
writel(DDRMC_CR78_Q_FULLNESS(7) | DDRMC_CR78_BUR_ON_FLY_BIT(12),
&ddrmr->cr[78]);writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
- writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0,
&ddrmr->cr[87]);
- writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]);
Why is this not enabled for read anymore (DDRMC_CR87_ODT_RD_MAPCS0)?
writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]); writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]); writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]);
- writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]);
- writel(DDRMC_CR98_WRLVL_DL_0, &ddrmr->cr[98]);
- writel(DDRMC_CR99_WRLVL_DL_1, &ddrmr->cr[99]);
- writel(DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN,
&ddrmr->cr[102]);
- writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]);
- writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]);
- writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]);
- writel(DDRMC_CR105_RDLVL_DL_0(0), &ddrmr->cr[105]);
- writel(DDRMC_CR106_RDLVL_GTDL_0(4), &ddrmr->cr[106]);
- writel(DDRMC_CR110_RDLVL_GTDL_1(4), &ddrmr->cr[110]);
- writel(DDRMC_CR114_RDLVL_GTDL_2(0), &ddrmr->cr[114]);
- writel(DDRMC_CR115_RDLVL_GTDL_2(0), &ddrmr->cr[115]);
- writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1),
- writel(DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), &ddrmr->cr[117]); writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), &ddrmr->cr[118]);
@@ -205,22 +214,40 @@ void ddr_ctrl_init(void) &ddrmr->cr[121]); writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
- writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1),
&ddrmr->cr[123]);
- writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]);
- writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]);
writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]); writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), &ddrmr->cr[132]);
writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]);
writel(DDRMC_CR138_PHY_WRLV_MXDL(256) | DDRMC_CR138_PHYDRAM_CK_EN(1),
&ddrmr->cr[138]);writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3), &ddrmr->cr[139]);
writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]);
writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) | DDRMC_CR143_RDLV_MXDL(128),
&ddrmr->cr[143]);writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
DDRMC_CR144_PHY_RDLV_DLL(3) | DDRMC_CR144_PHY_RDLV_EN(3),&ddrmr->cr[144]);writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]);
writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]);
writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]);
writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]);
writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]);writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]);- writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2),
DDRMC_CR154_PAD_ZQ_MODE(1) | DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]);The DDRMC_CR154_PAD_ZQ_HW_FOR enables a pad calibration. According to the data sheet we should wait until the pad calibration is done (see DDR_CR 156[PAD_ZQ_HW_IN_PROG]).
writel(DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), &ddrmr->cr[155]); writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]);ddr_phy_init();
Due to my patch recently which added the DDRMC_CR154_DDR_SEL_PAD_CONTR(3) flag (which essentially enabled DDR3 for newer SoC revisions) this patch currently does not apply cleanly. However, the merge is rather trivial.
I successfully tested that code on our Colibri VF61 and did some performance measurements using memtester (http://pyropus.ca/software/memtester/).
Old settings: real 8m25.427s user 8m19.730s sys 0m0.530s
New settings: real 8m47.152s user 8m40.720s sys 0m0.760s
So memory seems to be slightly slower now, I tried to isolate the change but was not successful so far. I run that test for both settings (old/new) multiple times, the measured time were always in the same range.
All in all there seem to be quite a lot unused/wrong writes before. The cleanup improves the situation a lot and makes the code aligned to the RM.
Hi Albert,
I would like to see this merged since it really fixes a lot of wrong/undocumented access in the RAM initialization code. It looks like the original code was copied from some other (full featured) SoC, whereas the Vybrid is a striped down variant of it.
I ran that code on Tower and our Vybrid based Colibri VF61, hence you can add a Tested-By: Stefan Agner stefan@agner.ch
As mentioned above, the patch currently does not apply cleanly, but the merge is trivial. In case you prefer a rebased/updated V2 of it, I can send one (since Anthony seems not very responsive).
-- Stefan
On Thu, Aug 14, 2014 at 6:08 PM, Stefan Agner stefan@agner.ch wrote:
Am 2014-07-22 00:42, schrieb Stefan Agner: I would like to see this merged since it really fixes a lot of wrong/undocumented access in the RAM initialization code. It looks like the original code was copied from some other (full featured) SoC, whereas the Vybrid is a striped down variant of it.
I ran that code on Tower and our Vybrid based Colibri VF61, hence you can add a Tested-By: Stefan Agner stefan@agner.ch
As mentioned above, the patch currently does not apply cleanly, but the merge is trivial. In case you prefer a rebased/updated V2 of it, I can send one (since Anthony seems not very responsive).
I also want this merged. This is a step further in dropping the U-Boot from, for Tower, from meta-fsl-arm.
participants (4)
-
Albert ARIBAUD -
Anthony Felice -
Otavio Salvador -
Stefan Agner