[U-Boot] [PATCH 0/4] J721e: Add USB support
Add USB support for J721e SoC. First patch fixes a compile issue with Cadence USB driver. Rest of the patches add env, DT and configs related to USB.
Vignesh Raghavendra (4): usb: cdns3: Fix include file path environment: ti: Add DFU environment variables k3_dfu.h arm: dts: k3-j721e: Add DT nodes for USB configs: j721e_evm_a72_defconfig: Enable USB related configs
.../k3-j721e-common-proc-board-u-boot.dtsi | 14 ++++ arch/arm/dts/k3-j721e-common-proc-board.dts | 37 ++++++++++ arch/arm/dts/k3-j721e-main.dtsi | 70 +++++++++++++++++++ .../arm/dts/k3-j721e-r5-common-proc-board.dts | 7 ++ configs/j721e_evm_a72_defconfig | 28 ++++++++ drivers/usb/cdns3/core.c | 2 +- drivers/usb/cdns3/host.c | 2 +- include/configs/j721e_evm.h | 10 +++ include/environment/ti/k3_dfu.h | 46 ++++++++++++ 9 files changed, 214 insertions(+), 2 deletions(-) create mode 100644 include/environment/ti/k3_dfu.h
xhci.h has now been moved to include/usb/ folder. Therefore, update the path in the Cadence USB drivers.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- drivers/usb/cdns3/core.c | 2 +- drivers/usb/cdns3/host.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c index f1e4bb627815..8c8e02169e81 100644 --- a/drivers/usb/cdns3/core.c +++ b/drivers/usb/cdns3/core.c @@ -18,7 +18,7 @@ #include <linux/kernel.h> #include <linux/io.h> #include <usb.h> -#include "../host/xhci.h" +#include <usb/xhci.h>
#include "core.h" #include "host-export.h" diff --git a/drivers/usb/cdns3/host.c b/drivers/usb/cdns3/host.c index 79be63001d44..425d9d053ddb 100644 --- a/drivers/usb/cdns3/host.c +++ b/drivers/usb/cdns3/host.c @@ -11,7 +11,7 @@ #include <dm.h> #include <linux/compat.h> #include <usb.h> -#include "../host/xhci.h" +#include <usb/xhci.h>
#include "core.h" #include "drd.h"
On 11/18/19 2:46 PM, Vignesh Raghavendra wrote:
xhci.h has now been moved to include/usb/ folder. Therefore, update the
s/folder/directory/ ; I can update it while applying.
path in the Cadence USB drivers.
[...]
Hi Marek,
On 18/11/19 7:42 PM, Marek Vasut wrote:
On 11/18/19 2:46 PM, Vignesh Raghavendra wrote:
xhci.h has now been moved to include/usb/ folder. Therefore, update the
s/folder/directory/ ; I can update it while applying.
Agree, Thanks!
path in the Cadence USB drivers.
[...]
On 11/18/19 2:46 PM, Vignesh Raghavendra wrote:
xhci.h has now been moved to include/usb/ folder. Therefore, update the path in the Cadence USB drivers.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com
Fixed and applied. thanks.
Setup env variables for updating firmwares on eMMC/OSPI/MMC via DFU
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- include/configs/j721e_evm.h | 10 +++++++ include/environment/ti/k3_dfu.h | 46 +++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) create mode 100644 include/environment/ti/k3_dfu.h
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index 639d87a4e578..b21eabc873f7 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -14,6 +14,7 @@ #include <environment/ti/mmc.h> #include <environment/ti/k3_rproc.h> #include <environment/ti/ufs.h> +#include <environment/ti/k3_dfu.h>
#define CONFIG_ENV_SIZE (128 << 10)
@@ -102,12 +103,21 @@ "7 /lib/firmware/j7-c66_1-fw " \ "8 /lib/firmware/j7-c71_0-fw "
+/* set default dfu_bufsiz to 128KB (sector size of OSPI) */ +#define EXTRA_ENV_DFUARGS \ + "dfu_bufsiz=0x20000\0" \ + DFU_ALT_INFO_MMC \ + DFU_ALT_INFO_EMMC \ + DFU_ALT_INFO_RAM \ + DFU_ALT_INFO_OSPI + /* Incorporate settings into the U-Boot environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_MMC_TI_ARGS \ EXTRA_ENV_J721E_BOARD_SETTINGS \ EXTRA_ENV_J721E_BOARD_SETTINGS_MMC \ EXTRA_ENV_RPROC_SETTINGS \ + EXTRA_ENV_DFUARGS \ DEFAULT_UFS_TI_ARGS
/* Now for the remaining common defines */ diff --git a/include/environment/ti/k3_dfu.h b/include/environment/ti/k3_dfu.h new file mode 100644 index 000000000000..2f503b8de880 --- /dev/null +++ b/include/environment/ti/k3_dfu.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * + * Environment variable definitions for DFU on TI K3 SoCs. + * + */ + +#ifndef __TI_DFU_H +#define __TI_DFU_H + +#define DFU_ALT_INFO_MMC \ + "dfu_alt_info_mmc=" \ + "boot part 1 1;" \ + "rootfs part 1 2;" \ + "tiboot3.bin fat 1 1;" \ + "tispl.bin fat 1 1;" \ + "u-boot.img fat 1 1;" \ + "uEnv.txt fat 1 1;" \ + "sysfw.itb fat 1 1\0" + +#define DFU_ALT_INFO_EMMC \ + "dfu_alt_info_emmc=" \ + "rawemmc raw 0 0x800000 mmcpart 1;" \ + "rootfs part 0 1 mmcpart 0;" \ + "tiboot3.bin.raw raw 0x0 0x400 mmcpart 1;" \ + "tispl.bin.raw raw 0x400 0x1000 mmcpart 1;" \ + "u-boot.img.raw raw 0x1400 0x2000 mmcpart 1;" \ + "u-env.raw raw 0x3400 0x100 mmcpart 1;" \ + "sysfw.itb.raw raw 0x3600 0x800 mmcpart 1\0" + +#define DFU_ALT_INFO_OSPI \ + "dfu_alt_info_ospi=" \ + "tiboot3.bin raw 0x0 0x080000;" \ + "tispl.bin raw 0x080000 0x200000;" \ + "u-boot.img raw 0x280000 0x400000;" \ + "u-boot-env raw 0x680000 0x020000;" \ + "sysfw.itb raw 0x6c0000 0x100000;" \ + "rootfs raw 0x800000 0x3800000\0" + +#define DFU_ALT_INFO_RAM \ + "dfu_alt_info_ram=" \ + "tispl.bin ram 0x80080000 0x100000;" \ + "u-boot.img ram 0x81000000 0x100000\0" \ + +#endif /* __TI_DFU_H */
J721e has two instances of Cadence USB3 controller. Add DT nodes for the same. USB0 is configured to device mode and USB1 is configured to host mode. For now only high speed mode is supported.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- .../k3-j721e-common-proc-board-u-boot.dtsi | 14 ++++ arch/arm/dts/k3-j721e-common-proc-board.dts | 37 ++++++++++ arch/arm/dts/k3-j721e-main.dtsi | 70 +++++++++++++++++++ .../arm/dts/k3-j721e-r5-common-proc-board.dts | 7 ++ 4 files changed, 128 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index c4f2dd6b4fb2..c66e029b88ad 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -311,6 +311,20 @@ u-boot,dm-spl; };
+&main_usbss0_pins_default { + u-boot,dm-spl; +}; + +&usbss0 { + u-boot,dm-spl; + ti,usb2-only; +}; + +&usb0 { + dr_mode = "peripheral"; + u-boot,dm-spl; +}; + &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts index c978cabd1335..137da7e425a1 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-common-proc-board.dts @@ -77,3 +77,40 @@ voltage-ranges = <1800 1800 3300 3300>; ti,driver-strength-ohm = <50>; }; + +&main_pmx0 { + main_usbss0_pins_default: main_usbss0_pins_default { + pinctrl-single,pins = < + J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ + J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ + >; + }; + + main_usbss1_pins_default: main_usbss1_pins_default { + pinctrl-single,pins = < + J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ + >; + }; +}; + +&usbss0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_usbss0_pins_default>; + ti,vbus-divider; +}; + +&usb0 { + dr_mode = "otg"; + maximum-speed = "super-speed"; +}; + +&usbss1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_usbss1_pins_default>; + ti,usb2-only; +}; + +&usb1 { + dr_mode = "host"; + maximum-speed = "high-speed"; +}; diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi index 3a0763209fc2..5083a0c3aef0 100644 --- a/arch/arm/dts/k3-j721e-main.dtsi +++ b/arch/arm/dts/k3-j721e-main.dtsi @@ -340,6 +340,76 @@ resets = <&k3_reset 15 1>; };
+ usbss0: cdns_usb@4104000 { + compatible = "ti,j721e-usb"; + reg = <0x00 0x4104000 0x00 0x100>; + dma-coherent; + power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; + clock-names = "usb2_refclk", "lpm_clk"; + assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ + #address-cells = <2>; + #size-cells = <2>; + ranges; + + phy@4108000 { + compatible = "ti,j721e-usb2-phy"; + reg = <0x00 0x4108000 0x00 0x400>; + }; + + usb0: usb@6000000 { + compatible = "cdns,usb3"; + reg = <0x00 0x6000000 0x00 0x10000>, + <0x00 0x6010000 0x00 0x10000>, + <0x00 0x6020000 0x00 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ + interrupt-names = "host", + "peripheral", + "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + + usbss1: cdns_usb@4114000 { + compatible = "ti,j721e-usb"; + reg = <0x00 0x4114000 0x00 0x100>; + dma-coherent; + power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; + clock-names = "usb2_refclk", "lpm_clk"; + assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ + #address-cells = <2>; + #size-cells = <2>; + ranges; + + phy@4118000 { + compatible = "ti,j721e-usb2-phy"; + reg = <0x00 0x4118000 0x00 0x400>; + }; + + usb1: usb@6400000 { + compatible = "cdns,usb3"; + reg = <0x00 0x6400000 0x00 0x10000>, + <0x00 0x6410000 0x00 0x10000>, + <0x00 0x6420000 0x00 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ + interrupt-names = "host", + "peripheral", + "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + ufs_wrapper: ufs-wrapper@4e80000 { compatible = "ti,j721e-ufs"; reg = <0x0 0x4e80000 0x0 0x100>; diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 41af48214f6f..1a8e10786110 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -112,6 +112,13 @@ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ >; }; + + main_usbss0_pins_default: main_usbss0_pins_default { + pinctrl-single,pins = < + J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ + J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ + >; + }; };
&wkup_uart0 {
Enable USB host and device related configs.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- configs/j721e_evm_a72_defconfig | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 748179e82317..0abbfc02e614 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -29,6 +29,8 @@ CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_SPI_LOAD=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPT=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_ASKENV=y @@ -37,6 +39,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_UFS=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y @@ -60,8 +64,17 @@ CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_FASTBOOT_BUF_SIZE=0x2F000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_TI_SCI_PROTOCOL=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y @@ -91,6 +104,7 @@ CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_RAM=y CONFIG_REMOTEPROC_TI_K3_DSP=y CONFIG_REMOTEPROC_TI_K3_R5F=y CONFIG_DM_RESET=y @@ -105,7 +119,21 @@ CONFIG_CADENCE_QSPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_SPL_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6163 CONFIG_UFS=y CONFIG_CADENCE_UFS=y CONFIG_TI_J721E_UFS=y +CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT_OVERLAY=y
On 18/11/19 7:16 PM, Vignesh Raghavendra wrote:
Add USB support for J721e SoC. First patch fixes a compile issue with Cadence USB driver. Rest of the patches add env, DT and configs related to USB.
patches 2,3,4 merged into u-boot-ti.
Thanks and regards, Lokesh
Vignesh Raghavendra (4): usb: cdns3: Fix include file path environment: ti: Add DFU environment variables k3_dfu.h arm: dts: k3-j721e: Add DT nodes for USB configs: j721e_evm_a72_defconfig: Enable USB related configs
.../k3-j721e-common-proc-board-u-boot.dtsi | 14 ++++ arch/arm/dts/k3-j721e-common-proc-board.dts | 37 ++++++++++ arch/arm/dts/k3-j721e-main.dtsi | 70 +++++++++++++++++++ .../arm/dts/k3-j721e-r5-common-proc-board.dts | 7 ++ configs/j721e_evm_a72_defconfig | 28 ++++++++ drivers/usb/cdns3/core.c | 2 +- drivers/usb/cdns3/host.c | 2 +- include/configs/j721e_evm.h | 10 +++ include/environment/ti/k3_dfu.h | 46 ++++++++++++ 9 files changed, 214 insertions(+), 2 deletions(-) create mode 100644 include/environment/ti/k3_dfu.h
participants (3)
-
Lokesh Vutla -
Marek Vasut -
Vignesh Raghavendra