[U-Boot] [PATCHv2 1/5] fsl: serdes: ensure accessing the initialized maps of serdes protocol
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Up to now, the function is_serdes_configed() doesn't check if the map of serdes protocol is initialized before accessing it. The function is_serdes_configed() will get wrong result when it was called before the serdes protocol maps initialized. As the first element of the map isn't used for any device, so use it as the flag to indicate if the map has been initialized.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - Check initialization-state of the serdes protocol map before serdes init. - Comment the element 'NONE' used as a initialization-state flag.
arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c | 15 +++++++++++++-- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c | 12 ++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 12 ++++++++++++ .../arm/include/asm/arch-fsl-layerscape/fsl_serdes.h | 8 ++++++++ arch/arm/include/asm/arch-ls102xa/fsl_serdes.h | 4 ++++ arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c | 9 +++++++++ arch/powerpc/cpu/mpc85xx/c29x_serdes.c | 9 +++++++++ arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 18 ++++++++++++++++++ arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 8 ++++++++ arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c | 20 +++++++++++++++++++- arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c | 20 +++++++++++++++++++- arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c | 9 +++++++++ arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c | 9 +++++++++ arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c | 9 +++++++++ arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c | 9 +++++++++ arch/powerpc/cpu/mpc85xx/p1010_serdes.c | 20 +++++++++++++++++++- arch/powerpc/cpu/mpc85xx/p1021_serdes.c | 9 +++++++++ arch/powerpc/cpu/mpc85xx/p1022_serdes.c | 20 +++++++++++++++++++- arch/powerpc/cpu/mpc85xx/p1023_serdes.c | 12 +++++++++++- arch/powerpc/cpu/mpc85xx/p2020_serdes.c | 9 +++++++++ arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c | 20 +++++++++++++++++++- arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c | 20 +++++++++++++++++++- arch/powerpc/include/asm/fsl_serdes.h | 4 ++++ 23 files changed, 276 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c index 9b78acb..86ace90 100644 --- a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c +++ b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c @@ -23,9 +23,15 @@ int is_serdes_configured(enum srds_prtcl device) u64 ret = 0;
#ifdef CONFIG_SYS_FSL_SRDS_1 + if (!(serdes1_prtcl_map & (1ULL << NONE))) + fsl_serdes_init(); + ret |= (1ULL << device) & serdes1_prtcl_map; #endif #ifdef CONFIG_SYS_FSL_SRDS_2 + if (!(serdes2_prtcl_map & (1ULL << NONE))) + fsl_serdes_init(); + ret |= (1ULL << device) & serdes2_prtcl_map; #endif
@@ -87,19 +93,24 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift) serdes_prtcl_map |= (1ULL << lane_prtcl); }
+ /* Set the first bit to indicate serdes has been initialized */ + serdes_prtcl_map |= (1ULL << NONE); + return serdes_prtcl_map; }
void fsl_serdes_init(void) { #ifdef CONFIG_SYS_FSL_SRDS_1 - serdes1_prtcl_map = serdes_init(FSL_SRDS_1, + if (!(serdes1_prtcl_map & (1ULL << NONE))) + serdes1_prtcl_map = serdes_init(FSL_SRDS_1, CONFIG_SYS_FSL_SERDES_ADDR, RCWSR4_SRDS1_PRTCL_MASK, RCWSR4_SRDS1_PRTCL_SHIFT); #endif #ifdef CONFIG_SYS_FSL_SRDS_2 - serdes2_prtcl_map = serdes_init(FSL_SRDS_2, + if (!(serdes2_prtcl_map & (1ULL << NONE))) + serdes2_prtcl_map = serdes_init(FSL_SRDS_2, CONFIG_SYS_FSL_SERDES_ADDR + FSL_SRDS_2 * 0x1000, RCWSR4_SRDS2_PRTCL_MASK, diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c index f73092a..29cd28e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c @@ -22,9 +22,15 @@ int is_serdes_configured(enum srds_prtcl device) int ret = 0;
#ifdef CONFIG_SYS_FSL_SRDS_1 + if (!serdes1_prtcl_map[NONE]) + fsl_serdes_init(); + ret |= serdes1_prtcl_map[device]; #endif #ifdef CONFIG_SYS_FSL_SRDS_2 + if (!serdes2_prtcl_map[NONE]) + fsl_serdes_init(); + ret |= serdes2_prtcl_map[device]; #endif
@@ -98,6 +104,9 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, u32 cfg; int lane;
+ if (serdes_prtcl_map[NONE]) + return; + memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask; @@ -115,6 +124,9 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, else serdes_prtcl_map[lane_prtcl] = 1; } + + /* Set the first element to indicate serdes has been initialized */ + serdes_prtcl_map[NONE] = 1; }
void fsl_serdes_init(void) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index be6acc6..9110d7a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -28,9 +28,15 @@ int is_serdes_configured(enum srds_prtcl device) int ret = 0;
#ifdef CONFIG_SYS_FSL_SRDS_1 + if (!serdes1_prtcl_map[NONE]) + fsl_serdes_init(); + ret |= serdes1_prtcl_map[device]; #endif #ifdef CONFIG_SYS_FSL_SRDS_2 + if (!serdes2_prtcl_map[NONE]) + fsl_serdes_init(); + ret |= serdes2_prtcl_map[device]; #endif
@@ -79,6 +85,9 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, u32 cfg; int lane;
+ if (serdes_prtcl_map[NONE]) + return; + memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask; @@ -136,6 +145,9 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, #endif } } + + /* Set the first element to indicate serdes has been initialized */ + serdes_prtcl_map[NONE] = 1; }
void fsl_serdes_init(void) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index e1b3f44..7847bf4 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -11,6 +11,10 @@
#ifdef CONFIG_LS2080A enum srds_prtcl { + /* + * Nobody will check whether the device 'NONE' has been configured, + * So use it to indicate if the serdes_prtcl_map has been initialized. + */ NONE = 0, PCIE1, PCIE2, @@ -57,6 +61,10 @@ enum srds { }; #elif defined(CONFIG_FSL_LSCH2) enum srds_prtcl { + /* + * Nobody will check whether the device 'NONE' has been configured, + * So use it to indicate if the serdes_prtcl_map has been initialized. + */ NONE = 0, PCIE1, PCIE2, diff --git a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h index 3a92f5a..22a4275 100644 --- a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h +++ b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h @@ -10,6 +10,10 @@ #include <config.h>
enum srds_prtcl { + /* + * Nobody will check whether the device 'NONE' has been configured, + * So use it to indicate if the serdes_prtcl_map has been initialized. + */ NONE = 0, PCIE1, PCIE2, diff --git a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c index 399b208..4b5cd99 100644 --- a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c @@ -68,6 +68,9 @@ static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
int is_serdes_configured(enum srds_prtcl prtcl) { + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << prtcl) & serdes1_prtcl_map; }
@@ -79,6 +82,9 @@ void fsl_serdes_init(void) MPC85xx_PORDEVSR_IO_SEL_SHIFT; int lane;
+ if (serdes1_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -90,4 +96,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; serdes1_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c index 51972cb..74d27b9 100644 --- a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c @@ -32,6 +32,9 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
int is_serdes_configured(enum srds_prtcl device) { + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << device) & serdes1_prtcl_map; }
@@ -44,6 +47,9 @@ void fsl_serdes_init(void) const struct serdes_config *ptr; int lane;
+ if (serdes1_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -59,4 +65,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = ptr->lanes[lane]; serdes1_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 9920839..ebc9b81 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -92,15 +92,27 @@ int is_serdes_configured(enum srds_prtcl device) int ret = 0;
#ifdef CONFIG_SYS_FSL_SRDS_1 + if (!serdes1_prtcl_map[NONE]) + fsl_serdes_init(); + ret |= serdes1_prtcl_map[device]; #endif #ifdef CONFIG_SYS_FSL_SRDS_2 + if (!serdes2_prtcl_map[NONE]) + fsl_serdes_init(); + ret |= serdes2_prtcl_map[device]; #endif #ifdef CONFIG_SYS_FSL_SRDS_3 + if (!serdes3_prtcl_map[NONE]) + fsl_serdes_init(); + ret |= serdes3_prtcl_map[device]; #endif #ifdef CONFIG_SYS_FSL_SRDS_4 + if (!serdes4_prtcl_map[NONE]) + fsl_serdes_init(); + ret |= serdes4_prtcl_map[device]; #endif
@@ -184,6 +196,9 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, u32 cfg; int lane;
+ if (serdes_prtcl_map[NONE]) + return; + memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); #ifdef CONFIG_SYS_FSL_ERRATUM_A007186 struct ccsr_sfp_regs __iomem *sfp_regs = @@ -325,6 +340,9 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, else serdes_prtcl_map[lane_prtcl] = 1; } + + /* Set the first element to indicate serdes has been initialized */ + serdes_prtcl_map[NONE] = 1; }
void fsl_serdes_init(void) diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index ba22f90..85739e9 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -136,6 +136,9 @@ int is_serdes_configured(enum srds_prtcl device) if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) return 0;
+ if (!(serdes_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << device) & serdes_prtcl_map; }
@@ -514,6 +517,8 @@ void fsl_serdes_init(void) if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; #endif + if (serdes_prtcl_map & (1 << NONE)) + return;
/* Is serdes enabled at all? */ if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) @@ -857,6 +862,9 @@ void fsl_serdes_init(void) SRDS_RSTCTL_SDPD); } #endif + + /* Set the first bit to indicate serdes has been initialized */ + serdes_prtcl_map |= (1 << NONE); }
const char *serdes_clock_to_string(u32 clock) diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c index baf52d5..8c075f1 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c @@ -71,11 +71,19 @@ static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
int is_serdes_configured(enum srds_prtcl device) { - int ret = (1 << device) & serdes1_prtcl_map; + int ret; + + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + + ret = (1 << device) & serdes1_prtcl_map;
if (ret) return ret;
+ if (!(serdes2_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << device) & serdes2_prtcl_map; }
@@ -88,6 +96,10 @@ void fsl_serdes_init(void) u32 tmp; int lane;
+ if (serdes1_prtcl_map & (1 << NONE) && + serdes2_prtcl_map & (1 << NONE)) + return; + srds1_io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> MPC85xx_PORDEVSR_IO_SEL_SHIFT;
@@ -221,6 +233,9 @@ void fsl_serdes_init(void) serdes1_prtcl_map |= (1 << lane_prtcl); }
+ /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); + if (srds2_io_sel >= ARRAY_SIZE(serdes2_cfg_tbl)) { printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_io_sel); return; @@ -230,4 +245,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds2_io_sel][lane]; serdes2_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes2_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c index ed78a66..b27763e 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c @@ -34,11 +34,19 @@ static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
int is_serdes_configured(enum srds_prtcl device) { - int ret = (1 << device) & serdes1_prtcl_map; + int ret; + + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + + ret = (1 << device) & serdes1_prtcl_map;
if (ret) return ret;
+ if (!(serdes2_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << device) & serdes2_prtcl_map; }
@@ -50,6 +58,10 @@ void fsl_serdes_init(void) MPC85xx_PORDEVSR_IO_SEL_SHIFT; int lane;
+ if (serdes1_prtcl_map & (1 << NONE) && + serdes2_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -61,6 +73,9 @@ void fsl_serdes_init(void) serdes1_prtcl_map |= (1 << lane_prtcl); }
+ /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); + if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) { printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); return; @@ -76,4 +91,7 @@ void fsl_serdes_init(void)
if (pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS) serdes2_prtcl_map &= ~(1 << SGMII_TSEC3); + + /* Set the first bit to indicate serdes has been initialized */ + serdes2_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c index d146955..f1042d5 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c @@ -24,6 +24,9 @@ static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
int is_serdes_configured(enum srds_prtcl prtcl) { + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << prtcl) & serdes1_prtcl_map; }
@@ -35,6 +38,9 @@ void fsl_serdes_init(void) MPC85xx_PORDEVSR_IO_SEL_SHIFT; int lane;
+ if (serdes1_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg);
if (srds1_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -46,4 +52,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_cfg][lane]; serdes1_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c index 9199f01..7c287a0 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c @@ -24,6 +24,9 @@ static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
int is_serdes_configured(enum srds_prtcl prtcl) { + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << prtcl) & serdes1_prtcl_map; }
@@ -35,6 +38,9 @@ void fsl_serdes_init(void) MPC85xx_PORDEVSR_IO_SEL_SHIFT; int lane;
+ if (serdes1_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -46,4 +52,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; serdes1_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c index 6c80b5e..cc8ddb2 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c @@ -33,6 +33,9 @@ static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
int is_serdes_configured(enum srds_prtcl prtcl) { + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << prtcl) & serdes1_prtcl_map; }
@@ -44,6 +47,9 @@ void fsl_serdes_init(void) MPC85xx_PORDEVSR_IO_SEL_SHIFT; int lane;
+ if (serdes1_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -55,4 +61,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; serdes1_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c index 3632eb5..1f0f474 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c @@ -28,6 +28,9 @@ static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
int is_serdes_configured(enum srds_prtcl prtcl) { + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << prtcl) & serdes1_prtcl_map; }
@@ -39,6 +42,9 @@ void fsl_serdes_init(void) MPC85xx_PORDEVSR_IO_SEL_SHIFT; int lane;
+ if (serdes1_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -62,4 +68,7 @@ void fsl_serdes_init(void)
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) serdes1_prtcl_map |= (1 << SGMII_TSEC4); + + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c index 4b965f7..d8c0b62 100644 --- a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c @@ -33,11 +33,19 @@ static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
int is_serdes_configured(enum srds_prtcl device) { - int ret = (1 << device) & serdes1_prtcl_map; + int ret; + + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + + ret = (1 << device) & serdes1_prtcl_map;
if (ret) return ret;
+ if (!(serdes2_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << device) & serdes2_prtcl_map; }
@@ -49,6 +57,10 @@ void fsl_serdes_init(void) MPC85xx_PORDEVSR_IO_SEL_SHIFT; int lane;
+ if (serdes1_prtcl_map & (1 << NONE) && + serdes2_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -60,6 +72,9 @@ void fsl_serdes_init(void) serdes1_prtcl_map |= (1 << lane_prtcl); }
+ /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); + if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) { printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); return; @@ -69,4 +84,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; serdes2_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes2_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c index 99a77bd..77b9439 100644 --- a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c @@ -41,6 +41,9 @@ static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
int is_serdes_configured(enum srds_prtcl prtcl) { + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << prtcl) & serdes1_prtcl_map; }
@@ -55,6 +58,9 @@ void fsl_serdes_init(void) int lane; u32 mask, val;
+ if (serdes1_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -67,6 +73,9 @@ void fsl_serdes_init(void) serdes1_prtcl_map |= (1 << lane_prtcl); }
+ /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); + /* Init SERDES Receiver electrical idle detection control for PCIe */
/* Lane 0 is always PCIe 1 */ diff --git a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c index 14d17eb..88013d4 100644 --- a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c @@ -72,11 +72,19 @@ static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
int is_serdes_configured(enum srds_prtcl device) { - int ret = (1 << device) & serdes1_prtcl_map; + int ret; + + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + + ret = (1 << device) & serdes1_prtcl_map;
if (ret) return ret;
+ if (!(serdes2_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << device) & serdes2_prtcl_map; }
@@ -88,6 +96,10 @@ void fsl_serdes_init(void) MPC85xx_PORDEVSR_IO_SEL_SHIFT; int lane;
+ if (serdes1_prtcl_map & (1 << NONE) && + serdes2_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -99,6 +111,9 @@ void fsl_serdes_init(void) serdes1_prtcl_map |= (1 << lane_prtcl); }
+ /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); + if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) { printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); return; @@ -108,4 +123,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; serdes2_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes2_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c index e83b0a3..b2b9f95 100644 --- a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c @@ -24,7 +24,12 @@ static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
int is_serdes_configured(enum srds_prtcl device) { - int ret = (1 << device) & serdes1_prtcl_map; + int ret; + + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + + ret = (1 << device) & serdes1_prtcl_map; return ret; }
@@ -36,6 +41,9 @@ void fsl_serdes_init(void) MPC85xx_PORDEVSR_IO_SEL_SHIFT; int lane;
+ if (serdes1_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -47,4 +55,6 @@ void fsl_serdes_init(void) serdes1_prtcl_map |= (1 << lane_prtcl); }
+ /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c index 59d402c..0890eaa 100644 --- a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c @@ -32,6 +32,9 @@ static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
int is_serdes_configured(enum srds_prtcl prtcl) { + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << prtcl) & serdes1_prtcl_map; }
@@ -43,6 +46,9 @@ void fsl_serdes_init(void) MPC85xx_PORDEVSR_IO_SEL_SHIFT; int lane;
+ if (serdes1_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -54,4 +60,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; serdes1_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c b/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c index 2a7e3bf..ea4f4c8 100644 --- a/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c +++ b/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c @@ -29,11 +29,19 @@ static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
int is_serdes_configured(enum srds_prtcl device) { - int ret = (1 << device) & serdes1_prtcl_map; + int ret; + + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + + ret = (1 << device) & serdes1_prtcl_map;
if (ret) return ret;
+ if (!(serdes2_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << device) & serdes2_prtcl_map; }
@@ -46,6 +54,10 @@ void fsl_serdes_init(void) MPC8610_PORDEVSR_IO_SEL_SHIFT; int lane;
+ if (serdes1_prtcl_map & (1 << NONE) && + serdes2_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -57,6 +69,9 @@ void fsl_serdes_init(void) serdes1_prtcl_map |= (1 << lane_prtcl); }
+ /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); + if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) { printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); return; @@ -66,4 +81,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; serdes2_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes2_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c b/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c index cc0f8e9..5b12cbd 100644 --- a/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c +++ b/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c @@ -38,11 +38,19 @@ static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
int is_serdes_configured(enum srds_prtcl device) { - int ret = (1 << device) & serdes1_prtcl_map; + int ret; + + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + + ret = (1 << device) & serdes1_prtcl_map;
if (ret) return ret;
+ if (!(serdes2_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << device) & serdes2_prtcl_map; }
@@ -55,6 +63,10 @@ void fsl_serdes_init(void) MPC8641_PORDEVSR_IO_SEL_SHIFT; int lane;
+ if (serdes1_prtcl_map & (1 << NONE) && + serdes2_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -66,6 +78,9 @@ void fsl_serdes_init(void) serdes1_prtcl_map |= (1 << lane_prtcl); }
+ /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); + if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) { printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); return; @@ -75,4 +90,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; serdes2_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes2_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index 45e248e..bef961c 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -10,6 +10,10 @@ #include <config.h>
enum srds_prtcl { + /* + * Nobody will check whether the device 'NONE' has been configured, + * So use it to indicate if the serdes_prtcl_map has been initialized. + */ NONE = 0, PCIE1, PCIE2,
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Move forward the basic non-secure access enable operation, so the subsequent individual device access permission can override it. And collect the dispersed callers in board level, and then move them to SoC level.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2 - no change
arch/arm/cpu/armv7/ls102xa/soc.c | 5 +++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 5 +++++ arch/arm/cpu/armv8/fsl-layerscape/spl.c | 4 ---- board/freescale/ls1012afrdm/ls1012afrdm.c | 5 ----- board/freescale/ls1012aqds/ls1012aqds.c | 5 ----- board/freescale/ls1012ardb/ls1012ardb.c | 5 ----- board/freescale/ls1021aqds/ls1021aqds.c | 4 ---- board/freescale/ls1021atwr/ls1021atwr.c | 4 ---- board/freescale/ls1043aqds/ls1043aqds.c | 4 ---- board/freescale/ls1043ardb/ls1043ardb.c | 5 ----- 10 files changed, 10 insertions(+), 36 deletions(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index b1b0c71..4c93ab7 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -10,6 +10,7 @@ #include <asm/arch/immap_ls102xa.h> #include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_stream_id.h> +#include <fsl_csu.h>
struct liodn_id_table sec_liodn_tbl[] = { SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), @@ -64,6 +65,10 @@ int arch_soc_init(void) struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; unsigned int major;
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + #ifdef CONFIG_FSL_QSPI out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index f62b78d..fac539d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -12,6 +12,7 @@ #include <asm/io.h> #include <asm/global_data.h> #include <asm/arch-fsl-layerscape/config.h> +#include <fsl_csu.h> #ifdef CONFIG_SYS_FSL_DDR #include <fsl_ddr_sdram.h> #include <fsl_ddr.h> @@ -303,6 +304,10 @@ void fsl_lsch2_early_init_f(void) struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + #ifdef CONFIG_FSL_IFC init_early_memctl_regs(); /* tighten IFC timing */ #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 19e34fa..b75547d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -8,7 +8,6 @@ #include <spl.h> #include <asm/io.h> #include <fsl_ifc.h> -#include <fsl_csu.h> #include <i2c.h>
DECLARE_GLOBAL_DATA_PTR; @@ -66,9 +65,6 @@ void board_init_f(ulong dummy) /* Clear the BSS */ memset(__bss_start, 0, __bss_end - __bss_start);
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif board_init_r(NULL, 0); } #endif diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index a94a458..5a2b1f4 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -11,7 +11,6 @@ #include <asm/arch/fsl_serdes.h> #include <asm/arch/soc.h> #include <hwconfig.h> -#include <fsl_csu.h> #include <environment.h> #include <fsl_mmdc.h> #include <netdev.h> @@ -175,10 +174,6 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - return 0; }
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 71eea82..852d683 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -17,7 +17,6 @@ #include <mmc.h> #include <scsi.h> #include <fm_eth.h> -#include <fsl_csu.h> #include <fsl_esdhc.h> #include <fsl_mmdc.h> #include <spl.h> @@ -207,10 +206,6 @@ int board_init(void) out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index f69768d..a3748de 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -14,7 +14,6 @@ #include <ahci.h> #include <mmc.h> #include <scsi.h> -#include <fsl_csu.h> #include <fsl_esdhc.h> #include <environment.h> #include <fsl_mmdc.h> @@ -207,10 +206,6 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - return 0; }
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index dbea0bf..291b0f4 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -446,10 +446,6 @@ int board_init(void)
ls102xa_smmu_stream_id_init();
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - #ifdef CONFIG_U_QE u_qe_init(); #endif diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 77482a9..85c036b 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -489,10 +489,6 @@ int board_init(void)
ls102xa_smmu_stream_id_init();
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - #ifdef CONFIG_U_QE u_qe_init(); #endif diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 941dfbc..1642557 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -17,7 +17,6 @@ #include <mmc.h> #include <scsi.h> #include <fm_eth.h> -#include <fsl_csu.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> #include <spl.h> @@ -316,9 +315,6 @@ int board_init(void) config_serdes_mux(); #endif
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif return 0; }
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index d3e37b4..0a73e0f 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -16,7 +16,6 @@ #include <mmc.h> #include <scsi.h> #include <fm_eth.h> -#include <fsl_csu.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> #include <fsl_sec.h> @@ -90,10 +89,6 @@ int board_init(void) init_final_memctl_regs(); #endif
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Add this API to make the individual device is able to be set to the specified permission.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2 - no change
board/freescale/common/ns_access.c | 34 ++++++++++++++++++++-------------- include/fsl_csu.h | 1 + 2 files changed, 21 insertions(+), 14 deletions(-)
diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c index d8d16c5..c3d7a5e 100644 --- a/board/freescale/common/ns_access.c +++ b/board/freescale/common/ns_access.c @@ -9,25 +9,31 @@ #include <fsl_csu.h> #include <asm/arch/ns_access.h>
-static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) +void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val) { u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR; u32 *reg; - uint32_t val; - int i; + uint32_t tmp;
- for (i = 0; i < num; i++) { - reg = base + ns_dev[i].ind / 2; - val = in_be32(reg); - if (ns_dev[i].ind % 2 == 0) { - val &= 0x0000ffff; - val |= ns_dev[i].val << 16; - } else { - val &= 0xffff0000; - val |= ns_dev[i].val; - } - out_be32(reg, val); + reg = base + ns_dev->ind / 2; + tmp = in_be32(reg); + if (ns_dev->ind % 2 == 0) { + tmp &= 0x0000ffff; + tmp |= val << 16; + } else { + tmp &= 0xffff0000; + tmp |= val; } + + out_be32(reg, tmp); +} + +static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) +{ + int i; + + for (i = 0; i < num; i++) + set_devices_ns_access(ns_dev + i, ns_dev[i].val); }
void enable_layerscape_ns_access(void) diff --git a/include/fsl_csu.h b/include/fsl_csu.h index f4d97fb..57a9985 100644 --- a/include/fsl_csu.h +++ b/include/fsl_csu.h @@ -30,5 +30,6 @@ struct csu_ns_dev { };
void enable_layerscape_ns_access(void); +void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val);
#endif
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2 - mv disable_pcie_ns_access() to set_pcie_ns_access().
.../include/asm/arch-fsl-layerscape/ns_access.h | 1 + board/freescale/common/ns_access.c | 28 ++++++++++++++++++++++ include/fsl_csu.h | 1 + 3 files changed, 30 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h index db76066..f46f1d8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h @@ -6,6 +6,7 @@
#ifndef __FSL_NS_ACCESS_H_ #define __FSL_NS_ACCESS_H_ +#include <fsl_csu.h>
enum csu_cslx_ind { CSU_CSLX_PCIE2_IO = 0, diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c index c3d7a5e..6d547fa 100644 --- a/board/freescale/common/ns_access.c +++ b/board/freescale/common/ns_access.c @@ -8,6 +8,7 @@ #include <asm/io.h> #include <fsl_csu.h> #include <asm/arch/ns_access.h> +#include <asm/arch/fsl_serdes.h>
void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val) { @@ -40,3 +41,30 @@ void enable_layerscape_ns_access(void) { enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); } + +void set_pcie_ns_access(int pcie, u16 val) +{ + switch (pcie) { +#ifdef CONFIG_PCIE1 + case PCIE1: + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1], val); + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1_IO], val); + return; +#endif +#ifdef CONFIG_PCIE2 + case PCIE2: + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2], val); + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2_IO], val); + return; +#endif +#ifdef CONFIG_PCIE3 + case PCIE3: + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3], val); + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3_IO], val); + return; +#endif + default: + debug("The PCIE%d doesn't exist!\n", pcie); + return; + } +} diff --git a/include/fsl_csu.h b/include/fsl_csu.h index 57a9985..42ca433 100644 --- a/include/fsl_csu.h +++ b/include/fsl_csu.h @@ -31,5 +31,6 @@ struct csu_ns_dev {
void enable_layerscape_ns_access(void); void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val); +void set_pcie_ns_access(int pcie, u16 val);
#endif
Hi All,
Drop this patch.
-----Original Message----- From: Zhiqiang Hou [mailto:Zhiqiang.Hou@nxp.com] Sent: 2016年8月2日 19:03 To: u-boot@lists.denx.de; albert.u.boot@aribaud.net; york sun york.sun@nxp.com; wd@denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Huan Wang alison.wang@nxp.com; Mingkai Hu mingkai.hu@nxp.com Cc: Yao Yuan yao.yuan@nxp.com; Qianyu Gong qianyu.gong@nxp.com; bmeng.cn@gmail.com; Shengzhou Liu shengzhou.liu@nxp.com; Zhiqiang Hou zhiqiang.hou@nxp.com Subject: [PATCH 4/5] fsl: csu: add an API to set R/W permission to PCIe
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
V2
- mv disable_pcie_ns_access() to set_pcie_ns_access().
.../include/asm/arch-fsl-layerscape/ns_access.h | 1 + board/freescale/common/ns_access.c | 28 ++++++++++++++++++++++ include/fsl_csu.h | 1 + 3 files changed, 30 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h index db76066..f46f1d8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h @@ -6,6 +6,7 @@
#ifndef __FSL_NS_ACCESS_H_ #define __FSL_NS_ACCESS_H_ +#include <fsl_csu.h>
enum csu_cslx_ind { CSU_CSLX_PCIE2_IO = 0, diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c index c3d7a5e..6d547fa 100644 --- a/board/freescale/common/ns_access.c +++ b/board/freescale/common/ns_access.c @@ -8,6 +8,7 @@ #include <asm/io.h> #include <fsl_csu.h> #include <asm/arch/ns_access.h> +#include <asm/arch/fsl_serdes.h>
void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val) { @@ -40,3 +41,30 @@ void enable_layerscape_ns_access(void) { enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); }
+void set_pcie_ns_access(int pcie, u16 val) {
- switch (pcie) {
+#ifdef CONFIG_PCIE1
- case PCIE1:
set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1], val);set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1_IO], val);return;+#endif +#ifdef CONFIG_PCIE2
- case PCIE2:
set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2], val);set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2_IO], val);return;+#endif +#ifdef CONFIG_PCIE3
- case PCIE3:
set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3], val);set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3_IO], val);return;+#endif
- default:
debug("The PCIE%d doesn't exist!\n", pcie);return;- }
+} diff --git a/include/fsl_csu.h b/include/fsl_csu.h index 57a9985..42ca433 100644 --- a/include/fsl_csu.h +++ b/include/fsl_csu.h @@ -31,5 +31,6 @@ struct csu_ns_dev {
void enable_layerscape_ns_access(void); void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val); +void set_pcie_ns_access(int pcie, u16 val);
#endif
2.1.0.27.g96db324
Thanks, Zhiqiang
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- .../include/asm/arch-fsl-layerscape/ns_access.h | 1 + board/freescale/common/ns_access.c | 28 ++++++++++++++++++++++ include/fsl_csu.h | 1 + 3 files changed, 30 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h index db76066..f46f1d8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h @@ -6,6 +6,7 @@
#ifndef __FSL_NS_ACCESS_H_ #define __FSL_NS_ACCESS_H_ +#include <fsl_csu.h>
enum csu_cslx_ind { CSU_CSLX_PCIE2_IO = 0, diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c index c3d7a5e..81c9211 100644 --- a/board/freescale/common/ns_access.c +++ b/board/freescale/common/ns_access.c @@ -8,6 +8,7 @@ #include <asm/io.h> #include <fsl_csu.h> #include <asm/arch/ns_access.h> +#include <asm/arch/fsl_serdes.h>
void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val) { @@ -40,3 +41,30 @@ void enable_layerscape_ns_access(void) { enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); } + +void set_pcie_ns_access(int pcie, u16 val) +{ + switch (pcie) { +#ifdef CONFIG_PCIE1 + case PCIE1: + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1], val); + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1_IO], val); + return; +#endif +#ifdef CONFIG_PCIE2 + case PCIE2: + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2], val); + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2_IO], val); + return; +#endif +#ifdef CONFIG_PCIE3 + case PCIE3: + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3], val); + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3_IO], val); + return; +#endif + default: + debug("The PCIE%d doesn't exist!\n", pcie); + return; + } +} diff --git a/include/fsl_csu.h b/include/fsl_csu.h index 57a9985..8582ac0 100644 --- a/include/fsl_csu.h +++ b/include/fsl_csu.h @@ -31,5 +31,6 @@ struct csu_ns_dev {
void enable_layerscape_ns_access(void); void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val); +void set_pcie_ns_access(int pcie, u16 val);
#endif
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
As the access to serders protocol unselected PCIe controller will hang. So disable the R/W permission to unselected PCIe controller including its CCSR, IO space and memory space according to the serders protocol field of RCW.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- Tested on LS1043A RDB board.
V2 - no change
arch/arm/cpu/armv7/ls102xa/soc.c | 14 ++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 16 ++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 4 ++++ arch/arm/include/asm/arch-ls102xa/config.h | 1 + arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 4 ++++ board/freescale/ls1012aqds/ls1012aqds.c | 4 ++++ board/freescale/ls1012ardb/ls1012ardb.c | 4 ++++ board/freescale/ls1021aqds/ls1021aqds.c | 4 ++++ board/freescale/ls1021atwr/ls1021atwr.c | 4 ++++ board/freescale/ls1043aqds/ls1043aqds.c | 4 ++++ board/freescale/ls1043ardb/ls1043ardb.c | 4 ++++ 12 files changed, 65 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 4c93ab7..31f00cb 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -7,6 +7,7 @@ #include <common.h> #include <asm/arch/clock.h> #include <asm/io.h> +#include <asm/arch/fsl_serdes.h> #include <asm/arch/immap_ls102xa.h> #include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_stream_id.h> @@ -59,6 +60,19 @@ unsigned int get_soc_major_rev(void) return major; }
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 +void erratum_a010315(void) +{ + int i; + + for (i = PCIE1; i <= PCIE2; i++) + if (!is_serdes_configured(i)) { + debug("PCIe%d: disabled all R/W permission!\n", i); + set_pcie_ns_access(i, 0); + } +} +#endif + int arch_soc_init(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index fac539d..c0d2610 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -8,11 +8,14 @@ #include <fsl_ifc.h> #include <ahci.h> #include <scsi.h> +#include <asm/arch/fsl_serdes.h> #include <asm/arch/soc.h> #include <asm/io.h> #include <asm/global_data.h> #include <asm/arch-fsl-layerscape/config.h> +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS #include <fsl_csu.h> +#endif #ifdef CONFIG_SYS_FSL_DDR #include <fsl_ddr_sdram.h> #include <fsl_ddr.h> @@ -299,6 +302,19 @@ void erratum_a008850_post(void) #endif }
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 +void erratum_a010315(void) +{ + int i; + + for (i = PCIE1; i <= PCIE4; i++) + if (!is_serdes_configured(i)) { + debug("PCIe%d: disabled all R/W permission!\n", i); + set_pcie_ns_access(i, 0); + } +} +#endif + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index b0ad4b4..159c25d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -167,6 +167,8 @@ #define CONFIG_SYS_FSL_SEC_BE
#define CONFIG_SYS_FSL_SRDS_1 + +#define CONFIG_SYS_FSL_ERRATUM_A010315 /* SoC related */ #ifdef CONFIG_LS1043A #define CONFIG_MAX_CPUS 4 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 8d4a7ad..4512732 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -100,6 +100,10 @@ void cpu_name(char *name); void erratum_a009635(void); #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 +void erratum_a010315(void); +#endif + bool soc_has_dp_ddr(void); bool soc_has_aiop(void); #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index d408fe4..a16d980 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -131,6 +131,7 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_ERRATUM_A008378 #define CONFIG_SYS_FSL_ERRATUM_A009663 +#define CONFIG_SYS_FSL_ERRATUM_A010315 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #else #error SoC not defined diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h index a354684..9c91354 100644 --- a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h @@ -11,4 +11,8 @@ unsigned int get_soc_major_rev(void); int arch_soc_init(void); int ls102xa_smmu_stream_id_init(void);
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 +void erratum_a010315(void); +#endif + #endif /* __FSL_LS102XA_SOC_H */ diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 852d683..874c122 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -206,6 +206,10 @@ int board_init(void) out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif + #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index a3748de..6598ab3 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -202,6 +202,10 @@ int board_init(void) */ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif + #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 291b0f4..4eb38a7 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -430,6 +430,10 @@ int board_init(void) struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; unsigned int major;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif + major = get_soc_major_rev(); if (major == SOC_MAJOR_VER_1_0) { /* Set CCI-400 control override register to diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 85c036b..4638bed 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -480,6 +480,10 @@ void ls1twr_program_regulator(void)
int board_init(void) { +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif + #ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 1642557..8835a49 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -308,6 +308,10 @@ int misc_init_r(void)
int board_init(void) { +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); board_retimer_init();
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 0a73e0f..2e56b30 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -85,6 +85,10 @@ int board_init(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif + #ifdef CONFIG_FSL_IFC init_final_memctl_regs(); #endif
On 08/02/2016 04:14 AM, Zhiqiang Hou wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Up to now, the function is_serdes_configed() doesn't check if the map of serdes protocol is initialized before accessing it. The function is_serdes_configed() will get wrong result when it was called before the serdes protocol maps initialized. As the first element of the map isn't used for any device, so use it as the flag to indicate if the map has been initialized.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
V2:
- Check initialization-state of the serdes protocol map before serdes init.
- Comment the element 'NONE' used as a initialization-state flag.
This set has been applied to fsl-qoriq master. Awaiting upstream. Thanks.
York
On 08/02/2016 04:14 AM, Zhiqiang Hou wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Up to now, the function is_serdes_configed() doesn't check if the map of serdes protocol is initialized before accessing it. The function is_serdes_configed() will get wrong result when it was called before the serdes protocol maps initialized. As the first element of the map isn't used for any device, so use it as the flag to indicate if the map has been initialized.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
V2:
- Check initialization-state of the serdes protocol map before serdes init.
- Comment the element 'NONE' used as a initialization-state flag.
Zhiqiang,
This patch has been merged but I found an issue with it today. Please try to boot P4080DS from NOR flash. It causes recursive calls fsl_serdes_init()->p4080_erratum_serdes_a005()->is_serdes_configured()->fsl_serdes_init(). Please check if you have any similar recursive case for other platforms. Please send a fix ASAP.
York
Hi York,
-----Original Message----- From: york sun Sent: 2016年11月30日 5:58 To: Z.Q. Hou zhiqiang.hou@nxp.com; u-boot@lists.denx.de; albert.u.boot@aribaud.net; wd@denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Alison Wang alison.wang@nxp.com; Mingkai Hu mingkai.hu@nxp.com Cc: Yao Yuan yao.yuan@nxp.com; Q.Y. Gong qianyu.gong@nxp.com; bmeng.cn@gmail.com; Shengzhou Liu shengzhou.liu@nxp.com Subject: Re: [PATCHv2 1/5] fsl: serdes: ensure accessing the initialized maps of serdes protocol
On 08/02/2016 04:14 AM, Zhiqiang Hou wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Up to now, the function is_serdes_configed() doesn't check if the map of serdes protocol is initialized before accessing it. The function is_serdes_configed() will get wrong result when it was called before the serdes protocol maps initialized. As the first element of the map isn't used for any device, so use it as the flag to indicate if the map has been initialized.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
V2:
- Check initialization-state of the serdes protocol map before serdes init.
- Comment the element 'NONE' used as a initialization-state flag.
Zhiqiang,
This patch has been merged but I found an issue with it today. Please try to boot P4080DS from NOR flash. It causes recursive calls fsl_serdes_init()->p4080_erratum_serdes_a005()->is_serdes_configured()->fsl_ serdes_init(). Please check if you have any similar recursive case for other platforms. Please send a fix ASAP.
This issue has been fixed by the patch below, did your test point include this patch? Anyway, I will try the latest commit of tree u-boot-fsl-qoriq. commit 5eef15ea9d297d270935510d8a635f8d8bf72439 Author: Hou Zhiqiang Zhiqiang.Hou@nxp.com Date: Mon Oct 31 10:59:16 2016 +0800
fsl: serdes: fix a deadloop issue for P4080
This deadloop is introduced by commit: 71fe222 fsl: serdes: ensure accessing the initialized maps of serdes protocol
deadloop detail: cpu_init_r => fsl_serdes_init => p4080_erratum_serdes_a005 => is_serdes_configured => fsl_serdes_init
Thanks, Zhiqiang
On 11/30/2016 12:41 AM, Z.Q. Hou wrote:
Zhiqiang,
This patch has been merged but I found an issue with it today. Please try to boot P4080DS from NOR flash. It causes recursive calls fsl_serdes_init()->p4080_erratum_serdes_a005()->is_serdes_configured()->fsl_ serdes_init(). Please check if you have any similar recursive case for other platforms. Please send a fix ASAP.
This issue has been fixed by the patch below, did your test point include this patch? Anyway, I will try the latest commit of tree u-boot-fsl-qoriq. commit 5eef15ea9d297d270935510d8a635f8d8bf72439 Author: Hou Zhiqiang Zhiqiang.Hou@nxp.com Date: Mon Oct 31 10:59:16 2016 +0800
fsl: serdes: fix a deadloop issue for P4080 This deadloop is introduced by commit: 71fe222 fsl: serdes: ensure accessing the initialized maps of serdes protocol deadloop detail: cpu_init_r => fsl_serdes_init => p4080_erratum_serdes_a005 => is_serdes_configured => fsl_serdes_init
You were right. Sorry for the false alarm. I merged this commit in fsl-qoriq but was testing mpc85xx in parallel without this commit.
York
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